Method, device and electronic device for generating hardware interface signals

Abstract

This application discloses a method, apparatus, and electronic device for generating a hardware interface signal. Here, the method includes: obtaining a request instruction by a first system; determining a plurality of logical bit information corresponding to the request instruction; and generating a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer. This application solves the technical problem that the design cost of a chip is high because in the prior art, it is necessary for the chip itself to have the hardware logic design of a controller.

Description

[Technical Field]

[0001] The present application relates to the field of communications technology, and more particularly to a method, device and electronic device for generating a hardware interface signal. [Background technology]

[0002] Currently, in the prior art, a chip needs to have a hardware logic design of an associated controller itself to communicate hardware interface signals with external devices, where the associated controller is used to specifically process the hardware interface signals. However, the introduction of related controllers increases the design and manufacturing costs of chips, so there is an urgent need to find new solutions to reduce the difficulty of chip design and the manufacturing costs of chips. Summary of the Invention [Problem to be solved by the invention]

[0003] The present application provides a method, device and electronic equipment for generating a hardware interface signal. [Means for solving the problem]

[0004] According to one aspect of the present application, there is provided a method for generating a hardware interface signal, including the steps of: acquiring a request command by a first system; determining a plurality of logical bit information corresponding to the request command; and generating a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer. In one embodiment of the present application, the method for generating a hardware interface signal further includes determining a reload value and a first match value corresponding to a timer based on a plurality of logical bit information, and generating a hardware interface signal corresponding to a request instruction based on the reload value and the first match value.

[0005] In one embodiment of the present application, the method for generating a hardware interface signal further includes the steps of obtaining an operation time corresponding to each logical bit information; determining a reload value based on the operation time; determining one first match value corresponding to a timer based on a logical bit of each logical bit information, and obtaining multiple first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0006] In one embodiment of the present application, the method for generating a hardware interface signal further includes the step of sequentially generating hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information according to a forward / backward order among a plurality of logical bit information corresponding to a request command, to obtain a hardware interface signal.

[0007] In one embodiment of the present application, a method for generating a hardware interface signal includes the steps of: performing a decrement operation on a reload value corresponding to each logical bit information based on a timer; outputting a first signal corresponding to each logical bit information by a first system before the reload value corresponding to each logical bit information is decremented to a first match value corresponding to the logical bit information, the first signal being a high level signal; and outputting a second signal corresponding to the logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to a first match value corresponding to the logical bit information, Second signalis a low-level signal; and when the reload value corresponding to each logical bit information is decremented to 0, determining to generate a hardware interface sub-signal corresponding to the logical bit information to obtain a hardware interface sub-signal corresponding to each logical bit information, wherein the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information.

[0008] In one embodiment of the present application, the method for generating a hardware interface signal further includes the steps of: triggering a first interrupt corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to a first match value corresponding to the logical bit information; and triggering a second interrupt corresponding to the logical bit information when the reload value corresponding to the logical bit information is decremented to 0.

[0009] In one embodiment of the present application, the method for generating hardware interface signals further includes the steps of: performing an interrupt count once each time a first interrupt or a second interrupt is triggered in the process of sequentially generating hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information; and determining, based on the interrupt count, a field in the request command that is currently undergoing signal conversion processing, where the signal conversion processing is used to generate hardware interface sub-signals corresponding to the logical bit information corresponding to each field in the request command.

[0010] In one embodiment of the present application, the method for generating a hardware interface signal further includes the steps of: obtaining the number of bytes corresponding to each field in the request command; determining the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information; determining the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information; and determining the field in the request command that is currently undergoing signal conversion processing based on the number of interrupts and the interrupt count.

[0011] In one embodiment of the present application, the method for generating a hardware interface signal further includes the steps of: determining logical bit information currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count; determining a byte corresponding to the logical bit information currently being converted into the hardware interface sub-signal as a target byte; and determining a field corresponding to the target byte as a field currently undergoing signal conversion processing in the request command.

[0012] In one embodiment of the present application, the data structure of the request data corresponding to the request command is a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters, where the device address is used to characterize the address of a target device, the target device is a device that generates response data based on a hardware interface signal, the instruction code is used to distinguish different request commands, the write length is used to characterize the number of bytes from the instruction code to the request data, the read length is used to characterize the number of bytes including the completion code and read data in the request data, and the request parameters are used to characterize the parameters of the request command.

[0013] In one embodiment of the present application, the method for generating a hardware interface signal further includes the steps of: acquiring request data when a first system detects a first request triggered by a second system, where the first system and the second system run on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system; and analyzing the request data to obtain a request command.

[0014] In one embodiment of the present application, the method for generating a hardware interface signal further includes the steps of: storing the requested data in a target memory by a second system before obtaining the requested data; and triggering a first request by the second system after completing the storage of the requested data, wherein the first request is used to notify the first system to read the requested data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0015] In one embodiment of the present application, the method for generating a hardware interface signal further includes generating a hardware interface signal corresponding to a request command based on logic bit information and a timer, and then converting a voltage of the hardware interface signal to obtain a target hardware interface signal. In one embodiment of the present application, the method for generating a hardware interface signal further includes inputting the hardware interface signal into a voltage conversion device and obtaining a target hardware interface signal output from the voltage conversion device.

[0016] In one embodiment of the present application, the method for generating a hardware interface signal further includes: after generating a hardware interface signal corresponding to a request command based on logical bit information and a timer, receiving response data corresponding to the hardware interface signal by a first system, where the transmission format of the response data is the same as the transmission format of the hardware interface signal; and adjusting the data structure of the response data to a second data structure.

[0017] In one embodiment of the present application, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize a completion code in the response data and data describing the state of a target device, and the target device is a device that generates the response data based on hardware interface signals.

[0018] In one embodiment of the present application, the method for generating a hardware interface signal further includes the step of triggering a second request by the first system after adjusting the data structure of the response data to a second data structure, where the second request is used to notify the second system to read the response data. In one embodiment of the present application, the hardware interface signal is any one of a PECI signal, an HDMI (registered trademark) signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal.

[0019] According to another aspect of an embodiment of the present application, there is provided a hardware interface signal generating device including: an acquisition module used to acquire a request command by a first system; a determination module used to determine a plurality of logical bit information corresponding to the request command; and a generation module used to generate a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer.

[0020] In one embodiment of the present application, the generating module includes a first determining unit and a second generating unit, where the first determining unit is used to determine a reload value and a first match value corresponding to a timer based on a plurality of logical bit information, and the second generating unit is used to generate a hardware interface signal corresponding to a request command based on the reload value and the first match value.

[0021] In one embodiment of the present application, the first determining unit further includes a first acquiring subunit, a first determining subunit, and a second determining subunit, wherein the first acquiring subunit is used to acquire an operation time corresponding to each logical bit information, the first determining subunit is used to determine a reload value according to the operation time, and the second determining subunit is used to determine one first match value corresponding to a timer according to a logical bit of each logical bit information, and obtain multiple first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0022] In one embodiment of the present application, the second generation unit further includes a first generation subunit used to sequentially generate hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information according to a forward / backward order among the plurality of logical bit information corresponding to the request instruction, to obtain a hardware interface signal.

[0023] In one embodiment of the present application, the first generating sub-unit further includes a decrementing sub-module, a first signal outputting sub-module, a second signal outputting sub-module, and a first determining sub-module, wherein the decrementing sub-module is used for performing a decrementing operation on a reload value corresponding to each logical bit information based on a timer, the first signal outputting sub-module is used for outputting a first signal corresponding to each logical bit information by the first system before the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where the first signal is a high-level signal, and the second signal outputting sub-module is used for outputting a second signal corresponding to each logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where Second signal is a low-level signal, and the first determination sub-module is used to determine the generation of a hardware interface sub-signal corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to 0, and to obtain a hardware interface sub-signal corresponding to each logical bit information, where the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information.

[0024] In one embodiment of the present application, the hardware interface signal generating device further includes a first interrupt trigger module and a second interrupt trigger module, wherein the first interrupt trigger module is used to trigger a first interrupt corresponding to each logical bit information when a reload value corresponding to the logical bit information is decremented to a first match value corresponding to the logical bit information, and the second interrupt trigger module is used to trigger a second interrupt corresponding to the logical bit information when a reload value corresponding to the logical bit information is decremented to 0.

[0025] In one embodiment of the present application, the hardware interface signal generating device further includes an interrupt counting module and a field determining module, where the interrupt counting module is used to perform an interrupt count once every time a first interrupt or a second interrupt is triggered, and the field determining module is used to determine a field in the request command that is currently undergoing signal conversion processing based on the interrupt count, where the signal conversion processing is used to generate a hardware interface sub-signal corresponding to logical bit information corresponding to each field in the request command.

[0026] In one embodiment of the present application, the field determination module further includes a second obtaining unit, a second determining unit, a third determining unit, and a fourth determining unit, wherein the second obtaining unit is used to obtain the number of bytes corresponding to each field in the request command, the second determining unit is used to determine the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information, the third determining unit is used to determine the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information, and the fourth determining unit is used to determine the field in the request command that is currently performing signal conversion processing based on the number of interrupts and the interrupt count.

[0027] In one embodiment of the present application, the fourth determining unit further includes a third determining subunit, a fourth determining subunit, and a fifth determining subunit, wherein the third determining subunit is used to determine logic bit information currently being converted into hardware interface sub-signals based on the interrupt number and the interrupt count, the fourth determining subunit is used to determine a byte corresponding to the logic bit information currently being converted into hardware interface sub-signals as a target byte, and the fifth determining subunit is used to determine a field corresponding to the target byte as a field currently undergoing signal conversion processing in the request command.

[0028] In one embodiment of the present application, the acquisition module further includes a request data acquisition unit and a request data analysis unit, where the request data acquisition unit is used to acquire request data when a first request triggered by a second system is detected by the first system, where the first system and the second system run on the same processor, the request data is generated by the second system, and the service response speed of the second system is lower than that of the first system, and the request data analysis unit is used to analyze the request data and obtain the request command.

[0029] In one embodiment of the present application, the hardware interface signal generating device further includes a request data storage module used by a second system to store request data in a target memory and, after the storage of the request data is completed, to trigger a first request by the second system, where the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0030] In one embodiment of the present application, the device for generating a hardware interface signal further includes a voltage conversion module used to convert the voltage of the hardware interface signal to obtain a target hardware interface signal. In one embodiment of the present application, the hardware interface signal generating apparatus further includes a signal input unit used to input the hardware interface signal to the voltage conversion device and obtain a target hardware interface signal output from the voltage conversion device.

[0031] In one embodiment of the present application, the device for generating a hardware interface signal further includes a response data receiving module and a data structure adjusting module, where the response data receiving module is used to receive response data corresponding to the hardware interface signal by a first system, where the transmission format of the response data is the same as the transmission format of the hardware interface signal, and the data structure adjusting module is used to adjust the data structure of the response data to a second data structure.

[0032] In one embodiment of the present application, the device for generating a hardware interface signal further includes a second request trigger module used to trigger a second request by the first system, the second request being used to notify the second system to read the response data.

[0033] To achieve the above object, according to another embodiment of the present disclosure, there is further provided a computer-readable storage medium storing a computer program, the computer program being configured, when operating, to perform the steps of any of the above method embodiments.

[0034] To achieve the above object, according to another embodiment of the present disclosure, there is further provided an electronic device including a storage device storing a computer program and a processor configured to execute the steps of any of the above method embodiments by executing the computer program. To achieve the above object, according to another aspect of the present application, there is further provided an embedded system including a first system and a processor, wherein the first system operates on the processor, and the first system is used to obtain a request instruction, determine a plurality of logical bit information corresponding to the request instruction, and generate a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer.

[0035] In one embodiment of the present application, a first system is used to determine a reload value and a first match value corresponding to a timer based on a plurality of logical bit information, and a second system is used to generate a hardware interface signal corresponding to a request instruction based on the reload value and the first match value. In one embodiment of the present application, a first system is used to obtain an operation time corresponding to each logical bit information, the first system is used to determine a reload value based on the operation time, the first system is used to determine one first match value corresponding to a timer based on a logical bit of each logical bit information, and obtain multiple first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0036] In one embodiment of the present application, the first system is used to sequentially generate hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information according to a forward / backward order among a plurality of logical bit information corresponding to a request command, and obtain a hardware interface signal.

[0037] In one embodiment of the present application, a first system is used to perform a decrement operation on a reload value corresponding to each logical bit information based on a timer, and the first system is used to output a first signal corresponding to each logical bit information by the first system before the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where the first signal is a high-level signal, and the first system is used to output a second signal corresponding to each logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where the second signal is a low-level signal, and the first system is used to determine the generation of a hardware interface sub-signal corresponding to each logical bit information when the reload value corresponding to each logical bit information is decremented to 0, and to obtain a hardware interface sub-signal corresponding to each logical bit information, where the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0038] In one embodiment of the present application, a first system is used to trigger a first interrupt corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to a first match value corresponding to the logical bit information, and a first system is used to trigger a second interrupt corresponding to the logical bit information when the reload value corresponding to the logical bit information is decremented to 0.

[0039] In one embodiment of the present application, the first system is used to perform an interrupt count once each time a first interrupt or a second interrupt is triggered, and the first system is used to determine a field in the request command that is currently undergoing signal conversion processing based on the interrupt count, where the signal conversion processing is used to generate a hardware interface sub-signal corresponding to logical bit information corresponding to each field in the request command.

[0040] In one embodiment of the present application, a first system is used to obtain the number of bytes corresponding to each field in a request command, and the first system is used to determine the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information, and the first system is used to determine the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information, and the first system is used to determine the field in the request command that is currently performing signal conversion processing based on the number of interrupts and the interrupt count.

[0041] In one embodiment of the present application, a first system is used to determine logical bit information currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count, the first system is used to determine a byte corresponding to the logical bit information currently being converted into a hardware interface sub-signal as a target byte, and the first system is used to determine a field corresponding to the target byte as a field currently undergoing signal conversion processing in a request command.

[0042] In one embodiment of the present application, the embedded system further includes a second system, wherein the second system and the first system both run on a processor, the second system is used to generate request data, and the first system is used to obtain the request data when detecting a first request triggered by the second system, wherein the service response speed of the second system is lower than the service response speed of the first system, and the first system is used to analyze the request data and obtain the request command.

[0043] In one embodiment of the present application, the second system is used to store the requested data in a target memory, and after completing the storage of the requested data, trigger the first request, where the first request is used to notify the first system to read the requested data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0044] In one embodiment of the present application, the first system is used to convert the voltage of the hardware interface signal to obtain the target hardware interface signal. In one embodiment of the present application, a first system is used to input a hardware interface signal to a voltage conversion device and obtain a target hardware interface signal output from the voltage conversion device.

[0045] In one embodiment of the present application, a first system is used to receive response data corresponding to a hardware interface signal, where the transmission format of the response data is the same as the transmission format of the hardware interface signal, and the first system is used to adjust the data structure of the response data to a second data structure. In one embodiment of the present application, the first system is used to trigger a second request, where the second request is used to notify the second system to read the response data.

[0046] According to another aspect of the present application, there is further provided a chip including at least one of programmable logic circuitry and executable instructions, the chip operating in an electronic device and used to perform the steps of any of the above method embodiments. According to another aspect of the present application, there is further provided a BMC chip including a memory unit and a processing unit connected to the memory unit, wherein the memory unit is used to store a program and the processing unit is used to execute the program, thereby performing the steps in any of the above method embodiments.

[0047] According to another aspect of the present application, there is further provided a motherboard including at least one processor and at least one storage used to store at least one program, wherein the at least one program, when executed by the at least one processor, causes the at least one processor to perform the steps in any of the above method embodiments.

[0048] According to another aspect of the present application, there is further provided a server including a processor, a communication interface, storage, and a communication bus, wherein the processor, communication interface, and storage communicate with each other via the communication bus, the storage is used to store a computer program, and the processor is used to implement the steps in any of the above method embodiments when executing the program stored in the storage. [Effects of the Invention]

[0049] The present application employs a method in which a first system generates a hardware interface signal corresponding to a request command, by first obtaining the request command, then determining a plurality of logical bit information corresponding to the request command, and finally generating the hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer. As can be seen from the above, the present application employs a first system to generate a hardware interface signal corresponding to the request command, thereby achieving the technical effect of simulating the generation of a hardware interface signal using a software method and achieving the objective of eliminating the need for a chip to have a hardware logic design for the relevant hardware interface signal, thereby reducing the difficulty and cost of the chip design. The present application achieves the objective of using a software system to generate a hardware interface signal without requiring a chip to have a hardware logic design for the hardware interface signal, thereby reducing the difficulty and cost of the chip design and solving the technical problem of the prior art, which requires a chip to have a hardware logic design for the controller, resulting in high chip design costs. [Brief explanation of the drawings]

[0050] The drawings described herein are provided to further the understanding of the present application and constitute a part of the present application, and the illustrative embodiments and the description thereof are to be used for interpreting the present application and are not to be construed as unduly limiting the present application. [Figure 1] FIG. 2 is a schematic diagram of a computer terminal provided by an embodiment of the present application. [Figure 2] 1 is a flowchart of a method for generating a hardware interface signal according to an embodiment of the present application; [Figure 3] FIG. 2 is a schematic diagram of a waveform signal with a logic bit of 0 according to an embodiment of the present application. [Figure 4] FIG. 2 is a schematic diagram of a waveform signal with a logic bit of 1 according to an embodiment of the present application. [Figure 5]10 is a flowchart of hardware interface sub-signal generation according to an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram of a request command according to an embodiment of the present application; [Figure 7] 10 is a flowchart of an initialization function call according to an embodiment of the present application; [Figure 8] 1 is a flowchart of a transfer function process according to an embodiment of the present application. [Figure 9] 10 is a flowchart of the processing of a timer interrupt function according to an embodiment of the present application; [Figure 10] FIG. 1 is a diagram illustrating the interaction of a dual system according to an embodiment of the present application. [Figure 11] FIG. 1 is a hardware topology architecture diagram for simulating hardware interface signals according to the present application. [Figure 12] FIG. 2 is an interaction diagram between selectable first and second systems according to an embodiment of the present application. [Figure 13] 1 is a schematic diagram of a selectable hardware interface signal generator according to an embodiment of the present application; [Figure 14] FIG. 2 is a block diagram of the structure of a computer terminal according to an embodiment of the present application; [Figure 15] FIG. 1 is a block diagram of the architecture of an embedded system according to an embodiment of the present application. [Figure 16] 1 is a flowchart of a communication method according to an embodiment of the present application; [Figure 17] 1 is a flowchart 1 of a selectable communication method according to an embodiment of the present application. [Figure 18] 2 is a flowchart 2 of a selectable communication method according to an embodiment of the present application. [Figure 19] FIG. 1 is a block diagram of the architecture of a selectable BMC chip according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0051] In order to help those skilled in the art understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments that those skilled in the art can devise without any creative efforts shall fall within the scope of protection of the present application.

[0052] It should be noted that the terms "first," "second," etc. in the specification, claims, and drawings are used to distinguish between similar objects and are not intended to describe a particular order or chronology. It should be understood that such terms may be interchanged where appropriate, such that the embodiments described herein may be practiced in orders other than those illustrated or described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions; for example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to the explicitly recited steps or units, but may include other steps or units not explicitly recited or inherent in such process, method, product, or apparatus.

[0053] In addition, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, electronic medical records, etc.) related to this application are all information and data authorized by the user or fully authorized by each party, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and a corresponding operation portal must be provided to allow the user to select permission or refusal.

[0054] According to an embodiment of the present application, a method for generating a hardware interface signal is provided, wherein the steps illustrated in the flowcharts of the drawings may be performed, for example, in a computer system as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than specified herein.

[0055] The embodiments of the methods provided herein may be implemented in a mobile terminal, a computer terminal, or a similar computing device. FIG. 1 shows a block diagram of the hardware structure of a computer terminal (or mobile device) for implementing the hardware interface signal generation method. As shown in FIG. 1, a computer terminal (or mobile device) 10 may include a processor 102 (which may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, and may also include a set of processors designated 102a, 102b, ..., 102n in FIG. 1), a storage 104 used for storing data, and a transmission module 106 used for communication functions. The computer terminal (or mobile device) may further include a display, an input / output interface (I / O interface), a Universal Serial Bus (USB) port (which may be included as one of the ports of a BUS bus), a network interface, a power supply, and / or a camera. As will be appreciated by those skilled in the art, the structure shown in FIG. 1 is merely exemplary and does not limit the structure of the electronic device. For example, computer terminal 10 may include more or fewer components than shown in FIG. 1, or may have them arranged differently than shown in FIG.

[0056] It should be noted that, herein, the one or more processors 102 and / or other data processing circuitry may be generally referred to as "data processing circuitry." Such data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination. Also, the data processing circuitry may be a single, separate processing module, or may be incorporated in whole or in part within any of the other elements of the computer terminal 10 (or mobile device).

[0057] Storage 104 may be a program instruction / data storage device corresponding to the hardware interface signal generation method of the present application, and may be used to store software programs and modules of application software. Processor 102 executes the software programs and modules stored in storage 104 to perform various functional applications and data processing, i.e., to realize the hardware interface signal generation method. Storage 104 may include high-speed random memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some embodiments, storage 104 may also include storage devices located remotely from processor 102, which may be connected to computer terminal 10 via a network. Examples of such networks include, but are not limited to, the Internet, a corporate intranet, a local area network, a mobile communication network, and combinations thereof.

[0058] The transmission device 106 is used to receive or transmit data via a network. A specific example of the network may include a wireless network provided by the carrier of the computer terminal 10. In one example, the transmission device 106 includes a network interface controller (NIC) that can communicate with the Internet by connecting to other network devices via a base station. In one example, the transmission device 106 may be a radio frequency (RF) module for communicating with the Internet wirelessly.

[0059] The display may be, for example, a touchscreen type liquid crystal display (LCD), which allows the user to interact with the user interface of the computer terminal 10 (or mobile device). In the above operating environment, the present application provides a method for generating a hardware interface signal as shown in Fig. 2. As shown in Fig. 2, the method includes the following steps S201 to S203.

[0060] In step S201, a request command is obtained by the first system. In step S201, the first system may be, for example, an RTOS (Real-time system) system, which may be a software system disposed on a chip, and the request command may be a command to generate a hardware interface signal. For example, if the hardware interface signal is a PECI (Platform Environment Control Interface) signal, the request command is a PECI request command based on the PECI protocol.

[0061] Furthermore, the above chip may be a BMC (baseboard management controller, a server platform management control chip that can realize functions such as server health monitoring, remote on / off, temperature (voltage) collection, and fault diagnosis) chip, or may be another type of chip, and the present application does not particularly limit the type of chip.

[0062] Optionally, the hardware interface signal may be, for example, an HDMI (high definition multimedia interface) signal, an RGMII (reduced gigabit media independent interface, a parallel bus) signal, an SGMII (serial gigabit media independent interface, a single-path serial bus) signal, a GPIO (general-purpose input / output) signal, or an SPI (serial peripheral interface) signal, or may be a hardware interface signal of another protocol type. In addition, the request command may be a request command of another protocol type; for example, if the hardware interface signal is a GPIO signal, the request command is a GPIO request command. The present application does not particularly limit the specific types of the request command and the hardware interface signal.

[0063] It should also be noted that the first system may be, in addition to an RTOS system, a Linux (registered trademark) system or other software systems developed for the vehicle, or may be other software systems; the present application only requires that the first system continuously generate and output hardware interface signals. In step S202, a plurality of pieces of logical bit information corresponding to the request command are determined.

[0064] In step S202, after obtaining the request command, the first system can analyze and obtain a plurality of logical bit information corresponding to the request command, where there is a sequence among the plurality of logical bit information, and the first system can generate a waveform signal (i.e., a hardware interface signal) corresponding to the request command according to the plurality of logical bit information corresponding to the request command, thereby transmitting the information contained in the request command to other devices through the hardware interface signal.

[0065] Optionally, the request command includes at least one field, and each field can be represented by a logical bit 0 or 1. In addition, the corresponding conversion relationship between each field and the logical bit 1 or 0 is logical bit information corresponding to the field, and when the request command corresponds to multiple fields, the request command corresponds to multiple logical bit information. Also, each logical bit can be represented by a combination of a high-level signal and a low-level signal, for example, logical bit 0 can be represented by a combination of a high-level signal of a first preset time length and a low-level signal of a second preset time length, and logical bit 1 can be represented by a combination of a high-level signal of a second preset time length and a low-level signal of the first preset time length, where the first preset time length and the second preset time length are different. In addition, since each logical bit includes both a high-level signal and a low-level signal, in reality, each logical bit is represented by a single waveform signal (the conversion between a high-level signal and a low-level signal becomes one waveform), and a request command corresponds to multiple logical bit information, i.e., corresponds to multiple logical bits, so the hardware interface signal corresponding to the request command is a single waveform signal obtained by combining the waveform signals corresponding to each logical bit information.

[0066] In step S203, a hardware interface signal corresponding to the request command is generated based on the plurality of logical bit information and the timer. Optionally, the timer in step S203 may be a timing program in the first system, or may be a register in a chip where the first system is located, where the timer can provide at least a timing function and a counting function. The present application uses the timing function and counting function of the timer to generate a hardware interface signal corresponding to a request command according to multiple logical bit information.

[0067] It should be noted that, for example, the chip is a BMC chip and the hardware interface signal is a PECI signal. In the prior art, to realize communication between the BMC chip and a device such as a CPU (central processing unit), the BMC chip itself needs to have the hardware logic design of a PECI controller, which causes a problem of high BMC chip design costs. In other words, in the prior art, to generate a PECI signal on the BMC chip, the hardware logic design of the PECI controller must be realized on the BMC chip in advance. In the present application, the PECI signal can be generated on the BMC chip using only the first system, and there is no need to realize the hardware logic design of the PECI controller on the BMC chip, thereby reducing the difficulty and cost of designing the BMC chip.

[0068] As can be seen from the contents of steps S201 to S203, the present application adopts a method in which a first system generates a hardware interface signal corresponding to a request command, in which the first system first acquires the request command, then determines multiple pieces of logical bit information corresponding to the request command, and finally generates a hardware interface signal corresponding to the request command based on the multiple pieces of logical bit information and a timer.

[0069] As can be seen from the above, the present application uses a first system to generate hardware interface signals corresponding to required commands, thereby achieving the technical effect of simulating the generation of hardware interface signals using a software method, and further achieving the objective of eliminating the need for the chip itself to have hardware logic design for the relevant hardware interface signals, which not only reduces the difficulty of chip design but also reduces chip design costs.

[0070] In this way, the present application achieves the objective of using a software system to generate hardware interface signals without the need for hardware logic design of hardware interface signals for the chip, thereby reducing the difficulty of chip design and solving the technical problem of high chip design costs caused by the need for the chip itself to have hardware logic design of the controller in the prior art.

[0071] In an alternative embodiment, to generate a hardware interface signal corresponding to a request instruction based on the plurality of logical bit information and a timer, the first system first determines a reload value and a first match value corresponding to the timer based on the plurality of logical bit information, and then generates a hardware interface signal corresponding to the request instruction based on the reload value and the first match value.

[0072] Alternatively, the reload value may be understood as the counting period of the timer, for example, if the reload value is 100 ms, the timer will restart counting every 100 ms. The first match value is used to control the logical bit corresponding to each logical bit information to 0 or 1. Optionally, in the process of determining a reload value and a first match value corresponding to the timer based on the plurality of logical bit information, the first system first obtains an operation time corresponding to each logical bit information, and then determines a reload value based on the operation time. The first system also determines a first match value corresponding to the timer based on a logical bit of each logical bit information, and obtains a plurality of first match values ​​corresponding to the timer, where the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0073] Generally, in signal transmission protocols, the operating time corresponding to each logical bit information among multiple logical bit information is the same. For example, assuming that the operating time corresponding to each logical bit information is tBIT, the reload value corresponding to the timer is a numerical value obtained by converting tBIT based on the timer's timing unit. For example, if the operating time tBIT is 100 seconds and the timer's timing unit is seconds, the reload value is 100.

[0074] Furthermore, the first match value corresponding to each piece of logical bit information is related to the logical bit corresponding to that piece of logical bit information. As shown in Fig. 3, tBIT is the operating time corresponding to one logical bit information, and when the logical bit of one logical bit information is 0, the signal corresponding to the logical bit information has a waveform with a duty ratio of approximately 1 / 4, and the high-level holding time here satisfies 0.2 to 0.4tBIT. Also, as shown in Fig. 4, when the logical bit of one logical bit information is 1, the signal corresponding to the logical bit information has a waveform with a duty ratio of 3 / 4, and the high-level holding time here satisfies 0.6 to 0.8tBIT.

[0075] As can be seen from the above, in order to emulate a hardware interface signal using software, it is essential to realize waveform conversion (waveform conversion between high and low levels exists for both logic 0 and logic 1). Therefore, the present application realizes waveform conversion using the timer's reload value and first match value. Optionally, the present application realizes control of the operation time of a logic bit, i.e., the operation time of one waveform signal, using the reload value, while realizing identification of different logic bits using the first match value, i.e., waveform signals corresponding to different logic bits have different duty cycles.

[0076] Optionally, the first system is required to sequentially generate hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information according to a forward / backward order among the plurality of logical bit information corresponding to the request command, to obtain a hardware interface signal. For example, assuming that the request command corresponds to logical bit information 1, logical bit information 2, logical bit information 3, ... logical bit information i, ... logical bit information N, the first system sequentially generates hardware interface sub-signals corresponding to each logical bit information, i.e., hardware interface sub-signal 1, hardware interface sub-signal 2, hardware interface sub-signal 3, ... hardware interface sub-signal i, ... hardware interface sub-signal N. Finally, hardware interface sub-signal 1, hardware interface sub-signal 2, hardware interface sub-signal 3, ... hardware interface sub-signal i, ... hardware interface sub-signal N are spliced ​​together to form a hardware interface signal.

[0077] Alternatively, the process of generating the hardware interface sub-signals corresponding to each logical bit information is as shown in FIG. In step S501, a decrement operation is performed on the reload value corresponding to each piece of logical bit information based on the timer.

[0078] In step S502, before the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, a first signal corresponding to the logical bit information is output by a first system, where the first signal is a high-level signal. In step S503, after the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, the first system outputs a second signal corresponding to the logical bit information, where the second signal is a low level signal.

[0079] In step S504, when the reload value corresponding to each logical bit information is decremented to 0, determine to generate a hardware interface sub-signal corresponding to the logical bit information, and obtain a hardware interface sub-signal corresponding to each logical bit information, where the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information.

[0080] Optionally, based on the operation principle of a timer, the timer includes a down counter, which triggers a timer interrupt when it counts down to 0 along with the system clock and automatically loads a reload value before restarting decrement counting, and also triggers an interrupt when the downcount value is equal to the first match value, where the interrupt may be understood as an identifier, and therefore the interrupt may be called an interrupt identifier, the first interrupt may be called a first interrupt identifier, and the second interrupt may be called a second interrupt identifier. In order to realize the waveforms of logical bit 0 and logical bit 1, the present application sets the timer's reload value to the operation time tBIT corresponding to the logical bit information, and sets the first match value to 3×tBIT / 4 to represent logical 0, and sets the first match value to 1×tBIT / 4 to represent logical 1.

[0081] The process of implementing the hardware interface sub-signals corresponding to each logical bit information by software will be described below using a transmission rate of 10 kbps as an example. Set the timer's reload value to 100ms. Set the high level output (every time you generate a signal, you need to pull the signal to high level), If the logical bit of one piece of logical bit information is 0, set the value of the first match value corresponding to the logical bit information to 75 ms; If the logical bit of one piece of logical bit information is 1, set the value of the first match value corresponding to the logical bit information to 25 ms; When the downcount value of the timer matches the first match value, the first system outputs a low level; When the timer reload value is decremented by 0, the first system determines to generate a hardware interface sub-signal corresponding to the logical bit, and raises the low level to a high level to continue generating a hardware interface sub-signal corresponding to the next logical bit information.

[0082] As can be seen from the above, the present invention realizes signal waveform conversion using the timer's reload value and first match value, thereby simulating the generation of a hardware interface signal. In an alternative embodiment, when the reload value corresponding to each logical bit information is decremented to the first match value corresponding to that logical bit information, the first system also triggers a first interrupt corresponding to that logical bit information, and when the reload value corresponding to each logical bit information is decremented to 0, the first system also triggers a second interrupt corresponding to that logical bit information.

[0083] In addition, the present application realizes interrupt counting by recording the first interrupt and the second interrupt triggered in response to each logical bit information, and further determines which field in the request command is currently performing signal conversion based on the interrupt count. Optionally, each time one first interrupt or one second interrupt is triggered, the first system performs an interrupt count once, and determines a field in the request command that is currently undergoing signal conversion processing based on the interrupt count, where the signal conversion processing is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request command.

[0084] Optionally, the first system may obtain the number of bytes corresponding to each field in the request command, and then determine the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information. Then, the first system determines the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information. Finally, the first system determines the field in the request command that is currently undergoing signal conversion processing based on the number of interrupts and the interrupt count.

[0085] For example, as shown in Figure 6, one request command includes four fields: an address rate negotiation bit, a target address addr, a message rate negotiation bit, and a write length. Here, the number of bytes corresponding to the address rate negotiation bit is 2, i.e., the address rate negotiation bit is composed of two bits, the number of bytes corresponding to the target address addr is 8, the number of bytes corresponding to the message rate negotiation bit is 1, and the number of bytes corresponding to the write length is 8. As a result, the request command in Figure 6 corresponds to a total of 19 bytes, and each byte corresponds to one logical bit information. Therefore, the request command corresponds to 19 logical bit information. Furthermore, each logical bit information corresponds to two interrupts. Therefore, the request command corresponds to a total of 38 interrupts, i.e., the number of interrupts for the request command is 38. In addition, based on the interrupt count, the first system can determine that the two bits of the address rate negotiation bit are processed by four interrupts 0 to 3, and that the write length field is processed by 16 interrupts 22 to 37.

[0086] Optionally, the first system determines logical bit information currently being converted into hardware interface sub-signals based on the number of interrupts and the interrupt count, and determines a byte corresponding to the logical bit information currently being converted into the hardware interface sub-signals as a target byte, whereby the first system determines a field corresponding to the target byte as a field currently undergoing signal conversion processing in the request command.

[0087] For example, still taking the request command in Figure 6 above as an example, assuming that the current interrupt count is 4, it can be determined that the logical bit information currently undergoing signal conversion is the second logical bit information among 19 logical bit information, and the target byte is the second byte among 19 bytes. Since the field corresponding to the second byte is the address rate negotiation bit, the first system can determine that the field currently undergoing signal conversion processing in the request command is the address rate negotiation bit.

[0088] In addition, in the present application, in addition to being able to determine the field undergoing signal conversion processing using the interrupt count method, it is also possible to determine the field undergoing signal conversion processing, or the field that has already completed signal conversion processing, or the field that has not yet completed signal conversion processing, by recording the number of times the reload value decreases to the first match value or the number of times the reload value decreases to 0.

[0089] Optionally, the present application may record fields that have already completed signal conversion processing alone. In addition, compared to determining the field undergoing signal conversion processing by recording the number of times the reload value decreases to the first match value and the number of times the reload value decreases to 0, recording only the fields that have already completed signal conversion processing and determining the field undergoing signal conversion processing using the interrupt count reduces the calculation load of the first system, thereby achieving the technical effect of determining the field more simply and efficiently.

[0090] In an optional embodiment, the first system may further transmit the fields currently undergoing signal conversion processing, the fields that have already completed signal conversion processing, and the fields that have not yet completed signal conversion processing to the display screen, so that if a failure occurs in the signal conversion, the operator can directly check the progress of the signal conversion from the display screen, and further help the operator quickly recover the signal conversion work; for example, the operator may send a control command to the first system to request the first system to resume signal conversion from the field that is undergoing signal conversion processing when a failure occurs in the signal conversion, and there is no need to repeat signal conversion for fields that have already completed signal conversion processing, thereby improving the signal conversion efficiency and avoiding waste of system computing resources.

[0091] In order to better explain the process of generating a hardware interface signal in the present invention, the hardware interface signal will be described as an example with reference to the drawings. As shown in Figure 7, first, the first system calls the initialization function, where the main function of the initialization function is to complete the initialization function before transmitting the request command. According to the signal transmission protocol specification, the default level state is low level, so the initialization function is used to control the level of the signal generating port to low level, where the signal generating port may be a GPIO port. Then, the first system proceeds to the transfer function processing process, and the specific steps are as shown in FIG.

[0092] In step 1, first, the first system extracts request parameters, which include a target address addr, a write length wl, a read length rl, an instruction code cmd, and a parameter para in a request command; In step 2, the first system calculates the number of interrupts required for this transmission, where two interrupts are required to complete the transmission of each logical bit information (one interrupt occurs when the downcount value reaches 0, and one interrupt occurs when the downcount value is equal to the first match value), the reload value is used to define the start of the logical bit information, and the first match value is used to control the logical bit corresponding to the output logical bit information to 0 or 1; In step 3, the first system sets the timer's reload value to one logical bit time tBIT; In step 4, the first system sets the timer's First Match Value to 3*tBIT / 4 time (corresponding to logic 0 because every transmission starts with logic 0); In step 5, the first system turns on the timer interrupt and starts the timer; In step 6, when the timer interrupt process is completed, the current transmission ends.

[0093] Optionally, Figure 9 shows a flowchart of the processing of the timer interrupt function according to an embodiment of the present application. As shown in Figure 9, after adding 1 to the interrupt count variable each time, the first system compares the obtained interrupt count with the previously calculated number of interrupts required for this transmission. If the interrupt count is greater than the number of interrupts, it turns off the timer and determines that the hardware interface signal corresponding to the request command has already been generated. If the interrupt count is less than or equal to the number of interrupts, it determines the field to be currently processed based on the interrupt count and the number of interrupts, and determines whether the logical bit of the logical bit information required for the next signal conversion is 1. If not, it updates the first match value to 3 x tBIT / 4. If it is 1, it updates the first match value to tBIT / 4, thereby realizing the control of the level change of the signal generation port.

[0094] In an alternative embodiment, the hardware interface system of the present application can be realized by a dual system, and optionally, when a first system detects a first request triggered by a second system, the first system obtains request data, where the first system and the second system run on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system. Finally, the first system analyzes the request data to obtain a request command.

[0095] Optionally, the second system may be a Linux system or any other type of software system, and the present application does not particularly limit the type of the second system. In addition, in order to smoothly and continuously generate the hardware interface signal, the free computing resources of the first system are greater than the free computing resources of the second system. In other words, the present application selects a system with more free resources to generate the hardware interface signal, thereby avoiding the problem of being unable to continuously generate the hardware interface signal due to a lack of system resources.

[0096] In another alternative embodiment, the free computing resources of the first system can be set to be greater than a preset threshold, and the preset threshold is used to characterize the maximum computing resource value required when constantly generating the hardware interface signal. Optionally, before obtaining the requested data, the present application stores the requested data in a target memory by a second system, and after the storage of the requested data is completed, triggers a first request by the second system, where the first request is used to notify the first system to read the requested data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0097] As shown in Figure 10, the first system is an RTOS system, the second system is a Linux system, and the hardware interface signal is a PECI signal. This application divides the software processing flow of the PECI communication protocol in the chip into two processes: command request and command response, and the two processes will be described in detail below.

[0098] As shown in Figure 10, for the command request process, first, the upper layer application (such as fault diagnosis, CPU temperature acquisition, etc.) related to the PECI service in the Linux system actively initiates a PECI request command as needed, and these request commands include but are not limited to the basic Ping() command, CPU temperature acquisition command, and MSR register information read command, etc., and the codes of different PECI request commands are realized by corresponding interface functions.

[0099] Optionally, the Linux system uses the instruction parameter structuring module in Fig. 10 to write request data such as the target address, read / write length, instruction code, and para parameters of each request instruction to the target memory according to the PECI protocol specification, and when all the request data is written to the target memory, the Linux system generates a first request using the interrupt event generation and detection function module in Fig. 10 to notify the RTOS system. Here, the first request may be an SGI interrupt request (software generated interrupt, a communication interrupt request between processor cores).

[0100] It should be noted that in the process of storing the request data in the target memory by the second system, the second system stores the request data in the target memory in the form of a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code and request parameters, the device address is used to characterize the address of the target device, the target device is a device that generates response data based on a hardware interface signal, the instruction code is used to distinguish different request commands, the write length is used to characterize the number of bytes from the instruction code to the request data, the read length is used to characterize the number of bytes including the completion code and read data in the request data, and the request parameters are used to characterize the parameters of the request command.

[0101] As shown in Table 1, Table 1 shows an example of a selectable data structure of request data (corresponding to the first data structure).

[0102] [Table 1]

[0103] Optionally, as shown in Figure 10, after detecting the first request triggered by the Linux system, the RTOS system reads the request data in the target memory, and then completes the data analysis process by the command analysis and parameter extraction function module in Figure 10. Then, the PECI command and parameter matching function module determines the corresponding PECI request command and command parameters based on the analyzed data, and finally transmits the PECI signal from the GPIO port of the BMC by the PECI waveform generation and transmission module in Figure 10.

[0104] In an alternative embodiment, the first system may also receive response data corresponding to the hardware interface signal, where the transmission format of the response data is the same as the transmission format of the hardware interface signal, and then the first system adjusts the data structure of the response data to a second data structure. Also, after adjusting the data structure of the response data to the second data structure, the present application triggers a second request by the first system, where the second request is used to notify the second system to read the response data.

[0105] Optionally, the hardware interface signal is still a PECI signal. Figure 10 further illustrates the instruction response process. As shown in Figure 10, the RTOS system first receives the response data sent from the PECI bus. The PECI instruction analysis and parameter extraction module in Figure 10 then completes data analysis to convert the response data signal format from the hardware interface signal format to the software signal format. For example, the PECI instruction analysis and parameter extraction module identifies waveform changes between high and low levels in the hardware interface signal to obtain corresponding logic bit information. Software signal data is then obtained based on the logic bit information. The analyzed response data is then adjusted by the instruction parameter structuring module and written to the target memory. After all the analyzed response data has been written, the interrupt event generation and detection module in the RTOS system triggers a second request to notify the Linux system. Upon detecting the second request, the Linux system actively reads the analyzed response data stored in the target memory, processes the data through the instruction analysis and parameter extraction module, and then returns it to the upper-layer application. Here, the second request is also an SGI interrupt request.

[0106] It should be noted that the shared memory in FIG. 10 is the target memory in the present application, and in the present application, the target memory may be other memory other than the shared memory, such as a random access memory (abbreviated as RAM) or a flash memory. In the alternative embodiment, both the first and second requests are interrupt requests (for example, SGI interrupt requests), and the interrupt requests will be described below.

[0107] Selective preemption and release of processing resources between different operating systems can be accomplished through inter-core interrupts, such as SGI interrupt requests. One operating system can request preemption or release of processing resources by sending a resource preemption request (e.g., a core preemption request) or a resource release request (e.g., a core release request) to another operating system via an IPI (Inter-Processor Interrupt). Taking the Linux system as an example, inter-core communication can be achieved in the Linux system based on a custom interrupt vector table and interrupt events between different operating systems. Here, IPIs are interrupts triggered between multiple cores within a system-on-chip (SOC) and are different from general external interrupts. Therefore, cores can reserve certain interrupt numbers specifically for IPIs. In the ARM 64 architecture (CPU architecture), there are 16 interrupt numbers, from 0 to 15. In one exemplary embodiment, a first interaction request of a first operating system (which may correspond to the first system) can be transmitted to a second operating system through an inter-core communication interface, and the processing method includes at least one of the following:

[0108] transmitting a first preemption request, having an interrupt number equal to the first interrupt number, via an inter-core communication interface to a second operating system (which may correspond to the second system), wherein the first preemption request is used to preempt processing resources of the second operating system; The inter-core communication interface sends a resource release request having the second interrupt number to the second operating system, where the resource release request is used to request the second operating system to release the processing resources occupied by the first operating system.

[0109] In this embodiment, preemption and release of processing resources between different operating systems can be completed by inter-core interrupts, and different interrupt events can be defined to correspond to different resource interaction types and different interrupt events to different interrupt numbers, where the interrupt number assigned to a first interrupt event in which a first operating system requests preemption of a processing resource from a second operating system is the first interrupt number, and the interrupt number assigned to a second interrupt event in which the first operating system actively releases a processing resource to the second operating system is the second interrupt number. As an optional embodiment, the first interaction request may be a first preemption request, i.e., a request used to request preemption of processing resources of a second operating system, and the first operating system transmits the first preemption request with an interrupt number of the first interrupt number to the second operating system via the inter-core communication interface, i.e., the trigger source of the inter-core communication interrupt with the interrupt number of the first interrupt number is the first operating system and the response source is the second operating system, and the meaning of this inter-core communication interrupt is that the first operating system preempts processing resources of the second operating system.

[0110] As another alternative embodiment, the first interaction request may be a resource release request, i.e., used to request the second operating system to release processing resources occupied by the first operating system, and the first operating system can send a resource release request with an interrupt number of the second interrupt number to the second operating system via the inter-core communication interface, i.e., the trigger source of the inter-core communication interrupt with the interrupt number of the second interrupt number is the first operating system and the response source is the second operating system, and the meaning of this inter-core communication interrupt is that the first operating system actively releases processing resources to the second operating system.

[0111] According to this embodiment, by assigning interrupt numbers for preemption and active release of processing resources between different operating systems, resource scheduling between operating systems is performed using the inter-core communication interrupt method, thereby improving the accuracy of resource scheduling. In one exemplary embodiment, transmitting the second interaction request of the second operating system to the first operating system over the inter-core communication interface includes: and transmitting a second preemption request for a third interrupt number to the second operating system via the inter-core communication interface, wherein the second preemption request is used to request preemption of processing resources of the first operating system.

[0112] In this embodiment, similar to the previous embodiment, preemption and release of processing resources between different operating systems can be completed by inter-core interrupts, and it can be defined that different interrupt events correspond to different resource interaction types and different interrupt events correspond to different interrupt numbers, where the interrupt number assigned to the third interrupt event in which the second operating system requests the first operating system to preempt the processing resources is the third interrupt number.

[0113] Optionally, the second interaction request may be a second preemption request, i.e., a request used to request preemption of processing resources of the first operating system, and the second operating system may transmit a second preemption request with an interrupt number of a third interrupt number to the first operating system via the inter-core communication interface, i.e., the trigger source of the inter-core communication interrupt with the interrupt number of the third interrupt number is the second operating system and the response source is the first operating system, and the meaning of this inter-core communication interrupt is that the second operating system preempts processing resources of the first operating system.

[0114] According to this embodiment, by assigning an interrupt number for preemption of processing resources between different operating systems, resource scheduling between operating systems is performed using an inter-core communication interrupt method, thereby improving the accuracy of resource scheduling. In one exemplary embodiment, the inter-core communication interface can obtain a second interaction response returned by the first operating system in response to the second interaction request, the second interaction response including at least one of the following:

[0115] sending a resource release permission response having an interrupt number of a fourth interrupt number to the second operating system via the inter-core communication interface, wherein the resource release permission response is used to instruct the first operating system to allow the second operating system to preempt processing resources of the first operating system; A resource release denial response having an interrupt number of the fifth interrupt number is sent to the second operating system via the inter-core communication interface, where the resource release denial response is used to instruct the first operating system to deny the second operating system from preempting the processing resources of the first operating system.

[0116] In this embodiment, similar to the previous embodiment, preemption and release of processing resources between different operating systems can be completed by inter-core interrupts, and it can be defined that different interrupt events correspond to different resource interaction types and different interrupt events correspond to different interrupt numbers, where the interrupt number assigned to the fourth interrupt event and the fifth interrupt event, in which the second operating system requests the first operating system to return a resource preemption response, is the fifth interrupt number, where the fourth interrupt event is an interrupt event that allows resource preemption, and the fifth interrupt event is an interrupt event that denies resource preemption.

[0117] As an optional embodiment, if the first operating system determines to allow the second operating system to occupy at least some of its processing resources, the first operating system can send a resource release permission response having an interrupt number of the fourth interrupt number to the second operating system via the inter-core communication interface, i.e., the trigger source of the inter-core communication interrupt having the interrupt number of the fourth interrupt number is the first operating system and the response source is the second operating system, and the meaning of this inter-core communication interrupt is that the first operating system passively releases the processing resources to the second operating system.

[0118] As another optional embodiment, if the first operating system determines that it refuses to allow the second operating system to occupy its processing resources, the first operating system can send a resource release refusal response having an interrupt number of the fifth interrupt number to the second operating system via the inter-core communication interface, i.e., the trigger source of the inter-core communication interrupt having the interrupt number of the fifth interrupt number is the first operating system and the response source is the second operating system, and the meaning of this inter-core communication interrupt is that the first operating system refuses to release the processing resources to the second operating system.

[0119] According to this embodiment, by allowing preemption of processing resources between different operating systems and assigning interrupt numbers used to deny preemption of processing resources, resource scheduling between operating systems is performed using an inter-core communication interrupt method, thereby improving the accuracy of resource scheduling. As an example, the following describes inter-core communication interrupts using an RTOS system and a Linux system. In a Linux system, inter-core communication can be achieved based on a custom interrupt vector table and interrupt events between different operating systems. The Linux operating system makes full use of SGI's undefined bit numbers to customize terminal signals and reduce the cost of inter-core communication. The undefined bit numbers can be numbers 8 to 15. In a multi-core heterogeneous operating system, to maximize compatibility with current resource allocation methods, the inter-core interrupt vector table is characterized using numbers 8 to 15 (a total of eight interrupts). Possible vector table allocation methods are shown in Table 2.

[0120] [Table 2]

[0121] Here, the first interrupt number corresponds to interrupt number 12, the second interrupt number corresponds to interrupt number 8, the third interrupt number corresponds to interrupt number 9, the fourth interrupt number corresponds to interrupt number 10, and the fifth interrupt number corresponds to interrupt number 11. As shown in Table 2, active release means that when the RTOS system has no traffic scheduling (i.e., is in idle state), it sends an SGI interrupt with interrupt number 8 to the Linux system, and the core resources of the RTOS are taken over by the Linux system, causing the RTOS system to enter sleep mode. Passive release means that when the traffic load on the Linux system increases suddenly, it sends an SGI interrupt with interrupt number 9 to the RTOS system, and if the RTOS system allows the processes it is running to be cut off (processes in the RTOS system have priorities, which can be arranged according to the actual situation, and the priorities can be set). If the interrupt level is higher than interrupt 9, it cannot be terminated, but if it is lower, it can be terminated). The RTOS system will send an SGI interrupt with interrupt number 10 to the Linux system, which will passively release the CPU core resources it occupies and allow the Linux system to schedule it. After that, the RTOS system will enter a sleep state. At this time, if the RTOS system does not allow it to be terminated, it will send an SGI interrupt with interrupt number 11 to the Linux system, which will notify the Linux system that the RTOS core resources cannot be released at this time. At this time, the Linux system will continue to run according to its current operating policy and will not change.

[0122] Note that the inter-core communication vector table is not unique and is not limited to the inter-core communication vector table limited to Table 2 above. Optionally, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize a completion code in the response data and data describing the state of a target device, and the target device is a device that generates the response data based on the hardware interface signals.

[0123] As shown in Table 3, Table 3 shows an example of a selectable data structure of response data (corresponding to the second data structure).

[0124] [Table 3]

[0125] Alternatively, Table 4 shows examples of the first and second requirements.

[0126] [Table 4]

[0127] In an alternative embodiment, after generating a hardware interface signal corresponding to the request command based on the logic bit information and the timer, the first system converts the voltage of the hardware interface signal to obtain a target hardware interface signal. Optionally, the first system can input a hardware interface signal to the voltage conversion device and obtain a target hardware interface signal output from the voltage conversion device.

[0128] Optionally, the voltage conversion device may be a CPLD (complex programmable logic device), and the CPLD may be connected to a target device, where the target device may be a CPU in a server. Taking the hardware interface signal as an example, where the chip is a BMC chip, FIG. 11 shows a hardware topology architecture diagram for simulating the generation of a PECI signal according to the present invention. As shown in FIG. 11, two software systems, a Linux system and an RTOS system (the two systems can run on different BMC cores), run on the BMC chip (corresponding to the BMC device in FIG. 11). Here, the Linux system is used to process BMC general management services and PECI services. The PECI service of the proposed method runs as an upper-layer application in the Linux system. When service data exchange is required (e.g., the BMC starts collecting fault register information), the Linux system interacts with the RTOS system, activates a GPIO port in the RTOS, and uses the RTOS system to simulate the PECI software module to generate a PECI signal.

[0129] It should be noted that the PECI signal sent from the BMC's GPIO port may not meet the electrical characteristics requirements of the PECI protocol. For example, the CPU's operating voltage is 5V, but the signal output from the BMC's GPIO port has a voltage of 3.3V. To simplify implementation, the present application may input the generated PECI signal to one GPIO port of the CPLD, and then use the CPLD's internal logic to perform voltage conversion. The converted PECI waveform meets the PECI protocol requirements and the voltage requirements of the target device (for example, the voltage of the converted PECI signal is 3.3V). Finally, the PECI signal is output from another GPIO of the CPLD, which is physically connected to the standard PECI interface on the CPU side.

[0130] It should be noted that the solution herein can be applied to generating PECI signals instead of the PECI interface, as well as other hardware interfaces, and in one alternative embodiment, Table 5 shows several types of hardware interfaces supported by embodiments of the present application.

[0131] [Table 5]

[0132] In an alternative embodiment, Figure 12 illustrates an interaction diagram between an alternative first system and a second system according to an embodiment of the present application. As shown in Figure 12, the specific steps of the interaction between the Linux system (corresponding to the second system) and the RTOS system (corresponding to the first system) are as follows:

[0133] In step 1, the Linux system, as the initiator and user of the request command, first stores the request data in the target memory before triggering the request command; In step 2, the Linux system triggers a first request to notify the RTOS system that the PECI request data is ready; In step 3, after receiving the first request, the RTOS system reads the request data from the target memory and generates a hardware interface signal based on the request data; In step 4, the RTOS system receives response data corresponding to the hardware interface signal; In step 5, the RTOS system stores the received response data in the target memory; In step 6, the RTOS triggers a second request to notify the Linux system that the response data is ready, In step 7, the Linux system retrieves and analyzes the response data from the target memory.

[0134] As can be seen from the above, the present application integrates a first system and a second system in an embedded system, realizes data exchange in the embedded system using inter-core interrupts and memory sharing, establishes a request command waveform generation functional module in an RTOS system, and realizes hardware interface signal communication between the embedded system and external devices using software simulation. Furthermore, the present application fully utilizes the high real-time characteristics of the RTOS system to ensure sequence accuracy when simulating request command waveforms, and is characterized by flexibility and efficiency. The solution of the present application significantly reduces the difficulty of chip design, and by generating hardware interface signals using software simulation, more possibilities are provided for optimizing the design between communication functions and other service functions in the embedded system. Furthermore, by eliminating the need for a controller specifically used to realize hardware interface signal communication on the chip, the design and manufacturing costs of the chip can be reduced.

[0135] In one alternative embodiment, the present application further provides a boot control process for an operating system, which includes the following steps: In step A, a first operating system running on a first processor core of a processor controls a hardware controller of the target device via a first bus to control the operating state of the target device.

[0136] For example, a server, a personal computer, an industrial computer, or other device may be provided with specific devices for performing operations related to the operation of the device. In the related art, these specific devices typically start operating when the system is powered on. After the system is powered on, an operating system running on a processor can only successfully take over and control the operating status of the specific devices after a certain period of time has elapsed. While the operating system is running, the specific devices are uncontrollable. For example, when the system is powered on, the fan starts running. After the system is powered on, the operating system running on the CPU must wait a certain period of time before it can properly take over the fan and set the fan speed. Therefore, the fan is uncontrollable while the operating system is booting.

[0137] For example, to achieve fan control while the operating system is booting, a server uses a control method that combines a BMC and a CPLD, a personal computer uses a control method using an EC chip (the EC chip has a function of adjusting the fan's rotation speed according to the temperature), and an industrial computer uses a control method using a custom chip.As a result, while the operating systems of the server, personal computer, and industrial computer are booting, the CPLD, EC chip, and custom chip are involved in controlling the fan's rotation speed, and once the operating system has fully started, control of the fan is handed over to the application program in the operating system for control.

[0138] In order to at least partially solve the above technical problems, a startup control method for a multi-core multi-system (e.g., a multi-core dual system) is used, which allows different operating systems of an embedded system to be run on different processor cores of a processor. When the response speeds of the different operating systems are different and the second operating system fails to start, restarts, or cannot control the operating state of a specific device, the operating state of the specific device can be controlled by a first operating system whose response speed is faster than that of the second operating system, thereby reducing the situation where the operating state of a specific device cannot be controlled. In addition, since there is no need to add extra costs, it also has good scalability.

[0139] In this embodiment, when the second operating system fails to start, reboots, or otherwise cannot control the operating state of a particular device, the first operating system can control the hardware controller of the target device via the first bus to control the operating state of the target device. The target device here may be a fan or other device that needs to operate when the system boots up. For a fan, the corresponding hardware controller is a fan controller, such as a PWM (Pulse Width Modulation) controller or a FanTach (fan rotation speed) controller. Using the first operating system (e.g., an RTOS system) instead of a conventional CPLD, EC chip, or custom chip can reduce hardware costs while providing high scalability by enabling device control through software.

[0140] For example, a dual system, an RTOS system, and a Linux system can be implemented based on a BMC dual core, and a fan can be implemented based on a multi-core dual system. By utilizing the high real-time characteristics of the RTOS system, the fan can be controlled by the RTOS system instead of the CPLD, EC chip, or custom chip while the Linux system is running. In other words, the fan control can be taken over and the operating state of the fan can be controlled at a sufficiently fast speed.

[0141] In step B, booting the second operating system on a second processor core of the processor. When the system is powered on or the second operating system is restarted, the second operating system can be booted to run on the second processor core of the processor, where booting the second operating system on the second processor core means scheduling the second processor core to the second operating system, and the system file or ISO file of the operating system may be stored in a memory on the chip where the processor is located or outside the chip, for example, in an external RAM (Random Access Memory).

[0142] In step C, after the second operating system is started, the second operating system takes over the hardware controller via the first bus and takes over control of the target device. After the second operating system has finished booting, the first operating system can always control the operating state of the target device. In consideration of the need for data exchange between multiple operating systems to run on a multi-core processor and the need to easily control the entire device using a single operating system, the second operating system may take over control of the target device. For example, the second operating system may take over the hardware controller via the first bus. The second operating system may take over control of the target device as follows: After the second operating system has started, the second operating system may send a device takeover request to the first operating system, for example, by sending an interrupt request via the second bus to request that the first operating system take over the hardware controller of the target device. The first operating system may receive the device takeover request from the second operating system and transfer control of the target device to the second operating system. Furthermore, the first operating system may perform an operation related to the takeover of control of the target device, for example, by stopping the execution of a service (process) for controlling the operating state of the target device.

[0143] For example, when the Linux system is fully booted, the RTOS system will hand over the fan control to the Linux system, which will then control the fan. The above process can also be performed after the system is powered on, i.e., using the boot method of a multi-core dual system, it is advantageous to start the RTOS system first and take part in fan control earlier; when the Linux system is fully booted, the RTOS system will hand over the fan control to the Linux system.

[0144] In one exemplary embodiment, before controlling a hardware controller of a target device via a first bus by a first operating system executed on a first processor core of the processor, the method further includes, after powering on a chip on which the processor is located, waking up the first processor core by the processor, and executing a boot loader program of the first operating system by the first processor core to boot the start of the first operating system on the first processor core.

[0145] The entire system may be divided into two stages, an initial startup stage and a real-time operation stage, depending on the operation period, and the startup control method in this embodiment may be performed in either the initial startup stage or the real-time operation stage. Regarding the initial startup stage, the initial startup stage begins with powering on the system, i.e., powering on the chip where the processor is located. When the system is powered on, one core is woken up to perform the boot operation of the operating system, and the remaining cores are temporarily in a sleep state, and the woken up core may be the first processor core.

[0146] Optionally, after being powered on, the system first executes one preset core scheduling policy (start-up boot policy), i.e., executes the core scheduling policy by one processor core of the processor, the core scheduling policy may be stored in RAM or Norflash (non-volatile flash memory) on the SOC, and the scheduling policy can be flexibly configured according to different design requirements, its main functions include specifying the initial processing resources (processor cores) that different operating systems need to run on and determining the boot process of heterogeneous operating systems, and powering on the chip may refer to powering on the SOC chip level.

[0147] After the first processor core is woken up, the boot loader program can boot the operation of the first operating system on the first processor core, i.e., the first processor core can boot the startup of the first operating system on the first processor core through the boot loader program. The boot loader program can be located in a computer or other computer application and refers to a program used to boot the loading of an operating system, for example, a specific program in a Boot ROM, which refers to code that boots the startup of an operating system and belongs to the Boot Loader program, and the Boot ROM is a small masked ROM (Read-Only Memory) or write-protected flash memory built into a processor chip on a CPU chip.

[0148] In the initial startup stage, if the boot loader boots the operating system on the corresponding processor core, the success rate of the operating system startup can be increased, and the system is prepared for the real-time operation stage. Although the above-described embodiments of the methods are described as a combination of a series of operations for ease of explanation, those skilled in the art will understand that the present application is not limited to the order of the operations described, and that some steps may be performed in other orders or simultaneously based on the present application. Next, those skilled in the art will understand that the embodiments described in the specification belong to preferred embodiments, and that such operations and modules are not necessarily required for the present application.

[0149] From the above description of the embodiments, it can be clearly understood by those skilled in the art that the methods according to the above embodiments can be realized by adding a required general-purpose hardware platform to software, and of course, they can also be realized by hardware, but the former is often a more preferred embodiment. Based on this understanding, the technical solution of the present application can be essentially embodied, or a part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium (e.g., ROM / RAM, magnetic disk, optical disk) and includes multiple instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0150] According to an embodiment of the present application, there is further provided a hardware interface signal generating device for implementing the above-mentioned hardware interface signal generating method, and as shown in FIG. 13, the hardware interface signal generating device includes an obtaining module 1301, a determining module 1302 and a generating module 1303. Optionally, the acquisition module 1301 is used to acquire a request command by the first system, the determination module 1302 is used to determine a plurality of logical bit information corresponding to the request command, and the generation module 1303 is used to generate a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer. In the hardware interface signal generating device provided in the embodiment of the present application, the generating module includes a first determining unit and a second generating unit, where the first determining unit is used to determine a reload value and a first match value corresponding to a timer according to a plurality of logical bit information, and the second generating unit is used to generate a hardware interface signal corresponding to a request command according to the reload value and the first match value. In the hardware interface signal generating device provided in the embodiment of the present application, the first determining unit further includes a first acquiring subunit, a first determining subunit, and a second determining subunit, wherein the first acquiring subunit is used to acquire an operation time corresponding to each logical bit information, the first determining subunit is used to determine a reload value according to the operation time, and the second determining subunit is used to determine a first match value corresponding to a timer according to a logical bit of each logical bit information, and obtain a plurality of first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0151] In the hardware interface signal generating device provided in the embodiment of the present application, the second generating unit further includes a first generating subunit, which is used to sequentially generate hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information according to the order of the multiple logical bit information corresponding to the request command, to obtain a hardware interface signal.

[0152] In the hardware interface signal generating device provided in the embodiment of the present application, the first generating sub-unit further includes a decrement sub-module, a first signal output sub-module, a second signal output sub-module, and a first determining sub-module, wherein the decrement sub-module is used for performing a decrement operation on a reload value corresponding to each logical bit information based on a timer, the first signal output sub-module is used for outputting a first signal corresponding to each logical bit information by the first system before the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where the first signal is a high-level signal, and the second signal output sub-module is used for outputting a second signal corresponding to each logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where Second signal is a low-level signal, and the first determination sub-module is used to determine the generation of a hardware interface sub-signal corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to 0, and to obtain a hardware interface sub-signal corresponding to each logical bit information, where the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information.

[0153] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes a first interrupt trigger module and a second interrupt trigger module, wherein the first interrupt trigger module is used to trigger a first interrupt corresponding to each logical bit information when a reload value corresponding to the logical bit information is decremented to a first match value corresponding to the logical bit information, and the second interrupt trigger module is used to trigger a second interrupt corresponding to the logical bit information when a reload value corresponding to the logical bit information is decremented to 0.

[0154] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes an interrupt counting module and a field determining module, where the interrupt counting module is used to perform an interrupt count once every time a first interrupt or a second interrupt is triggered, and the field determining module is used to determine a field in the request command that is currently undergoing signal conversion processing according to the interrupt count, where the signal conversion processing is used to generate hardware interface sub-signals corresponding to logical bit information corresponding to each field in the request command.

[0155] In the hardware interface signal generating device provided in the embodiment of the present application, the field determination module further includes a second obtaining unit, a second determining unit, a third determining unit, and a fourth determining unit, wherein the second obtaining unit is used to obtain the number of bytes corresponding to each field in the request command, the second determining unit is used to determine the number of logical bit information corresponding to the request command according to the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information, the third determining unit is used to determine the number of interrupts corresponding to the request command according to the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information, and the fourth determining unit is used to determine the field in the request command that is currently performing signal conversion processing according to the number of interrupts and the interrupt count.

[0156] In the hardware interface signal generating device provided in the embodiment of the present application, the fourth determining unit further includes a third determining sub-unit, a fourth determining sub-unit, and a fifth determining sub-unit, wherein the third determining sub-unit is used to determine logical bit information currently being converted into a hardware interface sub-signal according to the interrupt number and the interrupt count, the fourth determining sub-unit is used to determine a byte corresponding to the logical bit information currently being converted into a hardware interface sub-signal as a target byte, and the fifth determining sub-unit is used to determine a field corresponding to the target byte as a field currently undergoing signal conversion processing in a request command.

[0157] In the hardware interface signal generating device provided in the embodiment of the present application, the data structure of the request data corresponding to the request command is a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code and request parameters, the device address is used to characterize the address of the target device, the target device is a device that generates response data based on the hardware interface signal, the instruction code is used to distinguish different request commands, the write length is used to characterize the number of bytes from the instruction code to the request data, the read length is used to characterize the number of bytes including the completion code and read data in the request data, and the request parameters are used to characterize the parameters of the request command.

[0158] In the hardware interface signal generating device provided in the embodiment of the present application, the acquisition module further includes a request data acquisition unit and a request data analysis unit, where the request data acquisition unit is used to acquire request data when a first request triggered by a second system is detected by the first system, where the first system and the second system run on the same processor, the request data is generated by the second system, and the service response speed of the second system is lower than that of the first system, and the request data analysis unit is used to analyze the request data and obtain the request command.

[0159] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes a request data storage module used by a second system to store request data in a target memory, and to trigger a first request by the second system after the storage of the request data is completed, where the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0160] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes a voltage conversion module used to convert the voltage of the hardware interface signal to obtain a target hardware interface signal. In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes a signal input unit used to input the hardware interface signal to the voltage conversion device and obtain a target hardware interface signal output from the voltage conversion device.

[0161] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes a response data receiving module and a data structure adjusting module, where the response data receiving module is used to receive response data corresponding to the hardware interface signal from a first system, where the transmission format of the response data is the same as the transmission format of the hardware interface signal, and the data structure adjusting module is used to adjust the data structure of the response data to a second data structure.

[0162] In the hardware interface signal generating device provided in the embodiment of the present application, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, wherein the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, the response valid data is used to characterize the completion code in the response data and data for describing the status of the target device, and the target device is a device that generates the response data based on the hardware interface signal.

[0163] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal generating device further includes a second request trigger module used to trigger a second request by the first system, where the second request is used to notify the second system to read the response data.

[0164] In the hardware interface signal generating device provided in the embodiment of the present application, the hardware interface signal is any one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal. An embodiment of the present application further provides a computer-readable storage medium, which can optionally be used to store program code executed by the provided method for generating a hardware interface signal.

[0165] Optionally, in this embodiment, the storage medium can be located in any one of a group of computer terminals in a computer network, or in any one of a group of mobile terminals. An embodiment of the present application further provides an electronic device including: a storage device in which a computer program is stored; and a processor configured to execute the computer program to perform the method for generating a hardware interface signal provided above.

[0166] An embodiment of the present application may provide a computer terminal, which may be any computer terminal device in a group of computer terminals. Optionally, in this embodiment, the computer terminal may be replaced by a terminal device such as a mobile terminal. Optionally, in this embodiment, the computer terminal can be located on at least one network device of a plurality of network devices of a computer network.

[0167] In this embodiment, the computer terminal can execute program codes for the method for generating a hardware interface signal, including the steps of obtaining a request command by a first system, determining a plurality of logical bit information corresponding to the request command, and generating a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer.

[0168] The computer terminal can execute program code for a method for generating a hardware interface signal, the program code including the steps of determining a reload value and a first match value corresponding to a timer based on a plurality of logical bit information, and generating a hardware interface signal corresponding to a request command based on the reload value and the first match value. The computer terminal can execute program codes for the method for generating a hardware interface signal, including the steps of obtaining an operation time corresponding to each logical bit information, determining a reload value based on the operation time, and determining one first match value corresponding to a timer based on the logical bit of each logical bit information, and obtaining multiple first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0169] The computer terminal can execute a program code for a step in the method for generating a hardware interface signal, in which the hardware interface sub-signals corresponding to each logical bit information are sequentially generated based on a reload value and a first match value corresponding to each logical bit information according to a forward / backward order among a plurality of logical bit information corresponding to a request command, to obtain a hardware interface signal.

[0170] The computer terminal includes a method for generating a hardware interface signal, the method including: a step of performing a decrement operation on a reload value corresponding to each logical bit information based on a timer; a step of outputting a first signal corresponding to each logical bit information by a first system before the reload value corresponding to each logical bit information is decremented to a first match value corresponding to the logical bit information, the first signal being a high level signal; and a step of outputting a second signal corresponding to the logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to a first match value corresponding to the logical bit information, Second signal is a low-level signal; and when the reload value corresponding to each logical bit information is decremented to 0, determining to generate a hardware interface sub-signal corresponding to the logical bit information, and obtaining a hardware interface sub-signal corresponding to each logical bit information, wherein the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information.

[0171] The computer terminal can execute program code for the method for generating a hardware interface signal, including the steps of: triggering a first interrupt corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to the first match value corresponding to the logical bit information; and triggering a second interrupt corresponding to the logical bit information when the reload value corresponding to the logical bit information is decremented to 0.

[0172] The computer terminal can execute program codes for the hardware interface signal generating method, including the steps of: performing an interrupt count once each time a first interrupt or a second interrupt is triggered in the process of sequentially generating hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information; and determining, based on the interrupt count, a field in the request command that is currently undergoing signal conversion processing, where the signal conversion processing is used to generate hardware interface sub-signals corresponding to the logical bit information corresponding to each field in the request command.

[0173] The computer terminal can execute program codes for a method for generating a hardware interface signal, including the steps of: obtaining the number of bytes corresponding to each field in a request command; determining the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information; determining the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information; and determining the field in the request command currently performing signal conversion processing based on the number of interrupts and the interrupt count.

[0174] The computer terminal can execute program codes for the hardware interface signal generating method, including the steps of: determining logical bit information currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count; determining a byte corresponding to the logical bit information currently being converted into the hardware interface sub-signal as a target byte; and determining a field corresponding to the target byte as a field currently undergoing signal conversion processing in a request command.

[0175] Furthermore, the data structure of the request data corresponding to the request command is a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters, where the device address is used to characterize the address of the target device, the target device is a device that generates response data based on a hardware interface signal, the instruction code is used to distinguish different request commands, the write length is used to characterize the number of bytes from the instruction code to the request data, the read length is used to characterize the number of bytes including the completion code and read data in the request data, and the request parameters are used to characterize the parameters of the request command.

[0176] The computer terminal can execute program code for the following steps in the method for generating a hardware interface signal: when a first system detects a first request triggered by a second system, acquiring request data, where the first system and the second system run on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system; and analyzing the request data to obtain a request command.

[0177] The computer terminal can execute program code for the steps of the method for generating a hardware interface signal, in which the second system stores the requested data in a target memory before acquiring the requested data, and the second system triggers a first request after the storage of the requested data is completed, the first request being used to notify the first system to read the requested data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0178] The computer terminal can execute a program code for the method for generating a hardware interface signal, the program code including: generating a hardware interface signal corresponding to a request command based on logic bit information and a timer; and converting the voltage of the hardware interface signal to obtain a target hardware interface signal. The computer terminal can execute program code for the steps of inputting a hardware interface signal to a voltage conversion device and obtaining a target hardware interface signal output from the voltage conversion device in the method for generating a hardware interface signal.

[0179] The computer terminal can execute program codes for the method for generating a hardware interface signal, including: generating a hardware interface signal corresponding to a request command based on logic bit information and a timer; receiving response data corresponding to the hardware interface signal from a first system, where the transmission format of the response data is the same as the transmission format of the hardware interface signal; and adjusting the data structure of the response data to a second data structure.

[0180] Optionally, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize a completion code in the response data and data describing the state of a target device, and the target device is a device that generates the response data based on the hardware interface signals.

[0181] The computer terminal can execute program code for a step of, in the method for generating a hardware interface signal, triggering a second request by the first system after adjusting the data structure of the response data to a second data structure, where the second request is used to notify the second system to read the response data.

[0182] The hardware interface signal is one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal. Optionally, Figure 14 is a block diagram of the structure of a computer terminal according to an embodiment of the present application. As shown in Figure 14, the computer terminal 10 may include one or more (only one is shown in Figure 14) processors 102 and storage 104. The computer terminal 10 may further include a storage controller, which controls and manages the storage 104, and the computer terminal 10 may further include an external interface, which is connected to a radio frequency module, an audio module, a display screen, etc.

[0183] Here, the storage can be used to store software programs and modules, such as program instructions / modules corresponding to the hardware interface signal generation method and device in the embodiments of the present application. The processor executes the software programs and modules stored in the storage to perform various functional applications and data processing, i.e., to realize the hardware interface signal generation method. The storage can include high-speed random memory and can also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the storage can also include storage devices located remotely from the processor, which can be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the Internet, a corporate intranet, a local area network, a mobile communication network, and combinations thereof.

[0184] The processor can execute the following steps: calling information and an application program stored in storage by the transmission device, and detecting whether a serial port switching command is received by a first system in a first processor core, the serial port switching command having information to switch to a target serial port; when the serial port switching command is received, sending the serial port switching command by the first system to a second system in a second processor core, the service response speed of the second system being slower than the service response speed of the first system; and executing serial port switching by the second system in accordance with the serial port switching command.

[0185] As will be understood by those skilled in the art, the structure shown in Fig. 14 is merely schematic, and the computer terminal may be a terminal device such as a smartphone (e.g., an Android mobile phone, an iOS mobile phone, etc.), a tablet computer, a palmtop computer, a mobile Internet device (MID), a PAD, etc. Fig. 14 does not limit the structure of the electronic device. For example, the computer terminal 10 may include more or fewer components (e.g., a network interface, a display device, etc.) than those shown in Fig. 14, or may have components arranged differently from those shown in Fig. 14.

[0186] An embodiment of the present application further provides an embedded system, and as shown in FIG. 15 , the embedded system may include a chip and at least two operating systems, where the chip includes a processor 1502, a hardware controller 1504, a first bus 1506, and a second bus 1508, where the bandwidth of the first bus 1506 is higher than the bandwidth of the second bus 1508, and the first bus 1506 is arranged in a multi-master multi-slave mode, and the second bus 1508 is arranged in a single-master multi-slave mode, and the at least two operating systems operate based on the processor 1502, and the at least two operating systems communicate via the first bus 1506, and the at least two operating systems realize control over the hardware controller via the second bus 1508.

[0187] Here, the chip may be a BMC chip, the processor may be a multi-core processor, the hardware controller may be used to control an external device connected to a corresponding external interface, the first bus may be configured in a multi-master multi-slave mode and may be a bus used for communication between multiple processor cores of the processor, such as an AHB (Advanced High Performance Bus), the second bus may be configured in a single-master multi-slave mode and may be a bus used for control between the hardware controllers by the processor, such as an APB (Advanced Peripheral Bus), and the bandwidth of the first bus is higher than the bandwidth of the second bus.

[0188] The embedded system may include at least two operating systems, the at least two operating systems operating on a processor, processing resources of the processor being dynamically allocated to the at least two operating systems, the processing resources of the processor including a processor core, the at least two operating systems communicating via a first bus, and the at least two operating systems realizing control over a hardware controller by a second bus.

[0189] Optionally, the hardware controller may include one or more types, including, but not limited to, a controller corresponding to at least one chip peripheral among I2C, USB (Universal Serial Bus), UART, ADC (Analog to Digital Converter), JTAG (Joint Test Action Group), RTC (Real Time Clock), GPIO (General Purpose Input / Output), WDT (Watch Dog Timer), Virtual UART, Super I / O, SGPIO (Serial General Purpose Input / Output), PWM (Pulse Width Modulation), FanTach (Fan Speed ​​Adjustment), Timer, PECI (Platform Environment Control Interface), and MailBox, and may also include other types of controllers. The external interface may include one or more types, including but not limited to an external interface corresponding to any of the above controllers.

[0190] The first bus mentioned above is configured in a multi-master / multi-slave mode and may be a bus used for communication between multiple processor cores of a processor, such as an AHB (Advanced High Performance Bus), while the second bus is configured in a single-master / multi-slave mode and may be a bus used for control between hardware controllers by a processor, such as an APB (Advanced Peripheral Bus), and the bandwidth of the first bus is higher than that of the second bus. This will be explained below. The first bus has already been defined in AMBA2, and is initially used mainly as a system high-speed bus and is applied to high-performance, low-power system designs, mainly used for connecting high-performance modules (e.g., CPU, DMA, DSP, etc.) and is used as a system-on-chip bus for SoCs. In the AMBA protocol, AHB is primarily intended for system-level, high-bandwidth, high-performance system interconnect design. Its features include single-clock-edge operation, non-tristate implementation, support for burst transfers, support for hierarchical transfers, interconnection modes supporting multi-master and multi-slave, configurable bus widths from 32 bits to 128 bits, and support for byte, nibble, and word transfers. The AHB system consists of three parts: master modules, slave modules, and infrastructure. All transfers across the primary bus are initiated by the master module, and responded to by the slave modules. The infrastructure consists of an arbiter, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a dummy slave module, and a dummy master module.

[0191] APB is primarily used for connecting low-bandwidth peripherals, such as UART and 1284. Its bus architecture differs from AHB, which supports multiple master modules; the only master module in APB is the APB bridge. Its features include:

[0192] (1) It can operate at high frequencies, (2) It is a simple protocol, without complicated sequences. (3) It is a synchronous bus, meaning that all transactions on the bus (read and write operations) depend on the rising edge of the clock. (4) Single-master multi-slave. Generally, the APB is connected to a first bus system and transfers transactions between the first bus system via the AHB-APB Bridge. At this time, the Bridge is the master of the APB, and all other peripheral devices are slaves. (5) It has a simple interface, which is relatively simple compared to AXI and AHB. (6) Low power consumption (7) Can connect to multiple types of peripheral devices such as I2C, SPI, Timer, Keypad, and UART.

[0193] In one possible embodiment, in the multi-master multi-slave mode of the AHB, the master first sends a message transmission request to the arbiter, the arbiter determines the appropriate authority for the master to obtain bus access, and after obtaining the authority, the master sends data and control signals to the arbiter, which determines the corresponding slave path by address analysis and then sends the request to the corresponding destination. Similarly, the response data is analyzed by the decoder and then returned to the corresponding master. This multiplexing mechanism realizes multiple-to-multiple access.

[0194] In one alternative embodiment, in the single-master multi-slave mode of the APB, the APB is generally connected to a first bus system and transfers transactions between the first bus system via the AHB-APB Bridge, where the Bridge is the master of the APB and all other peripherals are slaves. Data requests are sent from the master to the slave, and the slave sends corresponding response data back to the master after receiving the request. This process can realize one-to-many access, and the access does not involve the arbiter and decoder analysis operations on the first bus.

[0195] The first bus also has high bandwidth characteristics and is used for interconnecting high-performance modules (such as CPUs and DMAs) in a system, while the APB bus has a relatively low bandwidth and is used for connecting peripheral devices (such as UARTs and I2Cs) in a system. The first bus logic circuit and bus protocol are complex, while the bus interface circuit and bus protocol are relatively simple.

[0196] Optionally, in the case where the RTOS occupies CPU resources when it wakes up from sleep, the RTOS does not completely occupy CPU resources after going to sleep, and when it wakes up (for example, an interrupt occurs in a peripheral or a wake-up timer, triggering a wake-up operation), it regains control of core 0 via an inter-core interrupt. During the period from the sleep state to regaining core control, the RTOS system does not require the participation of any cores.

[0197] In this embodiment, an embedded system is provided to realize the generation of a hardware interface signal. Two operating systems included in the embedded system may be a first system and a second system. In this embodiment, the first system is used to receive a request command, determine a plurality of logical bit information corresponding to the request command, and generate a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer.

[0198] Optionally, the first system is used to determine a reload value and a first match value corresponding to the timer based on the plurality of logical bit information, and the second system is used to generate a hardware interface signal corresponding to the request command based on the reload value and the first match value. Selectably, the first system is used to obtain an operation time corresponding to each logical bit information, the first system is used to determine a reload value based on the operation time, the first system is used to determine one first match value corresponding to a timer based on a logical bit of each logical bit information, and obtain multiple first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0199] Optionally, the first system is used to sequentially generate hardware interface sub-signals corresponding to each logical bit information based on a reload value and a first match value corresponding to each logical bit information according to a forward / backward order among the plurality of logical bit information corresponding to the request command, to obtain a hardware interface signal. Optionally, the first system is used to perform a decrement operation on a reload value corresponding to each logical bit information based on a timer, and the first system is used to output a first signal corresponding to each logical bit information by the first system before the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where the first signal is a high-level signal, and the first system is used to output a second signal corresponding to each logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, where the second signal is a low-level signal, and the first system is used to determine the generation of a hardware interface sub-signal corresponding to each logical bit information when the reload value corresponding to each logical bit information is decremented to 0, and to obtain a hardware interface sub-signal corresponding to each logical bit information, where the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0200] Selectably, the first system is used to trigger a first interrupt corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to a first match value corresponding to the logical bit information, and the first system is used to trigger a second interrupt corresponding to each logical bit information when the reload value corresponding to the logical bit information is decremented to 0.

[0201] Optionally, the first system is used to perform an interrupt count once each time one first interrupt or one second interrupt is triggered, and the first system is used to determine a field in the request command that is currently undergoing signal conversion processing based on the interrupt count, where the signal conversion processing is used to generate a hardware interface sub-signal corresponding to logical bit information corresponding to each field in the request command.

[0202] Optionally, the first system is used to obtain the number of bytes corresponding to each field in the request command, the first system is used to determine the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information, the first system is used to determine the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information, and the first system is used to determine the field in the request command that is currently performing signal conversion processing based on the number of interrupts and the interrupt count.

[0203] Optionally, the first system is used to determine logical bit information currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count, the first system is used to determine a byte corresponding to the logical bit information currently being converted into a hardware interface sub-signal as a target byte, and the first system is used to determine a field corresponding to the target byte as a field currently undergoing signal conversion processing in the request command.

[0204] Optionally, the data structure of the request data corresponding to the request command is a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code and request parameters, where the device address is used to characterize the address of the target device, the target device is a device that generates response data based on a hardware interface signal, the instruction code is used to distinguish different request commands, the write length is used to characterize the number of bytes from the instruction code to the request data, the read length is used to characterize the number of bytes including the completion code and read data in the request data, and the request parameters are used to characterize the parameters of the request command.

[0205] Optionally, the embedded system further includes a second system, wherein the second system and the first system both run on a processor, the second system is used to generate request data, and the first system is used to obtain the request data when detecting a first request triggered by the second system, wherein the service response speed of the second system is lower than the service response speed of the first system, and the first system is used to analyze the request data and obtain the request command.

[0206] Optionally, the second system is used to store the requested data in a target memory, and after completing the storage of the requested data, trigger the first request, where the first request is used to notify the first system to read the requested data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0207] Optionally, the first system is used to convert the voltage of the hardware interface signal to obtain the target hardware interface signal. Optionally, the first system is used to input a hardware interface signal to a voltage conversion device and obtain a target hardware interface signal output from the voltage conversion device.

[0208] Optionally, the first system is used to receive response data corresponding to the hardware interface signal, where the transmission format of the response data is the same as the transmission format of the hardware interface signal, and the first system is used to adjust the data structure of the response data to a second data structure. Optionally, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize a completion code in the response data and data describing the state of a target device, and the target device is a device that generates the response data based on the hardware interface signals.

[0209] Optionally, the first system is used to trigger a second request, where the second request is used to notify the second system to read the response data. Optionally, the hardware interface signal is one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal.

[0210] In an optional embodiment, the above-mentioned first system and second system can each operate on different processor cores of a processor, and therefore, the communication between the first system and the second system is an inter-core communication method, and an inter-core communication method is provided as shown in FIG. 16, which is realized by the embedded system of the above-mentioned embodiment, where the first operating system in FIG. 16 may correspond to the above-mentioned first system, and the second operating system may correspond to the above-mentioned second system, and includes the following steps S1602 to S1606.

[0211] In step S1602, the first operating system sends target data to a target virtual channel in a processor memory, where the first operating system and the second operating system run on the processor. Specifically, the first operating system and the second operating system may be real-time operating systems or non-real-time operating systems, the first operating system and the second operating system may be single-core operating systems or multi-core operating systems, the target data is data to be transmitted, the target virtual channel is free storage space in memory, and the first operating system transmitting the target data to the target virtual channel in the processor memory refers to the CPU core of the first operating system writing the data to be transmitted to the target virtual channel.

[0212] In step S1604, an interrupt notification message is sent to the second operating system. Specifically, a CPU core of a first operating system sends an interrupt notification message to a CPU core of a second operating system, and the interrupt notification message may have an address of a target virtual channel and is used to notify the second operating system to obtain target data from the target virtual channel, and the interrupt notification message may be a software trigger or a hardware trigger.

[0213] In step S1606, the second operating system responds to the interrupt notification message and obtains the target data from the target virtual channel in memory. Specifically, the CPU core of the second operating system responds to the interrupt notification message, analyzes the address of the target virtual channel from the interrupt notification message, locates the target virtual channel in memory based on the analyzed address, obtains target data from the target virtual channel, and realizes data exchange between the first operating system and the second operating system.

[0214] Through the above steps, when multiple operating systems running on a processor need to transmit data to each other, the first operating system sending the data sends the target data to a target virtual channel in the processor memory and sends an interrupt notification message to the second operating system, and the second operating system receiving the data responds to the interrupt notification message and obtains the target data from the target virtual channel, thereby solving the problems of resource waste and high dependency on operating systems in the inter-core communication process and achieving the effects of reducing resource waste and dependency on operating systems in the inter-core communication process.

[0215] Moreover, FIG. 17 is a flowchart 1 of an optional communication method according to an embodiment of the present application, specifically, as shown in FIG. 17, the process is a process in which a non-real-time operating system sends data to a real-time operating system. First, the application layer of the non-real-time operating system fills the data to be sent in the corresponding format, and then creates a device file ipidev in the system's / dev path. When the application layer needs to read or write data from the driving layer, it first uses the open function provided by the system to turn on the device / dev / ipidev, and then uses the write function to send the data to be sent from the application layer of the non-real-time operating system to the driving layer. The driving layer of the non-real-time operating system puts the data into shared memory, and then triggers a soft interrupt to notify the real-time operating system of another core to read the data.

[0216] Specifically, the shared memory area is divided into multiple memory channels, each corresponding to a channel structure (IpiHeader), and the structure data is used to record relevant information about the memory channel. The non-real-time operating system's driving layer first uses the GetEmptyChannel interface based on the size of the data to be sent to find a memory channel that satisfies two conditions: first, the empty flag Flag in the channel structure IpiHeader is not equal to 0xA5A5A5A5; and second, the channel size ChannelSize in the channel structure IpiHeader is greater than the size of the data to be sent. After finding a free channel that meets the requirements, it sets the channel as not empty, i.e., sets the empty flag in the channel structure IpiHeader to 0xA5A5A5A5, copies the data to be sent to the free channel, and then triggers a soft interrupt to notify the real-time operating system of another core.

[0217] In one exemplary embodiment, the real-time operating system receives an interrupt and triggers a corresponding interrupt handling function, which then sends a task notification to wake up the corresponding task, which then reads and analyzes data from the shared memory. Specifically, the task first uses the GetNoEmptyChannel interface to find all channels that meet three conditions: the empty flag in the channel structure IpiHeader is equal to 0xA5A5A5A5; the TargetId in the channel structure is equal to the ID of the current CPU; and the TargetId in the channel structure is not equal to the SrcId. After finding a non-empty channel that meets the requirements, the task analyzes the data of the non-empty channel and completes specific functions based on the NetFn and Cmd in the channel structure IpiHeader. Finally, the task marks the channel as empty, i.e., sets the empty flag in the channel structure to 0.

[0218] FIG. 18 is a flowchart 2 of an optional communication method according to an embodiment of the present application, specifically, the process in which a real-time operating system sends data to a non-real-time operating system, as shown in FIG. First, if the real-time operating system has data to send, it finds an available channel in the shared sub-memory. If an available channel is found, it sets this channel as available and copies the data to be sent to the available channel. It then generates a soft interrupt to notify the non-real-time operating system. The non-real-time operating system then calls a corresponding interrupt handling function. The interrupt handling function scans the IpiHeader structure of all channels and determines which application layer program to send the signal to based on the NetFn and Cmd fields in the structure, and sends the corresponding channel ID to the application program. Note that when the system is initialized, the application layer program for inter-core communication must register the NetFn, Cmd, and PID corresponding to the application layer program in the driver. After receiving the signal, the application layer calls the corresponding processing function, turns on the device / dev / ipidev, and reads the data. The driver finds the corresponding data in the shared memory based on the channel ID, returns the data and data length to the application layer, and sets this channel as available, i.e., sets the available flag in the channel structure to 0.

[0219] This embodiment of the present invention provides a method for inter-core communication in a multi-core multi-operating system. The physical layer uses a shared memory approach for data exchange, and a virtual channel is added to manage the shared memory. When a sending CPU core places data to be transmitted in the shared memory in a specified protocol format, a soft interrupt is triggered to notify the receiving CPU core that the data has been read. The data is then analyzed in the specified protocol format. After reading the data, the receiving CPU core can choose whether to send a response to the sending CPU core or not. Inter-core communication is achieved using shared memory and soft interrupts. The virtual channel management method and virtual channel structure format are used. No additional components are required, simplifying development and saving system resources. Furthermore, only general-purpose functions such as operating system tasks and signaling are used, significantly reducing dependency on the operating system.

[0220] From the above description of the embodiments, it can be clearly understood by those skilled in the art that the method according to the above embodiment can be realized by adding a required general-purpose hardware platform to software, and of course, it can also be realized by hardware, but the former is often a more preferred embodiment. Based on this understanding, the technical solution of the present application can be essentially embodied in the form of a software product, or a part that contributes to the prior art, and the computer software product can be stored in a storage medium (e.g., ROM / RAM, magnetic disk, optical disk), It includes a plurality of instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a network device, etc.) to execute the method of each embodiment of the present application.

[0221] To achieve the above object, according to another aspect of the present application, there is further provided a chip including at least one of a programmable logic circuit and executable instructions, the chip operating in an electronic device and used to perform the steps of any of the above method embodiments. An embodiment of the present application further provides a BMC chip, where the BMC chip includes a storage unit and a processing unit connected to the storage unit, the storage unit is used to store a program, and the processing unit is used to execute the program to perform the steps of any of the above method embodiments.

[0222] For example, an example of a BMC chip may be as shown in FIG. 19, and the hardware of the BMC chip may include, but is not limited to, a SOC sub-module and a BMC out-band sub-module. The SOC sub-module mainly includes an ARM core (ARM Core 1, ARM Core 2, ARM Core X), which may include, but is not limited to, a DDR (Double Data Rate)4 controller (memory controller), a MAC (Media Access Control Address) controller (network controller), an SD (Secure Digital) Card / eMMC (Embedded Multi Media Card) controller (storage controller), a PCIe RC (Root Complex) controller, an SRAM (Static Random-Access Memory) and an SPI controller.

[0223] The cores and each controller are connected to each other via a first bus, realizing interactions between the cores and each controller. The ARM cores are connected to the first bus (for example, they may be connected via an AXI (Advanced eXtensible Interface) bridge), and inter-core communication is realized by the first bus. The SOC submodule also realizes interconnection between the first bus and the second bus (for example, by converting an APB bridge), thus providing a physical channel for the SOC submodule to access peripheral devices on the second bus.

[0224] The DDR4 controller can be connected to other components or devices via a DDR4 PHY (Physical Layer) interface, the MAC controller is connected to other components or devices via an RGMII (Reduced Gigabit Media Independent Interface), the SD card eMMC controller is connected to other components or devices via an SD interface, and the PCIe RC controller is connected to other components or devices via a PCIe PHY interface.

[0225] The BMC out-of-band sub-module mainly includes controllers corresponding to chip peripherals such as PWM, GPIO, FanTech (fan speed adjustment), mailbox, etc. These controllers can realize out-of-band management functions such as PECI communication with the BMC (for example, PECI is simulated using GPIO), fan adjustment control, etc. As can be seen from Figure 19, the BMC out-of-band sub-module can realize interaction with the SOC sub-module through a second bus, but is not limited to this.

[0226] The BMC chip uses the AHB and second bus to interconnect the ARM cores, memory units, and controller hardware resources within the chip. Dynamic processor resource equalization scheduling primarily refers to the scheduling of ARM core resources on the BMC chip, and inter-core communication refers to communication between ARM cores. For example, suppose a Linux system preempts an RTOS system core. The Linux system first sends an inter-core interrupt (interrupt number 9) from one of cores 2 through N to core 1 via the first bus on the chip. If the RTOS system is idle and allows preemption, core 1 will respond with an inter-core interrupt (interrupt number 10) via the first bus, releasing the external controller resources (e.g., PWM / PECI) currently mapped to core 1. The Linux system then receives inter-core interrupt 10 and initiates the preemption process, adding core 1 to the Linux SMP scheduling and taking control of the PWM / PECI peripherals, which it can then control via the second bus.

[0227] On the one hand, the at least two operating systems include a first operating system and a second operating system, wherein the chip loads a communication value to a first bus, and the first bus sends a communication signal having the communication value to a communication register corresponding to the second operating system to realize communication between the first operating system and the second operating system, wherein the communication value is used to indicate the communication content between the first operating system and the second operating system.

[0228] On the other hand, the chip loads the control value to the second bus, and the second bus sends a control signal having the control value to a register corresponding to the hardware controller to realize the control of the hardware controller by the operating system, where the control value is used to instruct the control content of the hardware controller by the operating system.

[0229] The first bus mentioned above is configured in a multi-master multi-slave mode and may be a bus used for communication between multiple processor cores of a processor, such as an AHB (Advanced High Performance Bus), and the second bus is configured in a single-master multi-slave mode and may be a bus used for control between hardware controllers by a processor, such as an APB (Advanced Peripheral Bus), and the bandwidth of the first bus is higher than the bandwidth of the second bus. This will be described below.

[0230] The AHB bus has already been defined in AMBA2. The AHB bus was initially used mainly as a system high-speed bus, and was applied to high-performance, low-power system designs. It was mainly used to connect high-performance modules (such as CPU, DMA, and DSP) and was used as a system-on-chip bus for SoCs. In the AMBA protocol, AHB is primarily aimed at system-level high-bandwidth, high-performance system interconnect design, with several features including single clock edge operation, non-tristate implementation, support for burst transfers, support for hierarchical transfers, interconnection modes supporting multi-master and multi-slave, configurable bus widths of 32 bits to 128 bits, and support for byte, nibble, and word transfers. The AHB system consists of three parts: master modules, slave modules, and infrastructure. All transfers on the entire AHB bus are sent by the master module, and responded to by the slave module. The infrastructure consists of an arbiter, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a dummy slave module, and a dummy master module.

[0231] APB is primarily used for connecting low-bandwidth peripherals, such as UART and 1284. Its bus architecture differs from AHB, which supports multiple master modules; the only master module in APB is the APB bridge. Its features include:

[0232] (1) It can operate at high frequencies, (2) It is a simple protocol, without complicated sequences. (3) It is a synchronous bus, meaning that all transactions on the bus (read and write operations) depend on the rising edge of the clock. (4) Single-master multi-slave. Generally, the APB is connected to the AHB bus system, and transactions are transferred between the AHB bus systems via the AHB-APB Bridge. At this time, the Bridgre is the APB master, and all other peripheral devices are slaves. (5) It has a simple interface, which is relatively simple compared to AXI and AHB. (6) Low power consumption (7) Can connect to multiple types of peripheral devices such as I2C, SPI, Timer, Keypad, and UART.

[0233] In one possible embodiment, in the multi-master multi-slave mode of the AHB, the master first sends a message transmission request to the arbiter, the arbiter determines the appropriate authority for the master to obtain bus access, and after obtaining the authority, the master sends data and control signals to the arbiter, which determines the corresponding slave path by address analysis and then sends the request to the corresponding destination. Similarly, the response data is analyzed by the decoder and then returned to the corresponding master. This multiplexing mechanism realizes multiple-to-multiple access.

[0234] In one alternative embodiment, the APB is in single-master, multi-slave mode. Generally, the APB is connected to the AHB bus system and transfers transactions between the AHB bus systems via the AHB-APB Bridge. In this case, the Bridge is the master of the APB, and all other peripherals are slaves. Data requests are sent from the master to the slave, and the slave sends corresponding response data back to the master after receiving the request. This process can realize one-to-many access, and the access does not involve the arbiter and decoder analysis operations on the AHB bus.

[0235] In addition, the AHB bus has high bandwidth characteristics and is used for interconnecting high-performance modules in a system (such as CPUs and DMA controllers), while the APB bus has a relatively low bandwidth and is used for connecting peripheral devices in a system (such as UARTs and I2C controllers). The AHB bus logic circuit and bus protocol are complex, while the bus interface circuit and bus protocol are relatively simple.

[0236] The operating system controls the hardware controllers by accessing the registers of each hardware controller (e.g., by performing read and write operations), and the manner in which the operating system accesses the registers of the hardware controllers may be, but is not limited to, by reading or writing the register addresses of each hardware controller, and these register addresses may be unique and determined during chip design, but are not limited to this. For example, when the operating system writes a specific value (i.e., the communication value or control value) to a specific address (i.e., the communication register or a register corresponding to the hardware controller), a specific function (e.g., a communication function between the operating systems or a control function of the operating system over the hardware controller) can be realized. That is, different functions correspond to different control values, and a correspondence between the functions of the hardware controllers and the control values ​​is maintained in the chip. For example, a control value of 00 indicates that the air conditioner is to be accelerated by one level, and a control value of 01 indicates that the air conditioner is to be decelerated by one level.

[0237] Interactions such as communication and control between the operating systems and between the operating systems and the hardware controllers may be performed via a bus, but this is not limited to this. The read / write operations of the operating systems to the registers of each hardware controller are ultimately converted into control signals for the hardware controller via the first bus (or second bus). This conversion operation and the control process for the hardware controller via the first bus (or second bus) may be automatically realized by hardware within the chip, but this realization process follows the bus specifications. Here, in the operation process of the first bus (or second bus), physical signals related to the bus protocol can be transmitted and controlled, while valid data can be transmitted to each hardware controller via the physical data channel.

[0238] In the above-mentioned embedded system, the first operating system and the second operating system run on a processor, and buses with different functions are used to realize communication between the operating systems and control of the hardware controller. Because the first operating system and the second operating system run on the same processor, it is possible to avoid increasing and distributing hardware devices, reduce system costs, and rationally utilize processor resources to support inter-system operations, thereby solving the technical problem of low operating efficiency of the operating systems and achieving the technical effect of improving the operating efficiency of the operating systems.

[0239] An embodiment of the present application further provides a motherboard, wherein the motherboard includes at least one processor and at least one storage used to store at least one program, and the at least one program, when executed by the at least one processor, causes the at least one processor to perform the steps in any of the above method embodiments.

[0240] An embodiment of the present application further provides a server including a processor, a communication interface, a storage, and a communication bus, wherein the processor, the communication interface, and the storage communicate with each other via the communication bus, the storage is used to store a computer program, and the processor, when executing the program stored in the storage, is used to implement the steps in any of the above method embodiments to achieve similar technical effects.

[0241] The communication bus of the server may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. The communication interface is used for communication between the server and other devices.

[0242] The storage may include RAM (Random Access Memory) and may include NVM (Non-Volatile Memory), for example, at least one magnetic disk memory. Optionally, the storage may be at least one storage device located remotely from the processor. The processor may be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc., and may be a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0243] Regarding servers, they are characterized by high scalability and stability. However, since it is impossible for a company's network to remain unchanged for a long time, in today's information-based network environment, if a server does not have a certain level of scalability, it may affect the future development of the company. Therefore, scalability is one of the most basic characteristics of a server, and scalability includes not only hardware scalability but also software scalability. Since the functions of a server are much more complex than those of a computer, not only hardware configuration but also software configuration is important. To achieve more functions, comprehensive software support is essential. In addition, because servers need to process large amounts of data to support the continuous operation of services, high stability is an important characteristic of servers, and if the server's data transmission cannot operate stably, it will have a significant impact on the implementation of the service.

[0244] The solution of the present application takes advantage of the high scalability of servers and introduces dual software systems, a first system and a second system, to generate hardware interface signals, and hardware devices such as a GPLD and a BMC chip to respectively adjust the transmission voltage of the hardware interface signals and monitor the operating status of other devices within the server. In addition, the present application adopts a method in which the first system generates a hardware interface signal corresponding to a request command, first obtaining the request command, then determining a plurality of logical bit information corresponding to the request command, and finally generating the hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer. As can be seen from the above, the present application uses the first system to generate a hardware interface signal corresponding to the request command, thereby achieving the technical effect of simulating the generation of a hardware interface signal using a software method and achieving the objective of eliminating the need for the chip itself to have a hardware logic design for the related hardware interface signals, thereby reducing the difficulty and cost of chip design. The present application achieves the objective of using a software system to generate hardware interface signals without the need for hardware logic design of hardware interface signals for the chip, thereby reducing the difficulty of chip design and solving the technical problem that the prior art requires the chip itself to have the hardware logic design of the controller, resulting in high chip design costs.

[0245] In addition, the introduction of a dual software system consisting of a first system and a second system can ensure the stability of the server. Since the service response speed of the second system is slower than that of the first system, the first system, which has a faster service response speed, is used to generate the hardware interface signal, which ensures that the generation of the hardware interface signal is not interrupted, thereby ensuring that the hardware interface signal can be output continuously and stably.

[0246] As can be understood by those skilled in the art, all or some of the steps in the various methods of the above embodiments may be completed by instructing hardware related to the terminal device by a program, and the program may be stored in a computer-readable storage medium, which may include a flash memory disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0247] The numbers of the above embodiments of the present application are merely for illustrative purposes and do not represent the superiority or inferiority of the embodiments. In the above embodiments of the present application, the description of each embodiment has its own emphasis, and for parts not described in detail in one embodiment, reference can be made to the relevant descriptions of other embodiments.

[0248] It should be understood that in some embodiments provided in the present application, the disclosed technical contents may be realized in other ways. Here, the device embodiments described above are merely exemplary. For example, the division of units is merely a division of logical functions, and other division methods may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. Meanwhile, the shown or discussed mutual couplings, direct couplings, or communicative connections may be indirect couplings or communicative connections via some interfaces, units, or modules, and may be electrical or other forms.

[0249] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Depending on actual needs, some or all of the units may be selected to achieve the objective of the solution of this embodiment. Furthermore, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist physically alone, or two or more units may be integrated into one unit. The integrated unit may be realized in the form of hardware or in the form of a software functional unit.

[0250] When an integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially embodied in a software product, or a part of the technical solution can be entirely or partially embodied in a software product, and the computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes various media capable of storing program code, such as a U disk, a read-only memory (ROM), a random access memory (RAM), a portable hard disk, a magnetic disk, or an optical disk.

[0251] It should be pointed out that the above are only preferred embodiments of the present application, and those skilled in the art may make some improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

1. obtaining a request command by a first system; determining a plurality of logical bit information corresponding to the request command; generating a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer; generating a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer, determining a reload value and a first match value corresponding to the timer based on the plurality of logical bit information; generating a hardware interface signal corresponding to the request instruction based on the reload value and the first match value; determining a reload value and a first match value corresponding to a timer based on the plurality of logical bit information, obtaining an operation time corresponding to each piece of logical bit information; determining the reload value based on the operating time; a step of determining one first match value corresponding to the timer based on the logical bit of each piece of logical bit information to obtain a plurality of first match values ​​corresponding to the timer, wherein the first match value corresponding to each piece of logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

2. generating a hardware interface signal corresponding to the request command based on the reload value and the first match value, 2. The method of claim 1, further comprising: sequentially generating hardware interface sub-signals corresponding to each of the logical bit information based on the reload value and a first match value corresponding to each of the logical bit information in accordance with a forward / backward order among the plurality of logical bit information corresponding to the request instruction, to obtain the hardware interface signal.

3. the step of sequentially generating hardware interface sub-signals corresponding to each of the logical bit information based on the reload value and the first match value corresponding to each of the logical bit information, performing a decrement operation on a reload value corresponding to each of the logical bit information based on the timer; outputting a first signal corresponding to each of the logic bit information by the first system before the reload value corresponding to the logic bit information is decremented to the first match value corresponding to the logic bit information, the first signal being a high level signal; outputting a second signal corresponding to each logic bit information by the first system after the reload value corresponding to the logic bit information has been decremented to the first match value corresponding to the logic bit information, the second signal being a low level signal; 3. The method of claim 2, further comprising: when the reload value corresponding to each logical bit information is decremented to 0, determining generation of a hardware interface sub-signal corresponding to the logical bit information, and obtaining the hardware interface sub-signal corresponding to each logical bit information, wherein the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information.

4. triggering a first interrupt corresponding to each of the logical bit information when the reload value corresponding to the logical bit information is decremented to a first match value corresponding to the logical bit information; 4. The method of claim 3, further comprising the step of: triggering a second interrupt corresponding to each of the logical bit information when the reload value corresponding to that logical bit information is decremented to 0.

5. In the step of sequentially generating hardware interface sub-signals corresponding to each of the logical bit information based on the reload value and the first match value corresponding to each of the logical bit information, performing an interrupt count once each time one of the first interrupt or the second interrupt is triggered; 5. The method of claim 4, further comprising: determining a field in the request instruction currently undergoing signal conversion processing based on the interrupt count, the signal conversion processing being used to generate hardware interface sub-signals corresponding to logical bit information corresponding to each field in the request instruction.

6. The step of determining a field in the request command that is currently performing signal conversion processing based on the interrupt count includes: obtaining the number of bytes corresponding to each field in the request command; determining the number of logical bit information corresponding to the request command based on the number of bytes, wherein each byte corresponding to the request command corresponds to one logical bit information; determining the number of interrupts corresponding to the request instructions based on the number of pieces of logical bit information, the number of interrupts corresponding to the request instructions being twice the number of pieces of logical bit information; and determining a field in said request instruction that is currently performing signal conversion processing based on said number of interrupts and said interrupt count.

7. an acquisition module used by the first system to acquire a request command; a determination module used to determine a plurality of logical bit information corresponding to the request command; a generating module used to generate a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer; The generation module: a first determination unit used to determine a reload value and a first match value corresponding to the timer based on the plurality of logical bit information; a second generating unit adapted to generate a hardware interface signal corresponding to the request instruction based on the reload value and the first match value; The first determination unit: a first acquisition sub-unit used for acquiring an operation time corresponding to each logical bit information; a first determination subunit used to determine the reload value based on the operation time; a second determination subunit used to determine one first match value corresponding to the timer based on the logical bit of each logical bit information to obtain a plurality of first match values ​​corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

8. An electronic device comprising a storage device, a processor, and a computer program stored in the storage device and executable by the processor, wherein the processor, when executing the computer program, implements the steps of the method for generating a hardware interface signal according to any one of claims 1 to 6.

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