Electronic Components

Abstract

An electronic component (101) according to the present invention is provided with: a substrate (1); an insulator layer (2) which expands along a surface of the substrate (1); a planar conductor (4) which is formed on the substrate (1) or in the insulator layer (2) and planarly expands so as to be parallel to the surface of the substrate (1); and a conductor pattern (5) for inductors, the conductor pattern (5) being formed on the insulator layer (2) or in the insulator layer (2). When viewed from a direction that is perpendicular to the surface of the substrate (1), if Ls is the length in the longitudinal direction of a region where the formation region of the conductor pattern (5) for inductors and the planar conductor (4) overlap with each other, and d is the distance between the conductor pattern (5) for inductors and the planar conductor (4), the value of Ls / d is 1 to 60.

Description

[Technical Field]

[0001] The present invention relates to an electronic component having a conductor pattern that forms a capacitor or inductor on a substrate. [Background technology]

[0002] An electronic component having a conductor pattern that forms a capacitor or inductor on a substrate is used as, for example, an LC composite component.

[0003] Patent Document 1 discloses an LC composite component in which an electrode for a capacitor is disposed outside the air-core portion of a coil made of a helical conductor pattern.

[0004] Patent Document 2 shows an LC composite component in which electrodes for a capacitor are arranged so as not to overlap the central axis of a coil conductor formed by a spiral conductor pattern.

[0005] Patent document 3 shows an LC composite component in which a capacitor with a comb-shaped electrode is placed on an upper or lower layer other than the central region of a coil conductor with a spiral conductor pattern, and the comb-shaped electrode is formed perpendicular to the conductor wiring for the inductor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-079973 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-178717 [Patent Document 3] Japanese Patent Application Publication No. 2019-091847 Summary of the Invention [Problem to be solved by the invention]

[0007] In the LC composite elements shown in Patent Documents 1, 2, and 3, the magnetic field generated by the coil does not pass through the electrodes of the capacitance section, so the Q value of the inductor does not deteriorate. However, in the LC composite components with the structures shown in Patent Documents 1, 2, and 3, the capacitor electrodes must be arranged to avoid the center of the coil, which increases the planar area of ​​the LC composite component. In other words, if the capacitor electrodes are arranged to avoid the center of the coil, the desired capacitance cannot be ensured, and if the coil conductor is arranged to avoid the capacitor electrodes, the desired inductance cannot be ensured, making it impossible to miniaturize the LC composite component.

[0008] The above problem is not limited to LC composite components that combine an inductor and a capacitor, but also occurs in electronic components that include a planar conductor and a conductor pattern for an inductor.

[0009] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a miniaturized electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor having a desired size. [Means for solving the problem]

[0010] An example of an electronic component disclosed herein comprises a substrate, an insulator layer extending along a surface of the substrate, one or more sheet conductors formed on or within the substrate and extending in a plane parallel to the surface of the substrate, and an inductor conductor pattern formed on or within the insulator layer, wherein, when viewed from a direction perpendicular to the surface of the substrate, Ls represents the longitudinal length of a single area where the inductor conductor pattern formation area and the sheet conductor overlap, or the combined longitudinal length in a predetermined direction of multiple areas where the inductor conductor pattern formation area and the sheet conductor overlap, and d represents the distance between the inductor conductor pattern and the sheet conductor closest to the inductor conductor pattern, and the value of Ls / d is 1 or greater and 60 or less. [Effects of the Invention]

[0011] According to the present invention, it is possible to obtain a miniaturized electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor having a desired size. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view and a front view of an electronic component 101 according to a first preferred embodiment. [Figure 2] FIG. 2 is a plan view and a cross-sectional view of the main part of the electronic component 101. [Figure 3] FIG. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the sheet conductor 4. As shown in FIG. [Figure 4] FIG. 4 shows the trends of Ls / d and Q / Q0 found from multiple combinations of Ls and d. [Figure 5] 5(A), 5(B), 5(C), and 5(D) are diagrams showing examples of the shape of the area where the inductor conductor pattern 5 is formed and the area where the sheet conductor 4 overlaps. [Figure 6] FIG. 6 is a plan view and a cross-sectional view of an electronic component 102 according to the second preferred embodiment. [Figure 7] FIG. 7 is an equivalent circuit diagram of the electronic component 102. [Figure 8] FIG. 8 is a diagram showing the structure of each layer of the electronic component 102. [Figure 9] 9(A), 9(B), 9(C), and 9(D) are cross-sectional views of the electronic component 102 in each manufacturing process. [Figure 10] 10(A), 10(B), 10(C), and 10(D) are cross-sectional views of the electronic component 102 in each manufacturing process. [Figure 11] FIG. 11 is a plan view and a cross-sectional view of an electronic component 103 according to the third preferred embodiment. [Figure 12] FIG. 12 is a diagram showing the structure of each layer of the electronic component 103. [Figure 13] 13(A), 13(B), 13(C), and 13(D) are cross-sectional views of the electronic component 103 in each manufacturing process. [Figure 14]14(A), 14(B), and 14(C) are cross-sectional views of the electronic component 103 in each manufacturing process. [Figure 15] FIG. 15 is a plan view and a cross-sectional view of an electronic component 104 according to the fourth preferred embodiment. [Figure 16] FIG. 16 is a plan view and a cross-sectional view of an electronic component 105 according to the fifth preferred embodiment. [Figure 17] FIG. 17 is an equivalent circuit diagram of the electronic component 105. [Figure 18] FIG. 18 is a diagram showing the structure of each layer of the electronic component 105. [Figure 19] 19(A), 19(B), 19(C), and 19(D) are cross-sectional views of the electronic component 105 in each manufacturing process. [Figure 20] 20(A), 20(B), and 20(C) are cross-sectional views of the electronic component 105 in each manufacturing process. [Figure 21] FIG. 21 is a cross-sectional view of an electronic component 106 according to the sixth preferred embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, several specific examples will be given with reference to the drawings to illustrate several embodiments for carrying out the present invention. The same reference numerals are used for the same parts in each drawing. For the sake of convenience, the embodiments are shown divided into several embodiments, taking into account ease of explanation and understanding of the main points, but partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0014] First Embodiment The upper part of Fig. 1 is a perspective view of an electronic component 101 according to a first preferred embodiment. In this perspective view, the outer shape is represented by a two-dot chain line. The lower part of Fig. 1 is a front view of the electronic component 101 as viewed in the Y-axis direction.

[0015] This electronic component 101 comprises an electrically insulating substrate 1, an insulator layer 2 extending along the surface of the substrate 1, a planar conductor 4 formed on the substrate 1 or in the insulator layer 2 and extending in a plane parallel to the surface of the substrate 1, and a rectangular spiral coil type inductor conductor pattern 5 formed on the substrate 1 or in the insulator layer 2.

[0016] The upper part of Fig. 2 is a plan view of the main part of the electronic component 101, and the lower part of Fig. 2 is a cross-sectional view of the part XX in the plan view. Fig. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the sheet conductor 4. However, for convenience of explanation, the distance between the inductor conductor pattern 5 and the sheet conductor 4 is intentionally drawn wider.

[0017] The inductor conductor pattern 5 has an opening MH for magnetic flux φ where magnetic flux is concentrated, and in response to this magnetic flux (high frequency magnetic flux) φ, an eddy current EC flows in the sheet conductor 4. The eddy current EC increases as the magnetic flux φ increases.

[0018] In Figure 2, the width of the sheet conductor 4 is represented by W. If the distance between the inductor conductor pattern 5 and the sheet conductor 4 is represented by d, the smaller the distance d between the inductor conductor pattern 5 and the sheet conductor 4, the larger the eddy current EC. Also, if the longitudinal length of the area where the inductor conductor pattern 5 overlaps with the sheet conductor 4 when viewed from the perpendicular direction to the surface of the substrate 1 is represented by Ls, the larger Ls becomes, the larger the eddy current EC becomes. Therefore, the larger the value of Ls / d becomes, the larger the eddy current EC becomes.

[0019] Table 1 shows the relationship between the longitudinal length Ls of the area where the inductor conductor pattern 5 is formed and the sheet conductor 4 overlap, the distance d between the inductor conductor pattern 5 and the sheet conductor 4, and the deterioration of the inductor's Q value, etc.

[0020] [Table 1]

[0021] In Table 1, S [μm 2] is the area of ​​the area where the inductor conductor pattern 5 and the sheet conductor 4 overlap when they are square. In Table 1, Q0 is the Q value of the inductor formed by the inductor conductor pattern 5 when there is no sheet conductor 4, and Q / Q0 is the area S [μm 2 ] is placed at a distance d [μm] from the inductor conductor pattern 5. Furthermore, L0 is the inductance of the conductor pattern 5 for inductor in the absence of the planar conductor 4, and L / L0 is the ratio of the Q value to Q0 when the planar conductor 4 is not present. 2 ] is placed at a distance d [μm] from the inductor conductor pattern 5, and the ratio of L value to L0. .

[0022] FIG. 4 shows the trends between Ls / d and Q / Q0 found from the above-mentioned multiple combinations of Ls and d. In FIG. 4, the horizontal axis represents Ls / d, and the vertical axis represents Q / Q0. As is clear from FIG. 4, when the value of Ls / d (the value of √(S) / d) is in the range of 1 to 60, Q / Q0 is 0.3 or more, so the presence of the sheet conductor 4 does not reduce the Q value of the inductor very much. Furthermore, when the value of Ls / d is in the range of 1 to 55, the reduction in Q / Q0 is further reduced.

[0023] The examples in Table 1 and Figure 4 are examples where the overlapping area between the inductor conductor pattern 5 and the sheet conductor 4 is square, i.e., the worst case. Therefore, if the overlapping area between the formation area of ​​the inductor conductor pattern 5 and the sheet conductor 4 is not square, the longitudinal length of this overlapping area can be treated as Ls.

[0024] In the example shown in Figure 1, when viewed from a direction perpendicular to the surface of the substrate 1, there is only one area where the area where the inductor conductor pattern 5 is formed overlaps with the sheet conductor 4. However, if there are multiple such areas, the total longitudinal length in a specified direction of the multiple areas where the inductor conductor pattern 5 is formed overlaps with the sheet conductor 4 can be treated as Ls.

[0025] 5(A), 5(B), 5(C), and 5(D) are diagrams showing examples of the shape of the region where the inductor conductor pattern 5 overlaps with the sheet conductor 4. As shown in FIG. 5(A), if the region of the sheet conductor 4 overlapping with the region where the inductor conductor pattern 5 is formed is L-shaped, the longitudinal dimension of that region is defined as Ls. Also, as shown in FIG. 5(B), if the region of the sheet conductor 4 overlapping with the region where the inductor conductor pattern 5 is formed is circular or elliptical, the longitudinal dimension of that region is defined as Ls. Furthermore, as shown in FIG. 5(C), if the region of the sheet conductor 4 overlapping with the region where the inductor conductor pattern 5 is formed is T-shaped, the longitudinal dimension of the width Lx height Ly of that region is defined as Ls.

[0026] 5(D), when there are multiple areas of the sheet conductor overlapping the area where the inductor conductor pattern 5 is formed, the combined longitudinal length of those overlapping areas in a predetermined direction is defined as Ls. In the example shown in Fig. 5(D), of the two sheet conductor areas overlapping the area where the inductor conductor pattern 5 is formed, one has an X-axis dimension of Lx1 and a Y-axis dimension of Ly1, while the other has an X-axis dimension of Lx2 and a Y-axis dimension of Ly2. In this example, the combined dimension of Ly1+Ly2 is greater than the combined dimension of Lx1+Lx2, so the value of Ly1+Ly2 is the longitudinal length Ls.

[0027] Second Embodiment In the second embodiment, an LC composite electronic component will be illustrated. The upper part of Fig. 6 is a plan view of an electronic component 102 according to the second embodiment, and the lower part of Fig. 6 is a cross-sectional view taken along the line XX in the upper part of Fig. 6.

[0028] The electronic component 102 comprises a substrate 1, an insulator layer 2 extending along the surface of the substrate 1, an inductor formed in the insulator layer 2, sheet conductors 3 and 4 formed on the substrate 1 and extending along the substrate 1, sheet conductor connecting conductors 7A, 7B, and 7C that are electrically connected to the sheet conductor 3, and a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4.

[0029] Terminal electrodes 10A and 10B are formed on the surface of the insulating layer 2. The terminal electrodes 10A and 10B are electrically connected to the terminal electrodes 9A and 9B.

[0030] The inductor is a spiral coil type inductor formed by a conductor pattern 5 for the inductor along the surface of the substrate 1.

[0031] The sheet conductors 3 and 4 are capacitor electrodes. That is, a capacitor is composed of the sheet conductors 3 and 4 and the dielectric layer 11 sandwiched between these sheet conductors 3 and 4. That is, the sheet conductors 3 and 4 are capacitor electrodes that constitute the capacitor together with the dielectric layer 11.

[0032] When viewed perpendicularly to the surface of the substrate 1, the formation area of ​​the inductor conductor pattern 5 overlaps with both the sheet conductor 3 and the sheet conductor 4. Of these sheet conductors 3 and 4, the sheet conductor 4 is closer to the inductor conductor pattern 5, so the distance between the inductor conductor pattern 5 and the sheet conductor 4 is represented by d. Furthermore, the longitudinal length of the largest area of ​​overlap between the inductor conductor pattern 5 and the sheet conductor 4 is represented by Ls.

[0033] 6, the value of Ls is 190 μm, and the distance d between the inductor conductor pattern 5 and the sheet conductor 4 is 20 μm. Therefore, Ls / d is 9.5, which is smaller than 60 and even smaller than 55. As a result of creating and simulating the structural model shown in FIG. 6, according to this embodiment, the ratio Q / Q0 of the Q value when the sheet conductor 4 is present to the Q value when the sheet conductor 4 is absent is 0.48, and although the Q value decreases, it is not an extreme decrease, and an electronic component having an inductor with an effective Q value can be obtained.

[0034] 7 is an equivalent circuit diagram of the electronic component 102. As such, the electronic component 102 forms a series circuit of the inductor L1 and the capacitor C1. This electronic component 102 can be used as a frequency filter or an impedance matching circuit.

[0035] Fig. 8 is a diagram showing the structure of each layer of electronic component 102. In Fig. 8, layer La is the layer of substrate 1, layer Lb is the layer where sheet conductor 3 is formed, layer Lc is the layer where dielectric layer 11 and sheet conductor connecting conductor 7A are formed, and layer Ld is the layer where sheet conductor 4 and sheet conductor connecting conductor 7B are formed. Layer Le is the layer where sheet conductor connecting conductors 7C and 8 are formed, and layer Lf is the layer where inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed. And layer Lg is the layer where terminal electrodes 10A and 10B are formed.

[0036] Next, a method for manufacturing an electronic component 102 composed of the layers shown in FIG. 8 will be illustrated. FIG. 9(A) is a cross-sectional view of a substrate. This substrate 1 can be a semiconductor substrate such as a Si substrate or a GaAs substrate, as well as a glass substrate or a ceramic substrate. FIG. 9(B) is a cross-sectional view of the state in which a planar conductor 3 has been formed. In this process, an Al film or Cu film is evaporated on the surface of the substrate 1 and lifted off, or the Al film or Cu film is formed by sputtering or CVD and lithography is performed, It is formed by a semiconductor process such as etching.

[0037] 9(C) is a cross-sectional view showing a state in which a dielectric layer 11 has been formed. In this step, the dielectric layer 11, such as an SiO2 film or an SiN film, is formed on the surface of the planar conductor 3 by a semiconductor process such as sputtering or CVD. 9(D), an opening is formed in the portion where the conductor 7A for connecting the planar conductor is to be formed, and the conductors 7A, 7B for connecting the planar conductor and the planar conductor 4 are formed. In this process, an opening is formed by lithography and etching, an Al film or a Cu film is evaporated and lifted off, or an Al film or a Cu film is formed by sputtering or CVD, lithography is performed, and etching is performed. The pattern of the sheet conductor 4 is formed by a semiconductor process such as etching.

[0038] FIG. 10(A) is a cross-sectional view showing a state in which an insulating layer 2 is formed and an opening AP is formed. In this configuration, a resin (organic) film or an inorganic film such as an SiO2 film or an SiN film is formed by a method such as spin coating, CVD, or sputtering, and then an opening is formed in a predetermined position by lithography and etching. Forms the oral AP.

[0039] Fig. 10(B) is a cross-sectional view of the state after the formation of the conductors 7C and 8 for connecting planar conductors. In this process, the conductors 7C and 8 for connecting planar conductors are formed in the opening AP shown in Fig. 10(A). For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0040] 10(C) is a cross-sectional view of the state after the inductor conductor pattern 5 and terminal electrodes 9A and 9B have been formed. In this step, the inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed on the surface of the insulator layer 2. For example, they can be formed by depositing a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0041] 10(D) is a cross-sectional view of the state after the terminal electrodes 10A and 10B have been formed. In this process, the terminal electrodes 10A and 10B are electrodes for mounting, and are formed by plating the surfaces of the terminal electrodes 9A and 9B with Ni, Au, or the like. After that, a protective film is formed, and the portions corresponding to the terminal electrodes 10A and 10B are opened to expose the terminal electrodes 10A and 10B.

[0042] Third Embodiment In the third embodiment, an electronic component having a sheet conductor configuration different from the examples shown in the first and second embodiments will be illustrated.

[0043] Fig. 11 is a diagram showing the structure of an electronic component 103 according to a third embodiment. The <Plan View> in Fig. 11 is a plan view of the electronic component 103. The <Cross Section View> in Fig. 11 is a cross section taken along the line XX in the plan view of the electronic component 103.

[0044] The electronic component 103 comprises a substrate 1, an insulator layer 2 extending along the surface of the substrate 1, an inductor conductor pattern 5 formed in the insulator layer 2, a dielectric layer 11 and a sheet conductor 4 formed on the substrate 1 and extending along the substrate 1, a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4, and sheet conductor connecting conductors 7A, 7B, and 7C that are electrically connected to the substrate 1.

[0045] A dielectric layer 11 is formed on the surface of the substrate 1, and a sheet conductor 4 is formed on the surface of this dielectric layer 11. Furthermore, a sheet conductor connecting conductor 7A is formed at a predetermined position on the surface of the substrate 1. The substrate 1 is a semiconductor substrate with high conductivity. The other configurations are as shown in the second embodiment.

[0046] 11, the value of Ls is 210 μm, and the distance d between the inductor conductor pattern 5 and the sheet conductor 4 is 30 μm. Therefore, Ls / d is 7, which is smaller than 60 and even smaller than 55. According to this embodiment, the ratio Q / Q0 of the Q value when the sheet conductor 4 is present to the Q value Q0 when there is no sheet conductor 4 is 0.61, and an electronic component having an inductor with an effective Q value is obtained.

[0047] Fig. 12 is a diagram showing the structure of each layer of electronic component 103. In Fig. 12, layer La is the layer of substrate 1, layer Lb is the layer on which conductor 7A for connecting a planar conductor and dielectric layer 11 are formed, layer Lc is the layer on which dielectric layer 11 and planar conductor 4 are formed, and layer Ld is the layer on which conductors 7C and 8 for connecting a planar conductor are formed. Layer Le is the layer on which inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed. And layer Lf is the layer on which terminal electrodes 10A and 10B are formed.

[0048] Next, a method for manufacturing an electronic component 103 composed of the layers shown in FIG. 11 will be illustrated. FIG. 13(A) is a cross-sectional view of a substrate. This substrate 1 can be a semiconductor substrate such as a Si substrate or a GaAs substrate, as well as a glass substrate or a ceramic substrate. FIG. 13(B) is a cross-sectional view of a state in which a dielectric layer 11 is formed and an opening AP is formed at a predetermined position. FIG. 13(C) is a cross-sectional view of a state in which a conductor 7A for connecting a planar conductor is formed in the opening AP, and a conductor 7B for connecting a planar conductor and a planar conductor 4 are formed on the upper surface of the dielectric layer 11. FIG. 13(D) is a cross-sectional view of a state in which an insulator layer 2 is formed and an opening AP is formed. In this configuration, a resin (organic) film or an inorganic film such as a SiO2 film or a SiN film is formed by a method such as spin coating, CVD, or sputtering. After that, an opening AP is formed at a predetermined location by lithography and etching.

[0049] Fig. 14(A) is a cross-sectional view of the state after the formation of the conductors 7C and 8 for connecting planar conductors. In this process, the conductors 7C and 8 for connecting planar conductors are formed in the opening AP shown in Fig. 13(D). For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0050] 14(B) is a cross-sectional view of the state after the inductor conductor pattern 5 and terminal electrodes 9A, 9B have been formed. In this step, the inductor conductor pattern 5 and terminal electrodes 9A, 9B are formed on the surface of the insulator layer 2. For example, they can be formed by depositing a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0051] 14(C) is a cross-sectional view of the state after the terminal electrodes 10A and 10B have been formed. In this process, the terminal electrodes 10A and 10B are electrodes for mounting, and are formed by plating the surfaces of the terminal electrodes 9A and 9B with Ni, Au, or the like. Thereafter, a protective film is formed, and the portions corresponding to the terminal electrodes 10A and 10B are opened to expose the terminal electrodes 10A and 10B.

[0052] Fourth Embodiment In the fourth embodiment, an electronic component having a planar conductor on the back surface of a substrate is illustrated. The plan view in Fig. 15 is a plan view of electronic component 104. The cross-sectional view in Fig. 15 is a cross-sectional view of part XX in the plan view of electronic component 104.

[0053] The electronic component 104 comprises a substrate 1, a dielectric layer 11 formed on the upper surface of the substrate 1, a terminal electrode 9A formed on the lower surface of the substrate 1, an insulator layer 2, an inductor conductor pattern 5 formed in the insulator layer 2, a sheet conductor 4 extending along the substrate 1, and a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4.

[0054] In the electronic component 104 of this embodiment, the capacitance generated between the planar conductor 4 and the terminal electrode 9A is used as a capacitor. The terminal electrodes 9A and 9B on the top and bottom surfaces are also used.

[0055] In this embodiment, the value of Ls is 210 μm, and the value of d is 30 μm. Except for the back electrode, this is the same as electronic component 103 shown in the third embodiment. Therefore, the value of Ls / d is the same as the result shown in the third embodiment.

[0056] Fifth Embodiment In the fifth embodiment, an electronic component having three terminal electrodes and an electronic component including a resistor element will be exemplified.

[0057] Fig. 16 is a diagram showing the structure of an electronic component 105 according to a fifth embodiment. The <Plan View> in Fig. 16 is a plan view of the electronic component 105. The <Cross Section View> in Fig. 16 is a cross section taken along the line XX in the plan view of the electronic component 105.

[0058] The electronic component 105 includes a substrate 1, an insulator film 20 extending along the surface of the substrate 1, an inductor conductor pattern 5 formed in an insulator layer 2, a resistor film 21 formed on the insulator film 20 and extending along the insulator film 20, a planar conductor connecting conductor 7 electrically connecting the resistor film 21 to a terminal electrode 9A, and a planar conductor connecting conductor 8 electrically connecting the resistor film 21 to a terminal electrode 9B. In this embodiment, the resistor film 21 corresponds to a planar conductor according to the present invention.

[0059] 17 is an equivalent circuit diagram of electronic component 105. As described above, electronic component 105 constitutes a composite component of inductor L1 and resistor element R1.

[0060] Fig. 18 is a diagram showing the structure of each layer of the electronic component 105. In Fig. 18, layer La is the layer where the insulator film 20 and resistor film 21 are formed, layer Lb is the layer where the planar conductor connecting conductors 7 and 8 are formed, layer Lc is the layer where the inductor conductor pattern 5 and terminal electrodes 9A, 9B, and 9C are formed, and layer Ld is the layer where the terminal electrodes 10A, 10B, and 10C are formed.

[0061] Next, a method for manufacturing an electronic component 105 composed of the layers shown in Fig. 18 will be illustrated. Fig. 19(A) is a cross-sectional view of the substrate. Fig. 19(B) is a cross-sectional view of the state after the insulator film 20 has been formed. Fig. 19(C) is a cross-sectional view of the state after the resistor film 21 has been formed on the insulator film 20. Fig. 19(D) is a cross-sectional view of the state after the insulator layer 2 has been formed and an opening AP has been formed.

[0062] The resistor film 21 is made of a material having a conductivity between that of the insulator layer and that of the conductor forming the terminal electrodes and the conductor pattern for the inductor. The resistor film 21 may be made of, for example, NiCr, Si containing impurities, or a film in which an insulator and a conductor are stacked.

[0063] Fig. 20(A) is a cross-sectional view showing the state after forming the planar conductor connecting conductors 7 and 8. In this step, the planar conductor connecting conductors 7 and 8 are formed in the opening AP shown in Fig. 19(D).

[0064] 20(B) is a cross-sectional view of the state after the inductor conductor pattern 5 and terminal electrodes 9A, 9B, and 9C are formed. In this step, the inductor conductor pattern 5 and terminal electrodes 9A, 9B, and 9C are formed on the surface of the insulator layer 2.

[0065] 20(C) is a cross-sectional view of the state after the terminal electrodes 10A, 10B, and 10C for mounting have been formed. In this process, the surfaces of the terminal electrodes 9A, 9B, and 9C are plated with Ni, Au, or the like. After that, a protective film is formed, and the portions corresponding to the terminal electrodes 10A, 10B, and 10C are opened to expose the terminal electrodes 10A, 10B, and 10C.

[0066] In this embodiment, the value of Ls is 250 μm, the value of d is 30 μm, and Ls / d is approximately 8.3. In this example, Ls / d is also smaller than 55, and Q / Q0 is 0.52, resulting in an electronic component with a sufficiently large inductor Q value.

[0067] Sixth Embodiment In the sixth embodiment, an electronic component having a capacitor electrode inside a dielectric layer will be exemplified.

[0068] 21 is a cross-sectional view of an electronic component 106 according to a sixth embodiment. This electronic component 106 includes a substrate 1, a dielectric layer 11 extending along the surface of the substrate 1, sheet conductors 3 and 4 formed in the dielectric layer 11, a spiral coil-type inductor conductor pattern 5 formed on the insulator layer 2, and terminal electrodes 9A, 9B, 10A, and 10B. One end of the inductor conductor pattern 5 is electrically connected to the sheet conductor 4 and terminal electrode 9A, and the other end of the inductor conductor pattern 5 is electrically connected to the sheet conductor 3 and terminal electrode 9B. This electronic component 106 constitutes a parallel circuit of an inductor and a capacitor.

[0069] In this embodiment, too, when the longitudinal length of the area where the inductor conductor pattern 5 overlaps with the sheet conductor 4 is represented by Ls and the distance between the inductor conductor pattern and the sheet conductor is represented by d, Ls / d is a value between 1 and 60.

[0070] In each of the above-described embodiments, an example is shown in which the conductor pattern for the inductor has an opening MH of the magnetic flux φ where the magnetic flux is concentrated, and a sheet conductor is arranged in all or part of the opening MH, and an example in which the sheet conductor covers the entire opening MH of the magnetic flux φ is not necessarily explicitly stated, but the sheet conductor may cover the entire opening MH of the magnetic flux φ.

[0071] In addition, while the above-described embodiments have shown electronic components that include a capacitor or a resistor as a passive component in addition to an inductor, electronic components that include passive components that include both a capacitor and a resistor can be similarly configured. Electronic components that include passive components that include multiple capacitors or multiple inductors can also be similarly configured.

[0072] The present invention can also be applied to electronic components used as LC parallel resonant circuits, bandpass filters including a plurality of inductors and capacitors, diplexers, and the like.

[0073] Furthermore, in the present invention, the substrate is a semiconductor substrate, and the planar conductor can be similarly applied to electronic components that, together with the semiconductor substrate, constitute a semiconductor active element, such as a high-frequency power amplifier in which an active component is provided on a semiconductor substrate.

[0074] Finally, the present invention is not limited to the above-described embodiments. Those skilled in the art can make appropriate modifications and variations. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications and variations from the embodiments within the scope of the claims and their equivalents.

[0075] The configuration of the electronic component of the present invention is listed below.

[0076] <1> a substrate; an insulating layer extending along the surface of the substrate; a single or multiple sheet conductors formed on or in the substrate and extending in a plane parallel to the surface of the substrate; and an inductor conductor pattern formed on or in the insulating layer, wherein, when viewed from a direction perpendicular to the surface of the substrate, the longitudinal length of a single area where the inductor conductor pattern formation area and the sheet conductor overlap is represented by Ls, or the combined longitudinal length in a predetermined direction of multiple areas where the inductor conductor pattern formation area and the sheet conductor overlap is represented by d, and the distance between the inductor conductor pattern and the sheet conductor closest to the inductor conductor pattern is represented by d, the value of Ls / d is 1 or more and 60 or less.

[0077] <2> The value of Ls / d is 1 or more and 55 or less, <1> The electronic component according to claim 1.

[0078] <3> a dielectric layer formed between the substrate and the insulator layer, and the planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer; <1> or <2> The electronic component according to claim 1.

[0079] <4> the substrate is a low-resistivity semiconductor substrate, and the planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate; <1> or <2> The electronic component according to claim 1.

[0080] <5> the substrate is a semiconductor substrate, and the planar conductor forms a semiconductor active element together with the semiconductor substrate; <1> or <2> The electronic component according to claim 1.

[0081] <6> the planar conductor is a resistive thin film; <1> from <5> 1. An electronic component according to any one of the preceding claims.

[0082] <7> The inductor conductor pattern has a magnetic flux opening where magnetic flux concentrates, and the planar conductor is disposed in the opening. <1> from <6> 1. An electronic component according to any one of the preceding claims.

[0083] <8> The planar conductor covers the entire opening. <7> The electronic component according to claim 1. [Explanation of symbols]

[0084] AP…Aperture C1: Capacitor d...Spacing EC…Eddy current Ls: longitudinal length L1...inductor Lx…width Ly…height La, Lb, Lc, Ld, Le, Lf, Lg… layers MH...magnetic flux opening R1: Resistor element φ...Magnetic flux 1...Substrate 2...Insulator layer 3, 4... Planar conductor 5...Inductor conductor pattern 7, 8...Conductors for connecting sheet conductors 7A, 7B, 7C, 8...Conductors for connecting sheet conductors 9A,9B,9C,10A,10B,10C…Terminal electrode 11...Dielectric layer 20...insulating film 21...Resistor film 101~106...Electronic components

Claims

1. A substrate; an insulating layer extending along the surface of the substrate; a single or multiple planar conductors formed on the substrate or in the insulating layer and extending in a plane parallel to the surface of the substrate; an inductor conductor pattern formed on or in the insulator layer, When viewed from a direction perpendicular to the surface of the substrate, the longitudinal length of a single region where the region where the inductor conductor pattern is formed and the sheet conductor overlap, or the combined longitudinal length in a predetermined direction of a plurality of regions where the region where the inductor conductor pattern is formed and the sheet conductor overlap, is represented by Ls, and the distance between the inductor conductor pattern and the sheet conductor closest to the inductor conductor pattern is represented by d, the value of Ls / d is 1 or more and 60 or less. Electronic components.

2. The value of Ls / d is 1 or more and 55 or less, The electronic component according to claim 1 .

3. a dielectric layer formed between the substrate and the insulator layer; the planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer; The electronic component according to claim 1 or 2.

4. the substrate is a low-resistivity semiconductor substrate, the planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate; The electronic component according to claim 1 or 2.

5. the substrate is a semiconductor substrate; the planar conductor constitutes a semiconductor active element together with the semiconductor substrate; The electronic component according to claim 1 or 2.

6. the planar conductor is a resistive thin film; The electronic component according to claim 1 or 2.

7. The inductor conductor pattern has a magnetic flux opening where magnetic flux concentrates, and the planar conductor is disposed in the opening. The electronic component according to claim 1 or 2.

8. the sheet conductor covers the entire opening; The electronic component according to claim 7.

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