Restoring the register mapping state of a flushed instruction by traversing the reorder buffer (ROB) entries in the processor using snapshots of other register mapping states

Abstract

A register mapping circuit is disclosed that restores register mapping states associated with flushed instructions by traversing ROB entries from snapshots of other register mapping states. The register mapping circuit includes a ROB control circuit, a snapshot circuit, and a register rename restore circuit (RRRC). The ROB control circuit assigns ROB entries to instructions entering a processor pipeline, and the ROB entries include a target ROB entry assigned to the target instruction and other ROB entries assigned to other instructions. The snapshot circuit captures snapshots of logical-to-physical register mapping states in a rename map table associated with a subset of instructions that may be flushed. When a target instruction is flushed, the RRRC restores the rename map table register mapping states corresponding to the target instruction based on the snapshots in the ROB entries assigned to the other instructions and traverses the register mapping updates in the intervening ROB entries.

Description

[Technical Field]

[0001] The disclosed technology relates to instruction processing in an instruction pipeline within a computer processor (“processor”), and more particularly to restoring the structural state of an instruction pipeline within a processor after a speculative misprediction of a conditional control (e.g., branch) instruction. [Background technology]

[0002] Microprocessors, also known as "processors," perform computational tasks for a wide variety of applications. A conventional microprocessor includes a central processing unit (CPU) that contains one or more processor cores, also known as "CPU cores." The CPU executes computer program instructions ("instructions"), which process input data and generate data results. The data results generated in an instruction sequence may be intermediate data that is stored for use as input data to subsequent instructions. To avoid delays incurred by storing the intermediate data in external memory and then reading the intermediate data back from the external memory into the processor, the intermediate data may be temporarily stored in persistent registers within the processor.

[0003] An instruction set architecture (ISA) makes a certain number of registers available for use as instruction operands. However, to avoid multiple instructions in the instruction pipeline using the same register, there may not be enough registers available in the ISA. Therefore, it is generally desirable to provide more physical registers than the number of logical registers specified in the ISA to store intermediate data. Therefore, for different instructions, the processor can assign the logical registers available in the ISA to different physical registers. The processor maps the logical registers of a processed instruction to physical registers via a rename map table to track the actual physical registers in which data is stored. The processor includes a register renaming circuit in the instruction pipeline that renames the logical registers to physical registers to access data in the physical registers for instruction execution. The logical register-to-physical register mappings in the rename map table are released when the physical register becomes obsolete, completes, or is no longer in use. Obsolete means that a newer write to the same logical register has been committed. Completed means that the result corresponding to that physical register has been written to the physical register file. No longer in use means that all instructions that need to consume that physical register have passed the time to read the register file. The processor stores the renaming information associated with each instruction in program order in a reorder buffer (ROB) and keeps the latest rename state in a rename map table. When an instruction to be executed is committed, the instruction's logical to physical register renamings are saved in a committed map table (CMT).

[0004] A control hazard may occur in an instruction pipeline if the next instruction in the instruction pipeline cannot be executed without leading to an erroneous computation result. For example, a control hazard may occur as a result of the execution of a control flow instruction that causes a precise interrupt in a processor. One example of a control flow instruction that may cause a control hazard is a conditional branch instruction. A conditional branch instruction may redirect the flow path of instruction execution based on a condition evaluated when the condition of the control branch instruction is executed. As a result, the processor may have to stop fetching further instructions until the conditional branch instruction has completed execution, which may result in reduced processor performance and increased power consumption. One approach to maximizing processor performance involves utilizing a prediction circuit to speculatively predict the outcome of the condition of the conditional branch instruction. Processing new instructions based on the prediction may include changes to register mapping information in a rename map table. However, a mispredicted branch instruction requires the execution of a misprediction recovery process, which flushes the instruction pipeline and redirects the instruction pipeline fetch unit to fetch new instructions starting from the address of the conditional branch instruction. As part of this misprediction recovery process, the rename map table, which contains register mapping information for uncommitted instructions in the instruction pipeline, must be restored to its previous state of register mapping before instructions in the correct branch are processed. Because the ROB maintains the latest register rename state in the rename map table for uncommitted instructions, the instruction entry in the ROB containing the latest register rename state can be used to restore the previous state of register mapping that was executed prior to the speculatively mispredicted instruction. To minimize performance losses due to speculative mispredictions, it is desirable to restore the processor's register state as early as possible during misprediction recovery. Summary of the Invention

[0005] Exemplary aspects disclosed herein include restoring the register mapping state of a flushed instruction by traversing reorder buffer (ROB) entries within the processor using snapshots of other register mapping states. Instructions in a processor pipeline are committed in program order, even if they are processed out of order for efficiency. Because all instructions use the same logical register set, different instructions may use the same logical register operands for different purposes. For this reason, logical register operands for an instruction are mapped to unique physical registers using a rename map table. To maintain the most recent logical register-to-physical register mapping, the rename map table is updated each time a new instruction enters the processor pipeline. Updates from each instruction are stored in the corresponding reorder buffer (ROB) entry in program order. When a processor pipeline is flushed due to a target instruction that failed to execute as intended, all instructions following the target instruction may be flushed from the processor pipeline, and the rename map table state is restored to the logical register-to-physical register mapping state that existed before the target instruction entered the processor pipeline.

[0006] In this regard, one exemplary aspect discloses a register mapping circuit that restores a register mapping state associated with a flushed instruction by traversing ROB entries from one having a snapshot of the other register mapping state. The register mapping circuit includes a ROB control circuit, a snapshot circuit, and a register rename recovery circuit (RRRC). The ROB control circuit assigns ROB entries in the ROB to uncommitted instructions entering the processor's pipeline. The uncommitted instructions may include a target instruction and other instructions that are older or newer than the target instruction. The ROB entries include a target ROB entry assigned to the target instruction and other ROB entries assigned to the other instructions. The snapshot circuit is configured to capture snapshots of the rename map table state corresponding to only a subset of the uncommitted instructions that may be flushed. For example, the snapshot circuit may be configured to capture snapshots of the rename map table every given number of instructions or only for a predetermined ROB entry in the ROB. The snapshot circuit stores each rename map table snapshot in association with the snapshot ROB entry assigned to the corresponding instruction.

[0007] In the exemplary aspects disclosed herein, when the RRRC receives an indication of a flush of instructions in the pipeline from a target instruction, the RRRC restores the logical register-to-physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry. That is, the RRRC first restores the rename map table to the state of the snapshot from another instruction in the ROB, and then walks through the updates stored in the ROB entries of the intervening instructions to restore the register mapping state of the target instruction. The RRRC first restores the rename map table to the state of the snapshot from another instruction in the ROB because the snapshot circuitry is not configured to capture rename map table snapshots for all instructions or for all instructions that may be flushed. Thus, to restore the rename map table, the RRRC may be required to walk the ROB between the entry assigned to the target instruction and the entries of other instructions that have captured rename map table snapshots. Thus, the snapshot circuitry does not need to capture rename map table snapshots for every instruction that may be flushed, and the amount of snapshot resources required by the register mapping circuitry is reduced compared to snapshot-based restore. Furthermore, using rename map table snapshots captured in association with uncommitted instructions significantly reduces the number of ROB entries that must be walked to or from a target ROB entry in a typical flush compared to typical ROB walking methods.

[0008] In this regard, one exemplary aspect of the present disclosure provides a register mapping circuit in a processor, the register mapping circuit including a ROB control circuit configured to assign a plurality of ROB entries in a ROB to a plurality of uncommitted instructions in a processor pipeline, the plurality of uncommitted instructions including a target instruction and other instructions, the plurality of ROB entries including a target ROB entry assigned to the target instruction and other ROB entries assigned to the other instructions, the other instructions including old instructions that precede the target instruction in the processor pipeline and young instructions that follow the target instruction in the processor pipeline, the register mapping circuit also including a snapshot circuit configured to capture a rename map table snapshot having a logical register-to-physical register mapping state of a rename map table, the rename map table snapshot corresponding to a first other instruction of the other instructions, and to store the rename map table snapshot in association with the snapshot ROB entry assigned to the first other instruction of the other instructions. The register mapping circuit further includes a register rename restore circuit configured to receive an indication to flush instructions in the processor pipeline from the target instruction, and in response to the flush indication, restore a logical register-to-physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry.

[0009] In another exemplary aspect herein, a register mapping circuit is disclosed, the register mapping circuit including ROB control circuitry configured to assign a ROB entry of a plurality of ROB entries in a ROB to each of a plurality of uncommitted instructions in a processor pipeline, the plurality of uncommitted instructions including a target instruction and other instructions, the plurality of ROB entries including a target ROB entry assigned to the target instruction and other ROB entries assigned to the other instructions, the other instructions including old instructions that precede the target instruction in the processor pipeline and young instructions that follow the target instruction in the processor pipeline, the register mapping circuit including a snapshot circuit configured to capture at least one rename map table snapshot, each having a logical register-to-physical register mapping state of a rename map table, each rename map table snapshot corresponding to a respective one of the other instructions and to store the at least one rename map table snapshot in association with one of the other ROB entries assigned to the respective one of the other instructions. The register mapping circuit includes a register rename restoration circuit configured to receive an instruction to flush instructions in the processor pipeline from a target instruction and, in response to the flush instruction, determine that a first number of other ROB entries between the target ROB entry and a closest one of the other ROB entries associated with the rename map table snapshot is greater than a second number of other ROB entries from the target ROB entry to an end ROB entry, the end ROB entry having one of a top ROB entry assigned to the oldest instruction among the old side instructions and a bottom ROB entry assigned to the newest instruction among the young side instructions.The register rename restoration circuit is further configured to, in response to the end ROB entry having the top ROB entry, restore the logical register-physical register mapping state of the rename map table based on the committed map table (CMT) and register mapping information in other ROB entries from the top ROB entry to the target ROB entry, and to, in response to the end ROB entry having the bottom ROB entry, restore the logical register-physical register mapping state of the rename map table based on the rename map table and register mapping information in other ROB entries from the bottom ROB entry to the target ROB entry.

[0010] In another exemplary aspect, a method of register mapping circuitry in a processor is disclosed. The method includes allocating a plurality of ROB entries in a reorder buffer (ROB) to a plurality of uncommitted instructions in a processor pipeline, including allocating a target ROB entry of the plurality of ROB entries to a target instruction of the plurality of uncommitted instructions and allocating other ROB entries of the plurality of ROB entries to other instructions of the plurality of uncommitted instructions, the other instructions including old instructions that precede the target instruction in the processor pipeline and young instructions that follow the target instruction in the processor pipeline. The method further includes capturing a rename map table snapshot having a logical register-to-physical register mapping state of a rename map table, the rename map table snapshot corresponding to a first other instruction of the other instructions, and storing the rename map table snapshot in association with the snapshot ROB entry allocated to the first other instruction of the other instructions. The method still further includes receiving an indication to flush instructions in the processor pipeline from the target instruction, and in response to the flush indication, restoring a logical register-to-physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry.

[0011] In another exemplary aspect, a method is disclosed that is executed by a register mapping circuit. The method includes allocating a plurality of ROB entries in a ROB to a plurality of uncommitted instructions in a processor pipeline, the allocating including allocating a target ROB entry of the plurality of ROB entries to a target instruction of the plurality of uncommitted instructions and allocating other ROB entries of the plurality of ROB entries to other instructions of the plurality of uncommitted instructions, the other instructions including old instructions that precede the target instruction in the processor pipeline and young instructions that follow the target instruction in the processor pipeline. The method further includes capturing at least one rename map table snapshot, each having a logical register-to-physical register mapping state of a rename map table, each rename map table snapshot corresponding to a respective one of the other instructions and storing the at least one rename map table snapshot in association with one of the other ROB entries allocated to the respective one of the other instructions. The method further includes receiving an instruction to flush instructions in the processor pipeline from the target instruction, and in response to the flush instruction, determining that a first number of other ROB entries between the target ROB entry and a closest one of the other ROB entries associated with the rename map table snapshot is greater than a second number of other ROB entries from the target ROB entry to an end ROB entry, the end ROB entry having one of a top ROB entry assigned to the oldest instruction among the old side instructions and a bottom ROB entry assigned to the newest instruction among the young side instructions.The method still further includes, in response to the ending ROB entry having the top ROB entry, restoring the logical register-physical register mapping state of the rename map table based on the CMT and register mapping information in other ROB entries from the top ROB entry to the target ROB entry, and, in response to the ending ROB entry having the bottom ROB entry, restoring the logical register-physical register mapping state of the rename map table based on the rename map table and register mapping information in other ROB entries from the bottom ROB entry to the target ROB entry. [Brief explanation of the drawings]

[0012] The accompanying drawing figures, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Figure 1] 1 is a schematic diagram of instruction processing circuitry including an instruction pipeline that processes computer instructions for execution, where register mapping circuitry, in combination with speculative instruction flow control, maintains the program order of committed instructions. [Figure 2] FIG. 1 is a schematic diagram of an instruction processing circuit including an exemplary register mapping circuit configured to restore a register mapping state of a rename map table based on a snapshot of a rename map table corresponding to another instruction in response to an indication of a target instruction. [Figure 3] 3 is a flowchart illustrating an exemplary process of the register mapping circuit of FIG. 2 for restoring the register mapping state of the rename map table based on a snapshot of the rename map table that captures the register mapping state for other instructions in response to an indication of a target instruction. [Figure 4]2 is a schematic diagram including components of the instruction processing circuit of FIG. 1 provided to describe a snapshot-based method for restoring the previous state of a corresponding rename map table when a target instruction to be flushed entered the processor. [Figure 5] 2 is a schematic diagram including components of the instruction processing circuit of FIG. 1 provided to describe a method for walking a reorder buffer (ROB) to restore the previous state of a corresponding rename map table when a target instruction to be flushed enters the processor. [Figure 6] 5 and 6 are schematic diagrams including components of the exemplary register mapping circuit of FIG. 2 to illustrate the previously known method of restoring the register mapping state of a rename map table in response to an indication of a target instruction by comparing it with snapshots of a rename map table corresponding to other instructions. [Figure 7] 3 is a schematic diagram including components of the exemplary register mapping circuit of FIG. 2 to illustrate a further example of restoring the register mapping state of a rename map table based on a snapshot of a rename map table corresponding to another instruction in response to an indication of a target instruction. [Figure 8] 3 is a block diagram of an exemplary processor-based system including a processor including the register mapping circuit of FIG. 2 configured to restore the register mapping state of a rename map table based on a snapshot of a rename map table corresponding to another instruction in response to an indication of a target instruction. DETAILED DESCRIPTION OF THE INVENTION

[0013] Exemplary aspects disclosed herein include restoring the register mapping state of a flushed instruction by traversing reorder buffer (ROB) entries within the processor using snapshots of other register mapping states. Instructions in a processor pipeline are committed in program order, even if they are processed out of order for efficiency. Because all instructions use the same logical register set, different instructions may use the same logical register operands for different purposes. For this reason, logical register operands for an instruction are mapped to unique physical registers using a rename map table. To maintain the most recent logical register-to-physical register mapping, the rename map table is updated each time a new instruction enters the processor pipeline. Updates from each instruction are stored in the corresponding reorder buffer (ROB) entry in program order. When a processor pipeline is flushed due to a target instruction that failed to execute as intended, all instructions following the target instruction may be flushed from the processor pipeline, and the rename map table state is restored to the logical register-to-physical register mapping state that existed before the target instruction entered the processor pipeline.

[0014] In this regard, one exemplary aspect discloses a register mapping circuit that restores a register mapping state associated with a flushed instruction by traversing ROB entries from one having a snapshot of the other register mapping state. The register mapping circuit includes a ROB control circuit, a snapshot circuit, and a register rename recovery circuit (RRRC). The ROB control circuit assigns ROB entries in the ROB to uncommitted instructions entering the processor's pipeline. The uncommitted instructions may include a target instruction and other instructions that are older or newer than the target instruction. The ROB entries include a target ROB entry assigned to the target instruction and other ROB entries assigned to the other instructions. The snapshot circuit is configured to capture snapshots of the rename map table state corresponding to only a subset of the uncommitted instructions that may be flushed. For example, the snapshot circuit may be configured to capture snapshots of the rename map table every given number of instructions or only for a predetermined ROB entry in the ROB. The snapshot circuit stores each rename map table snapshot in association with the snapshot ROB entry assigned to the corresponding instruction.

[0015] In the exemplary aspects disclosed herein, when the RRRC receives an indication from a target instruction to flush instructions in the pipeline, the RRRC restores the logical register-to-physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry. That is, the RRRC first restores the rename map table to the state of the snapshot from another instruction in the ROB, and then walks through the updates stored in the ROB entries of the intervening instructions to restore the register mapping state of the target instruction. The RRRC first restores the rename map table to the state of the snapshot from another instruction in the ROB because the snapshot circuitry is not configured to capture rename map table snapshots for all instructions or for all instructions that may be flushed. Thus, to restore the rename map table, the RRRC may be required to walk the ROB between the entry assigned to the target instruction and the entries of other instructions that have captured rename map table snapshots. Thus, the snapshot circuitry does not need to capture rename map table snapshots for every instruction that may be flushed, and the amount of snapshot resources required by the register mapping circuitry is reduced compared to snapshot-based restore. Furthermore, using rename map table snapshots captured in association with uncommitted instructions significantly reduces the number of ROB entries that must be walked to or from a target ROB entry in a typical flush compared to typical ROB walking methods.

[0016] 1 illustrates an instruction processing circuit 100 provided in a CPU core 102 within a processor 104. The instruction processing circuit 100 includes one or more instruction pipelines I0-I1 for processing computer instructions 106F fetched for execution by an instruction fetch circuit 108 from a set of instructions 106 stored, for example, in an instruction cache memory 110 or an instruction memory 112. N The instruction fetch circuitry 108 transmits the fetched instructions 106F to one or more instruction pipelines I0-I1 as an instruction stream 114 in the instruction processing circuitry 100. N The instruction pipelines I0-I1 are configured to provide the fetched instructions 106F with preprocessing before they reach the execution circuitry 116 for execution. N are provided across multiple different processing circuits or stages of instruction processing circuitry 100 to pre-process and process fetched instructions 106F in a series of steps that can be performed simultaneously to improve throughput, prior to execution of fetched instructions F by execution circuitry 116.

[0017] 1, instruction processing circuitry 100 includes instruction decode circuitry 118 configured to decode fetched instructions 106F fetched by instruction fetch circuitry 108 into decoded instructions 106D to determine the instruction type and required action. N , P0, P1, ..., P2, ..., P3, ..., P4, ..., P5, ..., P6, ..., P7, ..., P8, ..., P9, ..., P10, ..., P11, ..., P12, ..., P13, ..., P14, ..., P15, ..., P16, ..., P17, ..., P18, ..., P19, ..., P20, ..., P21, ..., P22, ..., P23, ..., P24, ..., P25, ..., P26, ..., P27, ..., P28, ..., P29, ..., P30, ..., P31, ..., P32, ..., P40, ..., P41, ..., P42, ..., P43, ..., P44, ..., P45, ..., P46, ..., P47, ..., P48, ..., P49, ..., P50, ..., P51, ..., P52, ..., P53, ..., P54, ..., P55, ..., P56, ..., P57, ..., P58, ..., P59, ..., P60, ..., P61, ..., P62, ..., P63, ..., P64, ..., P65, ..., P66, ..., P67, ..., P68, ..., P69, ..., P70, ..., P71, ..., P72, ..., P73, ..., P74, ..., P75, ..., P76, ..., P77, ..., P78, ..., P79, ..., P80, ..., P81, ..., P82, ..., P83, ..., P84, ..., P85, ..., P90, ..., P91, ..., P92, ..., P93, ..., P94, ..., P95, ..., P96, ..., P106, X ) to request that the RMT 122 rename each of the logical registers R0-RP The mapping entries are configured to store information in the form of address pointers to physical registers 124(1)-124(X) of PRF 126. Each physical register 124(1)-124(X) in PRF 126 is configured to store data for a source and / or destination register operand of decoded instruction 106D.

[0018] Instruction processing circuit 100 also includes logical registers R0-R1, which are designated as source register operands of decoded instruction 106D. P The instruction processing circuit 100 also includes a register access (RACC) circuit 128 configured to access one of the physical registers 124(1)-124(X) in the PRF 126 that is designated by a mapping entry in one of the instruction pipelines 106(1)-106(X). The RACC circuit 128 retrieves a value in the PRF 126 that was generated by an instruction 106E that was previously executed in the execution circuit 116. Also in the instruction processing circuit 100, a scheduler circuit 130 schedules instruction pipelines 106(1)-106(X) in the PRF 126. N and configured to store the decoded instruction 106D in the reservation entry until all of the source register operands of the decoded instruction 106D are available. Write circuitry 132 is provided in the instruction processing circuitry 100 for writing back (i.e., committing) values ​​generated from the executed instruction 106E to memory, such as the PRF 126, a data cache memory system (not shown), or main memory (not shown).

[0019] 1, instruction processing circuitry 100 also includes flow control prediction circuitry 134. Flow control prediction circuitry 134 determines which path within the instruction control flow path of instruction stream 114, such as a conditional branch instruction, will be selected for execution in instruction pipelines I0-I1. NThe flow control prediction circuit 134 is configured to speculatively predict the outcome of a condition of a fetched conditional flow control instruction 106F that controls whether a given instruction 106 is fetched into the instruction processing circuit 100. With accurate speculative prediction, the condition of the fetched conditional flow control instruction 106F does not need to be resolved upon execution by the execution circuit 116, and the instruction processing circuit 100 can then continue to speculatively process the fetched instruction 106F. The prediction made by the flow control prediction circuit 134 is provided to the instruction fetch circuit 108 as prediction information 136 and is used by the instruction fetch circuit 108 to determine which instruction 106 to fetch next.

[0020] However, if, when the conditional flow control instruction 106F is executed by the execution circuitry 116, it is determined that the condition of the conditional flow control instruction 106F was incorrectly predicted, the instruction 106F is aborted. N Speculatively fetched instructions 106F processed in the FIFO are flushed because the direction of program flow is not as expected and does not include processing of these instructions. A load or store instruction 106F for which the calculated address of a memory location may be invalid or inaccessible for some other reason may also cause a flush of subsequent instructions 106F. Under these conditions, program flow in the instruction processing circuit 100 is aborted, and the instruction processing circuit 100 is restored to its previous state. The previous state to which the instruction processing circuit 100 is restored depends on the type of aborted instruction and may be the state that existed before or as a result of the aborted instruction 106F, which is the target instruction of the flush. The CPU core 102 includes a register mapping circuit 138, which includes the RMT 122 and the PRF 126, to maintain logical register-to-physical register mapping. The register mapping circuit 138 is responsible for updating the instruction pipelines I0-I1 of the processing circuit 100 after the target instruction 106 in the event of a flush due to the target instruction. NThe logical register to physical register mapping control circuit 140 is capable of restoring the logical register to physical register mapping state that may have been altered by the instruction 106 entered into the logical register to physical register mapping control circuit 140.

[0021] Continuing to refer to FIG. 1, the register mapping circuit 138 also includes a reorder buffer (ROB) 142 that contains entries (“ROB entries”) 144(1)-144(N) assigned to instructions 106 (“uncommitted instructions”) that are being processed by the instruction processing circuit 100 but have not yet been committed. A ROB index identifies the location of each ROB entry 144(1)-144(N) within the ROB 142. The ROB entries 144(1)-144(N) are assigned to instructions 106 in program order. The ROB entry 144(1)-144(N) assigned to the oldest uncommitted instruction 106 within the ROB 142 is known as the head entry 146. The head entry 146 becomes the next ROB entry 144(1)-144(N) once the oldest uncommitted instruction 106 is committed. The instruction pipelines I0-I N The new ROB entry 144(1)-144(N) assigned to the newest uncommitted instruction 106 entering the ROB table is known as the tail entry 148. The tail entry 148 changes each time a new instruction 106 is assigned a new ROB entry 144(1)-144(N). The ROB index for each instruction 106 is reported to the instruction processing circuitry 100 when the instruction 106 is first assigned a ROB entry 144(1)-144(N). In this way, the instruction processing circuitry 100 can identify the ROB index assigned to the target instruction 106. The logical registers R0-R1 in the RMT 122 as a result of the instruction 106 P Information about changes to the mapping of an instruction 106 ("register mapping information") is stored in association with the ROB entry 144(1)-144(N) assigned to that instruction 106. The register mapping information stored for an uncommitted instruction 106 is used to accomplish RMT 122 restoration in response to a flush.

[0022] Continuing with FIG. 1, the register mapping circuit 100 also maps each logical register R0-R1 of the processor 104 to a corresponding logical register R2 as a result of the committed instruction 106. P The RMT 122 includes a committed map table (CMT) 150 of mapping entries in which the logical register-to-physical register mappings of instructions 106 are stored. The CMT 150 is updated only when an instruction 106 is committed. The CMT 150 is not modified in response to a flush. The mapping control circuit 140 controls the register mapping circuit 138, which includes managing the flush restoration of the RMT 122.

[0023] FIG. 2 illustrates an exemplary register mapping circuit 200 within an instruction processing circuit 202 according to the present disclosure. The register mapping circuit 200 performs register mapping as described with respect to the register mapping circuit 138 of FIG. 1, but the register mapping circuit 200 is optimized for restoring logical register-to-physical register mapping state from a pipeline flush of a target instruction by using snapshots of the RMT 204 corresponding to instructions other than the target instruction, as described below. The register mapping circuit 200 of FIG. 2 includes a RMT 204, a CMT 206, and a ROB 208. The RMT 204 and CMT 206 contain entries including logical register names (LRNs) and associated physical register names (PRNs) to indicate the logical register-to-physical register mapping or relationship for an instruction. The physical register names identify physical registers within a physical register file (not shown in FIG. 2). The register mapping circuit 200 is controlled by a mapping control circuit 210 that interfaces to the instruction processing circuit 202.

[0024] Although not shown in FIG. 2, the instruction processing circuitry 202 includes the instruction decode circuitry 118, the rename circuitry 120, the RACC circuitry 128, and the scheduler circuitry 130, and is a part of the instruction pipelines I0-I1 of the instruction processing circuitry 100 of FIG. NThe processing circuitry 202 also includes, but is not shown, the instruction pipelines I0-I1, including the instruction fetch circuitry 108, the flow control prediction circuitry 134, the execution circuitry 116, and the write circuitry 132. N 1 at each end, and may also include an optional instruction cache 110. These circuits operate within instruction processing circuit 202 as described above with respect to instruction processing circuit 100 of FIG.

[0025] The instruction 212 is input to the instruction pipelines I0-I1 of the instruction processing circuit 202. N When the instruction 212 enters the instruction pipeline I0-I1, the logical register-to-physical register mapping state ("register mapping state") in the RMT 204 is updated. N The register mapping state of RMT 204 includes the logical register-to-physical register mapping state of all architected registers of instruction processing circuit 202 at the time of entry into instruction pipelines I0-I1. N The instruction flow is interrupted and the instruction pipeline I0-I1 after the target instruction 216 is updated with register mapping information 214 (i.e., information pointing to the physical registers to which the logical registers are mapped for the corresponding instruction) for each new instruction entering the target instruction pipeline. N All instructions within (i.e., all "young side instructions 212") are flushed. The target instruction 216 is the instruction that changes flow control and is referred to herein as the target of the flush. Instructions prior to the target instruction 216 ("old side instructions 212") are not affected by the flush. Depending on the type of target instruction 216, the register mapping information 214 of the target instruction 216 may or may not be overridden (i.e., undone) when restored from the flush.

[0026] Under normal operation, ROB control circuitry 218 assigns target instruction 216 a target ROB entry 220 in ROB 208. ROB control circuitry 218 also controls whether other instructions are being routed through instruction pipelines I0-I1. N When the RMT 204 is entered, it is assigned another ROB entry 222. All other instructions 212 are uncommitted instructions 212, including old side instructions 212 and young side instructions 212. As will be further described below, a snapshot circuit 224 in register mapping circuit 200 captures a snapshot of RMT 204 ("RMT snapshot 226"), which is then sent to instruction pipelines I0-I1. N The snapshot circuit 224 captures an RMT snapshot 226 corresponding to the instruction 212, and the RMT snapshot 226 is associated with a snapshot ROB entry 227 in the ROB 208. The RMT snapshot 226 may be captured before or after the RMT 204 is modified by the register mapping information 214 of the corresponding instruction 212.

[0027] Storing the RMT snapshot 226 in association with the snapshot ROB entry 227 may involve storing the RMT snapshot 226 in the snapshot ROB entry 227 of the ROB 208 or in another register, table, or memory that can be referenced, for example, by an index in the snapshot ROB entry 227. Other means for storing the RMT snapshot 226 in association with the ROB entry 222 are within the scope of this disclosure. To identify which ROB entries 222 are snapshot ROB entries 227, the location of the snapshot ROB entry 227 associated with the RMT snapshot 226 may be tracked or recorded, for example, in a list or table. Alternatively, each ROB entry 222 may include an indicator, and the indicator in the snapshot ROB entry 227 may be updated to indicate that the snapshot ROB entry 227 is associated with the RMT snapshot 226. As disclosed herein, the snapshot circuit 224 of the register mapping circuit 200 does not capture RMT snapshots 226 corresponding to all instructions 212 that can be targets of a flush.

[0028] The register mapping circuit 200 controls the instruction pipelines I0-I NWhen the register mapping circuit 200 receives an instruction to flush an instruction in the register mapping circuit 200 and identifies the target instruction 216, the register rename restore circuit (RRRC) 228 receives the flush instruction. The flush instruction may be an electrical signal at a certain voltage or current level received by the register mapping circuit 200. In response to the flush instruction, the RRRC 228 restores the register mapping state of the RMT 204 to the state corresponding to the target instruction 216. As described below with reference to FIG. 4 , the snapshot circuit 224 will occasionally capture an RMT snapshot 226 corresponding to the target instruction 216. In this case, the register mapping state of the RMT 204 can be restored by simply copying the RMT snapshot 226 to the RMT 204. However, because such an approach requires significant snapshot resources, as described above, the snapshot circuit 224 of the register mapping circuit 200 does not capture RMT snapshots 226 corresponding to all instructions 212 that may be targets of a flush. If there is no RMT snapshot 226 associated with the target instruction 216, the register mapping state of the RMT 204 corresponding to the target instruction 216 may be restored based on the RMT snapshot 226 stored in association with the snapshot ROB entry 227 assigned to one of the other instructions 212.

[0029] To better understand the operation of the register mapping circuit 200, a detailed description of several scenarios for restoring the register mapping state of the RMT 204 under various circumstances will be provided with reference to FIG. 2 . In a first example, the RRRC 228 can use an RMT snapshot 226 that is older than the target instruction 216. In the first situation under this example, an RMT snapshot 226 corresponding to the next-oldest uncommitted instruction 212 (i.e., the next-oldest after the target instruction 216) has been captured by the snapshot circuit 224. The RMT snapshot 226 for the next-oldest instruction 212 is associated with a snapshot ROB entry 227 that is adjacent to the target ROB entry 220. Therefore, no other ROB entries 222 are between the target ROB entry 220 and the snapshot ROB entry 227. As described above, the RMT snapshot 226 can be captured before or after the register mapping information 214 of the next-oldest instruction 212 is applied to the RMT 204. If the RMT snapshot 226 is captured after the register mapping information of the next-oldest instruction 212 has been applied, then the RMT snapshot 226 corresponds to the register mapping state of the RMT 204 immediately before the target instruction 216, and when the register mapping information of the target instruction 216 is flushed, the register mapping state of the RMT 204 is restored by simply copying the RMT snapshot 226 to the RMT 204. Copying the RMT snapshot 226 corresponding to the old-side instruction 212 into the register mapping state of the RMT 204 restores the register mapping state of the RMT 204 to the state where the old-side instruction 212 was in the instruction pipeline I0-I1. N 204 was most recently entered, effectively undoing all changes to the RMT 204 since that state existed.

[0030] In a second situation, which is a variation on the first situation above, if the RMT snapshot 226 corresponding to the next-oldest uncommitted instruction 212 is captured by the snapshot circuitry 224 before the register mapping information 214 of the next-oldest instruction 212 is applied to the RMT 204, then the effect of the register mapping information 214 of the next-oldest instruction 212 needs to be discarded. Thus, after the RMT snapshot 226 is copied to the RMT 204, the RRRC 228 retrieves the register mapping information of the next-oldest instruction 212 from the other ROB entry 222 assigned to the next-oldest instruction 212 to restore the register mapping state of the RMT 204 to the state corresponding to the target instruction 216.

[0031] In a third situation, which is a variation on either the first or second situations above, the register mapping information for the target instruction 216 is not flushed for that instruction type. Thus, after the RMT snapshot 226 is copied to the RMT 204, the RRRC 228 obtains the register mapping information 214 for the target instruction 216 from the target ROB entry 220 and modifies the register mapping information 214 in the register mapping state of the RMT 204 accordingly. Modifying the register mapping state of the RMT 204 based on the register mapping information 214 from the target ROB entry 220 or from one of the other ROB entries 222 after copying the contents of the RMT snapshot 226 corresponding to the old instruction 212 to the RMT 204 is redoing or reapplying the changes made by such register mapping information 214.

[0032] In a fourth situation under the first example, the RMT snapshot 226 corresponding to the next-oldest uncommitted instruction 212 has not been captured by the snapshot circuitry 224. In this situation, the closest RMT snapshot 226 corresponding to the other instruction 212 corresponds to an old-side instruction 212 assigned to a snapshot ROB entry 227 that is not adjacent to the target ROB entry 220. The snapshot ROB entry 227 may be separated from the target ROB entry 220 by several other ROB entries 222, depending on the size of the ROB 208. In this situation, the RRRC 228 first copies the contents of the RMT snapshot 226 corresponding to that old-side ROB instruction 212 to the RMT 204. Next, if the second situation above applies (i.e., the RMT snapshot 226 was captured before the register mapping information 214 of the old-side instruction 212 was applied to the RMT 204), the RRRC 228 obtains the register mapping information 214 from the snapshot ROB entry 227 and modifies the RMT 204. Then, for each other ROB entry 222 between the snapshot ROB entry 227 and the target ROB entry 220, the RRRC 228 obtains register mapping information 214 from the other ROB entry 222 and modifies the RMT 204 based on the register mapping information 214 from the other ROB entries 222, sequentially from the snapshot ROB entry 227 to the target ROB entry 220. This sequential application of register mapping information 214 from the other ROB entries 222 is referred to herein as “walking” the other ROB entries 222. If the target instruction 216 is not flushed, as in the third situation above, the register mapping information 214 in the target ROB entry 220 assigned to the target instruction 216 may also be obtained and applied to the RMT 204 to restore the register mapping state of the RMT 204.

[0033] In the above example, even if snapshot ROB entry 227 is away from target ROB entry 220 by some number of other ROB entries 222, snapshot ROB entry 227 is still closer to target ROB entry 220 than the current head entry 230 of ROB 208, which is assigned to the oldest uncommitted instruction 212. Thus, walking the other ROB entries 222 from RMT snapshot 226 associated with snapshot ROB entry 227 requires walking fewer other ROB entries 222 than would be required if the register mapping state of RMT 204 were restored from CMT 206, as described further below.

[0034] In a second example, the RRRC 228 may use an RMT snapshot 226 that is more recent than the target instruction 216. In a fifth situation, under the second example, the young RMT snapshot 226 corresponding to the next-new uncommitted instruction 212 may have been captured by the snapshot circuitry 224 before or after the register mapping information 214 of the next-new instruction 212 was applied to the RMT 204. The young RMT snapshot 226 is associated with a snapshot ROB entry 227 that is adjacent to the target ROB entry 220. Thus, no other ROB entries 222 are between the target ROB entry 220 and the snapshot ROB entry 227. If the young RMT snapshot 226 was captured after the register mapping information of the next-new instruction 212 was applied, then the RMT snapshot 226 would correspond to the register mapping state of the RMT 204 immediately after the target instruction 216. If the register mapping information for the target instruction 216 is not flushed, the register mapping state of the RMT 204 may be restored by copying the young side RMT snapshot 226 to the RMT 204. Copying the young side RMT snapshot 226 corresponding to the young side instruction 212 into the register mapping state of the RMT 204 restores the register mapping state of the RMT 204 to the state it had when the young side instruction 212 was the youngest instruction, effectively undoing all changes to the RMT 204 from any other instructions more recent than the young side instruction 212 (i.e., from the young side instruction 212 to the young side instruction 212 allocated to the tail entry 232 of the ROB 208).

[0035] In a sixth situation, which is a variation on the fifth situation above under the second example, if the young RMT snapshot 226 corresponding to the next-new uncommitted instruction 212 is captured by the snapshot circuit 224 after the register mapping information 214 of the next-new instruction 212 has been applied to the RMT 204, it will be necessary to discard the effect of the register mapping information 214 of the next-new instruction 212 on the RMT 204. Thus, after the young RMT snapshot 226 is copied to the RMT 204, the RRRC 228 retrieves the register mapping information 214 of the next-new instruction 212 from the other ROB entry 222 allocated to the next-new instruction 212 and discards (undoes) the effect of the register mapping information 214 applied by the next-new instruction 212 to the register mapping state of the RMT 204. Thus, the register mapping state of the RMT 204 corresponding to the target instruction 216 is restored.

[0036] In a seventh situation, which is a variation on either the fifth or sixth situations above under the second example, the register mapping information 214 of the target instruction 216 is flushed. Thus, after the young side RMT snapshot 226 is copied to the RMT 204, the RRRC 228 obtains the register mapping information 214 of the target instruction 216 from the target ROB entry 220 and modifies the register mapping information 214 in the register mapping state of the RMT 204 accordingly. Modifying the register mapping information 214 in the register mapping state of the RMT 204 based on the register mapping information 214 from the target ROB entry 220 or from one of the other ROB entries 222 after copying the contents of the young side RMT snapshot 226 corresponding to the young side instruction 212 to the RMT 204 is to undo or discard the register mapping changes made by that young side instruction 212.

[0037] In an eighth situation under the second example, the young side RMT snapshot 226 corresponding to the next-young uncommitted instruction 212 has not been captured by the snapshot circuit 224. In this situation, the closest young side RMT snapshot 226 corresponds to other instructions 212 assigned to a snapshot ROB entry 227 that is not adjacent to the target ROB entry 220. In this situation, the snapshot ROB entry 227 may be separated from the target ROB entry 220 by a certain number of other ROB entries 222. Here, the RRRC 228 first copies the contents of the RMT snapshot 226 corresponding to that young side ROB instruction 212 to the RMT 204. Next, if the second situation above applies (i.e., the young-side RMT snapshot 226 was captured after the register mapping information 214 of the young-side instruction 212 was applied to the RMT 204), the RRRC 228 obtains the register mapping information 214 from the snapshot ROB entry 227 and modifies the RMT 204 (discarding the effect of the register mapping information 214 on the RMT 204). Then, for each of the other ROB entries 222 between the snapshot ROB entry 227 and the target ROB entry 220, the RRRC 228 obtains the register mapping information 214 from the other ROB entry 222 and modifies the RMT 204 based on the register mapping information 214 from the other ROB entry 222, sequentially from the snapshot ROB entry 227 to the target ROB entry 220. When the target instruction 216 is flushed, as in the seventh situation above under the second example above, the register mapping information 214 of the target instruction 216 may also be obtained from the target ROB entry 220 and discarded in the RMT 204 to restore the register mapping state of the RMT 204 to the state corresponding to the target instruction 216.

[0038] In a second example where the RRRC 228 uses a young RMT snapshot 226, the snapshot ROB entry 227 is closer to the target ROB entry 220 than the current tail entry 230 of the ROB 208, which is the entry assigned to the newest uncommitted instruction 212. Thus, walking the other ROB entries 222 backward from the RMT snapshot 226 associated with the snapshot ROB entry 227 requires walking fewer other ROB entries 222 backward than walking the other ROB entries 222 backward from the tail entry 232 if the young RMT snapshot 226 were not present.

[0039] In a third example, instead of statically using the old-side RMT snapshot 226 or statically using the young-side RMT snapshot 226, the RRRC 228 determines a first number of other ROB entries 222 between the target ROB entry 220 and the old-side snapshot ROB entry 227 (the snapshot ROB entry 227 between the head entry 230 and the target ROB entry 220), and determines a second number of other ROB entries 222 between the target ROB entry 220 and the young-side snapshot ROB entry 227 (the snapshot ROB entry 227 between the tail entry 232 and the target ROB entry 220). Next, the RRRC 228 determines that the first number is less than the second number, which means that fewer other ROB entries 222 need to be walked when restoring the register mapping state of the RMT 204 by walking the other ROB entries 222 on the old side than when restoring the register mapping state of the RMT 204 by walking the other ROB entries 222 on the young side. To reduce the time required to restore the register mapping state of the RMT 204, the RRRC 228 may dynamically choose to walk a shorter path with a smaller number of other ROB entries 222, as described above.

[0040] The illustrations of ROB 208, mapping control circuit 210, RMT 204, and CMT 206 are merely examples for purposes of illustrating the circuits and processes disclosed herein and are not intended to limit the present disclosure. For example, the number of ROB entries 222 in ROB 208 may be greater or fewer than those shown, and may contain more or other information than that shown and disclosed herein. RMT 204 and CMT 206 may also contain a different number of entries and different data than that shown in FIG. 2, and the present disclosure is not limited in this respect.

[0041] 3 illustrates a flowchart of an exemplary process 300 of the register mapping circuit 200 of FIG. 2 for restoring the register mapping state of the RMT 204 to the state corresponding to the target ROB entry 220 using an RMT snapshot 226 corresponding to another instruction 212. The process 300 transfers multiple ROB entries 220, 222 in the ROB 208 to the processor pipelines I0-I1. N (block 302), which includes allocating a target ROB entry 220 of the plurality of ROB entries 220, 222 to a target instruction 216 of the plurality of uncommitted instructions 212 (block 304), and allocating another ROB entry 222 of the plurality of ROB entries 222 to another instruction 212 of the plurality of uncommitted instructions 212 (block 306), the other instruction being allocated to one of the processor pipelines I0-I1. N The old instruction 212 before the target instruction 216 in the processor pipeline I0-I Nand a young instruction 212 after the target instruction 216 in the other instructions 212. The process 300 further includes capturing an RMT snapshot 226 (block 308) that includes a logical register-to-physical register mapping state of the RMT 204, the RMT snapshot 226 corresponding to a first other instruction 212 of the other instructions 212. The process 300 also includes storing the RMT snapshot 226 (block 310) in association with a snapshot ROB entry 227 assigned to the first other instruction 212 of the other instructions 212. The process 300 also includes capturing a logical register-to-physical register mapping state of the RMT 204 in the other instructions 212. N The process 300 further includes receiving an indication to flush the instructions in the RMT 204 (block 312). In response to the flush indication, the process 300 still further includes restoring the logical register-to-physical register mapping state of the RMT 204 to a state corresponding to the target instruction 216 based on the RMT snapshot 226 stored in association with the snapshot ROB entry 227 (block 314).

[0042] The process 300 of the register mapping circuit 200 restores the register mapping state of the RMT 204 to the state corresponding to the target instruction 216 based on the RMT snapshot 226 corresponding to the other instruction 212, and by walking the other ROB entries 222, if any, between the snapshot ROB entry 227 associated with the RMT snapshot 226 and the target ROB entry 220. The determination of the other instruction 212 for which the corresponding RMT snapshot 226 is captured can be customized according to various factors, such as test results, statistical analysis, program type, history results, worst-case snapshot resource required, etc. For example, if the Nth instruction (where N is an integer) is in the instruction pipeline I0-I1, N, resulting in an RMT snapshot 226 being stored in association with every Nth ROB entry 222. Alternatively, an RMT snapshot 226 may be captured every Nth branch instruction. In another example, RMT snapshots 226 may be captured to correspond only to instructions 212 that are likely to be mispredicted, e.g., based on a probability threshold determined by a heuristic. For example, a history of which conditional instructions are likely to be mispredicted may be kept and used to generate the probability threshold. Other methods of determining when to capture an RMT snapshot 226 are possible.

[0043] The above-described method for determining when an RMT snapshot 226 is captured differs from the previously known snapshot-based method described with reference to FIG. 4. FIG. 4 is another diagram of the register mapping circuit 138 of FIG. 1, including only the RMT 122, the ROB 142, and the CMT 150. The ROB 142 includes a head entry 146 and a tail entry 148. FIG. 4 also includes diagrams of RMT snapshots 402 and 404, which are copies of the RMT 122. The RMT snapshots 402 and 404 are associated with ROB entries 406 and 408, respectively. That is, the RMT snapshot 402 is a copy of the register mapping state of the RMT 122 associated with the snapshot ROB entry 406, and the RMT snapshot 404 is a copy of the register mapping state of the RMT 122 associated with the snapshot ROB entry 408. Snapshot ROB entry 406 is assigned to a first conditional branch instruction 410, and snapshot ROB entry 408 is assigned to a second conditional branch instruction 412. In accordance with the method implemented as shown in FIG. 4, RMT snapshots are captured only for instructions that may cause a flush (e.g., due to a misprediction), and are captured to correspond to all instructions that may cause a flush. The fact that RMT snapshots 406 and 408 are the only snapshots associated with any of entries 144(1)-144(N) in ROB 142 means that only the first and second conditional branch instructions 410 and 412 are assigned to instruction pipelines I0-I1 that may cause a flush. N4 indicates that the instruction is within the specified range. Therefore, in this method, there is an RMT snapshot 406, 408 corresponding to every instruction that can cause a flush, and by copying the corresponding RMT snapshot 406, 408 to the RMT 122, the register mapping state of the RMT 122 can be instantly restored to the state corresponding to instruction 410 or 412. Because the ROB entries are not "walked" in this method, register mapping information from ROB entries 144(1)-144(N) is not required. However, the snapshot-based method of FIG. 4 may require a large number of snapshot resources to store the snapshots in a worst-case scenario. For example, the actual number of ROB entries 144(1)-144(N) may be significantly larger than the number of ROB entries 144(1)-144(N) shown in FIG. 4. If all ROB entries 144(1)-144(N) are assigned to conditional branch instructions that may result in flushing, RMT snapshots must be saved for all of those many ROB entries 144(1)-144(N), requiring significant additional snapshot resources within instruction processing circuit 100. If snapshot resources are insufficient, the instruction pipeline will be stalled until snapshot resources are available, which may cause delays in instruction processing circuit 100.

[0044] Another previously known method that does not require snapshot resources is described with reference to FIG. 5. FIG. 5 is another diagram of register mapping circuit 138 of FIG. 1, including only RMT 122, ROB 142, and CMT 150. Rather than capturing an RMT snapshot that can be copied to RMT 122, the method of walking ROB entries 144(1)-144(N) avoids the use of snapshot resources entirely. For example, target ROB entry 502 in ROB 142 is assigned to target instruction 504 (e.g., a conditional branch instruction) that can cause a flush. In this case, because there is no RMT snapshot available, the only known state of RMT 122 is the current state of RMT 122 and the state of CMT 150 at the time of the last committed instruction.

[0045] Register mapping circuit 138 may determine to “walk” ROB entries 144(1)-144(N) between target ROB entry 502 and head entry 146 by obtaining register mapping information for each instruction assigned to ROB entries 144(1)-144(N) and sequentially redoing or undoing the effects of that register mapping information (depending on the walking direction). For example, as described above, CMT 150 can be copied to RMT 122, and instructions can be walked back from head entry 146 to target ROB entry 502. Alternatively, all register mapping information in RMT 122 that has changed since target instruction 504 can be identified and restored by sequentially walking back through ROB entries 144(1)-144(N) from target ROB entry 502 to head entry 146, completing the restoration with register mapping information from CMT 150.

[0046] 5 can also decide to walk the ROB entries between the target ROB entry 502 and the tail entry 148. Specifically, the ROB entries 142 can be walked from the target ROB entry 502 to the tail entry 148, or from the tail entry 148 back to the target ROB entry 502. Alternatively, the register mapping circuit 138 can select the direction to walk (i.e., to / from the head entry 146 or to / from the tail entry 148) depending on where the target ROB entry 502 is at the time of the flush and which direction allows for faster restoration of the register mapping state of the RMT 122.

[0047] Figure 6 is a diagram of the RMT 204, CMT 206, and ROB 208 of Figure 2 for reference in further description of the example register mapping circuit 200 of Figure 2. As will be explained, the register mapping circuit 200 of Figure 2 may, under certain circumstances, operate in accordance with the previously known methods described above with respect to Figures 4 and 5.

[0048] In Figure 6, if snapshot circuitry 224 happens to capture an RMT snapshot 226 associated with target ROB entry 220 (assigned to target instruction 216), the register mapping state of RMT 204 can be restored to the state corresponding to target instruction 216 by simply copying RMT snapshot 226 to RMT 204 in a manner similar to the snapshot-based method described with reference to Figure 4. However, that is not typically the case in Figure 6 because register mapping circuitry 200 does not have an RMT snapshot 226 corresponding to every instruction that can result in a flush. Therefore, if an RMT snapshot 226 corresponding to target instruction 216 has not been captured, the register mapping state of RMT 204 must be restored based on a known state of RMT 204, such as an RMT snapshot 226 associated with another ROB entry 222 or CMT 206 on the young side. Between the target ROB entry 220 assigned to the target instruction 216 in the ROB 208 and the head entry 230 assigned to the oldest uncommitted instruction 212, there are two old other ROB entries 222. Between the target ROB entry 220 and one of the other ROB entries 222, the snapshot ROB entry 227 associated with the RMT snapshot 226, there are five young other ROB entries 222 in the ROB 208. Therefore, restoring the register mapping state of the RMT 204 based on the CMT 206 only requires copying the CMT 206 to the RMT 204 and walking the head entry 230 and the two old other ROB entries 222. On the other hand, restoring the register mapping state of the RMT 204 based on the RMT snapshot 226 requires walking the five young other ROB entries 222.If walking the two old side other ROB entries 222 based on the CMT 206 can restore the RMT 204 faster than walking the five young side other ROB entries 222 based on the RMT 222 snapshot 226, the register mapping circuit 200 may choose to restore the RMT 204 based on the CMT 206 in a manner similar to that described with respect to FIG. 5.

[0049] FIG. 7 is another diagram of the register mapping circuit 200 of FIG. 2, including the RMT 204, the CMT 206, and the ROB 208. The RRRC 228 of the mapping control circuit 210, the ROB control circuit 218, and the snapshot circuit 224 are not shown here. The snapshot circuit 224 captures one of the RMT snapshots 226(1)-226(3) every Nth instruction 212, where N=5. RMT snapshot 226(1) corresponds to instruction 212(1), RMT snapshot 226(2) corresponds to instruction 212(6), and RMT snapshot 226(3) corresponds to instruction 212(11). Thus, every fifth other ROB entry 222 is assigned to one of the other instructions 212. The target ROB entry 220 is assigned to the target instruction 216, which is a conditional branch instruction whose condition is mispredicted and indicates a flush. A further example of the operation of the register mapping circuit 200 based on the above scenario will now be described with reference to FIG.

[0050] In a first example of restoring the register mapping state of RMT 204 to the state corresponding to target ROB entry 220 using RMT snapshot 226 corresponding to other instruction 212, RRRC 228 uses old RMT snapshot 226 in snapshot ROB entry 227. In this example, the register mapping state of RMT 204 is restored based on RMT snapshot 226(1) corresponding to other instruction 212(1).

[0051] In a second example, RRRC 228 uses young-side RMT snapshot 226. Here, young-side RMT snapshot 226(2) and young-side RMT snapshot 226(3) currently exist. RRRC 228 can determine a first number of other ROB entries 222 between RMT snapshot 226(2) and the snapshot ROB entry 227 associated with it, and a second number of other ROB entries 222 between RMT snapshot 226(2) and the snapshot ROB entry 227 associated with it, and RMT snapshot 226(3). In this case, because there are fewer other ROB entries 222 to walk, the register mapping state of RMT 204 can be restored in a shorter amount of time based on RMT snapshot 226(2).

[0052] In a third example, the RRRC 228 may determine the closest snapshot ROB entry 227 associated with the RMT snapshot 226 in each direction (i.e., the direction in which fewer other ROB entries 222 will be walked) and select the option with the fewer number. In Figure 7, the RMT snapshot 226(2) is associated with the closest snapshot ROB entry 227 and is selected to complete the restore in the shortest time.

[0053] FIG. 8 is a block diagram of an exemplary processor-based system 800 including a processor 802 (e.g., a microprocessor) that includes an instruction processing circuit 804. The processor-based system 800 may, for example, be the instruction processing circuit 100 of FIG. 1 . The instruction processing circuit 804 may, for example, be the instruction processing circuit 202 of FIG. 2 . The processor-based system 800 may represent one or more circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. The processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or the like. More specifically, the processor 802 may be an EDGE instruction set microprocessor or other processor that implements an instruction set that supports explicit consumer naming for communicating generated values ​​obtained by execution of producer instructions. Processor 802 is configured to execute instruction processing logic to perform the operations and steps described herein. In this example, processor 802 includes an instruction cache 808 for temporary, fast-access memory storage of instructions accessible by instruction processing circuitry 804. Instructions fetched or prefetched from memory, such as from main memory 810 over system bus 812, are stored in instruction cache 808. Instruction processing circuitry 804 is configured to process instructions fetched into instruction cache 808 and prepare those instructions for execution. The processor 802 may include an RRRC 814 that restores the state of the RMT in the instruction processing circuit 804 in response to a flush instruction that instructs the flushing of some instructions in the instruction pipeline due to an instruction failure. The processor 802 may be the processor 104 of FIG. 1 that may be configured to minimize traversal of a reorder buffer in restoring the RMT. The processor-based system 800 may also include a cache memory 816 that temporarily stores data from the main memory 810 for fast access by the processor 802.

[0054] The processor 802 and main memory 810 are coupled to a system bus 812, which can interconnect peripheral devices included in the processor-based system 800. As is well known, the processor 802 communicates with these other devices by exchanging address, control, and data information over the system bus 812. For example, the processor 802 can communicate bus transaction requests to a memory controller 819 in the main memory 810, which serves as an example of a slave device. Although not shown in FIG. 8, multiple system buses 812 may be provided, with each system bus constituting a different fabric. In this example, the memory controller 819 is configured to provide memory access requests to a memory array 820 in the main memory 810. The memory array 820 comprises an array of storage bit cells for storing data. The main memory 810 can be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM), such as a synchronous DRAM (SDRAM), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0055] Other devices may be connected to the system bus 812. As shown in FIG. 8, these devices may include, by way of example, a main memory 810, one or more input devices 822, one or more output devices 824, a modem 826, and one or more display controllers 828. The input device(s) 822 may include any type of input device, including but not limited to, input keys, switches, audio processors, etc. The output device(s) 824 may include any type of output device, including but not limited to, audio, video, other visual indicators, etc. The modem 826 may be any device configured to enable the exchange of data with the network 830. The network 830 may be any type of network, including but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem 826 may be configured to support any type of communication protocol desired. The processor 802 may also be configured to access display controller(s) 828 over the system bus 812 to control information sent to one or more displays 832. The display(s) 832 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0056] 8 may include a set of instructions 834 that are executed by processor 802 for any desired application in accordance with the instructions. The instructions 834 may be stored in main memory 810, processor 802, and / or instruction cache 808, as examples of non-transitory computer-readable medium 836. The instructions 834 may also reside, completely or at least partially, within main memory 810 and / or processor 802 during their execution. The instructions 834 may also be transmitted or received over network 830 via modem 826, such that network 830 includes computer-readable medium 836.

[0057] Although the computer-readable medium 836 is shown in the illustrated embodiment as being a single medium, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" should therefore be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0058] The embodiments disclosed herein include various steps, which may be formed by hardware components, embodied in machine-executable instructions that can be used to program a general-purpose or special-purpose processor with instructions to perform the steps, or performed by a combination of hardware and software.

[0059] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices), and the like.

[0060] Unless otherwise noted, and as is clear from the foregoing description, throughout the description, descriptions using terms such as "processing," "computing," "determining," "displaying," and the like will be understood to refer to the operations and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the computer system's registers into other data that is similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display device.

[0061] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the above description. Further, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0062] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or other computer-readable medium and executed by a processor or other processing device, or as a combination of both. The components of the distributed antenna system described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, by way of example. The memories disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0063] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller may be a processor. A processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of multiple computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0064] The embodiments disclosed herein may be embodied in hardware and instructions stored in hardware, which may reside in, for example, RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0065] It should also be noted that the operational steps described in any of the exemplary embodiments herein are set forth to provide examples and explanations. The described operations may be performed in many different sequences other than the illustrated sequence. Also, an operation described as a single operational step may actually be performed in multiple different steps. Furthermore, one or more operational steps described in an exemplary embodiment may be combined. Those skilled in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0066] Unless otherwise specified, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order in which its steps must be followed, or unless it is otherwise specifically stated in the claim or description that the steps are limited to a particular order, no particular order is intended to be inferred.

[0067] It will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and modifications of the disclosed embodiments that incorporate the spirit and content of the present invention will occur to those skilled in the art, the present invention should be construed as including all modifications within the scope of the appended claims and their equivalents.

Claims

1. A register mapping circuit within a processor, comprising: a reorder buffer (ROB) control circuit configured to allocate a plurality of ROB entries in the ROB to a plurality of uncommitted instructions in a processor pipeline; the plurality of uncommitted instructions include a target instruction and another instruction; the plurality of ROB entries include a target ROB entry allocated to the target instruction and another ROB entry allocated to the other instruction, the other instructions include an old instruction that precedes the target instruction in the processor pipeline and a young instruction that follows the target instruction in the processor pipeline; an ROB control circuit; It is a snapshot circuit, capturing a rename map table snapshot having a logical register-to-physical register mapping state of a rename map table, the rename map table snapshot corresponding to a first other instruction among the other instructions; and storing the rename map table snapshot in association with a snapshot ROB entry assigned to the first other instruction among the other instructions; a snapshot circuit configured as follows: A register rename restore circuit, receiving an indication from the target instruction to flush instructions in the processor pipeline; and In response to the indication of the flush, restoring the logical register-to-physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry. A register rename restoration circuit configured as follows: and If the first other instruction has an old side instruction, There is no rename map table snapshot stored in association with any of the other ROB entries assigned to the young side instruction, the first number of other ROB entries between the target ROB entry and the snapshot ROB entry is less than the second number of other ROB entries from the target ROB entry to the last ROB entry of the other ROB entries allocated to the newest instruction among the young instructions; or If the first other instruction has a young side instruction, There is no rename map table snapshot stored in association with any of the other ROB entries assigned to the old side instruction, the first number of other ROB entries between the target ROB entry and the snapshot ROB entry is less than the second number of other ROB entries from the target ROB entry to a leading ROB entry among the other ROB entries assigned to the oldest instruction among the old-side instructions; Register mapping circuit.

2. The register rename restoration circuit further restores the logical register-physical register mapping state of the rename map table by: the snapshot ROB entry, One or more of the other ROB entries between the snapshot ROB entry and the target ROB entry; and the target ROB entry, 2. The register mapping circuit of claim 1, configured to restore the register mapping information based on at least one of:

3. the rename map table snapshot is a first rename map table snapshot; The snapshot circuitry further comprises: capturing a second rename map table snapshot corresponding to a second one of the other instructions; and storing the second rename map table snapshot in association with a second ROB entry among the other ROB entries allocated to the second other instruction; It is configured as follows: a first number of other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of other ROB entries between the target ROB entry and the second ROB entry; 2. The register mapping circuit of claim 1.

4. 4. The register mapping circuit of claim 3, wherein the first other instruction and the second other instruction each comprise an old instruction.

5. 4. The register mapping circuit of claim 3, wherein the first other instruction and the second other instruction each comprise a young side instruction.

6. a first one of the first other instruction and the second other instruction comprises an old instruction; a second one of the first other instruction and the second other instruction comprises a young side instruction; 4. The register mapping circuit of claim 3.

7. the first other instruction comprises an old side instruction; To restore the logical register-to-physical register mapping state of the rename map table to the state corresponding to the target instruction, the register rename restore circuitry further comprises: copying the logical register-to-physical register mapping state in the rename map table snapshot to the rename map table; modifying the register mapping information of the logical register to physical register mapping state of the rename map table based on the register mapping information in the target ROB entry; and changing the register mapping information of the logical register-physical register mapping state of the rename map table sequentially based on the register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry; It is configured as follows:

2. The register mapping circuit of claim 1.

8. the first other instruction comprises an old side instruction; To restore the logical register-to-physical register mapping state of the rename map table to the state corresponding to the target instruction, the register rename restore circuitry further comprises: Identifying register mapping information of the logical register-physical register mapping state of the rename map table updated by the target instruction or the young instruction, the identified register mapping information having first register mapping information and second register mapping information; changing the first register mapping information of the identified register mapping information sequentially based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry; modifying the first register mapping information of the identified register mapping information based on register mapping information in the target ROB entry; and changing the second register mapping information of the identified register mapping information based on the rename map table snapshot; It is configured as follows:

2. The register mapping circuit of claim 1.

9. the first other instruction comprises a Young side instruction; To restore the logical register-to-physical register mapping state of the rename map table to the state corresponding to the target instruction, the register rename restore circuitry further comprises: copying the logical register-to-physical register mapping state from the rename map table snapshot into the rename map table; changing the logical register-physical register mapping state in the rename map table sequentially based on the register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry; It is configured as follows:

2. The register mapping circuit of claim 1.

10. the first other instruction comprises a Young side instruction; To restore the logical register-to-physical register mapping state of the rename map table to the state corresponding to the target instruction, the register rename restore circuitry further comprises: Identifying register mapping information of the logical register-to-physical register mapping state in the rename map table updated by the target instruction or the young instruction, the identified register mapping information having first register mapping information and second register mapping information; Modifying the first register mapping information of the identified register mapping information sequentially based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry; and changing the second register mapping information of the identified register mapping information based on the rename map table snapshot; It is configured as follows:

2. The register mapping circuit of claim 1.

11. 2. The register mapping circuit of claim 1, wherein none of the other ROB entries are between the target ROB entry and the snapshot ROB entry.

12. a reorder buffer (ROB) control circuit configured to assign a ROB entry of a plurality of ROB entries in a ROB to each of a plurality of uncommitted instructions in a processor pipeline; the plurality of uncommitted instructions include a target instruction and another instruction; the plurality of ROB entries include a target ROB entry allocated to the target instruction and another ROB entry allocated to the other instruction, the other instructions include an old instruction that precedes the target instruction in the processor pipeline and a young instruction that follows the target instruction in the processor pipeline; an ROB control circuit; It is a snapshot circuit, capturing at least one rename map table snapshot, each having a logical register-to-physical register mapping state of a rename map table, each rename map table snapshot corresponding to a respective one of the other instructions; and storing the at least one rename map table snapshot in association with one of the other ROB entries assigned to the respective one of the other instructions; a snapshot circuit configured as follows: A register rename restore circuit, receiving an indication from the target instruction to flush instructions in the processor pipeline; determining, in response to the indication of the flush, that a first number of other ROB entries between the target ROB entry and a closest one of the other ROB entries associated with a rename map table snapshot is greater than a second number of the other ROB entries from the target ROB entry to an end ROB entry, the end ROB entry having one of a head ROB entry assigned to an oldest instruction of the old side instructions and a tail ROB entry assigned to a newest instruction of the young side instructions; In response to the end ROB entry having the top ROB entry, restore the logical register-physical register mapping state of the rename map table based on a committed map table (CMT) and register mapping information in the other ROB entries from the top ROB entry to the target ROB entry; In response to the end ROB entry having the tail ROB entry, restoring the logical register-physical register mapping state of the rename map table based on the rename map table and register mapping information in the other ROB entries from the tail ROB entry to the target ROB entry; A register rename restoration circuit configured as follows: A register mapping circuit having:

13. 1. A method of register mapping circuitry in a processor, comprising: allocating a plurality of reorder buffer (ROB) entries in a ROB to a plurality of uncommitted instructions in a processor pipeline; assigning a target ROB entry from the plurality of ROB entries to a target instruction from the plurality of uncommitted instructions; assigning other ROB entries of the plurality of ROB entries to other instructions of the plurality of uncommitted instructions; the other instructions include old instructions that precede the target instruction in the processor pipeline and young instructions that follow the target instruction in the processor pipeline. and capturing a rename map table snapshot having a logical register-to-physical register mapping state of a rename map table, the rename map table snapshot corresponding to a first one of the other instructions; storing the rename map table snapshot in association with a snapshot ROB entry assigned to the first one of the other instructions; receiving an indication from the target instruction to flush instructions in the processor pipeline; in response to the indication of the flush, restoring the logical register-to-physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry; and If the first other instruction has an old side instruction, No rename map table snapshot is stored in association with any of the other ROB entries assigned to the young instruction, the first number of other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of other ROB entries from the target ROB entry to a last ROB entry among the other ROB entries allocated to the newest one of the young instructions; or If the first other instruction has a young side instruction, No rename map table snapshot is stored in association with any of the other ROB entries assigned to the old side instruction, the first number of other ROB entries between the target ROB entry and the snapshot ROB entry is less than the second number of other ROB entries from the target ROB entry to a leading ROB entry among the other ROB entries assigned to the oldest instruction among the old-side instructions; method.

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