Imaging device

Abstract

To provide an imaging apparatus capable of improving image quality.SOLUTION: The imaging apparatus includes a pixel 10e and a pixel 10f. Each of the pixel 10e and the pixel 10f includes a pixel electrode 11, a counter electrode 12, a photoelectric conversion layer 15, and an electron blocking layer 16. The photoelectric conversion layer 15 is arranged astride the pixel 10e and the pixel 10f. The area of the electron blocking layer 16 in the pixel 10e is larger than the area of the pixel electrode 11 in the pixel 10e and the area of the electron blocking layer 16 in the pixel 10f is larger than the area of the pixel electrode 11 in the pixel 10f. The imaging apparatus further includes an interlayer insulation layer 50 located below the electron blocking layer 16 of the pixel 10e and the electron blocking layer 16 of the pixel 10f and an interlayer insulation layer 51 located between the electron blocking layer 16 of the pixel 10e and the electron blocking layer 16 of the pixel 10f and including a material different from that of the interlayer insulation layer 50.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] In recent years, stacked imaging devices have been developed in which photoelectric conversion elements are provided on a semiconductor substrate. In stacked imaging devices, the photoelectric conversion layer of the photoelectric conversion element can be formed using a material different from that of the semiconductor substrate. Therefore, as disclosed in Patent Documents 1 and 2, for example, it is possible to form the photoelectric conversion layer using an inorganic or organic material different from conventional semiconductor materials such as silicon, thereby realizing imaging devices with physical properties or functions different from conventional imaging devices, such as sensitivity to a different wavelength band. Furthermore, in stacked imaging devices, a charge-blocking layer may be stacked between the photoelectric conversion layer and the electrode to prevent charges other than the signal charge from flowing into the photoelectric conversion layer from the electrode for extracting the signal charge. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-152393 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-127264 Summary of the Invention [Problem to be solved by the invention]

[0004] In a stacked-type imaging device, if the electrical conductivity of the charge-blocking layer and the photoelectric conversion layer is increased to increase the speed and efficiency of charge extraction, the probability of charge spreading to adjacent pixels also increases, leading to color mixing and reduced resolution and image quality. Furthermore, if the photoelectric conversion layer is patterned to prevent color mixing, the photoelectric conversion layer will be damaged, increasing the dark current generated in the photoelectric conversion layer and degrading image quality.

[0005] Therefore, the present disclosure provides an imaging device that can improve image quality. [Means for solving the problem]

[0006] An imaging device according to an embodiment of the present disclosure includes a first pixel and a second pixel adjacent to the first pixel, each of the first pixel and the second pixel including a first electrode, a second electrode located above the first electrode and facing the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode, and a first charge blocking layer located between the first electrode and the photoelectric conversion layer, the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel being separated, and the photoelectric conversion layer being disposed across the first pixel and the second pixel, In this view, an area of ​​the first charge blocking layer in the first pixel is larger than an area of ​​the first electrode in the first pixel, and an area of ​​the first charge blocking layer in the second pixel is larger than an area of ​​the first electrode in the second pixel. The pixel further comprises a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel, and a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel and containing a material different from that of the first insulating layer.

[0007] Also, an imaging device according to an aspect of the present disclosure includes a first pixel and a second pixel adjacent to the first pixel, each of the first pixel and the second pixel including a first electrode, a second electrode located above the first electrode and facing the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode, and a first charge blocking layer located between the first electrode and the photoelectric conversion layer, the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel being separated, and the photoelectric conversion layer being disposed across the first pixel and the second pixel, In a planar view, the area of ​​the first charge blocking layer in the first pixel is smaller than the area of ​​the first electrode in the first pixel, and the area of ​​the first charge blocking layer in the second pixel is smaller than the area of ​​the first electrode in the second pixel, and the pixel further includes a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel, and a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel and containing a material different from that of the first insulating layer. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, an imaging device capable of improving image quality can be provided. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram showing a circuit configuration of an imaging device according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing the cross-sectional structure of two adjacent pixels of the imaging device according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to a first comparative example. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to a second comparative example. [Figure 5]FIG. 5 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of the imaging device according to the first embodiment. [Figure 6] FIG. 6 is a plan view showing the planar layout of pixel electrodes and electron blocking layers of the imaging device according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a cross-sectional structure of a photoelectric conversion unit of an imaging device according to another example of the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to the second embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to the third embodiment. [Figure 10] FIG. 10 is a plan view showing the planar layout of pixel electrodes and electron blocking layers of an imaging device according to the third embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to Comparative Example 3. As shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to the fourth embodiment. [Figure 13] FIG. 13 is a plan view showing the planar layout of pixel electrodes, shield electrodes, and electron blocking layers of an imaging device according to the fourth embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to the fifth embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit of an imaging device according to the sixth embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a cross-sectional structure of a photoelectric conversion unit of an imaging device according to another example of the sixth embodiment. [Figure 17] FIG. 17 is a plan view showing a planar layout of pixel electrodes, a shield electrode, and an electron blocking layer in an imaging device according to another example of the sixth embodiment. [Figure 18] FIG. 18 is a plan view showing the planar layout of pixel electrodes, electron blocking layers, and color filters of an imaging device according to the seventh embodiment. [Figure 19] FIG. 19 is a block diagram showing the structure of a camera system according to the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Summary of the Disclosure) An imaging device according to one embodiment of the present disclosure includes a first pixel and a second pixel adjacent to the first pixel. Each of the first pixel and the second pixel includes a first electrode, a second electrode located above the first electrode and facing the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode, and a first charge blocking layer located between the first electrode and the photoelectric conversion layer. The first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel are separated from each other. The photoelectric conversion layer is disposed across the first pixel and the second pixel. In a plan view, the area of ​​the first charge blocking layer of the first pixel is larger than the area of ​​the first electrode of the first pixel. In a plan view, the area of ​​the first charge blocking layer of the second pixel is larger than the area of ​​the first electrode of the second pixel.

[0011] As a result, the first charge blocking layer, which transports signal charges to the first electrode and suppresses the movement of charges in the opposite direction to the signal charges, is separated between two adjacent pixels. This makes it difficult for signal charges that have moved into the first charge blocking layer to move across two adjacent pixels, preventing signal charges from crossing over between two adjacent pixels. This suppresses color mixing and improves image quality.

[0012] Furthermore, because the area of ​​the first charge blocking layer is larger than the area of ​​the first electrode in the corresponding pixel, the first electrode and the photoelectric conversion layer located above the first charge blocking layer are less likely to come into contact with each other. This allows the first charge blocking layer, which suppresses the movement of charges in the opposite direction to the signal charges from the first electrode to the photoelectric conversion layer, to function more effectively, thereby suppressing dark current. This reduces dark current, thereby improving image quality.

[0013] Also, for example, in a planar view, the first electrode in the first pixel may be located inside the first charge blocking layer in the first pixel, and in a planar view, the first electrode in the second pixel may be located inside the first charge blocking layer in the second pixel.

[0014] As a result, the first electrode is positioned inside the first charge blocking layer in the corresponding pixel, and the first electrode and the photoelectric conversion layer are not in contact with each other. This separates the first electrode and the photoelectric conversion layer through the first charge blocking layer, thereby suppressing the movement of charges in the opposite direction to the signal charges to the photoelectric conversion layer and reducing dark current.

[0015] Furthermore, for example, in each of the first pixel and the second pixel, the conductivity of the first charge blocking layer may be greater than the conductivity of the photoelectric conversion layer.

[0016] Also, for example, the imaging device may further include a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel, and a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel.

[0017] As a result, the second insulating layer insulates the first charge blocking layers of each of the two adjacent pixels, preventing signal charges from moving between the two first charge blocking layers. This further suppresses the movement of signal charges between the two adjacent pixels, thereby further reducing color mixing.

[0018] Furthermore, for example, the first insulating layer and the second insulating layer may contain the same material.

[0019] This allows the second insulating layer, which provides insulation between the first charge blocking layers, to be formed of the same material as the first insulating layer, and therefore can be formed easily.

[0020] Furthermore, for example, the imaging device may further include a third electrode that is in contact with the second insulating layer and is located between the first electrode of the first pixel and the first electrode of the second pixel in a plan view.

[0021] As a result, the third electrode is positioned between the first pixels of each of the two adjacent pixels, and by applying a voltage to the third electrode, the signal charge moving between the two adjacent pixels is attracted to the interface between the photoelectric conversion layer and the second insulating layer located on the third electrode. This prevents signal charge from crossing over between the two adjacent pixels, further reducing color mixing.

[0022] Also, for example, the imaging device may further include, in a planar view, a third electrode located between the first electrode of the first pixel and the first electrode of the second pixel, and a second charge blocking layer located between the third electrode and the photoelectric conversion layer, and at least one selected from the group consisting of the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel may be separated from the second charge blocking layer.

[0023] As a result, the third electrode is disposed between the first pixels of each of the two adjacent pixels. The third electrode is also disposed below the photoelectric conversion layer via the second charge-blocking layer. Therefore, by applying a voltage to the third electrode, the third electrode collects signal charges that move between the two adjacent pixels via the second charge-blocking layer. This prevents signal charges from crossing over between the two adjacent pixels, further reducing color mixing.

[0024] Furthermore, for example, the area of ​​the second charge blocking layer may be larger than the area of ​​the third electrode in a plan view.

[0025] As a result, the area of ​​the second charge blocking layer is larger than the area of ​​the third electrode located below the second charge blocking layer, reducing the number of contact points between the third electrode and the photoelectric conversion layer located above the second charge blocking layer. This allows the second charge blocking layer, which suppresses the movement of charges in the opposite direction to the signal charges from the third electrode to the photoelectric conversion layer, to function more effectively, thereby suppressing dark current.

[0026] Also, for example, the second charge blocking layer may be an electron blocking layer.

[0027] This allows the first charge blocking layer to suppress the movement of electrons and transport holes, so when holes are used as signal charges, the holes, which are the signal charges, can be transported to the third electrode and the movement of electrons, which are the opposite charge to the signal charges, can be suppressed.

[0028] Furthermore, for example, a portion of the photoelectric conversion layer may be located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel.

[0029] As a result, the photoelectric conversion layer is located between the first charge blocking layers, and the first charge blocking layers can be formed after planarizing the top surfaces of the first electrode and the first insulating layer. Therefore, the first charge blocking layers that are not separated can be formed on the top surfaces of the first electrode and the first insulating layer, and the first charge blocking layers that are separated between adjacent pixels can be formed simply by patterning using dry etching or the like. Therefore, a planarization process is not required after forming the first charge blocking layers, and the first charge blocking layers that are separated between adjacent pixels can be easily formed.

[0030] Also, an imaging device according to one aspect of the present disclosure includes a first pixel and a second pixel adjacent to the first pixel. Each of the first pixel and the second pixel includes a first electrode, a second electrode located above the first electrode and facing the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode, and a first charge blocking layer located between the first electrode and the photoelectric conversion layer. The first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel are separated. The photoelectric conversion layer is disposed across the first pixel and the second pixel. In a plan view, the area of ​​the first charge blocking layer in the first pixel is smaller than the area of ​​the first electrode in the first pixel. In a plan view, the area of ​​the first charge blocking layer in the second pixel is smaller than the area of ​​the first electrode in the second pixel.

[0031] As a result, the first charge blocking layer, which transports signal charges to the first electrode and suppresses the movement of charges in the opposite direction to the signal charges, is separated between two adjacent pixels. This makes it difficult for signal charges that have moved into the first charge blocking layer to move across two adjacent pixels, preventing signal charges from crossing over between two adjacent pixels. This suppresses color mixing and improves image quality.

[0032] Furthermore, because the area of ​​the first charge blocking layer is smaller than the area of ​​the first electrode in the corresponding pixel, the distance between the first charge blocking layers of two adjacent pixels is longer than the distance between the first electrodes of the two adjacent pixels. Therefore, for signal charges collected by the first electrodes via the first charge blocking layer, signal charges that should be collected by the first electrode of one of the two adjacent pixels are less likely to be collected by the first electrode of the other pixel. This makes it possible to suppress color mixing and further improve image quality.

[0033] Also, for example, the imaging device may further include a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel, and a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel.

[0034] As a result, the first charge blocking layers of each of the two adjacent pixels are insulated by the second insulating layer, and signal charges cannot move between the two first charge blocking layers, thereby further suppressing the movement of signal charges between the two adjacent pixels and further suppressing color mixing.

[0035] Also, for example, the first charge blocking layer may be an electron blocking layer.

[0036] This allows the first charge blocking layer to suppress the movement of electrons and transport holes, so when holes are used as signal charges, the holes, which are the signal charges, can be transported to the first electrode and the movement of electrons, which are the opposite charges to the signal charges, can be suppressed.

[0037] Hereinafter, an embodiment of an imaging device according to the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to the following embodiment. Furthermore, appropriate modifications are possible within the scope of the effects of the present disclosure. Furthermore, one embodiment can be combined with another embodiment. In the following description, identical or similar components are designated by the same reference numerals. Furthermore, duplicated descriptions may be omitted.

[0038] Furthermore, in this specification, terms indicating relationships between elements, such as "equal," terms indicating the shapes of elements, such as "square" or "circle," and numerical ranges are not expressions that express only the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0039] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0040] (Embodiment 1) [Circuit configuration of imaging device] First, the circuit configuration of the imaging device according to the present embodiment will be described with reference to FIG.

[0041] Fig. 1 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the present embodiment. The imaging device 100 shown in Fig. 1 has a pixel array PA including a plurality of pixels 10 arranged two-dimensionally. Fig. 1 schematically shows an example in which the pixels 10 are arranged in a matrix of two rows and two columns. The number and arrangement of the pixels 10 in the imaging device 100 are not limited to the example shown in Fig. 1. For example, the imaging device 100 may be a line sensor in which a plurality of pixels 10 are arranged in a single column.

[0042] Each pixel 10 includes a photoelectric conversion unit 13 and a signal detection circuit 14. As will be described later with reference to the drawings, the photoelectric conversion unit 13 includes a photoelectric conversion layer sandwiched between two opposing electrodes and generates a signal upon receiving incident light. The entire photoelectric conversion unit 13 does not need to be an independent element for each pixel 10; for example, a portion of the photoelectric conversion unit 13 may span multiple pixels 10. The signal detection circuit 14 is a circuit that detects a signal generated by the photoelectric conversion unit 13. In this example, the signal detection circuit 14 includes a signal detection transistor 24 and an address transistor 26. The signal detection transistor 24 and the address transistor 26 are typically field-effect transistors (FETs). Here, N-channel metal oxide semiconductor field-effect transistors (MOSFETs) are used as examples of the signal detection transistor 24 and the address transistor 26. Each transistor, including the signal detection transistor 24, the address transistor 26, and a reset transistor 28 (described later), has a control terminal, an input terminal, and an output terminal. The control terminal is, for example, a gate. The input terminal is one of the drain and the source, for example, the drain, and the output terminal is the other of the drain and the source, for example, the source.

[0043] As shown schematically in FIG. 1 , the control terminal of the signal detection transistor 24 is electrically connected to the photoelectric conversion unit 13. Signal charges generated by the photoelectric conversion unit 13 are accumulated in a charge accumulation node 41 between the gate of the signal detection transistor 24 and the photoelectric conversion unit 13. Here, the signal charges are holes or electrons. The charge accumulation node 41 is an example of a charge accumulation unit and is also called a "floating diffusion node." In this specification, the charge accumulation node is called a charge accumulation region. The structure of the photoelectric conversion unit 13 will be described in detail later.

[0044] The photoelectric conversion unit 13 of each pixel 10 is further connected to a counter electrode 12. The counter electrode 12 is connected to a voltage supply circuit 32. The voltage supply circuit is also called a counter electrode supply circuit. The voltage supply circuit 32 is a circuit configured to be able to supply any variable voltage. When the imaging device 100 is in operation, the voltage supply circuit 32 supplies a predetermined voltage to the photoelectric conversion unit 13 via the counter electrode 12. The voltage supply circuit 32 is not limited to a specific power supply circuit, and may be a circuit that generates a predetermined voltage or a circuit that converts a voltage supplied from another power source into a predetermined voltage.

[0045] The voltage supplied from the voltage supply circuit 32 to the photoelectric conversion unit 13 is switched between a plurality of different voltages, thereby controlling the start and end of accumulation of signal charges from the photoelectric conversion unit 13 to the charge accumulation node 41. The same function as the above control can also be achieved by controlling the voltage on the charge accumulation node 41 side or the voltage of a pixel electrode, which will be described later. In other words, in this embodiment, an electronic shutter operation is performed by switching the voltage supplied from the voltage supply circuit 32 to the photoelectric conversion unit 13, or the initial voltage of the charge accumulation node 41 or the pixel electrode. An example of the operation of the imaging device 100 will be described later. In the configuration shown in FIG. 1, the charge accumulation node 41 and the pixel electrode are connected and have the same potential.

[0046] Each pixel 10 is connected to a power supply line 40 that supplies a power supply voltage VDD. As shown in the figure, an input terminal of a signal detection transistor 24 is connected to the power supply line 40. The power supply line 40 functions as a source follower power supply, so that the signal detection transistor 24 amplifies and outputs the signal generated by the photoelectric conversion unit 13.

[0047] An input terminal of an address transistor 26 is connected to an output terminal of the signal detection transistor 24. An output terminal of the address transistor 26 is connected to one of a plurality of vertical signal lines 47 arranged for each column of the pixel array PA. A control terminal of the address transistor 26 is connected to an address control line 46, and by controlling the potential of the address control line 46, the output of the signal detection transistor 24 can be selectively read out to the corresponding vertical signal line 47.

[0048] In the illustrated example, the address control lines 46 are connected to the vertical scanning circuit 36. The vertical scanning circuit is also called a "row scanning circuit." The vertical scanning circuit 36 ​​applies a predetermined voltage to the address control lines 46 to select a plurality of pixels 10 arranged in each row on a row-by-row basis. This causes signals from the selected pixels 10 to be read and the charge storage nodes 41 to be reset.

[0049] The vertical signal lines 47 are main signal lines that transmit pixel signals from the pixel array PA to peripheral circuits. Column signal processing circuits 37 are connected to the vertical signal lines 47. The column signal processing circuits are also called "row signal accumulation circuits." The column signal processing circuits 37 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion). As shown in the figure, a column signal processing circuit 37 is provided corresponding to each column of pixels 10 in the pixel array PA. Horizontal signal readout circuits 38 are connected to these column signal processing circuits 37. The horizontal signal readout circuits are also called "column scanning circuits." The horizontal signal readout circuits 38 sequentially read out signals from the multiple column signal processing circuits 37 to a horizontal common signal line 49.

[0050] Each pixel 10 includes a reset transistor 28. The reset transistor 28 is, for example, a field-effect transistor, similar to the signal detection transistor 24 and the address transistor 26. The following description will discuss an example in which an N-channel MOSFET is used as the reset transistor 28, unless otherwise noted. As shown in the figure, the reset transistor 28 is connected between a reset voltage line 44 that supplies a reset voltage Vr and a charge storage node 41. A control terminal of the reset transistor 28 is connected to a reset control line 48. By controlling the potential of the reset control line 48, the potential of the charge storage node 41 can be reset to the reset voltage Vr. In this example, the reset control line 48 is connected to a vertical scanning circuit 36. Therefore, by the vertical scanning circuit 36 ​​applying a predetermined voltage to the reset control line 48, the pixels 10 arranged in each row can be reset row by row.

[0051] In this example, a reset voltage line 44 that supplies a reset voltage Vr to the reset transistor 28 is connected to the reset voltage source 34. The reset voltage source is also referred to as a "reset voltage supply circuit." The reset voltage source 34 is not limited to a specific power supply circuit, as long as it has a configuration that allows it to supply a predetermined reset voltage Vr to the reset voltage line 44 during operation of the imaging device 100. Similarly to the voltage supply circuit 32 described above, the reset voltage source 34 is not limited to a specific power supply circuit. The voltage supply circuit 32 and the reset voltage source 34 may each be part of a single voltage supply circuit or may be separate, independent voltage supply circuits. One or both of the voltage supply circuit 32 and the reset voltage source 34 may be part of a vertical scanning circuit 36. Alternatively, the counter electrode voltage from the voltage supply circuit 32 and / or the reset voltage Vr from the reset voltage source 34 may be supplied to each pixel 10 via the vertical scanning circuit 36.

[0052] It is also possible to use the power supply voltage VDD of the signal detection circuit 14 as the reset voltage Vr. In this case, a voltage supply circuit (not shown in FIG. 1) that supplies a power supply voltage to each pixel 10 and the reset voltage source 34 can be shared. Furthermore, since the power supply line 40 and the reset voltage line 44 can be shared, the wiring in the pixel array PA can be simplified. However, using different voltages for the reset voltage Vr and the power supply voltage VDD of the signal detection circuit 14 allows for more flexible control of the imaging device 100.

[0053] [Cross-sectional structure of pixel] Next, the cross-sectional structure of the pixel of the imaging device 100 according to the present embodiment will be described with reference to FIG.

[0054] FIG. 2 is a schematic cross-sectional view showing the cross-sectional structure of two adjacent pixels 10a and 10b among the multiple pixels 10 shown in FIG. 1. The two adjacent pixels 10a and 10b are an example of a first pixel and a second pixel. The two adjacent pixels 10a and 10b shown in FIG. 2 have the same structure. The following describes one of the two adjacent pixels 10a and 10b, pixel 10a. The two adjacent pixels 10a and 10b may have partially different structures. In the configuration illustrated in FIG. 2, the signal detection transistor 24, address transistor 26, and reset transistor 28 are formed on a semiconductor substrate 20. The semiconductor substrate 20 is not limited to a substrate made entirely of semiconductor. The semiconductor substrate 20 may be an insulating substrate having a semiconductor layer formed on the surface on which the photosensitive region is formed. Here, an example is described in which a P-type silicon (Si) substrate is used as the semiconductor substrate 20.

[0055] The semiconductor substrate 20 has impurity regions 26s, 24s, 24d, 28d, and 28s, and an element isolation region 20t for electrical isolation between the pixels 10. Here, the impurity regions 26s, 24s, 24d, 28d, and 28s are N-type regions. The element isolation region 20t is also provided between the impurity region 24d and the impurity region 28d. The element isolation region 20t is formed, for example, by ion implantation of acceptors under predetermined implantation conditions.

[0056] The impurity regions 26s, 24s, 24d, 28d, and 28s are, for example, impurity diffusion layers formed in the semiconductor substrate 20. As schematically shown in FIG. 2, the signal detection transistor 24 includes impurity regions 24s and 24d and a gate electrode 24g. The gate electrode 24g is formed using a conductive material. The conductive material is, for example, polysilicon doped with impurities to provide conductivity, but may also be a metal material. The impurity regions 24s and 24d function as, for example, a source region and a drain region of the signal detection transistor 24, respectively. A channel region of the signal detection transistor 24 is formed between the impurity regions 24s and 24d.

[0057] Similarly, the address transistor 26 includes impurity regions 26s and 24s and a gate electrode 26g connected to the address control line 46. The gate electrode 26g is formed using a conductive material. The conductive material is, for example, polysilicon doped with impurities to make it conductive, but a metal material may also be used. In this example, the signal detection transistor 24 and the address transistor 26 are electrically connected to each other by sharing the impurity region 24s. The impurity region 24s functions as, for example, the drain region of the address transistor 26. The impurity region 26s functions as, for example, the source region of the address transistor 26. The impurity region 26s is connected to a vertical signal line 47 (not shown in FIG. 2 ). Note that the impurity region 24s does not necessarily have to be shared by the signal detection transistor 24 and the address transistor 26. Specifically, the source region of the signal detection transistor 24 and the drain region of the address transistor 26 are separated within the semiconductor substrate 20 and may be electrically connected via a wiring layer provided within the interlayer insulating layer 50.

[0058] The reset transistor 28 includes impurity regions 28d and 28s and a gate electrode 28g connected to a reset control line 48. The gate electrode 28g is formed using, for example, a conductive material. The conductive material is, for example, polysilicon that has been doped with impurities to make it conductive, but it may also be a metal material. The impurity region 28s functions as, for example, a source region of the reset transistor 28. The impurity region 28s is connected to a reset voltage line 44, not shown in FIG. 2 . The impurity region 28d functions as, for example, a drain region of the reset transistor 28.

[0059] An interlayer insulating layer 50 is disposed on the semiconductor substrate 20 so as to cover the signal detection transistor 24, the address transistor 26, and the reset transistor 28. The interlayer insulating layer 50 is an example of a first insulating layer. The interlayer insulating layer 50 is formed of an insulating material such as silicon dioxide. As shown in the figure, a wiring layer 56 is disposed in the interlayer insulating layer 50. The wiring layer 56 is typically formed of a metal such as copper and may include, for example, a signal line or a power line such as the above-mentioned vertical signal line 47. The number of insulating layers in the interlayer insulating layer 50 and the number of layers included in the wiring layer 56 disposed in the interlayer insulating layer 50 can be set arbitrarily and are not limited to the example shown in FIG. 2 .

[0060] 2, a plug 52, an interconnect 53, a contact plug 54, and a contact plug 55 are provided in the interlayer insulating layer 50. The interconnect 53 may be part of an interconnect layer 56. The plug 52, the interconnect 53, the contact plug 54, and the contact plug 55 are each formed using a conductive material. For example, the plug 52 and the interconnect 53 are formed from a metal such as copper. The contact plugs 54 and 55 are formed from, for example, polysilicon doped with impurities to provide conductivity. The plug 52, the interconnect 53, the contact plug 54, and the contact plug 55 may be formed using the same material or different materials.

[0061] The plug 52, the wiring 53, and the contact plug 54 constitute at least a part of the charge accumulation node 41 between the signal detection transistor 24 and the photoelectric conversion unit 13. In the configuration illustrated in Fig. 2, the gate electrode 24g of the signal detection transistor 24, the plug 52, the wiring 53, the contact plugs 54 and 55, and the impurity region 28d, which is one of the source region and drain region of the reset transistor 28, function as a charge accumulation region that accumulates signal charges collected by the pixel electrode 11 of the photoelectric conversion unit 13 located on the interlayer insulating layer 50. The pixel electrode 11 is an example of a first electrode.

[0062] Specifically, the pixel electrode 11 of the photoelectric conversion unit 13 is connected to the gate electrode 24g of the signal detection transistor 24 via the plug 52, the wiring 53, and the contact plug 54. In other words, the gate of the signal detection transistor 24 is electrically connected to the pixel electrode 11. The pixel electrode 11 is also connected to the impurity region 28d via the plug 52, the wiring 53, and the contact plug 55.

[0063] When the pixel electrode 11 collects the signal charge, a voltage corresponding to the amount of signal charge accumulated in the charge accumulation region is applied to the gate of the signal detection transistor 24. The signal detection transistor 24 amplifies this voltage. The voltage amplified by the signal detection transistor 24 is selectively read out as a signal voltage via the address transistor 26.

[0064] The above-described photoelectric conversion unit 13 is disposed on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 10 constituting the pixel array PA shown in FIG. 1 are formed in and on the semiconductor substrate 20. When the semiconductor substrate 20 is viewed from above, the plurality of pixels 10 arranged two-dimensionally form a photosensitive region. The photosensitive region is also called a pixel region. The distance between two adjacent pixels 10a and 10b shown in FIG. 2, i.e., the pixel pitch, may be, for example, about 2 μm.

[0065] The photoelectric conversion unit 13 includes a pixel electrode 11, a counter electrode 12, a photoelectric conversion layer 15, and an electron blocking layer 16. That is, each of the multiple pixels 10 includes the pixel electrode 11, a counter electrode 12 located above the pixel electrode 11 and facing the pixel electrode 11, a photoelectric conversion layer 15 located between the pixel electrode 11 and the counter electrode 12, and an electron blocking layer 16 located between the pixel electrode 11 and the photoelectric conversion layer 15. The interlayer insulating layer 50 is located below the electron blocking layer 16.

[0066] 2, a color filter 18 may be disposed on the photoelectric conversion unit 13. The color filter 18 is, for example, a bandpass filter that transmits light in the wavelength range of red light, green light, or blue light. The color filter 18 may be a longpass filter or a notch filter. The color filter 18 may also be a filter that transmits ultraviolet light or infrared light. The color filter 18 may also be a filter that can adjust the transmittance of the light that is transmitted.

[0067] [Configuration of photoelectric conversion unit] The specific configuration of the photoelectric conversion section 13 located on the interlayer insulating layer 50 will be described below.

[0068] The photoelectric conversion unit 13 includes a pixel electrode 11, a counter electrode 12, a photoelectric conversion layer 15 disposed between the pixel electrode 11 and the counter electrode 12, and an electron blocking layer 16 disposed between the pixel electrode 11 and the photoelectric conversion layer 15. In other words, the photoelectric conversion unit 13 includes the pixel electrode 11, the electron blocking layer 16 located on the pixel electrode 11, a counter electrode 12 facing the electron blocking layer 16 on the side opposite the pixel electrode 11, and the photoelectric conversion layer 15 located between the electron blocking layer 16 and the counter electrode 12. The electron blocking layer 16 is an example of a first charge blocking layer, and the counter electrode 12 is an example of a second electrode. In this example, the counter electrode 12 and the photoelectric conversion layer 15 are formed across two adjacent pixels 10a and 10b. The counter electrode 12 and the photoelectric conversion layer 15 may also be formed across other pixels 10. A pixel electrode 11 is provided for each of two adjacent pixels 10a and 10b. The pixel electrode 11 of pixel 10a is spatially separated from the pixel electrode 11 of the adjacent pixel 10b, and is thereby electrically separated from the pixel electrode 11 of pixel 10b. The same is true for the pixel electrodes 11 of the other pixels 10 not shown in FIG. 2, and a pixel electrode 11 is provided for each pixel 10. At least one of the counter electrode 12 and the photoelectric conversion layer 15 may be provided separately for each pixel 10.

[0069] The pixel electrode 11 is an electrode for reading out signal charges generated in the photoelectric conversion unit 13. At least one pixel electrode 11 exists for each pixel 10. The pixel electrode 11 is electrically connected to the gate electrode 24g of the signal detection transistor 24 and the impurity region 28d.

[0070] The pixel electrode 11 is formed using a conductive material, such as a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to provide conductivity.

[0071] The counter electrode 12 is, for example, a transparent electrode made of a transparent conductive material. The counter electrode 12 is disposed on the side of the photoelectric conversion layer 15 on which light is incident. Therefore, light that has passed through the counter electrode 12 is incident on the photoelectric conversion layer 15. Note that the light detected by the imaging device 100 is not limited to light within the wavelength range of visible light. For example, the imaging device 100 may detect infrared light or ultraviolet light. Here, the wavelength range of visible light is, for example, from 380 nm to 780 nm.

[0072] In this specification, "transparent" means that at least a part of the light in the wavelength range to be detected is transmitted, and it is not necessary that light is transmitted over the entire wavelength range of visible light. For convenience, in this specification, electromagnetic waves in general, including infrared and ultraviolet rays, are referred to as "light."

[0073] The counter electrode 12 is formed using a transparent conducting oxide (TCO) such as ITO, IZO, AZO, FTO, SnO2, TiO2, or ZnO2.

[0074] As described with reference to FIG. 1, the counter electrode 12 is connected to the voltage supply circuit 32. Also, as shown in FIG. 2, the counter electrode 12 is formed across two adjacent pixels 10a and 10b. Therefore, a counter electrode voltage of a desired magnitude can be applied from the voltage supply circuit 32 to the two adjacent pixels 10a and 10b collectively via the counter electrode 12. The counter electrode 12 may also be formed across multiple pixels 10 not shown in FIG. 2. Note that, as long as a counter electrode voltage of a desired magnitude can be applied from the voltage supply circuit 32, the counter electrode 12 may be provided separately for each of the two adjacent pixels 10a and 10b and for each of multiple pixels 10 not shown.

[0075] The voltage supply circuit 32 controls the potential of the counter electrode 12 relative to the potential of the pixel electrode 11, so that either the holes or the electrons of the hole-electron pairs generated in the photoelectric conversion layer 15 by photoelectric conversion can be collected by the pixel electrode 11 as signal charges. For example, when holes are used as signal charges, the pixel electrode 11 can selectively collect the holes by setting the potential of the counter electrode 12 higher than that of the pixel electrode 11. The following illustrates a case where holes are used as signal charges. Electrons can also be used as signal charges, in which case the potential of the counter electrode 12 can be set lower than that of the pixel electrode 11. The pixel electrode 11 facing the counter electrode 12 collects either the positive or negative charge generated by photoelectric conversion in the photoelectric conversion layer 15 by applying an appropriate bias voltage between the counter electrode 12 and the pixel electrode 11.

[0076] The photoelectric conversion layer 15 receives incident light and generates hole-electron pairs. The material of the photoelectric conversion layer may be, for example, a semiconducting inorganic material or a semiconducting organic material.

[0077] The material of the photoelectric conversion layer 15 may be a quantum dot material or a quantum well material having a quantum confinement effect, such as PbS, InSb, and Ge quantum dots.

[0078] The material of the photoelectric conversion layer 15 may be carbon nanotubes with wavelength selectivity due to chirality selection. Carbon nanotubes with wavelength selectivity due to chirality selection have absorption sensitivity characteristics with sharp and narrow absorption peaks, rather than broad absorption peaks that are seen in crystalline materials, and therefore enable narrowband wavelength imaging.

[0079] When a quantum dot material or carbon nanotubes is used as the material for the photoelectric conversion layer, if the photoelectric conversion layer is patterned after the photoelectric conversion layer is formed, the quantum dot material or carbon nanotubes used will suffer clear damage, which will result in an increase in the dark current of the imaging device.However, by configuring the imaging device according to this embodiment, there is no damage to the photoelectric conversion layer when the photoelectric conversion layer is patterned, and it is possible to reduce degradation of resolution and color mixing.

[0080] In a configuration in which the photoelectric conversion layer 15 is stacked on a circuit board, as in the imaging device 100 of this embodiment, unlike a CMOS (Complementary Metal Oxide Semiconductor) image sensor, the photoelectric conversion unit 13 can be constructed using a material other than Si, etc., that constitutes the circuit board, thereby achieving the effect of realizing imaging that is not dependent on the wavelength characteristics of the circuit board.

[0081] The electron blocking layer 16 functions to suppress the movement of electrons, which are charges opposite to the signal charges, from the adjacent pixel electrode 11 to the photoelectric conversion layer 15, and also transport holes, which are signal charges generated in the photoelectric conversion layer 15, to the electrode. This suppresses dark current in the imaging device. The material of the electron blocking layer 16 is, for example, a p-type semiconductor, specifically, semiconductors made of inorganic materials such as nickel oxide, copper oxide, chromium oxide, cobalt oxide, titanium oxide, and zinc oxide, but is not limited to these. The p-type semiconductor may also be a p-type semiconductor made of an inorganic material in which impurities are doped into a metal oxide or metal nitride, specifically, for example, a film in which silicon oxide is doped with phosphorus, arsenic, antimony, or the like. The material of the electron blocking layer 16 may also be a semiconductor made of an organic material, such as a hole-transporting organic compound.

[0082] The material of the electron blocking layer 16 may be an inorganic material, as described above. By using an inorganic material as the material for the electron blocking layer 16, it is possible to easily and accurately pattern the electron blocking layer 16 by photolithography. Furthermore, when an inorganic material is used as the material for the electron blocking layer 16, the inorganic material has high compatibility with CMOS processes, there is a low risk of contamination due to dust introduction, and flatness can be ensured by chemical mechanical polishing (CMP) after film formation, which reduces variations in photoelectric conversion efficiency. As a result, an imaging device with higher image quality is realized.

[0083] Furthermore, the conductivity of the signal charges in the electron blocking layer 16 may be higher than the conductivity of the signal charges in the photoelectric conversion layer 15 from the viewpoint of improving the charge extraction speed and efficiency.

[0084] The structure of the electron blocking layer 16 in the photoelectric conversion section 13 will be described in detail later.

[0085] In this embodiment, a structure has been described in which an electron blocking layer 16 is provided to reduce dark current when holes are accumulated as signal charges from the photoelectric conversion layer 15 and read out. Conversely, when electrons are accumulated as signal charges and read out, a hole blocking layer can be used as the first charge blocking layer instead of the electron blocking layer 16. The hole blocking layer has the function of suppressing the movement of holes from the adjacent pixel electrode 11 to the photoelectric conversion layer 15 and transporting electrons generated in the photoelectric conversion layer 15 to the electrode. The material of the hole blocking layer is, for example, an n-type semiconductor.

[0086] Next, the laminated structure of the electron blocking layer 16 of the imaging device 100 according to this embodiment will be described in detail.

[0087] First, an imaging device according to Comparative Example 1 will be described for explaining Embodiment 1. FIG. 3 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 60 of an imaging device according to Comparative Example 1. FIG. 3 shows the photoelectric conversion unit 60 formed across two adjacent pixels 70a and 70b. Note that FIG. 3 also shows a portion of the interlayer insulating layer 50. In each of the following schematic cross-sectional views showing the cross-sectional structure of the photoelectric conversion unit, configurations other than the photoelectric conversion unit and a portion of the interlayer insulating layer are not shown, but the configurations other than the photoelectric conversion unit are the same as the configurations of pixels 10a and 10b shown in FIG. 2.

[0088] As shown in FIG. 3 , two adjacent pixels 70a and 70b each include a counter electrode 12, a photoelectric conversion layer 15, and an electron blocking layer 16. The counter electrode 12, the photoelectric conversion layer 15, and the electron blocking layer 16 are formed across the two adjacent pixels 70a and 70b. Furthermore, the two adjacent pixels 70a and 70b each include a separate pixel electrode 11. Therefore, signal charges generated by photoelectric conversion of light A incident on the photoelectric conversion layer 15 tend to move from pixel 70a to pixel 70b within the photoelectric conversion layer 15 as indicated by arrow B, or move between pixels 70a and 70b within the electron blocking layer 16 as indicated by arrow C. Therefore, if charges that should be captured in the pixel electrode 11 of pixel 70a are instead captured in the pixel electrode 11 of pixel 70b, color mixing occurs between the two adjacent pixels 70a and 70b. Furthermore, due to a similar mechanism, problems such as a decrease in resolution due to the charge collection range becoming larger than the pitch of the pixel electrodes 11, and a narrowing of the allowable angle of incidence of light onto the imaging device 100 due to the restriction being placed on the angle of incidence to avoid color mixing, can occur.

[0089] If an attempt is made to improve the electrical conductivity of the photoelectric conversion layer 15 and the electron blocking layer 16 in order to collect the photoelectrically converted signal charges in the pixel electrode 11 at high speed, the problem of color mixing becomes more pronounced.

[0090] One possible approach to solving this color mixing problem is to separate the photoelectric conversion layer 15 for each pixel, but patterning the photoelectric conversion layer 15 would damage the photoelectric conversion layer 15, increasing dark current and degrading image quality. This effect becomes more pronounced when the photoelectric conversion layer 15 is made of a material with a nanostructure, such as carbon nanotubes or quantum dots.

[0091] Next, an imaging device according to Comparative Example 2 will be described. Fig. 4 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 60a of the imaging device according to Comparative Example 2. Fig. 4 shows the photoelectric conversion unit 60a formed across two adjacent pixels 70c and 70d. Note that Fig. 4 also shows a portion of the interlayer insulating layer 50.

[0092] As shown in FIG. 4 , two adjacent pixels 70c and 70d include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 70c and 70d. Each of the two adjacent pixels 70c and 70d also includes an individual electron blocking layer 16 and an individual pixel electrode 11. A portion of the interlayer insulating layer 50 is embedded between the two individual pixel electrodes 11, and an insulating material is present between the two individual pixel electrodes 11. A portion of the photoelectric conversion layer 15 is located between the two individual electron blocking layers 16, and a photoelectric conversion material is present between the two individual electron blocking layers 16.

[0093] As a result, the electron blocking layer 16, which has the function of transporting signal charges, is separated between the two adjacent pixels 70c and 70d, making it difficult for the signal charges that have moved from the photoelectric conversion layer 15 to the electron blocking layer 16 to move across the two adjacent pixels 70c and 70d, thereby suppressing color mixing between the two adjacent pixels 70c and 70d.

[0094] However, the imaging device according to Comparative Example 2 has the following problem. As shown in FIG. 4 , the electron blocking layer 16 has the same side position as the pixel electrode 11 in the corresponding pixel in a planar view. Although not shown, the electron blocking layer 16 is disposed so that it has the same area and periphery as the pixel electrode 11 in the corresponding pixel in a planar view. Therefore, at a point D where the pixel electrode 11 and the photoelectric conversion layer 15 contact each other, the electron blocking layer 16, which had been suppressing the movement of electrons from the pixel electrode 11 to the photoelectric conversion layer 15, does not function, resulting in the generation of dark current. This results in a deterioration in the image quality of the imaging device.

[0095] Next, an imaging device according to the present embodiment will be described with reference to FIGS. 5 and 6. FIG. 5 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 13 of an imaging device 100 according to the present embodiment. FIG. 5 shows the photoelectric conversion unit 13 formed across two adjacent pixels 10a and 10b. Note that the photoelectric conversion unit 13 may also be formed across other pixels not shown. FIG. 5 also shows a portion of an interlayer insulating layer 50. The photoelectric conversion unit 13 according to the present embodiment shown in FIG. 5 differs from the photoelectric conversion unit 60a according to Comparative Example 2 shown in FIG. 4 in the area of ​​the electron blocking layer 16. FIG. 6 is a plan view showing the planar layout of the pixel electrode 11 and the electron blocking layer 16 of the imaging device 100 according to the present embodiment. Components other than the pixel electrode 11 and the electron blocking layer 16 are omitted from FIG. 6.

[0096] 5, two adjacent pixels 10a and 10b include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10a and 10b. Note that the counter electrode 12 and the photoelectric conversion layer 15 may also be formed across other pixels not shown.

[0097] Furthermore, two adjacent pixels 10a and 10b each include an individual electron blocking layer 16 and an individual pixel electrode 11. A portion of the interlayer insulating layer 50 is embedded between the two individual pixel electrodes 11, and an insulating material exists between the two individual pixel electrodes 11. A portion of the photoelectric conversion layer 15 is located between the electron blocking layer 16 of pixel 10a and the electron blocking layer of pixel 10b, and a photoelectric conversion material exists between the two individual electron blocking layers 16. In other words, the electron blocking layer 16 of pixel 10a and the electron blocking layer 16 of pixel 10b are separated by a portion of the photoelectric conversion layer 15.

[0098] As a result, the electron blocking layer 16, which has the function of transporting charges, is separated between the two adjacent pixels 10a and 10b, making it difficult for signal charges that have moved from the photoelectric conversion layer 15 to the electron blocking layer 16 to move across the two adjacent pixels 10a and 10b, as indicated by arrow C in Figure 3. This prevents color mixing between the two adjacent pixels 10a and 10b.

[0099] As shown in FIG. 6 , the pixel electrode 11 has a square shape in a plan view, and multiple pixel electrodes 11 are arranged in a matrix. The electron blocking layer 16 also has a square shape in a plan view. In a plan view, the area of ​​the electron blocking layer 16 is larger than that of the pixel electrode 11 in the corresponding pixel. In a plan view, the outer periphery of the pixel electrode 11 is located inside the outer periphery of the electron blocking layer 16 in the corresponding pixel, and the electron blocking layer 16 completely covers the upper part of the pixel electrode 11. In other words, in a plan view, the entire pixel electrode 11 is located in the area inside the outer edge of the electron blocking layer 16. When the pixel electrode 11 is located inside the electron blocking layer 16, it is preferable that the pixel electrode 11 be arranged so that it is isotropically smaller than the electron blocking layer 16. The planar shapes of the pixel electrode 11 and the electron blocking layer 16 are not particularly limited. For example, the pixel electrode 11 and the electron blocking layer 16 may be circular or may be a regular polygon such as a regular hexagon or a regular octagon.

[0100] Thus, unlike the photoelectric conversion unit 60a according to Comparative Example 2 shown in FIG. 4 , the photoelectric conversion unit 13 according to this embodiment has an electron blocking layer 16 with a larger area than the pixel electrode 11 in the corresponding pixel, and the upper surface of the pixel electrode 11 is completely covered by the electron blocking layer 16. Therefore, the photoelectric conversion unit 13 does not have a contact point between the pixel electrode 11 and the photoelectric conversion layer 15, as shown in point D in FIG. 4 , and the electron blocking layer 16 functions to suppress the movement of electrons from the pixel electrode 11 to the photoelectric conversion layer 15, thereby suppressing dark current. Furthermore, because the two electron blocking layers 16 are separated as described above, color mixing can be reduced. Therefore, the imaging device 100 according to this embodiment can improve image quality.

[0101] Furthermore, because the structure has a portion of the photoelectric conversion layer 15 located between the electron blocking layers 16, the electron blocking layer 16 can be formed after planarizing the upper surfaces of the interlayer insulating layer 50 and the pixel electrode 11. Therefore, an unseparated electron blocking layer can be formed on the upper surfaces of the interlayer insulating layer 50 and the pixel electrode 11, and then a separated electron blocking layer 16 can be formed simply by patterning, such as dry etching. This eliminates the need for a planarization process, such as CMP, after forming the electron blocking layer 16, and allows the separated electron blocking layer 16 to be easily formed. Furthermore, organic materials that are easily degraded by CMP can also be used as the material for the electron blocking layer 16.

[0102] Furthermore, if a material that is prone to abnormal oxidation and abnormal growth, such as copper (Cu), is used for the plug 52 connected to the pixel electrode 11, there is a problem that part of the abnormally grown plug 52 material is exposed from the side surface of the pixel electrode 11, causing process contamination. By making the area of ​​the electron blocking layer 16 larger than the area of ​​the pixel electrode 11 in the corresponding pixel, the electron blocking layer 16 can suppress abnormal oxidation of the plug 52 material and suppress the exposure of part of the abnormally grown plug 52 material.

[0103] Next, an imaging device according to another example of the present embodiment will be described. Fig. 7 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 13a of an imaging device according to another example of the present embodiment. Fig. 7 shows the photoelectric conversion unit 13a formed across two adjacent pixels 10c and 10d. Fig. 7 also shows a part of the interlayer insulating layer 50.

[0104] As shown in FIG. 7 , two adjacent pixels 10c and 10d each include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10c and 10d. Each of the two adjacent pixels 10c and 10d also includes an individual electron blocking layer 16 and an individual pixel electrode 11. The photoelectric conversion unit 13a also includes a resistive layer 17 between the electron blocking layer 16 of pixel 10c and the electron blocking layer 16 of pixel 10d. That is, the electron blocking layer 16 of pixel 10c and the electron blocking layer 16 of pixel 10d are separated by the resistive layer 17. The resistive layer 17 is located between the interlayer insulating layer 50 and the photoelectric conversion layer 15. The thickness of the resistive layer 17 is the same as the thickness of the electron blocking layer 16. In plan view, the area of ​​the electron blocking layer 16 is larger than the pixel electrode 11 of the corresponding pixel.

[0105] The resistive layer 17 has lower signal charge conductivity and higher electrical resistance than the photoelectric conversion layer 15 and the electron blocking layer 16. This suppresses the transfer of signal charges between the electron blocking layer 16 of pixel 10c and the electron blocking layer 16 of pixel 10d. This suppresses color mixing between two adjacent pixels 10c and 10d. Furthermore, because the resistive layer 17, which has the same thickness as the electron blocking layer 16, is embedded between the two electron blocking layers 16, there is almost no step on the upper surface formed by the electron blocking layer 16 and the resistive layer 17. This makes it easier to form the photoelectric conversion layer 15 stacked thereon flat, suppressing the occurrence of cracks in the photoelectric conversion layer 15.

[0106] The use of the resistive layer 17 allows for a manufacturing method in which the electron blocking layer 16 is first formed and then a resistive layer 17 with a higher electrical resistance than the electron blocking layer 16 is embedded between the electron blocking layer 16, or the resistive layer 17 is first patterned and then the electron blocking layer 16 is embedded between the resistive layer 17. This facilitates subsequent film planarization. For example, when changing the material of the electron blocking layer 16, physical properties such as hardness of the electron blocking layer 16 and the resistive layer 17 have a significant impact on processes such as CMP to achieve flatness. However, in an imaging device including the photoelectric conversion unit 13a, the insertion of the resistive layer 17, which has a higher electrical resistance than the electron blocking layer 16, broadens the range of material options for the electron blocking layer 16. The flatness of the electron blocking layer 16 and the resistive layer 17 affects the flatness of the subsequently formed photoelectric conversion layer 15. Furthermore, the flatness of the photoelectric conversion layer 15 poses a problem of affecting the sensitivity variations caused by thickness variations between pixels, and therefore, with this configuration, it is possible to reduce the sensitivity variations of the imaging device.

[0107] (Embodiment 2) Next, a description will be given of embodiment 2. Embodiment 2 differs from embodiment 1 in that an interlayer insulating layer is present between two electron blocking layers. The following description will focus on the differences from embodiment 1, and explanation of commonalities will be omitted or simplified.

[0108] Fig. 8 is a schematic cross-sectional view showing the cross-sectional structure of the photoelectric conversion unit 13b of the imaging device according to the present embodiment. Fig. 8 shows the photoelectric conversion unit 13b formed across two adjacent pixels 10e and 10f. Fig. 8 also shows a part of the interlayer insulating layer 50.

[0109] As shown in FIG. 8, two adjacent pixels 10e and 10f include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10e and 10f. Furthermore, the two adjacent pixels 10e and 10f each include an individual electron blocking layer 16 and an individual pixel electrode 11. The photoelectric conversion unit 13b includes an interlayer insulating layer 51 that insulates the electron blocking layer 16 of the pixel 10e from the electron blocking layer 16 of the pixel 10f. The interlayer insulating layer 51 is an example of a second insulating layer. The interlayer insulating layer 51 is located between the electron blocking layer 16 of the pixel 10e and the electron blocking layer 16 of the pixel 10f. In other words, the electron blocking layer 16 of the pixel 10e and the electron blocking layer 16 of the pixel 10f are separated by the interlayer insulating layer 51. The upper surface of the interlayer insulating layer 51 and the upper surface of the electron blocking layer 16 form a flat surface. In plan view, the area of ​​the electron blocking layer 16 is larger than the area of ​​the pixel electrode 11 in the corresponding pixel.

[0110] As described above, in the photoelectric conversion unit 13b according to the present embodiment, the individual electron blocking layers 16 and the individual pixel electrodes 11 of the two adjacent pixels 10e and 10f are formed in the interlayer insulating layers 50 and 51, and the two electron blocking layers 16 are insulated from each other by the interlayer insulating layer 51. Therefore, signal charges cannot move between the electron blocking layer 16 of pixel 10e and the electron blocking layer 16 of pixel 10f, and therefore the movement of signal charges between the two adjacent pixels 10e and 10f is suppressed, thereby reducing color mixing.

[0111] The photoelectric conversion unit 13 according to this embodiment can be formed more simply and inexpensively by using a part of the interlayer insulating layer 50 with low electrical conductivity formed in a CMOS process before the formation of the electron blocking layer 16 as the interlayer insulating layer 51 disposed between the electron blocking layers 16 individually provided in two adjacent pixels 10e and 10f. The material of the interlayer insulating layer 51 formed between the two electron blocking layers 16 may be the same as or a different material from the interlayer insulating layer 50 in which the plug 52 connected to the pixel electrode 11 is embedded. For example, SiO2 is used as the material for the interlayer insulating layer 51, but AlO or SiN with low electrical conductivity may also be used.

[0112] Furthermore, by embedding the electron blocking layer 16 in the interlayer insulating layers 50 and 51 and reducing the step between the upper surface of the electron blocking layer 16 and the upper surfaces of the interlayer insulating layers 50 and 51, the photoelectric conversion layer 15 laminated thereon can be easily formed flat, and the occurrence of cracks in the photoelectric conversion layer 15 can be suppressed. After the electron blocking layer 16 is embedded in the interlayer insulating layers 50 and 51, a polishing process such as CMP can be used to reduce the step between the upper surface of the electron blocking layer 16 and the upper surfaces of the interlayer insulating layers 50 and 51. By using an inorganic material as the material for the electron blocking layer 16, a polishing process such as CMP can be easily used.

[0113] (Embodiment 3) Next, a description will be given of embodiment 3. Embodiment 3 differs from embodiment 2 in that the area of ​​the electron blocking layer in plan view is smaller than the area of ​​the pixel electrode. The following description will focus on the differences with embodiments 1 and 2, and will omit or simplify the description of the commonalities.

[0114] FIG. 9 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 13c of an imaging device according to this embodiment. FIG. 9 shows the photoelectric conversion unit 13c formed across two adjacent pixels 10g and 10h. FIG. 9 also shows a part of an interlayer insulating layer 50. FIG. 10 is a plan view showing the planar layout of a pixel electrode 11 and an electron blocking layer 16 of the imaging device according to this embodiment. In FIG. 10, configurations other than the pixel electrode 11 and the electron blocking layer 16 are omitted.

[0115] As shown in FIG. 9 , two adjacent pixels 10g and 10h each include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10g and 10h. Furthermore, the two adjacent pixels 10g and 10h each include an individual electron blocking layer 16 and an individual pixel electrode 11. The photoelectric conversion unit 13c includes an interlayer insulating layer 51 that insulates the electron blocking layer 16 of the pixel 10g from the electron blocking layer 16 of the pixel 10h. The interlayer insulating layer 51 is located between the electron blocking layer 16 of the pixel 10g and the electron blocking layer 16 of the pixel 10h. In other words, the electron blocking layer 16 of the pixel 10g and the electron blocking layer 16 of the pixel 10h are separated by the interlayer insulating layer 51. The upper surfaces of the interlayer insulating layer 51 and the electron blocking layer 16 form a flat surface. The interlayer insulating layer 51 is also disposed between the photoelectric conversion layer 15 and the surface of the pixel electrode 11 on which the electron blocking layer 16 is not formed.

[0116] 10 , in plan view, the area of ​​the electron blocking layer 16 is smaller than the area of ​​the pixel electrode 11 in the corresponding pixel. In plan view, the periphery of the pixel electrode 11 is located outside the periphery of the electron blocking layer 16 in the corresponding pixel, and the pixel electrode 11 is located outside all sides of the electron blocking layer 16.

[0117] As described above, in the photoelectric conversion unit 13c according to the present embodiment, the area of ​​the electron blocking layer 16 is smaller than the area of ​​the pixel electrode 11 in the corresponding pixel in a plan view. Furthermore, signal charges generated in the photoelectric conversion layer 15 move more easily in the electron blocking layer 16 than in the interlayer insulating layer 51. That is, signal charges collected in the pixel electrode 11 move to the pixel electrode 11 through the electron blocking layer 16 corresponding to each pixel. Because the area of ​​the electron blocking layer 16 is smaller than the area of ​​the pixel electrode 11 in the corresponding pixel in a plan view, the distance between the charge to be collected in the pixel electrode 11 of pixel 10g and the electron blocking layer 16 of pixel 10h adjacent to pixel 10g is increased. Therefore, the charge to be collected in the pixel electrode 11 of pixel 10g is less likely to be collected in the pixel electrode 11 of pixel 10h, thereby suppressing color mixing between the two adjacent pixels 10h and 10g.

[0118] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment in that a shield electrode is provided between two pixel electrodes and an electron blocking layer is disposed on the shield electrode. The following description will focus on the differences from the first to third embodiments, and will omit or simplify the description of the commonalities.

[0119] First, an imaging device according to Comparative Example 3 will be described for explaining Embodiment 4. Fig. 11 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 60b of the imaging device according to this embodiment. Fig. 11 shows the photoelectric conversion unit 60b formed across two adjacent pixels 70e and 70f. Note that Fig. 11 also shows a portion of the interlayer insulating layer 50.

[0120] As shown in FIG. 11 , two adjacent pixels 70e and 70f include a counter electrode 12, a photoelectric conversion layer 15, and an electron blocking layer 16. The counter electrode 12, the photoelectric conversion layer 15, and the electron blocking layer 16 are formed across the two adjacent pixels 70e and 70f. Each of the two adjacent pixels 70e and 70f includes an individual pixel electrode 11. The photoelectric conversion unit 60b includes a shield electrode 11a between the pixel electrode 11 of pixel 70e and the pixel electrode 11 of pixel 70f. The shield electrode 11a is stacked between the interlayer insulating layer 50 and the electron blocking layer 16. The shield electrode 11a is an example of a third electrode.

[0121] The shield electrode 11a is electrically connected to the semiconductor substrate 20 via a plug 52a and supplies a fixed potential. The shield electrode 11a differs from the pixel electrode 11 in the potential applied thereto, area, and circuit to which it is connected. The shield electrode 11a is formed using a conductive material. Examples of the conductive material include metals such as aluminum and copper, metal nitrides, and polysilicon that has been doped with impurities to provide conductivity.

[0122] The shield electrode 11a is located between the pixel electrodes 11 of the two adjacent pixels 70e and 70f, and by supplying a fixed potential to the shield electrode 11a, it can collect signal charges generated in the photoelectric conversion layer 15 when the signal charges move between the two adjacent pixels 70e and 70f. Therefore, the provision of the shield electrode 11a suppresses color mixing.

[0123] However, in the photoelectric conversion unit 60b, two adjacent pixels 70e and 70f have an electron blocking layer 16 formed across the pixels 70e and 70f, and the two pixel electrodes 11 and the shield electrode 11a are in contact with the same electron blocking layer 16. Therefore, not only does the shield electrode 11a collect signal charges from the photoelectric conversion layer 15 via the electron blocking layer 16 on the shield electrode 11a, but signal charges that have migrated to the electron blocking layer 16 other than those on the shield electrode 11a can also migrate through the electron blocking layer 16 and be collected by the shield electrode 11a. Therefore, if the amount of signal charges photoelectrically converted increases, excessive current may flow through the shield electrode 11a, potentially damaging the photoelectric conversion unit 60b.

[0124] Next, an imaging device according to this embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 13d of the imaging device according to this embodiment. FIG. 12 shows the photoelectric conversion unit 13d formed across two adjacent pixels 10i and 10j. FIG. 12 also shows a part of the interlayer insulating layer 50. FIG. 13 is a plan view showing the planar layout of the pixel electrode 11, shield electrode 11a, electron blocking layer 16, and electron blocking layer 16a of the imaging device according to this embodiment. In FIG. 13, configurations other than the pixel electrode 11, shield electrode 11a, electron blocking layer 16, and electron blocking layer 16a are omitted from the illustration.

[0125] As shown in FIG. 12 , two adjacent pixels 10i and 10j each include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10i and 10j. Furthermore, the two adjacent pixels 10i and 10j each include an individual electron blocking layer 16 and an individual pixel electrode 11. Furthermore, the photoelectric conversion unit 13d includes a shield electrode 11a between the pixel electrode 11 of pixel 10i and the pixel electrode 11 of pixel 10j. The shield electrode 11a is stacked on the interlayer insulating layer 50, and an electron blocking layer 16a is stacked on the shield electrode 11a. That is, the electron blocking layer 16a is located between the shield electrode 11a and the photoelectric conversion layer 15. A portion of the photoelectric conversion layer 15 is located between the electron blocking layer 16 of pixel 10i and the electron blocking layer 16 of pixel 10j and the electron blocking layer 16a on the shield electrode 11a. In other words, the electron blocking layer 16 of pixel 10i and the electron blocking layer 16a on the shield electrode 11a, and the electron blocking layer 16 of pixel 10j and the electron blocking layer 16a on the shield electrode 11a are separated by a portion of the photoelectric conversion layer 15. The electron blocking layer 16a is an example of a second charge blocking layer.

[0126] This allows the shield electrode 11a to collect signal charges that move across the two adjacent pixels 10i and 10j, thereby suppressing color mixing. Furthermore, unlike the photoelectric conversion unit 60b according to Comparative Example 3 shown in FIG. 11 , the photoelectric conversion unit 13d according to this embodiment has the electron blocking layer 16a on the shield electrode 11a separated from the electron blocking layer 16 of pixel 10i and the electron blocking layer 16 of pixel 10j. Therefore, signal charges that move from the photoelectric conversion layer 15 to the electron blocking layer 16 of pixel 10i or the electron blocking layer 16 of pixel 10j are less likely to move to the electron blocking layer 16a on the shield electrode 11a. Therefore, even if the amount of signal charges photoelectrically converted increases, excessive current is less likely to flow through the shield electrode 11a, thereby suppressing damage to the photoelectric conversion unit 13d.

[0127] Furthermore, the photoelectric conversion unit 13d has a structure in which the electron blocking layers 16 and 16a are embedded in the photoelectric conversion layer 15. This makes it suitable to form the pixel electrode 11 and the shield electrode 11a by a CMOS semiconductor process and then form layers above the pixel electrode 11. For example, the electron blocking layer is formed on the planarized upper surface of the pixel electrode 11, the shield electrode 11a, and the interlayer insulating layer 50, and then patterned to form the photoelectric conversion layer 15. Because the layers above the electron blocking layer 16 can be formed after the upper surface of the pixel electrode 11, the shield electrode 11a, and the interlayer insulating layer 50 has been planarized, it is possible to improve the in-plane uniformity of the photoelectric conversion characteristics. Furthermore, when inorganic materials are used as the materials for the electron blocking layers 16 and 16a, they have different solubility from the photoresist used for patterning, making patterning easier.

[0128] 13, the pixel electrode 11 has a square shape in plan view, and multiple pixel electrodes 11 are arranged in a matrix. The electron blocking layer 16 also has a square shape in plan view. In this case, the shield electrode 11a is provided in a lattice pattern between adjacent pixel electrodes 11 so as not to contact the pixel electrodes 11 and the electron blocking layer 16. The electron blocking layer 16a on the shield electrode 11a is also provided in a lattice pattern between adjacent pixel electrodes 11 so as not to contact the pixel electrodes 11 and the electron blocking layer 16.

[0129] In a plan view, the area of ​​the electron blocking layer 16 is larger than that of the pixel electrode 11 in the corresponding pixel. In a plan view, the outer periphery of the pixel electrode 11 is located inside the outer periphery of the electron blocking layer 16 in the corresponding pixel, and the electron blocking layer 16 completely covers the upper part of the pixel electrode 11. In addition, in a plan view, the area of ​​the electron blocking layer 16a is larger than that of the shield electrode 11a provided below the electron blocking layer 16a. In a plan view, the outer periphery of the shield electrode 11a is located inside the outer periphery of the electron blocking layer 16a provided above the shield electrode 11a, and the electron blocking layer 16a completely covers the upper part of the shield electrode 11a. In this way, by providing the shield electrodes 11a in a lattice pattern between adjacent pixel electrodes 11, the shield electrodes 11a are arranged without gaps between the pixel electrodes 11, and it is easy to supply a potential to the shield electrode 11a.

[0130] The shapes of pixel electrode 11, shield electrode 11a, electron blocking layer 16, and electron blocking layer 16a are not particularly limited. For example, pixel electrode 11 and electron blocking layer 16 may be circular or a regular polygon such as a regular hexagon or a regular octagon. In this case, shield electrode 11a and electron blocking layer 16a may be plate-shaped with a plurality of circular or regular polygonal openings arranged in a matrix.

[0131] As described above, the area of ​​the electron blocking layer 16 is larger than the area of ​​the pixel electrode 11 in the corresponding pixel, and the electron blocking layer 16 completely covers the area above the pixel electrode 11. The area of ​​the electron blocking layer 16a is larger than the area of ​​the shield electrode 11a located below the electron blocking layer 16a, and the electron blocking layer 16a completely covers the area above the shield electrode 11a. This prevents the pixel electrode 11 and the shield electrode 11a from contacting the photoelectric conversion layer 15. Therefore, the electron blocking layers 16 and 16a function to suppress the movement of electrons from the pixel electrode 11 and the shield electrode 11a to the photoelectric conversion layer 15, thereby suppressing dark current.

[0132] (Embodiment 5) Next, we will explain embodiment 5. Embodiment 5 differs from embodiment 2 in that a shield electrode is provided between two pixel electrodes and an electron blocking layer is disposed on the shield electrode. The following will mainly explain the differences from embodiments 1 to 4, and will omit or simplify explanations of commonalities.

[0133] Fig. 14 is a schematic cross-sectional view showing the cross-sectional structure of the photoelectric conversion unit 13e of the imaging device according to the present embodiment. Fig. 14 shows the photoelectric conversion unit 13e formed across two adjacent pixels 10k and 10l. Fig. 14 also shows a part of the interlayer insulating layer 50.

[0134] As shown in FIG. 14 , two adjacent pixels 10k and 10l each include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10k and 10l. The two adjacent pixels 10k and 10l each include an individual electron blocking layer 16 and an individual pixel electrode 11. The photoelectric conversion unit 13e includes a shield electrode 11a between the pixel electrode 11 of pixel 10k and the pixel electrode 11 of pixel 10l. The shield electrode 11a is stacked on an interlayer insulating layer 50, and an electron blocking layer 16a is stacked on the shield electrode 11a. The electron blocking layer 16a is located between the shield electrode 11a and the photoelectric conversion layer 15. The photoelectric conversion unit 13e also includes an interlayer insulating layer 51 that insulates the electron blocking layer 16 from the electron blocking layer 16a. The interlayer insulating layer 51 is located between the electron blocking layer 16 and the electron blocking layer 16a of the pixel 10k, and between the electron blocking layer 16 and the electron blocking layer 16a of the pixel 10l. That is, the electron blocking layer 16 and the electron blocking layer 16a are separated by the interlayer insulating layer 51. The top surfaces of the interlayer insulating layer 51, the electron blocking layer 16, and the electron blocking layer 16a form a flat surface. In addition, in a plan view, the area of ​​the electron blocking layer 16 is larger than the pixel electrode 11 in the corresponding pixel, and the area of ​​the electron blocking layer 16a is the same as the area of ​​the shield electrode 11a.

[0135] As described above, photoelectric conversion unit 13e includes shield electrode 11a, which can collect signal charges that move across two adjacent pixels 10k and 10l, thereby suppressing color mixing. Furthermore, interlayer insulating layer 51 insulates electron blocking layer 16 from electron blocking layer 16a, preventing signal charges from moving between electron blocking layer 16 and electron blocking layer 16a. Therefore, even if the amount of signal charges photoelectrically converted increases, excessive current is unlikely to flow through shield electrode 11a, thereby suppressing damage to photoelectric conversion unit 13e.

[0136] (Embodiment 6) Next, a sixth embodiment will be described. The sixth embodiment differs from the second embodiment in that a shield electrode is provided between two pixel electrodes. The following description will focus on the differences from the first to fifth embodiments, and the description of the commonalities will be omitted or simplified.

[0137] Fig. 15 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 13f of an imaging device according to the present embodiment. Fig. 15 shows the photoelectric conversion unit 13f formed across two adjacent pixels 10m and 10n. Fig. 15 also shows a part of the interlayer insulating layer 50.

[0138] As shown in FIG. 15 , two adjacent pixels 10m and 10n each include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10m and 10n. Furthermore, the two adjacent pixels 10m and 10n each include an individual electron blocking layer 16 and an individual pixel electrode 11. The photoelectric conversion unit 13f includes an interlayer insulating layer 51 that insulates the electron blocking layer 16 of the pixel 10m from the electron blocking layer 16 of the pixel 10n. The electron blocking layer 16 of the pixel 10m is separated from the electron blocking layer 16 of the pixel 10n by the interlayer insulating layer 51. Furthermore, the photoelectric conversion unit 13f includes a shield electrode 11a between the pixel electrode 11 of the pixel 10m and the pixel electrode 11 of the pixel 10n. The shield electrode 11a is formed in the interlayer insulating layer 50, and the upper surface of the shield electrode 11a is in contact with the interlayer insulating layer 51. In other words, the photoelectric conversion layer 15 and the shield electrode 11a are insulated by the interlayer insulating layer 51. The upper surface of the interlayer insulating layer 51 and the upper surface of the electron blocking layer 16 form a flat surface. In addition, in a plan view, the area of ​​the electron blocking layer 16 is larger than that of the pixel electrode 11 in the corresponding pixel.

[0139] In this manner, the shield electrode 11a is disposed between the pixel electrodes 11 of the two adjacent pixels 10m and 10n. When a voltage is applied to the shield electrode 11a, signal charges moving between the two adjacent pixels 10m and 10n are attracted to the interface between the photoelectric conversion layer 15 and the interlayer insulating layer 51 located on the shield electrode 11a, thereby reducing color mixing. Furthermore, since the shield electrode 11a and the photoelectric conversion layer 15 are insulated by the interlayer insulating layer 51, signal charge collection by the shield electrode 11a is limited. Therefore, even if the amount of signal charge photoelectrically converted increases, excessive current does not flow to the shield electrode 11a, thereby suppressing damage to the photoelectric conversion unit 13f.

[0140] Next, an imaging device according to another example of the present embodiment will be described. FIG. 16 is a schematic cross-sectional view showing the cross-sectional structure of a photoelectric conversion unit 13g of an imaging device according to another example of the present embodiment. FIG. 16 shows the photoelectric conversion unit 13g formed across two adjacent pixels 10o and 10p. FIG. 16 also shows a part of the interlayer insulating layer 50. FIG. 17 is a plan view showing the planar layout of the pixel electrode 11, shield electrode 11a, and electron blocking layer 16 of an imaging device according to another example of the present embodiment. In FIG. 17, configurations other than the pixel electrode 11, shield electrode 11a, and electron blocking layer 16 are omitted from the illustration.

[0141] As shown in FIG. 16 , two adjacent pixels 10o and 10p each include a counter electrode 12 and a photoelectric conversion layer 15. The counter electrode 12 and the photoelectric conversion layer 15 are formed across the two adjacent pixels 10o and 10p. Furthermore, the two adjacent pixels 10o and 10p each include an individual electron blocking layer 16 and an individual pixel electrode 11. The photoelectric conversion unit 13g includes an interlayer insulating layer 51 that insulates the electron blocking layer 16 of the pixel 10o from the electron blocking layer 16 of the pixel 10p. The electron blocking layer 16 of the pixel 10o is separated from the electron blocking layer 16 of the pixel 10p by the interlayer insulating layer 51. The photoelectric conversion unit 13g also includes a shield electrode 11a between the pixel electrode 11 of the pixel 10o and the pixel electrode 11 of the pixel 10p. The shield electrode 11a is formed in the interlayer insulating layer 50, and the upper surface of the shield electrode 11a is in contact with the interlayer insulating layer 51. In other words, the photoelectric conversion layer 15 and the shield electrode 11a are insulated from each other by the interlayer insulating layer 51. The upper surface of the interlayer insulating layer 51 and the upper surface of the electron blocking layer 16 form a flat surface.

[0142] 17, the pixel electrode 11 has a square shape in a plan view, and the pixel electrodes 11 are arranged in a matrix. The electron blocking layer 16 also has a square shape in a plan view. In this case, the shield electrode 11a is provided in a lattice pattern between adjacent pixel electrodes 11 so as not to come into contact with the pixel electrodes 11 and the electron blocking layer 16.

[0143] In a plan view, the area of ​​the electron blocking layer 16 is the same as that of the pixel electrode 11 in the corresponding pixel, and the periphery of the electron blocking layer 16 and the periphery of the pixel electrode 11 in the corresponding pixel are arranged in the same position. In this way, when the periphery of the electron blocking layer 16 and the periphery of the pixel electrode 11 in the corresponding pixel are arranged in the same position, the pixel electrode 11 and the electron blocking layer 16 can be easily formed on the interlayer insulating layer 50.

[0144] (Embodiment 7) Next, a seventh embodiment will be described. The seventh embodiment differs from the first embodiment in that it includes two sizes of pixel electrodes, large and small, and a color filter above the photoelectric conversion unit. The following description will focus on the differences from the first to sixth embodiments, and will omit or simplify the description of the commonalities.

[0145] 18 is a plan view showing the planar layout of pixel electrodes 11L and 11S, electron blocking layers 16R, 16G, and 16B, and color filters 18RL, 18RS, 18GL, 18GS, 18BL, and 18BS of an imaging device according to this embodiment. In FIG. 18, components other than pixel electrodes 11L and 11S, electron blocking layers 16R, 16G, and 16B, and color filters 18RL, 18RS, 18GL, 18GS, 18BL, and 18BS are not shown. As will be described later, in the imaging device according to this embodiment, the electron blocking layers are patterned to match the pattern of the color filters, thereby achieving further effects such as improved area utilization efficiency and improved yield.

[0146] 18, a plurality of pixel electrodes 11L and 11S of two sizes, large and small, are arranged alternately in a 45-degree diagonal direction. In a plan view, the area of ​​pixel electrode 11L is larger than the area of ​​pixel electrode 11S. The plan view shapes of pixel electrodes 11L and 11S are both regular octagons.

[0147] As a result, the pixel electrode 11L with a larger area can collect more signal charge due to its larger area, thereby capturing images with higher sensitivity even in low-illumination conditions where little signal charge is generated. Furthermore, the pixel electrode 11S with a smaller area can reduce the amount of signal charge collected by the pixel electrode 11S even when a large amount of signal charge is generated due to very bright light, thereby capturing images in high-illumination conditions. This results in an imaging device with an expanded dynamic range. Furthermore, in contrast to the pixel electrode area, from the perspective of noise reduction, it is preferable that the pixel electrode 11L has a small storage capacity for the signal charge collected and the pixel electrode 11S has a large storage capacity for the signal charge collected.

[0148] Furthermore, by arranging the two sizes of pixel electrodes 11L and 11S alternately in a diagonal direction, the pixel electrodes 11S with small areas are efficiently arranged between the pixel electrodes 11L with large areas, thereby improving the area utilization efficiency.

[0149] Above two pixel electrodes 11L and 11S adjacent to each other at a 45-degree angle, two different sizes of color filters 18RL and 18RS, 18GL and 18GS, or 18BL and 18GS of the same color are arranged so as to completely cover the pixel electrodes 11L and 11S.

[0150] Color filters 18RL and 18RS are red-transmitting filters that are transparent to red light and block light in the visible light band other than red light. Color filters 18GL and 18GS are green-transmitting filters that are transparent to green light and block light in wavelength bands other than green light. Color filters 18BL and 18GS are blue-transmitting filters that are transparent to blue light and block light in wavelength bands other than blue light. The areas of color filters 18RL, 18GL, and 18BL are larger than the areas of color filters 18RS, 18GS, and 18BS, respectively.

[0151] Furthermore, an electron blocking layer 16R, 16G, or 16B is disposed on two pixel electrodes 11L and 11S adjacent to each other in a 45-degree diagonal direction. Two sizes of color filters of the same color, large and small, 18RL and 18RS, 18GL and 18GS, and 18BL and 18GS, are disposed above the electron blocking layers 16R, 16G, and 16B, respectively.

[0152] In this way, two sizes of color filters (18RL and 18RS, 18GL and 18GS, or 18BL and 18GS) of the same color are arranged on two adjacent pixel electrodes 11L and 11S at a 45-degree angle. This allows for a larger area for the color filters per color, eliminating the need for detailed color filter patterning for each pixel electrode. Because the color filters are arranged below the same color filters, the electron blocking layers 16R, 16G, and 16B can also be patterned without being separated for the two adjacent pixel electrodes 11L and 11S at a 45-degree angle, as shown in FIG. 18 . As a result, the area for the electron blocking layers 16R, 16G, and 16B can be larger, eliminating the need for detailed color filter patterning for each pixel electrode 11L and 11S. This is expected to improve yields by relaxing processing accuracy.

[0153] Furthermore, the color filter arrangement of the imaging device according to this embodiment is a typical Bayer array, with green-transmitting color filters 18GL and 18GS adjacent to each other diagonally, as shown in FIG. 18 . In this case, two adjacent electron blocking layers 16G may be connected without being separated by patterning. Because the movement of signal charges between regions under color filters of the same color can mitigate the effects of color mixing compared to the movement of signal charges between regions under color filters of different colors, the electron blocking layer may be formed across multiple pixel electrodes, as described above. Furthermore, the two adjacent electron blocking layers 16G may be divided, as shown in FIG. 18 , to align the regularity of the pixel array with the electron blocking layers 16R and 16B and improve yield.

[0154] When a shield electrode is further arranged in the imaging device according to this embodiment, the shield electrode may be arranged between each of the pixel electrodes 11L and 11S, but the shield electrode does not have to be arranged between the pixel electrode 11L and the pixel electrode 11S located below the color filter of the same color.

[0155] (Embodiment 8) Next, an eighth embodiment will be described.

[0156] FIG. 19 is a block diagram showing the structure of a camera system 600 according to this embodiment.

[0157] As shown in FIG. 19, the camera system 600 includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing unit 604.

[0158] The lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. Light that has passed through the lens optical system 601 enters from the counter electrode 12 side and is photoelectrically converted by the photoelectric conversion layer 15. The imaging device 602 may be any of the imaging devices according to any of the first to seventh embodiments described above.

[0159] The system controller 603 controls the entire camera system 600. The system controller 603 can be realized by, for example, a microcomputer.

[0160] The camera signal processing unit 604 functions as a signal processing circuit that processes the output signal from the imaging device 602. The camera signal processing unit 604 performs processes such as gamma correction, color interpolation, spatial interpolation, auto white balance, distance measurement calculation, and wavelength information separation. The camera signal processing unit 604 can be realized by, for example, a DSP (Digital Signal Processor).

[0161] According to camera system 600 of this embodiment, by using the imaging device according to any one of the first to seventh embodiments, a high-image-quality camera system can be provided.

[0162] (Other embodiments) While imaging devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0163] For example, in the above-described fourth and fifth embodiments, the electron blocking layer on the shield electrode is separated from both of the electron blocking layers on the two pixel electrodes, but this is not limiting. One of the electron blocking layers on the two pixel electrodes does not have to be separated from the electron blocking layer on the shield electrode.

[0164] Furthermore, for example, in the above-described embodiment, the photoelectric conversion unit includes a counter electrode, a photoelectric conversion layer, an electron blocking layer, and a pixel electrode, but this is not limitative. The photoelectric conversion unit may further include a charge blocking layer separate from the charge transport layer and the electron blocking layer. Furthermore, the photoelectric conversion unit does not have to have one photoelectric conversion layer, and may have multiple photoelectric conversion layers stacked. [Industrial Applicability]

[0165] The imaging device according to the present disclosure can be applied to various camera systems and sensor systems, such as medical cameras, surveillance cameras, vehicle-mounted cameras, distance measuring cameras, microscope cameras, drone cameras, and robot cameras. [Explanation of symbols]

[0166] 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10l, 10m, 10n, 10o, 10p pixels 11, 11L, 11S pixel electrodes 11a Shield electrode 12 Counter electrode 13, 13a, 13b, 13c, 13d, 13e, 13f, 13g Photoelectric conversion section 14 Signal detection circuit 15 Photoelectric conversion layer 16, 16a, 16B, 16G, 16R Electron blocking layer 17 Resistance layer 18, 18BL, 18BS, 18GL, 18GS, 18RL, 18RS color filters 20 Semiconductor substrate 20t isolation region 24 Signal detection transistor 24d, 24s, 26s, 28d, 28s impurity region 24g, 26g, 28g gate electrodes 26 Address transistor 28 Reset transistor 32 Voltage supply circuit 34 Reset voltage source 36 Vertical scanning circuit 37 Column signal processing circuit 38 Horizontal signal readout circuit 40 Power line 41 Charge storage node 44 Reset voltage line 46 Address Control Line 47 Vertical signal line 48 Reset control line 49 Horizontal common signal line 50, 51 Interlayer insulating layer 52, 52a plug 53 Wiring 54, 55 Contact plug 56 wiring layer 100, 602 Imaging device 600 Camera System 601 Lens Optical System 603 System Controller 604 Camera signal processing unit

Claims

1. A first pixel; a second pixel adjacent to the first pixel, Each of the first pixel and the second pixel includes: A first electrode; a second electrode located above the first electrode and facing the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel are separated; the photoelectric conversion layer is disposed across the first pixel and the second pixel, In a plan view, an area of ​​the first charge blocking layer in the first pixel is larger than an area of ​​the first electrode in the first pixel, and an area of ​​the first charge blocking layer in the second pixel is larger than an area of ​​the first electrode in the second pixel; a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel; a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel, the second insulating layer comprising a different solid material than the first insulating layer; Imaging device.

2. A first pixel; a second pixel adjacent to the first pixel, Each of the first pixel and the second pixel includes: A first electrode; a second electrode located above the first electrode and facing the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel are separated; the photoelectric conversion layer is disposed across the first pixel and the second pixel, In a plan view, an area of ​​the first charge blocking layer in the first pixel is smaller than an area of ​​the first electrode in the first pixel, and an area of ​​the first charge blocking layer in the second pixel is smaller than an area of ​​the first electrode in the second pixel; a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel; a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel, the second insulating layer comprising a solid material different from that of the first insulating layer. Imaging device.

3. a third electrode in contact with a lower surface of the second insulating layer and located between the first electrode of the first pixel and the first electrode of the second pixel in a plan view; 3. The imaging device according to claim 1.

4. A first pixel; a second pixel adjacent to the first pixel, Each of the first pixel and the second pixel includes: A first electrode; a second electrode located above the first electrode and facing the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel are separated; the photoelectric conversion layer is disposed across the first pixel and the second pixel, In a plan view, an area of ​​the first charge blocking layer in the first pixel is larger than an area of ​​the first electrode in the first pixel, and an area of ​​the first charge blocking layer in the second pixel is larger than an area of ​​the first electrode in the second pixel; a first insulating layer located below the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel; a second insulating layer located between the first charge blocking layer of the first pixel and the first charge blocking layer of the second pixel; a third electrode overlapping the second insulating layer in a plan view and in contact with the second insulating layer; Imaging device.

5. the second insulating layer is made of aluminum oxide or silicon nitride; The imaging device according to claim 1 .

6. The first electrode is made of a metal nitride. The imaging device according to claim 1 .

7. the first charge blocking layer is made of an oxide semiconductor; The imaging device according to claim 1 .

Images