Digital Protection Relay

Abstract

To make it possible to execute protection control calculations using a CPU with relatively low processing capacity even when the number of input / output channels increases.SOLUTION: In a digital protection relay 100, a calculation processing board 40 includes a central processing unit 41 that performs power system protection control calculations based on input data, a memory 43 for storing output data and the input data, and a master controller 44 that controls data communication. The master controller 44 autonomously periodically performs data communication with a plurality of input / output boards 10, 20, and 30 without being controlled by the central processing unit 41, and issues an interrupt signal to the central processing unit 41 when writing of the input data from the plurality of input / output boards 10, 20, and 30 to the memory 43 is completed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to digital protection relays. [Background technology]

[0002] In recent digital protection relays, the number of analog input channels and the number of digital input / output channels have been increasing.

[0003] For example, the digital protection relay disclosed in JP 2021-141711 A (Patent Document 1) has a configuration in which a large number of input and output (IO) units are connected to a processing unit via an IO bus. These IO units include an IO unit for inputting a plurality of analog signals and an IO unit for inputting or outputting a plurality of digital signals. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-141711 Summary of the Invention [Problem to be solved by the invention]

[0005] As described above, when the number of analog input channels and digital input / output channels increases, the processing load required for data communication increases on the CPU (Central Processing Unit) provided in the calculation processing unit, resulting in a problem of a decrease in the CPU's processing power for protection and control calculations.

[0006] To address the above issues, it is not desirable to use a high-performance CPU that consumes a lot of power, because the CPUs used in digital protection relays must be low-cost and have a fanless design that does not require cooling by a fan.

[0007] The present disclosure has been made in consideration of the above-mentioned problems, and its purpose is to provide a digital protection relay that can perform protection control calculations using a CPU with relatively low processing power, even when the number of analog input channels and the number of digital input / output channels are increased. [Means for solving the problem]

[0008] A digital protective relay according to one embodiment includes a communication bus, a plurality of input / output boards, and an arithmetic processing board. Each of the plurality of input / output boards transmits output data to the outside of the digital protective relay or receives input data from the outside. The arithmetic processing board communicates the output data and input data with the plurality of input / output boards via the communication bus. The arithmetic processing board includes a central processing unit that performs calculations for protection and control of the power system based on the input data, a memory for storing the output data and the input data, and a master controller that controls data communication. The master controller periodically communicates data with the plurality of input / output boards autonomously without being controlled by the central processing unit, and stores the input data from the plurality of input / output boards in its memory. All When the writing is completed, an interrupt signal is issued to the central processing unit. [Effects of the Invention]

[0009] According to the above embodiment, by providing a master controller that autonomously controls data communication, it is possible to provide a digital protective relay that can perform protective control calculations using a CPU with relatively low processing power, even when the number of input and output channels increases. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a digital protection relay. [Figure 2] FIG. 4 is a state transition diagram showing the operation of the master controller. [Figure 3] 3 is a timing diagram showing the procedure of communication between boards at stages 0 and 1 in FIG. 2. [Figure 4] 3 is a timing diagram showing the procedure of inter-board communication at stage 2 in FIG. 2. [Figure 5] 3 is a timing diagram showing the procedure of inter-board communication at stage 3 in FIG. 2. [Figure 6] FIG. 10 is a diagram showing a specific example of a memory map of a memory provided in the master controller (for stage 1). [Figure 7] FIG. 10 is a diagram showing a specific example of a memory map of a memory provided in the master controller (for stage 2). [Figure 8] FIG. 10 is a diagram showing a specific example of a memory map of a memory provided in the master controller (for stage 3). DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, each embodiment will be described in detail with reference to the drawings. Note that the same or corresponding parts will be denoted by the same reference characters, and their description may not be repeated.

[0012] Embodiment 1 [Overall configuration of digital protection relay] Fig. 1 is a block diagram showing an example of the configuration of a digital protection relay. Referring to Fig. 1, the digital protection relay 100 includes X (an integer of 1 or more) analog input (AI) boards 10, X digital input (DI) boards 20, X digital output (DO) boards 30, a CPU board 40, and an inter-board communication bus 50 connecting these boards.

[0013] The analog input board 10, digital input board 20, and digital output board 30 are collectively referred to as input / output (IO) boards. Each I / O board has multiple input or output channels. While only three channels are shown in FIG. 1, the board may actually have more channels. Also, unlike the case of FIG. 1, the number of analog input boards 10, digital input boards 20, and digital output boards 30 may differ from one another. In this disclosure, the CPU board 40 is also referred to as the arithmetic processing board. The configurations and operations of the I / O boards 10, 20, and 30 and the CPU board 40 are briefly described below.

[0014] The analog input board 10 receives a plurality of analog signals representing electrical quantities (voltage or current) detected from the power system. As shown in Fig. 1, the analog input board 10 includes an input converter 11, an AD (Analog-to-Digital) converter 12, a memory 13, and a slave controller 14.

[0015] 1, only one input converter 11 is shown for each analog input board 10 for ease of illustration, but in reality one is provided for each input channel. Each input converter 11 converts the corresponding analog input signal to a signal size suitable for AD conversion processing by the AD converter 12 and arithmetic processing by the CPU board 40. As the input converter 11, for example, an auxiliary transformer is provided.

[0016] The AD converter 12 converts the analog signal whose magnitude has been changed by the input converter 11 into a digital signal. Although not shown in FIG. 1, an analog filter and a multiplexer are provided before the AD converter 12. An analog filter is provided for each input channel to remove aliasing errors that occur during AD conversion. The multiplexer sequentially selects multiple analog signals that have each passed through the analog filter. The AD converter 12 performs AD conversion on the analog signal selected by the multiplexer.

[0017] The memory 13 is a memory for the slave controller 14 that is accessed by the slave controller 14. The memory 13 stores digital signals of multiple channels obtained by AD conversion under the control of the slave controller 14. The memory 13 may be, for example, an electrically rewritable nonvolatile memory such as a flash memory.

[0018] The slave controller 14 communicates with the master controller 44 of the CPU board 40 via the inter-board communication bus 50. In response to a request from the master controller 44, the slave controller 14 transfers the digital data of multiple channels stored in the memory 13 to the CPU board 40.

[0019] The digital input board 20 receives digital signals transmitted from power equipment, other digital protection relays, etc. As shown in Fig. 1, the digital input board 20 includes an input interface (IF) 21, a memory 22, and a slave controller 23.

[0020] The input interface 21 is provided for each input channel and converts the input digital signal into a signal of a size suitable for internal data processing, separates input and output, etc. The input interface 21 includes, for example, a photocoupler.

[0021] The memory 22 is a memory for the slave controller 23 that is accessed by the slave controller 23. The memory 22 stores a plurality of input digital signals input from the outside in accordance with the control of the slave controller 23. The memory 22 may be, for example, an electrically rewritable non-volatile memory such as a flash memory.

[0022] The slave controller 23 communicates with the master controller 44 of the CPU board 40 via the inter-board communication bus 50. In response to a request from the master controller 44, the slave controller 23 transfers the input digital data of multiple channels stored in the memory 22 to the CPU board 40.

[0023] The digital output board 30 transmits digital signals to power equipment and other digital protection relays. For example, the digital output board 30 outputs a trip signal to a circuit breaker or a switch. As shown in FIG. 1 , the digital output board 30 includes an output interface (IF) 31, a memory 32, and a slave controller 33.

[0024] An output interface 31 is provided for each output channel, and outputs a high-level or low-level digital signal according to the data stored in the memory 32. This opens or closes the contacts of an analog relay provided outside the digital protection relay 100, for example.

[0025] The memory 32 is a memory for the slave controller 33 that is accessed by the slave controller 33. As the memory 32, for example, an electrically rewritable nonvolatile memory such as a flash memory may be used.

[0026] The slave controller 33 communicates with the master controller 44 on the CPU board 40 via the inter-board communication bus 50. The slave controller 33 stores the output digital data transferred from the master controller 44 in the memory 32. The slave controller 33 outputs the output digital data stored in the memory 32 to a corresponding external device.

[0027] The CPU board 40 transmits and receives data to and from each input / output board via the inter-board communication bus 50. Furthermore, the CPU board 40 executes protection control calculations based on data representing the amount of electricity in the power system acquired by the analog input board 10. As shown in FIG. 1 , the CPU board 40 includes a CPU 41, a CPU memory 42, a memory 43 for a master controller 44, and the master controller 44.

[0028] The CPU 41 executes protection control calculations and controls the entire digital protection relay 100. The CPU memory 42 includes a RAM (Random Access Memory) and a ROM (Read Only Memory) used as the main memory of the CPU 41. An electrically rewritable non-volatile memory such as a flash memory may be used as the ROM.

[0029] The memory 43 is a memory for the master controller 44 that is accessed by the master controller 44, but is also configured to be directly accessible from the CPU 41. The memory 43 may be an electrically rewritable nonvolatile memory such as a flash memory.

[0030] The master controller 44 communicates with each of the slave controllers 14, 23, and 33 via an inter-board communication bus 50. The master controller 44 stores digital data received from each of the analog input boards 10 and each of the digital input boards 20 via the inter-board communication bus 50 in memory 43. In addition, the master controller 44 transmits output digital data to the corresponding digital output board 30 via the inter-board communication bus 50 in accordance with a request from the CPU 41.

[0031] The master controller 44 and the slave controllers 14, 23, and 33 may be configured by dedicated circuits such as an ASIC (Application Specific Integrated Circuit), or may be configured by using an FPGA (Field Programmable Gate Array).

[0032] When the above input / output boards are compared in terms of transfer data capacity, the analog input board 10 has a relatively large transfer data capacity, whereas the digital input board 20 and digital output board 30 have a relatively small transfer data capacity.

[0033] [Features of board-to-board communication] Below is a summary of the features of inter-board communication in the above-mentioned configuration of the digital protection relay 100. One of the features of inter-board communication is that the master controller 44 has a communication control function within the digital protection relay 100 in order to reduce the control load for data communication on the CPU 41. After receiving the minimum necessary control from the CPU 41, the master controller 44 communicates with each of the slave controllers 14, 23, and 33 autonomously without being controlled by the CPU 41.

[0034] 2 is a state transition diagram showing the operation of the master controller 44. The master controller 44 performs data communication with each of the slave controllers 14, 23, and 33 in accordance with the state transition diagram (stages 0 to 3) of FIG.

[0035] First, in the initial setting (Stage 0), the CPU 41 initially sets the type designation (DI / DO / AI) and communication cycle of each input / output board to the master controller 44. The master controller 44 notifies the CPU 41 that the setting is complete.

[0036] In the next common configuration setting (Stage 1), the master controller 44 sets the initial setting information received from the CPU 41 in each of the slave controllers 14, 23, and 33. After confirming responses from each of the slave controllers 14, 23, and 33, the master controller 44 notifies the CPU 41 that the settings have been completed.

[0037] In the next individual configuration setting (Stage 2), the master controller 44 sets protection relay-specific settings such as power system information and analog-to-digital conversion characteristics for the slave controllers 14 of each analog input board 10. After confirming a response from the slave controllers 14 of each analog input board 10, the master controller 44 notifies the CPU 41 that the settings are complete.

[0038] In the next data transfer (Stage 3), the master controller 44 transfers data at regular intervals between the slave controllers 14, 23, and 33. When the master controller 44 completes data transfers with all of the input / output boards, it issues an interrupt signal to the CPU 41. This allows the CPU 41 to process the transferred data all at once by accessing the memory 43 of the master controller 44. The communication control by the master controller 44 will be described in more detail below with reference to FIGS. 3 to 5.

[0039] Figures 3 to 5 are timing diagrams showing the procedure of inter-board communication for each stage in Figure 2. Figure 3 shows the cases of stages 0 and 1, Figure 4 shows the case of stage 2, and Figure 5 shows the case of stage 3.

[0040] 3, in stage 0, CPU 41 directly writes initial settings such as the type of each input / output board and the communication cycle into memory 43 of master controller 44 (S1, S2). Master controller 44 notifies CPU 41 of completion of the settings by an interrupt signal (S3). In response to the interrupt signal, CPU 41 transitions the processing from stage 0 to stage 1 (S4). Based on a command from CPU 41, master controller 44 transitions the processing from stage 0 to stage 1 (S5).

[0041] In stage 1, the CPU 41 writes the initial settings of each of the analog input board 10, digital input board 20, and digital output board 30, No. 1 to No. X, all at once directly into the memory 43 of the master controller 44 (S6, S7).

[0042] Next, the master controller 44 first transmits the corresponding initial settings to the No. 1 analog input board 10 (S8). The slave controller 14 of the No. 1 analog input board 10 stores the received initial settings in memory 13 and responds to the master controller 44 (S9). Next, the master controller 44 transmits the corresponding initial settings to the No. 1 digital input board 20 (S10). The slave controller 23 of the No. 1 digital input board 20 stores the received initial settings in memory 22 and responds to the master controller 44 (S11). Subsequently, the initial settings are performed for each input / output board in the order in which the input / output boards are arranged. The master controller 44 transmits the corresponding initial settings to the No. X digital output board 30, which is the last input / output board (S12). The slave controller 33 of the No. X digital output board 30 stores the received initial settings in memory 32 and responds to the master controller 44 (S13).

[0043] This completes the confirmation of the board insertion location and type of input / output board. The master controller 44 notifies the CPU 41 of the completion of the setting by an interrupt signal (S14). In response to the interrupt signal, the CPU 41 transitions the processing from stage 1 to stage 2 (S15). Based on a command from the CPU 41, the master controller 44 transitions the processing from stage 1 to stage 2 (S16).

[0044] 4, in stage 2, the CPU 41 writes all the individual settings related to the protection relays No. 1 to No. X of the analog input boards 10 directly into the memory 43 of the master controller 44 (S20, S21). The individual settings refer to settings specific to the protection relay devices, such as information on the power system, analog-to-digital conversion characteristics, and setting values.

[0045] Next, the master controller 44 first transmits the corresponding individual settings to the No. 1 analog input board 10 (S22). The slave controller 14 of the No. 1 analog input board 10 stores the received individual settings in memory 13 and responds to the master controller 44 (S23). Subsequently, the individual settings are sequentially set for each analog input board 10 in the order in which the analog input boards 10 are arranged. The master controller 44 transmits the corresponding individual settings to the No. X analog input board 10, which is the last analog input board 10 (S24). The slave controller 14 of the No. X analog input board 10 stores the received individual settings in memory 13 and responds to the master controller 44 (S25).

[0046] This completes the setting of information such as the power system information in the analog input board 10. The master controller 44 notifies the CPU 41 of the completion of the setting by an interrupt signal (S26). In response to the interrupt signal, the CPU 41 transitions the processing from stage 2 to stage 3 (S27). Based on a command from the CPU 41, the master controller 44 transitions the processing from stage 2 to stage 3 (S28).

[0047] 5, in stage 3, first, CPU 41 collectively writes data to be output from No. 1 to No. X of digital output board 30 directly into memory 43 of master controller 44 (S30, S31).

[0048] In parallel with the above, each analog input board 10 and each digital input board 20 respectively acquires analog data and digital data from outside the digital protection relay 100 (S32, S33). This data acquisition is performed periodically, and this is the first time.

[0049] Based on the above data import, the master controller 44 first requests the No. 1 analog input board 10 to transmit the imported data (S34). In response to this request, the slave controller 14 of the No. 1 analog input board 10 transmits the imported data to the master controller 44 (S36). The master controller 44 stores the transferred data in memory 43. Thereafter, data imported by each analog input board 10 and each digital input board 20 is similarly transmitted to the master controller 44 and stored in memory 43.

[0050] Furthermore, the master controller 44 transmits the output data received from the CPU 41 to each digital output board 30. The slave controller 33 of each digital output board 30 writes the received output data to the memory 32. This sets data for, for example, opening and closing an external contact. Finally, the write data for the No. X digital output board 30 is output from the master controller 44 (S36) and stored in the memory 32 of the No. X digital output board 30 (S37).

[0051] This completes the first cycle of data exchange between the master controller 44 and each of the slave controllers 14, 23, and 33. When the master controller 44 receives a response from the No. X digital output board 30, it requests the CPU 41 to access the memory 43 by using an interrupt signal (S38). In response to this interrupt signal, the CPU 41 directly reads out all of the input data from each analog input board 10 and each digital input board 20 that is stored in the memory 43 (S40, S41). Furthermore, the CPU 41 directly writes all of the data to be output to the outside from the digital output boards 30 No. 1 through No. X into the memory 43 of the master controller 44 (S40, S41).

[0052] In parallel with the above, each analog input board 10 and each digital input board 20 respectively acquires analog data and digital data from outside the digital protection relay 100 as data acquisition for the second period (S42, S43). Furthermore, each digital output board 30 outputs output data that has already been received from the master controller 44 to outside the digital protection relay 100 (S42, S44).

[0053] Based on the above data import, the master controller 44 first requests the No. 1 analog input board 10 to transmit the imported data (S45). In response to this request, the slave controller 14 of the No. 1 analog input board 10 transmits the imported data to the master controller 44 (S46). The master controller 44 stores the received data in memory 43. Thereafter, data imported by each analog input board 10 and each digital input board 20 is similarly transmitted to the master controller 44 and stored in memory 43.

[0054] Furthermore, the master controller 44 transmits the output data received from the CPU 41 to each digital output board 30. The slave controller 33 of each digital output board 30 writes the received output data to the memory 32. Finally, the output data for the No. X digital output board 30 is output from the master controller 44 (S47) and stored in the memory 32 of the No. X digital output board 30 (S48).

[0055] This completes the second cycle of data exchange between the master controller 44 and each of the slave controllers 14, 23, and 33. When the master controller 44 receives a response from the No. X digital output board 30, it sends an interrupt signal to the CPU 41 requesting access to the memory 43 (S49). Thereafter, the same procedure is repeated.

[0056] The timing of the above inter-board communication can be summarized as follows: First, access from the CPU 41 to the master controller 44 occurs (i) at the start of each stage (S1, S6, S20, S30) and (ii) when an interrupt is received from the master controller 44 (S4, S15, S27, S38).

[0057] The master controller 44 and the slave controllers 14, 23, and 33 communicate with each other at regular intervals (S34 to S37, S45 to S48), whereby data is exchanged between the memories 43 and the memories 13, 22, and 32 of both the master controller 44 and the slave controllers 14, 23, and 33.

[0058] In response to an interrupt signal (S38) from the master controller 44, the CPU 41 accesses the memory 43 of the master controller 44 (S40, S41). This allows the data acquired by the analog input board 10 and the digital input board 20 to be taken in, and the output data from the digital output board 30 to be written, all at once.

[0059] The master controller 44 collectively provides the CPU 41 with the input data (S34, S35) received from each analog input board 10 and each digital input board 20 in the previous cycle (S41). The master controller 44 also outputs the output data (S31, S41) received collectively from the CPU 41 from each digital output board 30 to each digital output board 30 by the next cycle (S36, S47).

[0060] Each slave controller 14, 23, 33 acquires data from outside the digital protection relay 100 and controls the opening and closing of the corresponding contacts using the output data before receiving a request to send input data and an output command for output data from the master controller 44. Upon receiving a request to send input data, the slave controllers 14, 23 of each analog input board 10 and each digital input board 20 immediately return the input data for the current cycle as a response.

[0061] [Master controller memory control] To simplify the processing of the CPU 41 during data communication, the memory 43 of the master controller 44 is divided into areas according to use, communication frequency, board location, and write-only / read-only.

[0062] 6 to 8 are diagrams showing specific examples of memory maps of memory 43 provided in master controller 44. Fig. 6 shows the memory area used in stage 1, Fig. 7 shows the memory area used in stage 2, and Fig. 8 shows the memory area used in stage 3.

[0063] 6, common configuration memory area 60 is divided into memory areas for each input / output board that performs data communication. This allows master controller 44 to communicate directly with each input / output board without control by CPU 41.

[0064] 7, the specific configuration memory area 61 is divided into memory areas for each analog input board 10 that performs data communication. This allows the master controller 44 to communicate directly with each analog input board 10 without the control of the CPU 41.

[0065] 8, input data of each analog input board 10 and each digital input board 20 read by the CPU 41 in stage 3 is collected in an input buffer memory area 62. Also, output data of each digital output board 30 written by the CPU 41 in stage 3 is collected in an output buffer memory area 63. This makes it easier for the CPU 41 to access the input buffer memory area 62 and the output buffer memory area 63 in bulk. Also, the memory sizes of the buffer memory areas 62 and 63 are determined so as to maximize communication efficiency when the CPU 41 accesses them in bulk.

[0066] [Summary and Effects of the First Embodiment] The features of the digital protective relay of the first embodiment described above can be summarized as follows: First, data communication between each of the input / output boards 10 to 30 and the CPU board 40 is executed by a controller specialized for data communication within the digital protective relay 100. This reduces the processing load of the data communication processing on the CPU 41, and improves the data communication performance between the boards.

[0067] As the controller, a master controller 44 having a memory 43 accessible from a CPU 41 is provided on a CPU board 40. Slave controllers 14 and 23 for controlling the acquisition of input data are provided on analog input boards 10 and 20. A slave controller 33 for controlling the output of output data is provided on a digital output board 30.

[0068] The master controller 44 autonomously and periodically performs data communication with the slave controllers 14, 23, and 33 of the input / output boards without being controlled by the CPU 41. This reduces the load on the CPU 41.

[0069] When the master controller 44 performs data communication with each input / output board, it updates the memory contents of addresses predetermined for each input / output board. The data in the memory 43 is arranged together for each stage and input / output board to facilitate easy access by the CPU 41. In this way, the areas in the memory 43 where the input data and output data are stored are predetermined and shared by the CPU 41 and the master controller 44. This allows the CPU 41 to directly access the addresses.

[0070] When data communication with each input / output board is completed, the master controller 44 issues an interrupt signal to the CPU 41. In response to the interrupt signal, the CPU 41 accesses the memory 43 of the master controller 44. This reduces the frequency with which the CPU 41 monitors data communication.

[0071] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0072] 10 Analog input board (input / output board), 13, 22, 32, 43 Memory, 14, 23, 33 Slave controller, 20 Digital input board (input / output board), 30 Digital output board (input / output board), 40 CPU board, 41 CPU, 44 Master controller, 50 Inter-board communication bus, 100 Digital protection relay.

Claims

1. A digital protective relay, A communication bus; A plurality of input / output boards, each of which transmits output data to an external device of the digital protection relay or receives input data from the external device; a processing board that performs data communication of the output data and the input data with the plurality of input / output boards via the communication bus, The processing board includes: a central processing unit that performs a protection control calculation for the power system based on the input data; a memory for storing the output data and the input data; a master controller for controlling the data communication; The master controller autonomously performs data communication with the plurality of input / output boards at regular intervals without being controlled by the central processing unit, and issues an interrupt signal to the central processing unit when all of the input data from the plurality of input / output boards has been written to the memory.

2. The digital protection relay according to claim 1, wherein, when the central processing unit receives the interrupt signal from the master controller, the central processing unit directly reads the input data stored in the memory in a batch and directly writes the output data in a batch to the memory.

3. 3. The digital protection relay according to claim 2, wherein the area in the memory where the input data and the output data are stored is predetermined and shared by the central processing unit and the master controller.

4. each of the plurality of input / output boards includes a slave controller; The slave controller transmits the output data or receives the input data from outside the digital protection relay between periodic data communication with the master controller. Digital protection relay according to any one of claims 1 to 3.

5. The plurality of input / output boards include: a plurality of analog input boards that detect analog signals representing electrical quantities in the power system and convert them into digital data; A plurality of digital input boards for acquiring digital data from outside the digital protection relay; The digital protection relay according to claim 4, further comprising a plurality of digital output boards that output digital data to the outside of the digital protection relay.

6. 6. The digital protection relay according to claim 5, wherein the master controller, after being initialized by the central processing unit, communicates with the slave controller of each of the plurality of input / output boards to initialize the plurality of input / output boards, and then communicates with the slave controller of each of the plurality of analog input boards to configure settings specific to the plurality of analog input boards.

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