Gate driver and display device including the same

Abstract

To provide a gate drive part and a display device including the same.SOLUTION: In a display part, a gate drive part comprises a plurality of signal transmission parts which are cascaded through a carry line applied with a carry signal from a signal transmission part of a precedent stage, and the plurality of signal transmission parts each include: a first output circuit which inputs a carry signal from a signal transmission part of a precedent stage and outputs a first gate signal according to the voltage between a (1-1)st node and a (1-2)nd control node; a second output part which outputs a second gate signal according to the voltage between a (2-1)st control node connected to the (1-2)nd control node and a (2-2)nd control node connected to the (1-1)st node; and a third output circuit part which outputs a third gate signal according to the voltage between a (3-1)st control node connected to the (1-2)nd control node and a (3-2)nd control node connected to the (1-1)st control node.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a gate driver and a display device including the same. [Background technology]

[0002] The display devices include a liquid crystal display (LCD), an electroluminescence display (ELD), a field emission display (FED), a plasma display panel (PDP), and the like.

[0003] Electroluminescent displays are broadly classified into inorganic light-emitting displays and organic light-emitting displays depending on the material of the light-emitting layer. Active matrix type organic light-emitting displays include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light themselves, and have the advantages of fast response speed, luminous efficiency, brightness, and a wide viewing angle.

[0004] Some display devices, such as liquid crystal display devices and organic light emitting display devices, include a display panel including a plurality of pixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver, etc. The driver includes a gate driver that supplies gate signals such as scan signals and emission control signals to the display panel, and a data driver that supplies data signals to the display panel, etc.

[0005] Such a display device can display an image when drive signals, such as gate signals and data signals, are supplied to a plurality of pixels formed on a display panel, causing the selected pixels to transmit light or emit light themselves. Summary of the Invention [Problem to be solved by the invention]

[0006] Each of the pixels includes a pixel circuit, and a plurality of switch elements included in the pixel circuit are driven by a plurality of gate signals. As the number of switch elements increases, the number of gate signals increases, but the bezel size increases because additional gate drivers and signal lines must be provided to output the gate signals.

[0007] The present invention aims to address the above-mentioned needs and / or problems.

[0008] The present invention provides a gate driver and a display device including the same.

[0009] The objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0010] A gate driver according to an embodiment of the present invention may include a plurality of signal transmission units cascaded via a carry line to which a carry signal is applied from a previous signal transmission unit, and each of the plurality of signal transmission units may include: a first output circuit unit that receives the carry signal from a previous signal transmission unit and outputs a first gate signal in response to voltages between a first-1 control node and a first-2 control node; a second output circuit unit that outputs a second gate signal in response to voltages between a second-1 control node connected to the first-2 control node and a second-2 control node connected to the first-1 control node; and a third output circuit unit that outputs a third gate signal in response to voltages between a third-1 control node connected to the first-2 control node and a third-2 control node connected to the first-1 control node.

[0011] A display device according to an embodiment of the present invention includes a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels are arranged, a data driver for supplying data voltages of pixel data to the data lines, and a gate driver for supplying gate signals to the gate lines, the gate driver including a plurality of signal transmission units cascaded via a carry line to which a carry signal is applied from a previous signal transmission unit, and each of the plurality of signal transmission units receives a carry signal from the previous signal transmission unit. The transistor may include a first output circuit unit that outputs a carry signal and a first gate signal in response to voltages between a first control node (1-1) and a first control node (1-2), a second output circuit unit that outputs a second gate signal in response to voltages between a second control node (2-1) connected to the first control node and a second control node (2-2) connected to the first control node, and a third output circuit unit that outputs a third gate signal in response to voltages between a third control node (3-1) connected to the first control node and a third control node (3-2) connected to the first control node. [Effects of the Invention]

[0012] The present invention realizes one individually driven EM driver and two scan drivers in one gate driver, thereby reducing the number of gate drivers and the number of signal lines and pad pins required, thereby reducing the bezel size.

[0013] The present invention outputs a plurality of gate signals by utilizing internal signals without using other external signals, thereby reducing power consumption and enabling low-power driving.

[0014] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawings]

[0015] [Figure 1]FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. [Figure 3] FIG. 3 is a diagram showing a pixel circuit according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing the driving timing of the pixel circuit shown in FIG. [Figure 5] FIG. 5 is a diagram illustrating a configuration of a gate driver according to an embodiment of the present invention. [Figure 6] FIG. 6 is a diagram illustrating a signal application principle of the third gate driver shown in FIG. [Figure 7] FIG. 7 is a diagram illustrating a shift register of a gate driver according to an embodiment of the present invention. [Figure 8] FIG. 8 is a detailed circuit diagram of a first EM driver according to an embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing a driving waveform of the first EM driving unit shown in FIG. [Figure 10] FIG. 10 is a detailed circuit diagram of a gate driver according to an embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing driving waveforms of the gate driver shown in FIG. [Figure 12] FIG. 12 is a diagram for explaining the operation principle of the gate driver shown in FIG. [Figure 13] FIG. 13 is a diagram for explaining the operation principle of the gate driver shown in FIG. [Figure 14] FIG. 14 is a diagram for explaining the operation principle of the gate driver shown in FIG. [Figure 15] FIG. 15 is a diagram for explaining the operation principle of the gate driver shown in FIG. [Figure 16] FIG. 16 is a diagram for explaining the operation principle of the gate driver shown in FIG. [Figure 17] FIG. 17 is a diagram for explaining the operation principle of the gate driver shown in FIG. [Figure 18] FIG. 18 is a diagram showing a simulation result of the gate driver according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] The advantages and features of the present invention, as well as methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various separate forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the invention to those skilled in the art. The present invention is defined only by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present invention are merely examples, and the present invention is not limited to the shown details. The same reference numerals refer to the same components throughout the specification. Furthermore, when describing the present invention, if a detailed description of related known technology is deemed to obscure the gist of the present invention, the detailed description will be omitted.

[0018] When the terms "comprise," "include," "have," "consist of," etc. are used in this specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it includes the plural unless otherwise expressly stated.

[0019] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0020] When describing the positional relationship between two parts, for example, "above," "on top of," "below," "to the side of," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0021] In the description of the embodiments, terms such as "first" and "second" are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical concept of the present invention.

[0022] Like reference numbers refer to like elements throughout the specification.

[0023] The features of many of the embodiments can be partially or fully combined or combined with each other, and various technical interlocking and driving mechanisms are possible. Each embodiment can be implemented independently of the others, or can be implemented together in a linked relationship.

[0024] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0025] In the display device of the present invention, the pixel circuit and the gate drive circuit may include a plurality of transistors, which may be oxide TFTs (Thin Film Transistors) including an oxide semiconductor or LTPSTFTs including low temperature polysilicon (LTPS).

[0026] A transistor is a three-electrode device that includes a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Within a transistor, carriers flow out from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In an n-channel transistor, the carriers are electrons, so the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source side. In a p-channel transistor, the carriers are holes, so the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, holes flow from the source to the drain side, so current flows from the source to the drain side. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first and second electrodes.

[0027] The gate signal can swing between a gate on voltage and a gate off voltage. The gate on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0028] A transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage and the gate-off voltage may be a gate low voltage. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage and the gate-off voltage may be a gate high voltage.

[0029] 1 is a block diagram showing a display device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG.

[0030] 1 and 2, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply unit 400 for generating power required to drive the pixels and the display panel driving circuit.

[0031] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL that intersect with the data lines DL, and pixels 101 arranged in a matrix.

[0032] The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel line share a gate line GL. The pixels arranged in the column direction Y along the data line direction share the same data line DL. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0033] A touch sensor may be disposed on the display panel 100. The touch sensor is omitted in FIG. 1 . Touch input may be sensed using a separate touch sensor or through a pixel. The touch sensor may be an on-cell type or an add-on type disposed on the screen of the display panel, or an in-cell type incorporated into the pixel array AA.

[0034] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic thin film may be disposed on a back plate of the plastic OLED panel, and a pixel array AA may be formed on the organic thin film.

[0035] The back plate of the plastic OLED may be a PET (Polyethylene terephthalate) substrate. An organic thin film may be formed on the back plate. A pixel array AA and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture so that the pixel array AA is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multi-layer buffer film made of an insulating material (not shown) may be formed on the organic thin film. Wiring for supplying power and signals to the pixel array AA and the touch sensor array may be formed on the organic thin film.

[0036] Each pixel may be divided into a red pixel (hereinafter referred to as an "R pixel"), a green pixel (hereinafter referred to as a "G pixel"), and a blue pixel (hereinafter referred to as a "B pixel") for color implementation. Each pixel may further include a white pixel. Each pixel 101 includes a pixel circuit. The pixel circuit is connected to a data line DL and a gate line GL.

[0037] As shown in FIG. 2, the cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light emitting element layer EMIL, and an encapsulation layer ENC stacked on a substrate SUBS.

[0038] The circuit layer CIR may include pixel circuits, gate drivers, demultiplexers, etc., connected to wiring such as data lines, gate lines, and power lines. The circuit layer CIR may include a plurality of metal layers and semiconductor material layers insulated by insulating layers. All transistors formed in the circuit layer CIR may be implemented as n-channel oxide TFTs.

[0039] The light-emitting element layer EMIL may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a light-emitting element for a red subpixel, a light-emitting element for a green subpixel, and a light-emitting element for a blue subpixel. The light-emitting element layer EMIL may further include a light-emitting element for a white subpixel. In each subpixel, the light-emitting element layer EMIL may have a structure in which a light-emitting element and a color filter are stacked. The light-emitting element EL of the light-emitting element layer EMIL may be covered with multiple protective layers including organic films and inorganic films.

[0040] The encapsulation layer ENC covers the light-emitting element layer EMIL so as to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer ENC may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the migration path of moisture and oxygen becomes longer compared to a single layer, and the penetration of moisture and oxygen that affects the light-emitting element layer EMIL can be effectively blocked.

[0041] A touch sensor layer (not shown in the drawing) may be formed on the encapsulation layer ENC, and a polarizer and a color filter layer may be disposed thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern that forms the capacitance of the touch sensor and an insulating film. The insulating film may insulate crossing portions of the metal wiring pattern and planarize the surface of the touch sensor layer. The polarizer may convert the polarization of external light reflected by metals in the touch sensor layer and the circuit layer to improve visibility and contrast ratio. The polarizer may be embodied as a polarizer formed by bonding a linear polarizer and a phase delay film or a circular polarizer. A cover glass may be bonded on the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer absorbs part of the wavelengths of light reflected from the circuit layer and the touch sensor layer, thereby replacing the role of a polarizer and improving the color purity of an image reproduced by the pixel array.

[0042] The power supply unit 400 uses a DC-DC converter to generate a DC voltage (or a constant voltage) required to drive the pixel array and the display panel driving circuit of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 400 adjusts the level of a DC input voltage applied from a host system (not shown) to generate constant voltages such as a gamma reference voltage VGMA, gate-on voltages VGH, VEH, gate-off voltages VGL, VEL, pixel driving voltage EVDD, low-potential pixel base voltage EVSS, initialization voltage VINIT, and reference voltage VREF. The gamma reference voltage is supplied to the data driver 110. The gate-on voltage VGH and gate-off voltage VGL are supplied to the gate driver 120. Constant voltages such as a pixel driving voltage EVDD, a pixel base voltage EVSS, an initialization voltage VINIT, and a reference voltage VREF can be supplied to the pixels 101 through power lines commonly connected to the pixels 101.

[0043] The display panel drive circuit writes pixel data of an input video to the pixels of the display panel 100 under the control of a timing controller 130 .

[0044] The display panel driving circuit includes a data driver 110 and a gate driver 120 .

[0045] A demultiplexer may be further provided between the data driver 110 and the data lines DL. The demultiplexer is omitted in Fig. 1. The demultiplexer sequentially connects one channel of the data driver 110 to a plurality of data lines DL and distributes the data voltage output from one channel of the data driver 110 to the data lines DL in a time-division manner, thereby reducing the number of channels of the data driver 110.

[0046] The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in Fig. 1. In a mobile device, the timing controller 130, the power supply unit 400, the data driving unit 110, etc. may be integrated into one drive integrated circuit (IC).

[0047] The data driver 110 converts pixel data of an input image received from the timing controller 130 into a gamma compensation voltage every frame period using a DAC (Digital to Analog Converter) to generate a data voltage Vdata. The gamma reference voltage VGMA is divided by a voltage divider circuit for each gray scale. The gamma compensation voltages divided from the gamma reference voltage VGMA are provided to the DAC of the data driver 110. The data voltages Vdata are output from each channel of the data driver 110 via an output buffer.

[0048] In the data driver 110, the output buffer included in one channel may be connected to the adjacent data line DL through a demultiplexer. The demultiplexer may be formed directly on the substrate of the display panel 100 or may be integrated with the data driver 110 into one drive IC.

[0049] The gate driver 120 may be implemented as a GIP (Gate in Panel) circuit formed directly on a bezel region BZ of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driver 120 can sequentially supply the gate signals to the gate lines GL by shifting the gate signals using a shift register.

[0050] The clock output from the level shifter 140 swings between a gate-on voltage VGH and a gate-off voltage VGL and is supplied to the gate driver 120 via a clock line CL. The gate driver 120 can sequentially output gate signals using the clock output from the level shifter 140.

[0051] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized therewith from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, and a data enable signal DE. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted because the vertical period and horizontal period can be determined by counting the data enable signal DE. The data enable signal DE has a period of one horizontal period (1H).

[0052] The timing controller 130 can control the operation timing of the display panel drive circuit at an input frame frequency Xi (i is a positive integer greater than 0) Hz by multiplying the input frame frequency by i. The input frame frequency is 60 Hz for the NTSC (National Television Standards Committee) system and 50 Hz for the PAL (Phase-Alternating Line) system.

[0053] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0054] The voltage levels of the gate timing control signals output from the timing controller 130 may be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL through a level shifter (not shown) and supplied to the gate driver 120. That is, the level shifter converts the low level voltages of the gate timing control signals into gate low voltages VGL and VEL, and converts the high level voltages of the gate timing control signals into gate high voltages VGH and VEH. The gate timing control signals include a start pulse and a shift clock.

[0055] The host system may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. In the mobile device and the wearable device, the data driver 110, the gate driver 120, the timing controller 130, etc. may be integrated into one drive IC (DIC).

[0056] FIG. 3 is a diagram showing a pixel circuit according to a first embodiment of the present invention, and FIG. 4 is a diagram showing the driving timing of the pixel circuit shown in FIG.

[0057] 3, the pixel circuit according to the first embodiment of the present invention includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a plurality of switching elements T1 to T5 for switching a current path connected to the driving element DT, a first capacitor Cst for storing a voltage between the gate and source of the driving element DT, and a second capacitor C2. The driving element DT and the switching elements T1 to T7 may be implemented as, but are not limited to, n-channel TFTs.

[0058] The light-emitting element EL emits light by a current applied through a channel of the driving element DT in response to a gate-source voltage Vgs of the driving element DT, which changes in response to the data voltage Vdata. The light-emitting element EL may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. The anode of the light-emitting element EL is connected to the driving element DT through a fourth node n4, and the cathode of the light-emitting element EL is connected to a pixel ground voltage line to which a pixel ground voltage EVSS is applied or to the second power line 42.

[0059] The OLED used for the light-emitting element EL may have a tandem structure in which multiple light-emitting layers are stacked, which can improve the brightness and lifespan of the pixel.

[0060] The driving element DT supplies a current to the light emitting element EL in response to a gate-source voltage Vgs to drive the light emitting element EL. The driving element DT includes a gate electrode connected to the second node n2, a first electrode (or drain) connected to the first node n1, and a second electrode (or source) connected to the third node n3.

[0061] The first switch element T1 is turned on in response to the gate-on voltage of the first EM signal EM1 to supply the pixel driving voltage EVDD to the driving element DT. The first switch element T1 includes a gate electrode to which the first EM signal EM1 is applied, a first electrode connected to a pixel driving voltage line or a first power line 41 to which the pixel driving voltage is applied, and a second electrode connected to a first node n1.

[0062] The second switch element T2 is turned on in response to the gate-on voltage of the first scan signal SCAN1 to connect the data line DL to the second node n2 and apply the data voltage Vdata. The second switch element T2 includes a gate electrode to which the first scan signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0063] The third switch element T3 is turned on in response to the gate-on voltage of the second scan signal SCAN2 to connect the second node n2 to the reference voltage line or the third power supply line 43 to apply the reference voltage Vref. The third switch element T3 includes a gate electrode to which the second scan signal SCAN2 is applied, a first electrode connected to the third power supply line 43, and a second electrode connected to the second node n2.

[0064] The fourth switch element T4 is turned on in response to the gate-on voltage of the second EM signal EM2 to connect the third node n3 to the fourth node n4. The fourth switch element T4 includes a gate electrode to which the second EM signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0065] The fifth switch element T5 is turned on in response to the gate-on voltage of the third scan signal SCAN3 to connect the initialization voltage line or the fourth power supply line 44 to the fourth node n4 to apply the initialization voltage Vinit. The fifth switch element T5 includes a gate electrode to which the third scan signal SCAN3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth power supply line 44.

[0066] The first capacitor Cst may be connected between the second node n2 and the third node n3 and may charge the gate-source voltage Vgs of the driving device DT.

[0067] The second capacitor C2 may be coupled between the third node n3 and the first power line 41.

[0068] 3 and 4, the pixel circuit according to the embodiment of the present invention may be driven in the order of an initialization step Tini, a sensing step Ts, a data writing step Tw, an OBS step Tobs, and a light emitting step Tem.

[0069] In the initialization stage Tini, the pixel circuit is initialized. The reference voltage Vref initializes the second node n2, and the initialization voltage Vref initializes the third node n3. In the sensing stage Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst.

[0070] In the data writing stage Tw, the data voltage Vdata of the pixel data is applied to the first node n1.

[0071] In the OBS stage Tobs, the initialization voltage Vinit is applied to the third node n3 for initialization, and in the light-emitting stage Tem, after the voltages between the second node n2 and the third node n3 rise, the light-emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data.

[0072] FIG. 5 is a diagram illustrating the configuration of a gate driver according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating a signal application principle of the third gate driver shown in FIG.

[0073] 3 requires five gate signals, i.e., SCAN1, SCAN2, SCAN3, EM1, and EM2, and therefore five separate gate drivers must be configured. In order to reduce the number of gate drivers and thereby the bezel size, in the embodiment, one gate driver is configured to output multiple gate signals.

[0074] In this case, the gate driver that outputs SCAN1 may be implemented as a shift register type, and the gate drivers that output SCAN2, SCAN3, EM1, and EM2 may be implemented as edge trigger types. Therefore, in this embodiment, SCAN2, SCAN3, and EM2 of the same type may be implemented with one gate driver.

[0075] Referring to FIG. 5, the gate driver 120 according to an embodiment of the present invention may be configured to include a first gate driver 121 that outputs a first scan signal SCAN1, a second gate driver 122 that outputs a first EM signal EM1, and a third gate driver 123 that outputs a second scan signal SCAN2, a third scan signal SCAN3, and a second EM signal EM2.

[0076] Referring to FIG. 6, the third gate driver 123 according to the embodiment may apply a second scan signal SCAN2, a third scan signal SCAN3, and a second EM signal EM2 to the pixel circuit.

[0077] For example, the third gate driver 123 may apply a second scan signal SCAN2(1), a third scan signal SCAN3(1), and a second EM signal EM2(1) to the first pixel circuit P1.

[0078] As another example, the third gate driver 123 may apply a second scan signal SCAN2(n), a third scan signal SCAN3(n), and a second EM signal EM2(n) to the n-th pixel circuit Pn.

[0079] FIG. 7 is a diagram illustrating a shift register of a gate driver according to an embodiment of the present invention.

[0080] Referring to FIG. 7, the gate driver according to the embodiment includes a shift register that sequentially outputs gate signals in synchronization with a shift clock CLK.

[0081] The shift register includes a plurality of signal transmission units ST_D(1), ST_D(2), ST(1), ..., ST(n-2), ST(n-1), ST(n) cascaded (connected in series) via a carry line through which a carry signal is transmitted.

[0082] The start signal VST is generally input to a first signal transmission unit, where the first dummy signal transmission unit ST_D(1) may be the first signal transmission unit to which the start signal VST is input.

[0083] Each of the signal transmission units ST_D(1), ST_D(2), ST(1), ..., ST(n-2), ST(n-1), and ST(n) receives a start pulse or a carry signal output from a preceding signal transmission unit, and also receives a shift clock CLK. The first signal transmission unit ST_D(1) begins to operate in response to the start pulse VST, while the other signal transmission units ST_D(2), ST(1), ..., ST(n-2), ST(n-1), and ST(n) begin to operate in response to a carry signal input from a preceding signal transmission unit. The shift clock CLK may be an N-phase clock (N is a positive integer greater than or equal to 2). For example, the shift clock CLK may be two-phase clocks CLK1 and CLK2. The two-phase shift clocks CLK1 and CLK2 have opposite phases.

[0084] Each of the signal transmission units ST(1), ..., ST(n-2), ST(n-1), ST(n) can output a first EM pulse EM2(n) through a first output node, output a second scan signal SCAN2(n) through a second output node, and output a third scan signal SCAN3(n) through a third output node.

[0085] FIG. 8 is a circuit diagram showing in detail a first EM driver according to an embodiment of the present invention, and FIG. 9 is a diagram showing the driving waveforms of the first EM driver shown in FIG.

[0086] 8 and 9, the first EM driver according to the embodiment may output a first EM signal EM1(n) and may include a plurality of transistors T1 to T7.

[0087] The first transistor T1 is turned on when the shift clock CLK is at a high voltage VGH2 that is equal to or higher than the gate-on voltage VEH, and supplies the voltage of the carry signal C(n-1) to the buffer node Qh. The first transistor T1 includes a first electrode connected to the (n-1)th carry signal line C(n-1), a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the buffer node Qh.

[0088] The second transistor T1A is turned on when the shift clock CLK is at a voltage (VGH2) equal to or higher than the gate-on voltage VEH, and supplies the voltage of the buffer node Qh to the first control node Q(n), thereby charging the first control node. The second transistor T1A includes a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the first control node Q(n).

[0089] The first and second transistors T1 and T1A are connected in series between the (n-1)th carry signal line C(n-1) and the first control node Q(n).

[0090] The third q transistor T3q is turned on when the first control node Q(n) is charged and supplies a second high voltage to the buffer node Qh via a second high voltage line GVDD1. The second high voltage GVDD1 is supplied to the buffer node Qh via the second high voltage line. The third q transistor T3q includes a first electrode coupled to the second high voltage line GVDD1, a gate electrode coupled to the first control node Q(n), and a second electrode coupled to the buffer node Qh.

[0091] The 41st transistor T41 and the 41Ath transistor T41A are turned on when the voltage of the second control node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1) is a high voltage equal to or higher than the gate-on voltage VEH, and supply the second high potential voltage GVDD1 to the first node 80, thereby charging the first node 80 to the gate-on voltage VEH or higher. The 41st transistor T41 includes a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the second control node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1), and a second electrode connected to the first electrode of the 41Ath transistor T41A. The 41Ath transistor T41A includes a first electrode connected to the second electrode of the 41st transistor T41, a gate electrode connected to the second control node Qb(n-1) of the n-1th signal transmission unit ST(n-1), and a second electrode connected to the first node 80.

[0092] The fourth transistor T4 and the fourth A transistor T4A are turned on when the voltage of the first node 80 is a high voltage equal to or greater than the gate-on voltage VEH, connecting the second high potential voltage line GVDD1 to the second control node Qb(n) and charging the second control node Qb(n) with a high voltage equal to or greater than the gate-on voltage VEH. The fourth transistor T4 includes a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first node 80, and a second electrode connected to the first electrode of the fourth A transistor T4A. The fourth A transistor T4A includes a first electrode connected to the second electrode of the fourth transistor T4, a gate electrode connected to the first node 80, and a second electrode connected to the second control node Qb(n). A first capacitor CF is connected between the gate electrode and second electrode of the fourth A transistor T4A. When the fourth transistor T4A is turned on by the first capacitor CF, the voltage at the first node 80 can be boosted.

[0093] The 4q transistor T4q is turned on when the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, thereby connecting the first node 80 to the second control node Qb(n). The 4q transistor T4q includes a first electrode connected to the first node 80, a gate electrode connected to the buffer node Qh, and a second electrode connected to the second control node Qb(n).

[0094] The 5q transistor T5q is turned on when the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, and connects the second control node Qb(n) to the second low-potential voltage line GVSS1, thereby discharging the voltage of the second control node Qb(n) to the second low-potential voltage. The 5q transistor T5q includes a first electrode connected to the second control node Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low-potential voltage line GVSS1.

[0095] The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node in response to the voltages of the first control node Q(n) and the second control node Qb(n) to output a first EM signal EM1(n). The first pull-up transistor T6 has a gate electrode connected to the first control node Q(n), a first electrode connected to a first high-potential voltage line to which a first high-potential voltage is applied, and a second electrode connected to the first output node. The first pull-down transistor T7 is connected to the first pull-up transistor T6 across the first output node. The first pull-down transistor T7 has a gate electrode connected to the second control node Qb(n), a first electrode connected to the first output node, and a second electrode connected to a first low-potential voltage line GVSS0 to which a first low-potential voltage is applied. A second capacitor CB is connected between the gate electrode and second electrode of the first pull-up transistor T6. When the first pull-up transistor T6 is turned on by the second capacitor CB, the voltage of the first control node Q(n) can be boosted.

[0096] The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node in response to the voltages of the first control node Q(n) and the second control node Qb(n) to output the carry signal EM1_C(n) of the first EM driver. The second pull-up transistor T6cr has a gate electrode connected to the first control node Q(n), a first electrode connected to a second high-potential voltage line GVDD1 to which a second high-potential voltage is applied, and a second electrode connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr across the second output node. The second pull-down transistor T7cr has a gate electrode connected to the second control node Qb(n), a first electrode connected to the second output node, and a second electrode connected to a second low-potential voltage line GVSS1 to which a second low-potential voltage is applied.

[0097] FIG. 10 is a detailed circuit diagram of a gate driver according to an embodiment of the present invention.

[0098] Referring to FIG. 10, the gate driver according to the embodiment includes a first output circuit unit 71 that outputs a first gate signal, a second output circuit unit 72 that outputs a second gate signal, and a third output circuit unit 73 that outputs a third gate signal.

[0099] The first output circuit unit 71 can output a first gate signal, for example, a second EM signal EM2(n). Such a first output circuit unit 71 includes 1-1 to 1-13 transistors T1 to T13.

[0100] The 1-1th transistor T1 is turned on when the shift clock CLK is at a high voltage (VGH2) equal to or higher than the gate-on voltage VEH, and supplies the voltage of the (n-1)th carry signal line C(n-1) of the preceding signal transmission unit to the buffer node Qh. The 1-1th transistor T1 includes a first electrode connected to the (n-1)th carry signal line C(n-1), a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the buffer node Qh.

[0101] The first-second transistor T2 is turned on when the shift clock CLK is at a voltage (VGH2) equal to or higher than the gate-on voltage VEH, and supplies the voltage of the buffer node Qh to the first-first control node Q(n), thereby charging the first control node. The first-second transistor T2 includes a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the first-first control node Q(n).

[0102] The first and second transistors T1 and T2 are connected in series between the (n-1)th carry signal line C(n-1) and the first control node Q(n).

[0103] The first-third transistor T3 is turned on when the first-first control node Q(n) is charged and supplies a second high voltage to the buffer node Qh via a second high voltage line GVDD1. The second high voltage GVDD1 is supplied to the buffer node Qh via the second high voltage line GVDD1. The first-third transistor T3 includes a first electrode coupled to the second high voltage line GVDD1, a gate electrode coupled to the first-first control node Q(n), and a second electrode coupled to the buffer node Qh.

[0104] The 1-4th transistor T4 and the 1-5th transistor T5 are turned on when the voltage of the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1) is a high voltage equal to or higher than the gate-on voltage VEH, and supply the second high potential voltage GVDD1 to the first node 80, thereby charging the first node 80 to the gate-on voltage VEH or higher. The 1-4th transistor T4 includes a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1), and a second electrode connected to the first electrode of the 1-5th transistor T5. The 1-5th transistor T5 includes a first electrode connected to the second electrode of the 1-4th transistor T4, a gate electrode connected to the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1), and a second electrode connected to the first node 80.

[0105] The first-sixth transistor T6 and the first-seventh transistor T7 are turned on when the voltage of the first node 80 is a high voltage equal to or greater than the gate-on voltage VEH, and connect the second high-potential voltage line GVDD1 to the first-second control node Qb(n), thereby charging the first-second control node Qb(n) with a high voltage equal to or greater than the gate-on voltage VEH. The first-sixth transistor T6 has a first electrode connected to the second high-potential voltage line GVDD1, a gate electrode connected to the first node 80, and a second electrode connected to the first electrode of the first-seventh transistor T7. The first-seventh transistor T7 has a first electrode connected to the second electrode of the first-sixth transistor T6, a gate electrode connected to the first node 80, and a second electrode connected to the first-second control node Qb(n). A first capacitor CF is connected between the gate electrode and second electrode of the first-seventh transistor T7. When the first-seventh transistor T7 is turned on by the first capacitor CF, the voltage of the first node n1 can be boosted.

[0106] The 1-8th transistor T8 is turned on when the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, thereby connecting the first node 80 to the 1-2nd control node Qb(n). The 1-8th transistor T8 includes a first electrode connected to the first node 80, a gate electrode connected to the buffer node Qh, and a second electrode connected to the 1-2nd control node Qb(n).

[0107] The first-ninth transistor T9 is turned on when the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, and connects the first-second control node Qb(n) to the second low-potential voltage line GVSS1, thereby discharging the voltage of the first-second control node Qb(n) to the second low-potential voltage. The first-ninth transistor T9 includes a first electrode connected to the first-second control node Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low-potential voltage line GVSS1.

[0108] The transistor 1-10 or the pull-up transistor T10 and the transistor 1-11 or the pull-down transistor T11 charge or discharge the output node OUT1-1 in response to the voltages of the control node Q(n) of the transistor 1-1 and the control node Qb(n) of the transistor 1-2, and output a second gate signal, e.g., a second EM signal EM2(n). The pull-up transistor T10 includes a gate electrode connected to the control node Q(n), a first electrode connected to a first high-potential voltage line GVDD0 to which a first high-potential voltage is applied, and a second electrode connected to the output node OUT1-1. The pull-down transistor T11 is connected to the pull-up transistor T10 across the output node OUT1-1. The pull-down transistor T11 includes a gate electrode connected to the control node Qb(n) of the first transistor, a first electrode connected to the output node OUT1-1 of the first transistor, and a second electrode connected to a first low potential voltage line GVSS0 to which a first low potential voltage is applied.

[0109] The transistor 1-12 or the pull-up transistor T12 and the transistor 1-13 or the pull-down transistor T13 charge or discharge the output node OUT1-2 of the transistor 1-2 in response to the voltages of the control node Q(n) of the transistor 1-1 and the control node Qb(n) of the transistor 1-2, thereby outputting a carry signal EM2_C(n). The pull-up transistor T12 includes a gate electrode connected to the control node Q(n), a first electrode connected to a second high-potential voltage line GVDD1 to which a second high-potential voltage is applied, and a second electrode connected to the output node OUT1-2 of the transistor 1-2. The pull-down transistor T13 is connected to the pull-up transistor T12 across the output node OUT1-2 of the transistor 1-2. The first-second pull-down transistor T13 includes a gate electrode connected to the first-second control node Qb(n), a first electrode connected to the first-second output node OUT1-2, and a second electrode connected to a second low-potential voltage line GVSS1 to which a second low-potential voltage is applied.

[0110] The second output circuit unit 72 can output a second gate signal, for example, a second SCAN signal SCAN2(n). Such a second output circuit unit 72 includes 2-1 to 2-9 transistors T21 to T29.

[0111] The second-1st transistor T21 couples the second low potential voltage line GVSS1 to the second-1st node 81 in response to the voltage of the carry signal line EM2_C(n) of the first output circuit unit 71, thereby discharging the second low potential voltage line GVSS1 to the second low potential voltage. The second-1st transistor T21 includes a gate electrode coupled to the carry signal line EM2_C(n), a first electrode coupled to the second low potential voltage line GVSS1, and a second electrode coupled to the second-1st node 81.

[0112] The 2-2nd transistor T22 connects the 1-2nd control node Qb(n) of the first output circuit unit 71 to the 2-1st control node Q'(n) in response to the voltage of the 2-1st node 81. The 2-2nd transistor T22 includes a gate electrode connected to the 2-1st node 81, a first electrode connected to the 1-2nd control node Qb(n) of the first output circuit unit 71, and a second electrode connected to the 2-1st control node Q'(n).

[0113] The second-third transistor T23 connects the carry signal line EM1_C(n) of the first EM driver to the second-first node 81 in response to the voltage of the first-second control node Qb(n) of the first output circuit section 71. The second-third transistor T23 includes a gate electrode connected to the first-second control node Qb(n) of the first output circuit section 71, a first electrode connected to the carry signal line EM1_C(n) of the first EM driver, and a second electrode connected to the second-first node 81.

[0114] The 2-4th transistor T24 connects the 1-1st control node Q(n) of the first output circuit unit 71 to the 2-2nd control node Qb'(n) in response to the voltage of the 2-1st node 81. The 2-4th transistor T24 includes a gate electrode connected to the 2-1st node 81, a first electrode connected to the 1-1st control node Q(n) of the first output circuit unit 71, and a second electrode connected to the 2-2nd control node Qb'(n).

[0115] The 2-5th transistor T25 couples the second control node Qb(n) of the first EM driver to the 2-2nd node 82 in response to the voltage of the second control node Qb(n) of the first EM driver. The 2-5th transistor T25 includes a gate electrode and a first electrode coupled to the second control node Qb(n) of the first EM driver, and a second electrode coupled to the 2-2nd node 82.

[0116] The second-sixth transistor T26 discharges the second-first control node Q'(n) to the second low-potential voltage in response to the voltage of the second-second node 82. The second-sixth transistor T26 includes a gate electrode coupled to the second-second node 82, a first electrode coupled to the second-first control node Q'(n), and a second electrode coupled to the second low-potential voltage line GVSS1.

[0117] The 2-7th transistor T27 charges the 2-2nd control node Qb'(n) with the second high potential voltage GVDD1 in response to the voltage of the 2-2nd node 82. The 2-7th transistor T27 includes a gate electrode coupled to the 2-2nd node 82, a first electrode coupled to the 2-2nd control node Qb'(n), and a second electrode coupled to the second high potential voltage line GVDD1.

[0118] The second-8th transistor or second pull-up transistor T28 and the second-9th transistor or second pull-down transistor T29 charge and discharge the second output node OUT2 in response to the voltages of the second-1st control node Q'(n) and the second-2nd control node Qb'(n) to output a second gate signal, e.g., a second SCAN signal SCAN2(n). The second pull-up transistor T28 includes a gate electrode connected to the second-1st control node Q'(n), a first electrode connected to a first high-potential voltage line GVDD0 to which a first high-potential voltage is applied, and a second electrode connected to the second output node. The second pull-down transistor T29 is connected to the second pull-up transistor T28 across the second output node OUT2. The second pull-down transistor T29 includes a gate electrode connected to the second control node Qb'(n), a first electrode connected to the second output node OUT2, and a second electrode connected to the first low potential voltage line GVSS0 to which the first low potential voltage is applied.

[0119] The third output circuit unit 73 can output a third gate signal, for example, a third SCAN signal SCAN3(n). Such a third output circuit unit 73 includes 3-1 to 3-8 transistors T31 to T38.

[0120] The 3-1st transistor T31 connects the 1-2nd control node Qb(n) of the first output circuit unit 71 to the 3-1st control node Q''(n) in response to the voltage of the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1). The 3-1st transistor T31 includes a gate electrode connected to the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1), a first electrode connected to the 1-2nd control node Qb(n) of the first output circuit unit 71, and a second electrode connected to the 3-1st control node Q''(n).

[0121] The 3-2nd transistor T32 connects the 1-1st control node Q(n) to the 3-2nd control node Qb''(n) in response to the voltage of the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1). The 3-2nd transistor T32 includes a gate electrode connected to the 1-2nd control node Qb(n-1) of the n-1th signal transmission unit ST(n-1), a first electrode connected to the 1-1st control node Q(n), and a second electrode connected to the 3-2nd control node Qb''(n).

[0122] The 3-3rd transistor T33 connects the 2-2nd node 82 to the 2-3rd node 83 in response to the voltage of the carry signal line EM1_C(n) of the first EM driver. The 3-3rd transistor T33 includes a gate electrode connected to the carry signal line EM1_C(n) of the first EM driver, a first electrode connected to the 2-2nd node 82, and a second electrode connected to the 2-3rd node 83.

[0123] The third-fourth transistor T34 connects the carry signal line EM2_C(n) to the second-third node 83 in response to the voltage of the carry signal line EM1_C(n) of the first EM driver. The third-fourth transistor T34 includes a gate electrode connected to the carry signal line EM1_C(n) of the first EM driver, a first electrode connected to the carry signal line EM2_C(n), and a second electrode connected to the second-third node 83.

[0124] The 3-5th transistor T35 discharges the 3-1st control node Q''(n) to the second low potential voltage in response to the voltage of the 2-3rd node 83. The 3-5th transistor T35 includes a gate electrode coupled to the 2-3rd node 83, a first electrode coupled to the 3-1st control node Q''(n), and a second electrode coupled to the second low potential voltage line GVSS1.

[0125] The 3-6th transistor T36 charges the 3-2nd control node Qb''(n) with the second high potential voltage in response to the voltage of the 2-3rd node 83. The 3-6th transistor T36 includes a gate electrode coupled to the 2-3rd node 83, a first electrode coupled to the 3-2nd control node Qb''(n), and a second electrode coupled to the second high potential voltage line GVDD1.

[0126] The 3-7th transistor or third pull-up transistor T37 and the 3-8th transistor or third pull-down transistor T38 charge and discharge the third output node OUT3 in response to the voltages of the 3-1st control node Q''(n) and the 3-2nd control node Qb''(n) to output a third gate signal, for example, a third SCAN signal SCAN3(n). The third pull-up transistor T37 includes a gate electrode connected to the 3-1st control node Q''(n), a first electrode connected to a first high potential voltage line GVDD0 to which a first high potential voltage is applied, and a second electrode connected to the third output node OUT3. The third pull-down transistor T38 is connected to the third pull-up transistor T37 across the third output node OUT3. The third pull-down transistor T38 includes a gate electrode connected to the third-2 control node Qb''(n), a first electrode connected to the third output node OUT3, and a second electrode connected to the first low potential voltage line GVSS0 to which the first low potential voltage is applied.

[0127] FIG. 11 is a diagram showing the driving waveforms of the gate driver shown in FIG. 10, and FIGS. 12 to 17 are diagrams for explaining the operation principle of the gate driver shown in FIG.

[0128] 11 and 12, in section (1), the control node Q(n) of the first output circuit unit 1-1 becomes a high voltage, and the control node Qb(n) of the first output circuit unit 1-2 becomes a low voltage, causing the carry signal of the first output circuit unit 1-1 and the first gate signal to output a high voltage.

[0129] The control node Q'(n) of the second output circuit unit 2-1 becomes a low voltage, the control node Qb'(n) of the second output circuit unit 2-2 becomes a high voltage, and the second gate signal outputs a low voltage.

[0130] The control node Q''(n) of the 3-1 of the third output circuit unit becomes a low voltage, the control node Qb''(n) of the 3-2 becomes a high voltage, and the third gate signal outputs a low voltage.

[0131] 11 and 13, in section (2), the control node Q(n) of the first output circuit unit 1-1 is held at a high voltage, the control node Qb(n) of the first output circuit unit 1-2 is held at a low voltage, and the carry signal of the first output circuit unit 1-1 and the first gate signal are held at a high voltage.

[0132] The control node Q'(n) of the second output circuit unit 2-1 becomes low voltage, the control node Qb'(n) of the second output circuit unit 2-2 becomes high voltage, and the second gate signal maintains low voltage.

[0133] The control node Q''(n) of the 3-1 of the third output circuit unit becomes a low voltage, the control node Qb''(n) of the 3-2 becomes a high voltage, and the third gate signal is maintained at a low voltage.

[0134] 11 and 14, in section (3), the control node Q(n) of the first output circuit unit 1-1 becomes a low voltage, and the control node Qb(n) of the first output circuit unit 1-2 becomes a high voltage, causing the carry signal of the first output circuit unit 1-1 and the first gate signal to output a low voltage.

[0135] The control node Q'(n) of the 2-1 of the second output circuit unit becomes a high voltage, the control node Qb'(n) of the 2-2 becomes a low voltage, and the second gate signal outputs a high voltage.

[0136] The control node Q''(n) of the 3-1 of the third output circuit unit becomes a high voltage, the control node Qb''(n) of the 3-2 becomes a low voltage, and the third gate signal outputs a high voltage.

[0137] 11 and 15, in section (4), the control node Q(n) of the first output circuit unit 1-1 is held at a low voltage, the control node Qb(n) of the first output circuit unit 1-2 is held at a high voltage, and the carry signal of the first output circuit unit 1-1 and the first gate signal are held at a low voltage.

[0138] The control node Q'(n) of the second output circuit unit 2-1 becomes a high voltage, the control node Qb'(n) of the second output circuit unit 2-2 becomes a low voltage, and the second gate signal outputs a low voltage.

[0139] The control node Q''(n) of the 3-1 of the third output circuit unit becomes a high voltage, the control node Qb''(n) of the 3-2 becomes a low voltage, and the third gate signal maintains a high voltage.

[0140] 11 and 16, in section (5), the control node Q(n) of the first output circuit unit 1-1 becomes a high voltage, and the control node Qb(n) of the first output circuit unit 1-2 becomes a low voltage, causing the carry signal of the first output circuit unit 1-1 and the first gate signal to output a high voltage.

[0141] The control node Q'(n) of the second output circuit unit 2-1 becomes low voltage, the control node Qb'(n) of the second output circuit unit 2-2 becomes high voltage, and the second gate signal maintains low voltage.

[0142] The control node Q''(n) of the 3-1 of the third output circuit unit is held at a high voltage, the control node Qb''(n) of the 3-2 is held at a low voltage, and the third gate signal is held at a high voltage.

[0143] 11 and 17, in section (6), the control node Q(n) of the first output circuit unit 1-1 is held at a high voltage, the control node Qb(n) of the first output circuit unit 1-2 is held at a low voltage, and the carry signal of the first output circuit unit 1-1 and the first gate signal are held at a high voltage.

[0144] The control node Q'(n) of the second output circuit unit 2-1 becomes low voltage, the control node Qb'(n) of the second output circuit unit 2-2 becomes high voltage, and the second gate signal maintains low voltage.

[0145] The control node Q''(n) of the 3-1 of the third output circuit unit becomes a low voltage, the control node Qb''(n) of the 3-2 becomes a high voltage, and the third gate signal outputs a low voltage.

[0146] FIG. 18 is a diagram showing a simulation result of the gate driver according to the embodiment.

[0147] Referring to FIG. 18, the output waveforms of the first EM signal EM1(n), the second EM signal EM2(n), the second scan signal SCAN2(n), and the third scan signal SCAN3(n) of the first EM driver, the second EM driver, the second scan driver, and the third scan driver, respectively, according to an embodiment are shown.

[0148] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments and can be embodied in various modifications within the scope of the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only and do not limit the technical concept of the present invention. Therefore, the above-described embodiments should be understood to be illustrative and non-limiting in all respects. The scope of protection of the present invention should be interpreted by the scope of the claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0149] 100: Display panel 110: Data driver 120: Gate driver 130: Timing controller 400: Power supply section

Claims

1. a plurality of signal transmission units cascaded via a carry line to which a carry signal is applied from a signal transmission unit in a preceding stage; Each of the plurality of signal transmission units is a first output circuit unit that receives the carry signal from the preceding signal transmission unit and outputs the carry signal and a first gate signal according to a voltage at a first-1 control node and a voltage at a first-2 control node; a second output circuit unit configured to output a second gate signal in response to a voltage of a second-1 control node connected to the first-2 control node and a voltage of a second-2 control node connected to the first-1 control node; a third output circuit unit configured to output a third gate signal in response to a voltage of a 3-1 control node connected to the 1-2 control node and a voltage of a 3-2 control node connected to the 1-1 control node; The first output circuit unit a first pull-up transistor including a gate electrode connected to the first control node, a first electrode to which a first high potential voltage is applied, and a second electrode connected to the first output node; a first pull-down transistor including a gate electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode to which a first low potential voltage is applied; a first-second pull-up transistor including a gate electrode connected to the first-first control node, a first electrode to which a second high potential voltage is applied, and a second electrode connected to a first-second output node; a first-second pull-down transistor including a gate electrode connected to the first-second control node, a first electrode connected to the first-second output node, and a second electrode to which a second low potential voltage is applied; Including, The second output circuit unit a second-second transistor for connecting the second-first control node to the first-second control node in response to a gate-on voltage; a second-fourth transistor connecting the second-second control node connected to the first-first control node in response to a gate-on voltage; a second pull-up transistor including a gate electrode connected to the second control node, a first electrode to which a first high potential voltage is applied, and a second electrode connected to a second output node; a second-1st pull-down transistor including a gate electrode connected to the second-2nd control node, a first electrode connected to the second output node, and a second electrode to which a first low potential voltage is applied; Including, The third output circuit unit a third-1st transistor connecting the third-1st control node connected to the first-2nd control node in response to a gate-on voltage; a third-second transistor for connecting the third-second control node connected to the first-first control node in response to a gate-on voltage; a third-1st pull-up transistor including a gate electrode connected to the third-1st control node, a first electrode to which a first high potential voltage is applied, and a second electrode connected to a third output node; a third pull-down transistor including a gate electrode connected to the third control node, a first electrode connected to the third output node, and a second electrode to which a first low potential voltage is applied;

2. The 2-2 transistor includes a gate electrode coupled to the 2-1 node, a first electrode coupled to the 1-2 control node, and a second electrode coupled to the 2-1 control node; 2. The gate driver of claim 1, wherein the second-fourth transistor includes a gate electrode connected to the second-first node, a first electrode connected to the first-first control node, and a second electrode connected to the second-second control node.

3. the second output circuit unit further includes a 2-1 transistor, a 2-2 transistor, and a 2-3 transistor; the second-1st transistor includes a gate electrode connected to the first-2nd output node, a first electrode connected to a low potential voltage line, and a second electrode connected to a second-1st node; The second-third transistor has a gate electrode connected to the first-second control node, a first electrode to which a carry signal from a predetermined signal transfer unit is applied, and a second electrode connected to the second-first node. The gate driver of claim 2 .

4. the second output circuit unit further includes transistors 2-5 to 2-7; the second-5th transistor includes a gate electrode and a first electrode connected to a first-2nd control node of the predetermined signal transmission unit, and a second electrode connected to a second-2nd node; The second-6th transistor includes a gate electrode connected to the second-2nd node, a first electrode connected to the second-1st control node, and a second electrode connected to a low potential voltage line; 4. The gate driver of claim 3, wherein the second-7th transistor includes a gate electrode connected to the second-2nd node, a first electrode connected to the second-2nd control node, and a second electrode connected to a high potential voltage line.

5. The 3-1 transistor includes a gate electrode coupled to a 1-2 control node of the preceding signal transmission unit, a first electrode coupled to the 1-2 control node, and a second electrode coupled to a 3-1 control node; 2. The gate driver of claim 1, wherein the third-2nd transistor includes a gate electrode connected to a first-2nd control node of the preceding signal transmission unit, a first electrode connected to the first-1st control node, and a second electrode connected to the third-2nd control node.

6. the third output circuit unit further includes transistors 3-3 to 3-6; the 3-3 transistor includes a gate electrode to which a carry signal of a predetermined signal transfer unit is applied, a first electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node; the third-fourth transistor includes a gate electrode to which a carry signal of the predetermined signal transmission unit is applied, a first electrode connected to the first-second output node, and a second electrode connected to the second-third node; the third-fifth transistor includes a gate electrode connected to the second-third node, a first electrode connected to the third-first control node, and a second electrode connected to a low potential voltage line; 6. The gate driver of claim 5, wherein the third-sixth transistor includes a gate electrode connected to the second-third node, a first electrode connected to the third-second control node, and a second electrode connected to a high potential voltage line.

7. a display panel including a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels; a data driver for supplying a data voltage of pixel data to the data line; a gate driver for supplying gate signals to the gate lines; the gate driver includes a plurality of signal transmission units cascaded via a carry line to which a carry signal is applied from a preceding signal transmission unit; Each of the plurality of signal transmission units is a first output circuit unit that receives the carry signal from the preceding signal transmission unit and outputs the carry signal and a first gate signal according to a voltage at a first-1 control node and a voltage at a first-2 control node; a second output circuit unit configured to output a second gate signal in response to a voltage of a second-1 control node connected to the first-2 control node and a voltage of a second-2 control node connected to the first-1 control node; a third output circuit unit configured to output a third gate signal in response to a voltage of a 3-1 control node connected to the 1-2 control node and a voltage of a 3-2 control node connected to the 1-1 control node; The first output circuit unit a first pull-up transistor including a gate electrode connected to the first control node, a first electrode to which a first high potential voltage is applied, and a second electrode connected to the first output node; a first pull-down transistor including a gate electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode to which a first low potential voltage is applied; a first-second pull-up transistor including a gate electrode connected to the first-first control node, a first electrode to which a second high potential voltage is applied, and a second electrode connected to a first-second output node; a first-second pull-down transistor including a gate electrode connected to the first-second control node, a first electrode connected to the first-second output node, and a second electrode to which a second low potential voltage is applied; Including, The second output circuit unit a second-second transistor for connecting the second-first control node to the first-second control node in response to a gate-on voltage; a second-fourth transistor connecting the second-second control node connected to the first-first control node in response to a gate-on voltage; a second pull-up transistor including a gate electrode connected to the second control node, a first electrode to which a first high potential voltage is applied, and a second electrode connected to a second output node; a second-1st pull-down transistor including a gate electrode connected to the second-2nd control node, a first electrode connected to the second output node, and a second electrode to which a first low potential voltage is applied; Including, The third output circuit unit a third-1st transistor connecting the third-1st control node connected to the first-2nd control node in response to a gate-on voltage; a third-second transistor for connecting the third-second control node connected to the first-first control node in response to a gate-on voltage; a third-1st pull-up transistor including a gate electrode connected to the third-1st control node, a first electrode to which a first high potential voltage is applied, and a second electrode connected to a third output node; a third-1 pull-down transistor including a gate electrode connected to the third-2 control node, a first electrode connected to the third output node, and a second electrode to which a first low potential voltage is applied.

8. The 2-2 transistor includes a gate electrode coupled to the 2-1 node, a first electrode coupled to the 1-2 control node, and a second electrode coupled to the 2-1 control node; 8. The display device of claim 7, wherein the 2-4 transistor includes a gate electrode connected to the 2-1 node, a first electrode connected to the 1-1 control node, and a second electrode connected to the 2-2 control node.

9. the second output circuit unit further includes a 2-1 transistor, a 2-2 transistor, and a 2-3 transistor; the second-1st transistor includes a gate electrode connected to the first-2nd output node, a first electrode connected to a low potential voltage line, and a second electrode connected to a second-1st node; 9. The display device of claim 8, wherein the second-third transistor includes a gate electrode connected to the first-second control node, a first electrode to which a carry signal of a predetermined signal transmission unit is applied, and a second electrode connected to the second-first node.

10. the second output circuit unit further includes a 2-5 transistor, a 2-6 transistor, and a 2-7 transistor; the second-5th transistor includes a gate electrode and a first electrode connected to a first-2nd control node of the predetermined signal transfer unit, and a second electrode connected to a second-2nd node; The second-6th transistor includes a gate electrode connected to the second-2nd node, a first electrode connected to the second-1st control node, and a second electrode connected to a low potential voltage line; 10. The display device of claim 9, wherein the second-7th transistor includes a gate electrode connected to the second-2nd node, a first electrode connected to the second-2nd control node, and a second electrode connected to a high potential voltage line.

11. the third output circuit unit further includes a 3-1 transistor, a 3-2 transistor, a 3-3 transistor, a 3-4 transistor, a 3-5 transistor, and a 3-6 transistor; the 3-1 transistor includes a gate electrode connected to a 1-2 control node of the previous stage signal transmission unit, a first electrode connected to the 1-2 control node, and a second electrode connected to a 3-1 control node; the 3-2 transistor includes a gate electrode connected to a 1-2 control node of the previous signal transmission unit, a first electrode connected to the 1-1 control node, and a second electrode connected to the 3-2 control node; the 3-3 transistor includes a gate electrode connected to a carry signal line of a predetermined signal transmission unit, a first electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node; the third and fourth transistors each include a gate electrode connected to a carry signal line of the predetermined signal transmission unit, a first electrode connected to the first and second output nodes, and a second electrode connected to the second and third node; the third-fifth transistor includes a gate electrode connected to the second-third node, a first electrode connected to the third-first control node, and a second electrode connected to a low potential voltage line; 8. The display device of claim 7, wherein the third-sixth transistor includes a gate electrode connected to the second-third node, a first electrode connected to the third-second control node, and a second electrode connected to a high potential voltage line.

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