Semiconductor Devices

Abstract

To provide a semiconductor device that identifies a fault location in a plurality of memory management units with a hierarchical structure.SOLUTION: A semiconductor device includes a primary memory management unit provided corresponding to a processing unit, and a secondary memory management unit constituting a hierarchical structure with the primary memory management unit. The primary memory management unit includes a first address translation unit for translating a virtual address into a physical address, and a first self-diagnosis test unit for performing a self-diagnosis test of the first address translation unit. The secondary memory management unit includes a second address translation unit for translating the virtual address into a physical address, and a second self-diagnosis test unit for performing a self-diagnosis test of the second address translation unit. Self-diagnosis test results by the first and second self-diagnosis test units are stored in a result storage unit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and is particularly suitable for use in a semiconductor device having a memory management unit that converts virtual addresses into physical addresses. [Background technology]

[0002] In recent years, in-vehicle semiconductor devices have become more powerful and multifunctional, and in addition to a central processing unit (CPU), they also incorporate multiple dedicated processing units that perform specific processes at high speed. For example, dedicated processing units include an image processing unit that compresses and decompresses image data and a DMA (Direct Memory Access) controller for DMA transfers. These dedicated processing units control memory access using virtual addresses to efficiently use external memory, which is a shared resource.

[0003] A virtual address is an address in virtual memory where a dedicated processing unit accesses data, and is different from an address (physical address) that is valid in physical memory. If there are multiple dedicated processing units and each dedicated processing unit uses a different virtual memory space, a memory management unit (MMU) may be provided for each dedicated processing unit.

[0004] To speed up address translation, the MMU has a translation lookaside buffer (TLB), which acts as a cache for the page table, which is translation information for mapping virtual addresses to physical addresses.

[0005] Like a cache, a TLB can have a hierarchical structure. Therefore, MMUs with TLBs of different capacities are arranged in a hierarchy. When a dedicated processing unit accesses memory using a virtual address, address translation is first performed by the MMU closest to the dedicated processing unit (primary MMU). If a corresponding entry is not found in the TLB of the primary MMU, the TLB of the secondary MMU is searched. If a corresponding entry is not found in the TLB of the secondary MMU, the corresponding entry is obtained from the page table of external memory. In this way, a page table walk is performed in the order of the primary MMU, secondary MMU, and memory, and the virtual address is translated into a physical address.

[0006] Regarding MMUs, the following technologies have been disclosed.

[0007] Japanese Patent Laid-Open No. 2000-148589 (Patent Document 1) discloses a memory management device that divides a TLB into multiple parts, and if an input virtual address does not hit in a selected TLB, selects another TLB and performs address translation. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-148589 Summary of the Invention [Problem to be solved by the invention]

[0009] In-vehicle semiconductor devices are required to incorporate functional safety mechanisms, which means that fault detection is also required for the address translation function using the MMU.

[0010] The virtual address set in a memory access request from the dedicated processing unit is translated into a physical address by walking the page table in the order of the primary MMU, secondary MMU, and memory. Data is then read from physical memory based on the translated physical address. Therefore, a fault in the address translation function can be detected by comparing the data read from physical memory with expected data. However, this detection method makes it difficult to identify which MMU level has the fault. Therefore, if this detection method detects a fault in the address translation function, it is necessary to reset all address translation functions, including the primary MMU, secondary MMU, and memory, which may take a long time.

[0011] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0012] According to one embodiment, a semiconductor device has a processing unit that issues a memory access request using a virtual address, a primary memory management unit provided corresponding to the processing unit, and a secondary memory management unit that forms a hierarchical structure with the primary memory management unit, wherein the primary memory management unit includes a first address conversion unit that converts the virtual address of the memory access request into a physical address and a first self-diagnostic test unit that performs a self-diagnostic test of the first address conversion unit, and the second memory management unit includes a second address conversion unit that converts the virtual address of the memory access request into a physical address and a second self-diagnostic test unit that performs a self-diagnostic test of the second address conversion unit when the memory access request is not address converted by the primary memory management unit, and a result storage unit that stores first and second self-diagnostic test results that are the self-diagnostic test results of the first and second self-diagnostic test units.

[0013] According to another embodiment, a semiconductor device includes a primary memory management unit having a memory access request issuing unit that issues a memory access request having a virtual address set therein, a first address translation unit including a first translation lookaside buffer that holds a first portion of a page table stored in the memory, and a first self-diagnostic test unit that performs a self-diagnostic test on the first address translation unit, a secondary memory management unit having a second address translation unit that holds a second portion of the page table stored in the memory and includes a second translation lookaside buffer that is accessed when a page table entry corresponding to the virtual address is not present in the first translation lookaside buffer, and a second self-diagnostic test unit that performs a self-diagnostic test on the second address translation unit, and a result storage unit that stores first and second self-diagnostic test results that are results of the self-diagnostic tests by the first and second self-diagnostic test units. [Effects of the Invention]

[0014] According to the embodiment, it is possible to identify the location of a failure in the address translation function, and as a result, it is possible to execute an appropriate process according to the identified location of the failure. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing a configuration of a data processing device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of the MMU. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of the MMU. [Figure 4] FIG. 4 is a flowchart showing a self-diagnostic test of the address translation function of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a flowchart showing a self-diagnostic test of the address translation function of the semiconductor device according to the first embodiment. [Figure 6]FIG. 6 is a flowchart showing a self-diagnostic test of the address translation function of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating the configuration of a page table in a memory. [Figure 8] FIG. 8 is a diagram illustrating a modification of the first embodiment. [Figure 9] FIG. 9 is a diagram illustrating a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating a semiconductor device according to a first modification of the second embodiment. [Figure 11] FIG. 11 is a block diagram illustrating an example of the configuration of an MMU according to the third embodiment. [Figure 12] FIG. 12 is a block diagram illustrating an example of the configuration of an MMU according to the third embodiment. [Figure 13] FIG. 13 is a flowchart showing a self-diagnostic test of the address translation function of the semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a block diagram illustrating an example of the configuration of an MMU according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] A data processing device according to one embodiment will be described in detail below with reference to the drawings. In the specification and drawings, identical or corresponding components are designated by the same reference numerals, and duplicate explanations will be omitted. For the sake of convenience, some components may be omitted or simplified in the drawings. At least some of the embodiments may be combined with each other in any desired manner.

[0017] <First Embodiment> FIG. 1 is a block diagram showing the configuration of a data processing device according to a first embodiment. As shown in FIG. 1, the data processing device 100 includes a semiconductor device 10 and a memory 20. The semiconductor device 10 includes a CPU 1, a dedicated processing unit 2, MMUs 3 and 5, a bus 4, and a memory controller 6. The memory 20 is a physical memory and is configured, for example, by a dynamic random access memory (DRAM). Note that the physical memory is not limited to a DRAM.

[0018] The CPU 1 executes software programs such as an OS program and application programs stored in a storage device such as a ROM (Read Only Memory) (not shown).

[0019] The dedicated processing unit 2 is an accelerator that executes part of the processing of an application program. For example, the dedicated processing unit 2 may be an image processing unit that executes compression and decompression processing of image data, or a DMA controller for DMA transfer.

[0020] The MMUs 3 and 5 are hierarchically arranged memory management units that convert a virtual address set in a memory access request from the dedicated processing unit 2 into a physical address. In the first embodiment, the MMU 3 is a primary MMU (upper MMU), and the MMU 5 is a secondary MMU (lower MMU). That is, the MMU 3 connected to the dedicated processing unit 2 is the primary MMU (upper MMU), and the MMU 5 connected via the bus 4 is the secondary MMU (lower MMU). As will be described in detail later, the MMU 3 and MMU 5 each have a translation lookaside buffer (TLB) that caches a page table. The number of entries in the TLB of the MMU 3 is smaller than the number of entries in the TLB of the MMU 5. Therefore, the search operation of the TLB of the MMU 5 is slower than the search operation of the TLB of the MMU 3, which has fewer entries. Furthermore, as will be described in detail later, the MMUs 3 and 5 each have a self-test unit.

[0021] The memory controller 6 is connected to the bus 4 and the memory 20. The memory controller 6 accesses the memory 20 in response to an access request received via the bus, and transfers data.

[0022] The memory 20 stores data to be processed by the CPU 1 and the dedicated processing unit 2, data resulting from the processing, and a page table which is conversion information used to associate virtual addresses with physical addresses. Data is read from and written to the memory 20 via the memory controller 6.

[0023] The semiconductor device 10 is preferably configured on a single semiconductor chip, but is not limited to this. The CPU 1, the dedicated processing unit 2, the MMU 3, and the memory controller 6 can also be formed as separate semiconductor devices.

[0024] Next, a description will be given of the configuration of the MMU 3 according to the first embodiment. Fig. 2 is a block diagram showing an example of the configuration of the MMU 3. As shown in Fig. 2, the MMU 3 has an address translation unit 31 and a self-diagnostic test unit 32.

[0025] The address conversion unit 31 has a TLB 311 and an address conversion circuit 312. The TLB 311 has a plurality of page table entries and functions as a cache for the page table stored in the memory 20. Each page table entry has tag information and data.

[0026] The TLB 311 compares the virtual address set in the received memory access request with the tag information and outputs the search result. The address translation circuit 312 translates the virtual address into a physical address based on the search result output from the TLB 311.

[0027] The self-diagnostic test unit 32 includes a self-diagnostic test control unit 321 , a request control unit 322 , a TLB control unit 323 , a determination unit 324 , and a self-diagnostic test result storage unit 325 .

[0028] The self-diagnostic test control unit 321 receives a self-diagnostic test start signal 1000 from the CPU 1, which serves as a self-diagnostic test execution instruction unit, and starts self-diagnostic test control of the address translation function of the MMU 3. Specifically, in response to the self-diagnostic test start signal 1000, the self-diagnostic test control unit 321 outputs a self-diagnostic test instruction signal 1001 to the request control unit 322 and the TLB control unit 323.

[0029] The request control unit 322 receives the self-diagnostic test instruction signal 1001 and generates a memory access request 1003 for the self-diagnostic test. The memory access request 1003 for the self-diagnostic test is output to the address conversion unit 31.

[0030] The TLB control unit 323 generates a TLB rewrite signal 1002 in response to the self-test instruction signal 1001. The TLB rewrite signal 1002 includes page table entry data for the self-test and a TLB rewrite control signal. The TLB control unit 323 outputs the TLB rewrite signal 1002 to the TLB 311, and the TLB 311 rewrites the page table entry to the page table entry for the self-test based on the TLB rewrite signal 1002.

[0031] The determination unit 324 receives a TLB hit / miss signal 1004 indicating a hit / miss result of the TLB 311 and an address translation result 1005 from the address translation circuit 312. The determination unit 324 compares the TLB hit / miss signal 1004 and the address translation result 1005 with the expected value of the TLB hit / miss signal and the expected value of the address translation result, respectively. The determination unit 324 then determines the result of the self-diagnostic test of the address translation function based on the comparison result and outputs a self-diagnostic test determination result signal 1006. The determination unit 324 also receives response information 1008 from the MMU 5 as a response to the memory access request for the self-diagnostic test, which includes information on the TLB hit / miss and the address translation result of the MMU 5. The determination unit 324 compares the information on the TLB hit / miss and the address translation result included in the response information 1008 to determine whether they match the expected results, and determines the result of the self-diagnostic test of the address translation function of the MMU 5.

[0032] The self-diagnostic test result storage unit 325 stores the self-diagnostic test determination result signal 1006 determined by the determination unit 324. The self-diagnostic test result storage unit 325 may be configured, for example, as a register, but may be any device capable of storing data. The self-diagnostic test result storage unit 325 stores the self-diagnostic test results for each page table entry. For example, the self-diagnostic test result storage unit 325 may be a register having multiple bits, each bit storing the self-diagnostic test results for each page table entry of MMU3, each page table entry of MMU5, and each page table entry of memory 20. Alternatively, the self-diagnostic test result storage unit 325 may have multiple registers, and the self-diagnostic test results for each page table entry of MMU3, each page table entry of MMU5, and each page table entry of memory 20 may be stored in different registers. These self-diagnostic test results are read out to the CPU 1 as self-diagnostic test result information 1007.

[0033] 3 is a block diagram showing an example of the configuration of the MMU 5. As shown in FIG. 3, the MMU 5 includes an address translation unit 51 and a self-diagnostic test unit 52.

[0034] Like the address translation unit 31 of the MMU 3, the address translation unit 51 includes a TLB 511 and an address translation circuit 512. Like the TLB 311, the TLB 511 functions as a cache for page tables stored in the memory 20. Like the TLB 311, the TLB 511 also has page table entries consisting of tag information and data. The number of page table entries in the TLB 511 is greater than the number of page table entries in the TLB 311. The address translation circuit 512 translates virtual addresses into physical addresses based on the search results output from the TLB 511.

[0035] Unlike the self-diagnostic test unit 32 of the MMU 3 , the self-diagnostic test unit 52 is composed of a self-diagnostic test control unit 521 and a TLB control unit 523 .

[0036] Like the self-diagnostic test control unit 321, the self-diagnostic test control unit 521 receives a self-diagnostic test start signal 1000 from the CPU 1. In response to the self-diagnostic test start signal 1000, the self-diagnostic test control unit 521 outputs a self-diagnostic test instruction signal 1011 to the TLB 523.

[0037] The TLB control unit 523 receives the self-test instruction signal 1011 and generates a TLB rewrite signal 1012. Based on the TLB rewrite signal 1012, each entry in the TLB 511 is rewritten to an entry for the self-test.

[0038] (Address conversion operation) Next, the address translation operation of the MMUs 3 and 5 in normal operation will be described with reference to FIGS.

[0039] First, the MMU3, which is the primary MMU, receives a memory access request from the dedicated processing unit 2. The virtual address specified in the memory access request is compared with the tag information in the TLB311. If the TLB311 contains tag information corresponding to the virtual address (TLB hit), the TLB311 outputs the data of the hit entry to the address translation circuit 312. The address translation circuit 312 translates the virtual address into a physical address based on the received data. The memory 20 is then accessed using the physical address translated by the MMU3.

[0040] On the other hand, if the TLB 311 does not contain tag information corresponding to the virtual address (TLB miss), the memory access request is transferred to the MMU 5, which is a secondary MMU. The virtual address specified in the memory access request is compared with the tag information in the TLB 511. If the TLB 511 contains tag information corresponding to the virtual address (TLB hit), the TLB 511 outputs the data of the hit entry to the address translation circuit 512. The address translation circuit 512 translates the virtual address into a physical address based on the received data. The memory 20 is then accessed using the physical address translated by the MMU 5.

[0041] If there is no tag information corresponding to the virtual address in the TLB 511 (TLB miss), the MMU 5 issues a page table walk (PTW) request. Based on this PTW request, the page table in the memory 20 is accessed and the virtual address is translated into a physical address.

[0042] (Self-diagnostic test) Next, a description will be given of an example of a self-diagnostic test of the address translation function of the semiconductor device according to the embodiment 1. Figures 4 to 6 are flowcharts showing an example of a self-diagnostic test of the address translation function of the semiconductor device according to the embodiment 1.

[0043] First, the CPU 1 outputs a self-diagnostic test start signal 1000 to the MMUs 3 and 5 in accordance with the software program.

[0044] Next, the self-diagnostic test control units 321 and 521 receive the self-diagnostic test start signal 1000. As a result, the MMUs 3 and 5 enter the self-diagnostic test mode. The self-diagnostic test control unit 321 outputs a self-diagnostic test instruction signal 1001 to the request control unit 322 and the TLB control unit 323 based on the self-diagnostic test start signal 1000. The TLB control unit 323 rewrites all entries in the TLB 311 to page table entries for the self-diagnostic test in accordance with the self-diagnostic test instruction signal 1001. Similarly, the self-diagnostic test control unit 521 outputs a self-diagnostic test instruction signal 1011 to the TLB control unit 523 based on the self-diagnostic test start signal 1000. The TLB control unit 523 rewrites all entries in the TLB 511 to page table entries for the self-diagnostic test in accordance with the self-diagnostic test instruction signal 1011. 7, the CPU 1 instructs the memory 20 to rewrite a part of the page table area 201 of the memory 20 into the self-test page table 202 (step S1). Note that the TLBs 311 and 511 and the self-test page table 202 of the memory 20 store page table entries for different virtual addresses.

[0045] Upon receiving the self-diagnostic test instruction signal 1001, the request control unit 322 issues a memory access request 1003 for the self-diagnostic test. Hereinafter, the memory access request 1003 for the self-diagnostic test is referred to as a self-diagnostic test request 1003. The request control unit 322 first issues the self-diagnostic test request 1003 in which a virtual address that hits the tag information of the page table entry for the self-diagnostic test in the TLB 311 is set (step S2).

[0046] The address translation unit 31 receives the self-diagnostic test request 1003. The TLB 311 of the address translation unit 31 searches for an entry corresponding to the virtual address set in the self-diagnostic test request 1003 (step S3). Then, the TLB 311 outputs a TLB hit / miss signal 1004 as the search result. In the case of a TLB hit, the TLB 311 outputs data of the hit entry to the address translation circuit 312. The address translation circuit 312 translates the virtual address into a physical address using the data of the hit entry, and outputs the physical address to the determination unit 324 as the address translation result 1005.

[0047] The determination unit 324 compares the TLB hit / miss signal 1004 and the address translation result 1005 with the expected value of the TLB hit / miss signal and the expected value of the address translation result, respectively (step S4). If the TLB hit / miss signal 1004 and the address translation result 1005 differ from the expected values ​​(NO in step S4), the determination unit 324 determines that a failure has occurred in the MMU 3 (step S6). Then, the determination unit 324 generates a self-diagnostic test determination result signal 1006 indicating that a failure has occurred in the MMU 3 and stores it in the self-diagnostic test result storage unit 325. A virtual address that hits the tag information of the TLB 311 rewritten to the page table entry for the self-diagnostic test is set in the self-diagnostic test request 1003. If the TLB hit / miss signal indicates a TLB miss, there is a possibility that a failure has occurred in the TLB 311. Therefore, the determination unit 324 determines that a failure has occurred in the MMU 3. On the other hand, if the TLB hit / miss signal 1004 and the address translation result 1005 match the expected values ​​(YES in step S4), the judgment unit 324 stores the self-diagnostic test judgment result signal 1006 in the self-diagnostic test result storage unit 325 and proceeds to the next step (step S5).

[0048] If there is an entry in the TLB 311 for which a corresponding self-test request has not been issued, the process returns to step S2 (NO in step S5). Then, the request control unit 322 issues a self-test request 1003 corresponding to the remaining entries in the TLB 311. In this manner, the operations from step S2 to step S5 are repeated, and self-test requests 1003 are issued in sequence so as to hit all entries in the TLB 311 in order.

[0049] If self-test requests corresponding to all entries in the TLB 311 have been issued (YES in step S5), a self-test of the address translation function of the MMU 5 is performed. The request control unit 322 issues a self-test request 1003a in which a virtual address that hits the tag information of the TLB 511 rewritten to the page table entry for the self-test is set (step S7). In other words, the virtual address of the self-test request 1003a does not hit the tag information of the TLB 311.

[0050] The self-diagnostic test request 1003a is first supplied to the address translation unit 31. The TLB 311 of the address translation unit 31 searches for an entry corresponding to the virtual address set in the self-diagnostic test request 1003a (step S8). If an entry corresponding to the virtual address does not exist in the TLB 311 (TLB miss) (YES in step S9), the self-diagnostic test request 1003a is transferred to the MMU 5, which is the secondary MMU. Since the self-diagnostic test request 1003a does not have a virtual address that hits the tag information of the TLB 311, if the search result is a TLB hit (NO in step S9), it is determined that a fault has occurred in the TLB 311 (step S12).

[0051] Upon receiving the transferred self-diagnostic test request 1003a, the address translation unit 51 of the MMU 5 starts a search operation using the TLB 511. That is, the TLB 511 searches for an entry corresponding to the virtual address of the self-diagnostic test request 1003a (step S10). The address translation circuit 512 translates the virtual address into a physical address based on the search result of the TLB 511. The search result of the TLB 511 and the address translation result of the address translation circuit 512 are output to the determination unit 324 of the MMU 3 as response information 1008 for the self-diagnostic test request 1003a.

[0052] The determination unit 324 determines whether the search result of the TLB 511 and the address translation result of the address translation circuit 512, which are included in the response information 1008, are as expected. If the search result and the address translation result are as expected (YES in step S11), the determination unit 324 generates a self-diagnostic test determination result signal 1006 based on the determination result, stores it in the self-diagnostic test result storage unit 325, and proceeds to the next step (step S13). On the other hand, if the search result and the address translation result are different from the expected results (NO in step S11), the determination unit 324 determines that a fault has occurred in the MMU 5, generates a self-diagnostic test determination result signal 1006 indicating that a fault has occurred in the MMU 5, and stores it in the self-diagnostic test result storage unit 325.

[0053] If the self-test request 1003a corresponding to all entries of the TLB 511 has been issued (YES in step S13), a self-test of the address translation function is performed using the page table of the memory 20. The request control unit 322 issues the self-test request 1003b including the virtual addresses stored in the self-test page table 202 of the memory 20 (step S14). That is, the self-test request 1003b does not include the virtual addresses corresponding to the entries of the TLB 311 and 511.

[0054] The self-diagnostic test request 1003b is first supplied to the address translation unit 31. The TLB 311 searches for an entry corresponding to the virtual address of the self-diagnostic test request 1003b. If the entry corresponding to the virtual address of the self-diagnostic test request 1003b does not exist in the TLB 311 (TLB miss) (YES in step S15), the self-diagnostic test request 1003b is transferred to the MMU 5. The entry corresponding to the virtual address of the self-diagnostic test request 1003b should not exist in the TLB 311. Therefore, if the search result indicates that the entry corresponding to the virtual address of the self-diagnostic test request 1003b exists in the TLB 311 (NO in step S15), it is determined that a fault has occurred in the TLB 311 (step S18).

[0055] The address translation unit 51 of the MMU 5, which receives the transferred self-test request 1003b, performs a search using the TLB 511. The TLB 511 searches for an entry corresponding to the self-test request 1003b. If the TLB 511 does not contain an entry corresponding to the virtual address of the self-test request 1003b (YES in step S16), the MMU 5 issues a page table walk request (PTW request) to the memory 20. In accordance with the PTW request, address translation information is read from the self-test page table 202 of the memory 20. The MMU 5 translates the virtual address of the self-test request 1003b into a physical address based on the address translation information from the self-test page table 202 of the memory 20. The result of the address translation based on the translation information from the self-test page table 202 of the memory 20 is output to the determination unit 324 of the MMU 3 as response information 1008 corresponding to the self-test request 1003b. On the other hand, an entry corresponding to the virtual address of the self-diagnostic test request 1003b should not exist in the TLB 511. Therefore, if the search result indicates that an entry corresponding to the virtual address of the self-diagnostic test request 1003b exists in the TLB 511 (NO in step S16), it is determined that a fault has occurred in the TLB 511 (step S18).

[0056] The determination unit 324 determines whether the address translation result included in the response information 1008 is as expected. If the address translation result is as expected (YES in step S17), the self-diagnostic test of the address translation function of the semiconductor device 10 is completed. If the address translation result is different from the expected result (NO in step S17), it is determined that there is a fault in the address translation function using the self-diagnostic test page table 202 of the memory 20, for example, in the path from the MMU 3 to the memory 20 (step S18).

[0057] (Reset and recovery processing) As described above, according to this embodiment, a self-diagnostic test of the address translation function can be performed for each MMU. The self-diagnostic test results for each MMU are stored in the self-diagnostic test result storage unit 325. The CPU 1 reads the self-diagnostic test result information 1007 stored in the self-diagnostic test result storage unit 325 and performs a reset or restore process for the address translation function to ensure the safety of the data processing device 100. Because the self-diagnostic test result information 1007 includes the self-diagnostic test results for each MMU, the CPU 1 can identify the hierarchical level of the MMU in which a failure has occurred. Therefore, the CPU 1 can set the range in which the reset or restore process should be performed based on the self-diagnostic test result information 1007. For example, if the self-diagnostic test result information 1007 indicates that only MMU 3 contains an entry in which a failure has occurred, the CPU 1 issues a system reset signal 1010 to only MMU 3. On the other hand, if the self-diagnostic test result information 1007 indicates that only MMU 5 contains an entry in which a failure has occurred, the CPU 1 issues a system reset signal 1010 to MMU 5. In this way, it is possible to set the MMUs that should undergo reset or recovery processing based on the results of the self-diagnostic tests for each MMU.

[0058] It is also possible that a fault has occurred on the data bus between the lower MMU and the upper MMU. Therefore, if the self-diagnostic test result information 1007 indicates that an entry in which a fault has occurred exists in MMU 5, CPU 1 may issue a system reset signal 1010 not only to MMU 5 but also to the lower MMU 3.

[0059] As described above, according to the first embodiment, it is possible to execute a self-diagnostic test for each of a plurality of MMUs having a hierarchical structure, and to output the self-diagnostic test results for the MMUs at each level. This makes it possible to identify the level of the MMU in which a failure has occurred. Therefore, it is possible to set the range in which a reset or recovery process should be performed according to the identified location of the failure. This makes it possible to shorten the processing time for the reset or recovery process when a failure in the address translation function is detected.

[0060] Furthermore, the self-diagnostic test unit of each MMU starts the self-diagnostic test in response to an instruction from the CPU 1, rather than from the dedicated processing unit 2 that issued the memory access request. In other words, the execution of the self-diagnostic test for each MMU can be controlled by a software program. This makes it possible to arbitrarily set the execution timing of the MMU self-diagnostic test, reducing the effort required for system design.

[0061] Although the first embodiment has been described with reference to a semiconductor device having a two-tier MMU, the present invention is not limited to this. The semiconductor device 10 may also have a plurality of processing units that access memory using virtual addresses.

[0062] <Modification> In the above description, the address translation function of the semiconductor device 10 executes self-diagnostic tests in the order of MMU 3, MMU 5, and memory 20 in response to the self-diagnostic test start signal 1000 output from the CPU 1. However, the self-diagnostic test start signal 1000 may contain not only an instruction to start the execution of a self-diagnostic test, but also information specifying the MMU on which the self-diagnostic test is to be executed. This allows the self-diagnostic test to be executed for each MMU.

[0063] For example, suppose that CPU1 outputs a self-diagnostic test start signal 1000 that includes information specifying MMU3 as the target of the self-diagnostic test. Upon receiving the self-diagnostic test start signal 1000, the self-diagnostic test control unit 321 of MMU3 outputs a self-diagnostic test instruction signal 1001 to the TLB 323. In response to the self-diagnostic test instruction signal 1001, the TLB control unit 323 rewrites each entry in the TLB 311 with an entry for the self-diagnostic test. In response to the self-diagnostic test start signal 1000, the self-diagnostic test control unit 321 of MMU3 instructs the request control unit 322 to issue a self-diagnostic test request for MMU3, which is the target of the self-diagnostic test, and the self-diagnostic test of MMU3 is executed. However, in this modification, the request control unit 322 does not issue a self-diagnostic test request for MMU5, which is not the target of the self-diagnostic test. Furthermore, the self-diagnostic test control unit 521 of the MMU 5 that receives the self-diagnostic test start signal 1000 is not a target for the self-diagnostic test, and therefore does not output the self-diagnostic test instruction signal 1011. Therefore, the TLB 511 is not rewritten with an entry for the self-diagnostic test.

[0064] While the self-diagnostic test is being executed, it is not possible to process memory access requests issued by the dedicated processing unit 2. Therefore, by setting the target of the self-diagnostic test as in the present modification 1, it is possible to reduce the time required for the self-diagnostic test.

[0065] Furthermore, the semiconductor device 10 may include multiple dedicated processing units 2. A primary MMU may be provided for each of the multiple dedicated processing units, and the secondary MMU may be shared by the multiple dedicated processing units. That is, as shown in FIG. 8, the semiconductor device 10a includes multiple dedicated processing units 2_0 and 2_1. MMUs 3_0 and 3_1 may be provided as primary MMUs for the dedicated processing units 2_0 and 2_1, respectively, and an MMU 5 may be provided as a secondary MMU for the dedicated processing units 2_0 and 2_1. In such a configuration, as described in the first embodiment, when a self-diagnostic test of the address translation function for a memory access request from the dedicated processing unit 2_0 is executed, the MMU 3 and MMU 5 are set to the self-diagnostic test mode. Therefore, while this self-diagnostic test is being executed, the MMU 5 cannot perform address translation for a memory access request from the dedicated processing unit 2_1. Therefore, the execution of the self-diagnostic test may affect the performance of the entire system.

[0066] However, by setting the target of the self-diagnostic test for each MMU as in the present first modification, it is possible to reduce the impact of the execution of the self-diagnostic test on the performance of the entire system. For example, when the target of the self-diagnostic test is set to MMU3_0 among the address translation functions related to the dedicated processing unit 2_0, MMU5 can perform normal operation. Therefore, it can process memory access requests from the dedicated processing unit 2_1. In other words, it is not necessary to stop the operation of the dedicated processing unit 2_1 when the self-diagnostic test of MMU3_0 is executed. Therefore, it is possible to prevent performance degradation of the entire system due to the execution of the self-diagnostic test.

[0067] <Embodiment 2> A semiconductor device according to a second embodiment will be described with reference to Fig. 9. The second embodiment differs from the first embodiment in that a self-diagnostic test start signal 1000 is supplied from a timer module 7. Other than that, the second embodiment is the same as the first embodiment, and therefore description thereof will be omitted.

[0068] As described above, in the first embodiment, the self-diagnostic test start signal 1000 is output from the CPU 1, but in the second embodiment, the self-diagnostic test start signal 1000 is output from the timer module 7. That is, in the second embodiment, the self-diagnostic test units of the MMUs 3 and 5 receive the self-diagnostic test start signal 1000 output from the timer module 7 at predetermined intervals. Therefore, a self-diagnostic test of the address translation function of the semiconductor device 10 is performed at predetermined intervals, enabling periodic fault checking. This enhances the safety of the data processing device.

[0069] <First Modification of Second Embodiment> 10 is a diagram illustrating a semiconductor device according to a first modification of the second embodiment. In the second embodiment, the timer module 7 outputs the self-diagnostic test start signal 1000 at a constant cycle, but the cycle at which the self-diagnostic test start signal 1000 is output may be controlled. As shown in FIG. 10, a temperature sensor 8 and a voltage sensor 9 may be further provided, and the cycle at which the timer module 7 outputs the self-diagnostic test start signal 1000 may be controlled in accordance with the monitoring results of the temperature sensor 8 and the voltage sensor 9. Note that FIG. 10 shows only the components used to describe this modification, and the other components in FIG. 1 are omitted.

[0070] According to the first modification, the temperature sensor 8 measures the temperature inside the semiconductor device. The CPU 1 receives the measurement result of the temperature sensor and determines, based on the measurement result, whether the high temperature state of the semiconductor device has continued for a predetermined period or longer. If the CPU 1 determines that the high temperature state of the semiconductor device has continued for a predetermined period or longer, the CPU 1 controls the timer module 7 to change the cycle at which the self-diagnostic test start signal 1000 is output. For example, the timer module 7 is controlled to increase the frequency at which the self-diagnostic test start signal 1000 is output. The semiconductor device may further include a test temperature setting register (not shown) for setting the temperature at which the control of the timer module 7 is started.

[0071] Furthermore, a voltage sensor 9 measures the operating voltage within the semiconductor device. The measurement results are received by the CPU 1. If the CPU 1 determines that the semiconductor device has been in a low-voltage state or a high-voltage state for a long period of time, it controls the timer module 7. For example, the timer module 7 is controlled to increase the frequency at which it outputs a self-diagnostic test start signal 1000. The semiconductor device may further include a test voltage setting register (not shown) for setting a temperature at which the timer module 7 starts to control the device.

[0072] In this way, the state of the semiconductor device is monitored by the temperature sensor and the voltage sensor, and a self-diagnostic test of the address translation function can be executed according to the monitoring results. That is, the self-diagnostic test can be executed according to the operating environment of the semiconductor device. This can improve the fault detection rate.

[0073] In the first modification, an example in which both the temperature sensor 8 and the voltage sensor 9 are provided is described, but the state inside the semiconductor device may be monitored by only one of the temperature sensor 8 and the voltage sensor 9, and the interval at which the self-diagnostic test is executed may be controlled according to the monitoring result.

[0074] <Modification 2 of Embodiment 2> The cycle of the self-diagnostic test start signal 1000 output by the timer module 7 may be changed depending on the total usage time of the semiconductor device. The total usage time may be kept by a software program, and when the total usage time exceeds a preset time, the CPU 1 may control the timer module 7 to change the frequency at which the self-diagnostic test is executed.

[0075] <Third Embodiment> Next, a third embodiment will be described. In the third embodiment, MMUs 3a and 5a, which are alternatives to the MMU 3 and MMU 5 according to the first embodiment, will be described. FIGS. 11 and 12 are block diagrams showing examples of the configurations of MMUs 3a and 5a included in a semiconductor device 10a according to the third embodiment, respectively. In the third embodiment, the configurations of the semiconductor device 10a other than the MMUs 3a and 5a may be the same as those shown in FIG. 1. Therefore, the description thereof will be omitted here.

[0076] 11 is a block diagram showing an example of the configuration of an MMU 3a. The MMU 3a differs from the MMU 3 (see FIG. 2) described in the first embodiment in that it further includes an interrupt request unit 33. The MMU 3a also differs from the MMU 3 (see FIG. 2) described in the first embodiment in that it includes an address conversion unit 31a instead of the address conversion unit 31 and a self-diagnostic test unit 32a instead of the self-diagnostic test unit 32. Of the configurations of the address conversion unit 31a and the self-diagnostic test unit 32a shown in FIG. 11, components having the same functions as those in FIG. 2 are designated by the same reference numerals, and their description will be omitted.

[0077] Like the TLB 311 in the first embodiment, the TLB 311a in the address translation unit 31a has multiple page table entries for translating virtual addresses into physical addresses and functions as a cache for page tables stored in the memory 20. Each page table entry has secure information in addition to tag information and data. The secure information is information about the access right of the dedicated processing unit that is the source of the memory access request. For example, the secure information indicates whether the source of the memory access request is permitted to access a memory area specified by a virtual address (for example, read only, write only, or read and write). The TLB 311a compares the virtual address included in the memory access request with the tag information. Furthermore, the TLB 311a compares the secure information (for example, read / write information) set in the memory access request with the secure information in the TLB 311a. Even if the TLB 311a has a page table entry corresponding to the virtual address (TLB hit), if the secure information does not match, the TLB 311a outputs an address translation error notification signal indicating an address translation error. The TLB 311 a outputs the search result of the TLB 311 a to the address translation circuit 312 when a page table entry corresponding to the virtual address of the memory access request exists and the secure information matches.

[0078] 11 in that it further includes an error address register 236. The error address register 326 stores the virtual address of a memory access request that has been determined to be an address translation error by the address translation unit 31a, and the address information of the entry.

[0079] The TLB control unit 323a reads the virtual address and entry address information stored in the error address register 326 in response to a self-diagnostic test instruction signal 1001 output from the self-diagnostic test control unit 321. The TLB control unit 323a generates a page table entry for the self-diagnostic test based on the read virtual address. The tag information of the page table entry for the self-diagnostic test corresponds to the virtual address read from the error address register 326. The TLB control unit 323a outputs a TLB rewrite signal 1002 to rewrite the contents of the entry address read from the error address register 326 to the page table entry for the self-diagnostic test.

[0080] The interrupt request unit 33 receives the address translation error notification signal 1013 from the address translation unit 31a. Then, in response to the address translation error notification signal 1013, the interrupt request unit 33 outputs an address translation error interrupt notification signal 1009 to the CPU 1.

[0081] Next, an MMU 5a according to the second embodiment will be described, as shown in Fig. 12. Fig. 12 is a block diagram showing an example of the configuration of the MMU 5a according to the second embodiment. The MMU 5a differs from the MMU 5 (see Fig. 3) in that it includes an address conversion unit 51a instead of the address conversion unit 51, a self-diagnostic test unit 52a instead of the self-diagnostic test unit 52, and an error address register 526. Of the configurations of the address conversion unit 51a and the self-diagnostic test unit 52a shown in Fig. 12, components having the same functions as those in Fig. 3 are designated by the same reference numerals, and their description will be omitted.

[0082] Like the TLB 311a, the TLB 511a of the address translation unit 51a functions as a cache of page tables stored in the memory 20. Like the page table entries of the TLB 311a, each page table entry of the TLB 511a has secure information in addition to tag information and data. Even if the TLB 511a contains a page table entry corresponding to the virtual address of a memory access request, the TLB 511a also outputs an address translation error notification signal if the secure information of the memory access request does not match the secure information of the page table entry. The address translation error notification signal is sent back to the MMU 3a as a response to the memory access request given to the MMU 5a.

[0083] The self-diagnostic test unit 52 a includes a self-diagnostic test control unit 521 , a TLB control unit 523 a , and an error address register 526 .

[0084] Similar to the error address register 326 in FIG. 11, the error address register 526 stores the virtual address of a memory access request that has been determined to be an address translation error by the address translation unit 51a, and the address information of the entry.

[0085] The TLB control unit 523a reads the virtual address and entry address information stored in the error address register 526 in response to a self-diagnostic test instruction signal 1011 output from the self-diagnostic test control unit 521. The TLB control unit 523a generates a page table entry for self-diagnostic test having tag information generated based on the read virtual address. The TLB control unit 523a outputs a TLB rewrite signal 1012 to rewrite the contents of the entry address read from the error address register 526 to the page table entry for self-diagnostic test.

[0086] (Self-diagnostic test) Next, an example of a self-diagnostic test operation of the address translation function of the semiconductor device according to the third embodiment will be described. The semiconductor device according to the third embodiment executes a self-diagnostic test of the MMU in response to the occurrence of an address translation error. Fig. 13 is a flowchart illustrating a self-diagnostic test when an address translation error occurs in the semiconductor device according to the third embodiment. The following describes an example in which an address translation error occurs in the MMU 5a. The MMU 3a, which is the primary MMU, receives a memory access request from the dedicated processing unit 2. If the TLB 311a of the MMU 3a does not contain a page table entry corresponding to the virtual address of the memory access request, the memory access request is transferred to the MMU 5a, which is the secondary MMU.

[0087] When the MMU 5a receives a memory access request, the TLB 511a searches for a page table entry corresponding to the virtual address of the memory access request. If the page table entry corresponding to the virtual address is hit but the secure information of the memory access request does not match the secure information of the hit page table entry, the TLB 511a outputs an address translation error notification signal.

[0088] When an address translation error occurs, the virtual address and entry address of the memory access request that is determined to be an address translation error are stored in the error address register 526 (step S100). The address translation error notification signal output from the TLB 511a is sent back to the MMU 3a as a response to the memory access request given to the MMU 5a. The address translation error notification signal 1013 is received by the interrupt request unit 33 of the MMU 3a. In response to the address translation error notification signal 1013, the interrupt request unit 33 outputs an interrupt request 1009 to the CPU 1 (step S101). In response to the interrupt request 1009, the CPU 1 outputs a self-diagnostic test start signal 1000 to the MMU 3a and MMU 5a (step S102). This puts the MMUs 3a and 5a into self-diagnostic test mode.

[0089] In response to the self-diagnostic test start signal 1000, the self-diagnostic test control units 321 and 521 of the MMUs 3a and 5a output self-diagnostic test instruction signals 1001 and 1011 to the TLB control units 323a and 523a.

[0090] Upon receiving the self-diagnostic test instruction signals 1001 and 1011, the TLB control units 323a and 523a read the virtual addresses stored in the error address registers 326 and 526, respectively. The TLB control units 323a and 523a generate page table entries for self-diagnostic tests that have tag information based on the read virtual addresses. The generated page table entries for self-diagnostic tests are written to the error entry addresses read from the error address registers 326 and 526 of the TLBs 311a and 511a, respectively. Therefore, the entry in which the address translation error occurred in the TLB 511a is rewritten to the page table entry generated by the TLB control unit 523a (step S103).

[0091] Next, a self-test request 1003d is issued from the request control unit 322 (step S104). A virtual address is set in the self-test request 1003d, which is expected to be hit in the entry where the address translation error occurred, i.e., the entry in the TLB 511a where the address translation error occurred. Therefore, the virtual address of the self-test request 1003d is not translated in the MMU 3a, and the self-test request 1003d is transferred to the MMU 5a.

[0092] The MMU 5a performs address translation based on the self-diagnostic test request 1003d. If an address translation error is detected again in the address translation by the MMU 5a (NO in step S105), an address translation error notification signal is output. Therefore, this address translation error is sent back to the MMU 3a as response information to the self-diagnostic test request 1003d. Then, the interrupt request unit 33 of the MMU 3a outputs a translation error interrupt notification signal 1009 to the CPU 1 in response to the address translation error notification signal 1013 (step S107). On the other hand, if no address translation error is detected (YES in step S105), the TLB hit / miss result of the MMU 5a and the address translation result are sent to the MMU 3a as response information 1008 to the self-diagnostic test request 1003d, and input to the determination unit 324 of the MMU 3a.

[0093] The determination unit 324 determines whether the TLB hit / miss result and the address translation result included in the response information 1008 are as expected (step S106). If the TLB hit / miss result and the address translation result are not as expected (NO in step S106), it is determined that a fault has occurred in the TLB 511a, and a self-diagnostic test determination result signal 1006 indicating that a fault has occurred in the MMU 5a is generated and stored in the self-diagnostic test result storage unit 325. On the other hand, if the TLB hit / miss result and the address translation result are as expected (YES in step S106), it is determined that the address translation error is a transient fault of the TLB 511a.

[0094] When the CPU 1 receives the translation error interrupt notification signal 1009 while the MMUs 3a and 5a have transitioned to the self-diagnostic test mode, it can determine that a permanent failure has occurred in the MMU 3a or 5a. On the other hand, when the CPU 1 does not receive the translation error interrupt notification signal 1009 while the MMUs 3a and 5a have transitioned to the self-diagnostic test mode and does not obtain failure information for the MMUs 3a and 5a from the self-diagnostic test determination result signal, it determines that the address translation error is a transient failure of the TLB.

[0095] As described above, according to the third embodiment, a self-diagnostic test of the MMU is performed based on an address translation error. This makes it possible to determine whether the cause of the TLB failure is a transient failure or a permanent failure. For example, if the CPU 1 determines that the cause of the TLB failure is a transient failure, it can reset the TLB and then return to a normal operating state. Furthermore, if the cause of the TLB failure is a permanent failure, the CPU 1 controls the entire system including the semiconductor device to transition to a safe state. In this way, by determining whether the cause of the address translation error is transient or permanent, it is possible to execute processing appropriate to the cause of the failure.

[0096] <Fourth Embodiment> Next, a fourth embodiment will be described. In the fourth embodiment, an MMU 3b, which is another embodiment of the MMU 3 according to the first embodiment, will be described. FIG. 14 is a block diagram showing an example of the configuration of the MMU 3b included in the semiconductor device 10b according to the fourth embodiment. The MMU 3b includes an address translation unit 31b and a self-diagnostic test unit 32b. The address translation unit 31b differs from the address translation unit 31 of the first embodiment (see FIG. 2) in that it includes a TLB 311b instead of the TLB 311. The self-diagnostic test unit 32b also differs from the self-diagnostic test unit 32 of the first embodiment (see FIG. 2) in that it includes a determination unit 324b instead of the determination unit 324. Of the configurations of the address translation unit 31b and the self-diagnostic test unit 32b shown in FIG. 14, components having the same functions as those in FIG. 2 are designated by the same reference numerals, and their description will be omitted.

[0097] Similar to the TLB 311 in the first embodiment, the TLB 311b in the address translation unit 31b has a plurality of page table entries for translating virtual addresses into physical addresses, and functions as a cache for page tables stored in the memory 20. Each page table entry includes valid flag data in addition to tag information and data. The valid flag data indicates whether the entry is valid or invalid.

[0098] The determination unit 324b of the self-diagnostic test unit 32b receives the TLB hit / miss signal 1004 and the address translation result 1005, similar to the TLB 324 of the first embodiment, and determines the self-diagnostic test result of the address translation function of the address translation unit 31b. The determination unit 324b further outputs a valid flag control signal 1009 that sets valid flag data of the TLB 311b based on the self-diagnostic test result. For example, the determination unit 324b outputs the valid flag control signal 1009 to set valid flag data indicating invalid for an entry determined to have a fault as a result of the self-diagnostic test. As a result, the entry in which the fault has occurred is set to invalid. The MMU 3b can perform address translation operations using valid entries other than the invalid entries of the TLB 311b. Although the MMU 3b cannot use all entries in the TLB, it can continue address translation operations using some of the entries, thereby ensuring time until the system transitions to a safe state.

[0099] Furthermore, in addition to the self-diagnostic test results, the determination unit 324b also stores information about whether valid flag data has been set in the self-diagnostic test result storage unit 325. The self-diagnostic test results and information about the valid flag data setting are read out to the CPU 1 as self-diagnostic test result information 1007b. The CPU 1 can transition the system to an appropriate operating mode based on the self-diagnostic test result information 1007b, which includes information about the valid flag data setting. For example, the CPU 1 may determine whether to continue system operation or determine the operating mode to transition to based on the number of entries for which valid flag data indicating invalidity has been set.

[0100] Although the MMU 3b, which is the primary MMU, has been described, the TLB of the lower MMU may have valid flag data, similar to the TLB 311b, and may be set based on the results of a self-diagnostic test.

[0101] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0102] In addition, in the first to fourth embodiments, an example has been described in which the address translation function is configured with an MMU having two layers, but a hierarchical structure of more than two layers may be used. Also, the dedicated processing units may have a hierarchical structure, and the MMU may have a hierarchical structure corresponding to the dedicated processing units in the hierarchical structure. [Explanation of symbols]

[0103] 1 CPU 2, 2_0, 2_1 dedicated processing section 3, 3_0, 3_1, 3a, 3b, 5, 5a MMU 4. Bus 6 Memory Controller 7 Timer Module 8 Temperature Sensor 9 Voltage Sensor 10, 10a, semiconductor device 20 memory 31, 31a, 31b, 51, 51a Address conversion unit 32, 32a, 32b, 52 Self-diagnostic test section 100 Data processing device 311, 311a, 311b, 511, 511a Translation Lookaside Buffer 312, 312a, 512 Address conversion circuit 321, 521 Self-diagnosis test control section 322 Request control section 323, 323a, 523, 523a TLB control unit 324, 324b Judgment section 325 Self-diagnosis test result storage section 326, 526 Error Address Register 33 Interrupt request unit

Claims

1. a processing unit that issues a memory access request using a virtual address; a primary memory management unit provided corresponding to the processing unit; a secondary memory management unit that forms a hierarchical structure with the primary memory management unit and is connected to the primary memory management unit; Equipped with the primary memory management unit includes a first address translation unit that translates the virtual address of the memory access request into a physical address, and a first self-diagnostic test unit that performs a self-diagnostic test on the first address translation unit; the secondary memory management unit comprises: a second address translation unit that translates the virtual address of the memory access request into a physical address when the memory access request has not been address-translated by the primary memory management unit; and a second self-diagnostic test unit that performs a self-diagnostic test on the second address translation unit; a result storage unit for storing first and second self-diagnostic test results, which are the self-diagnostic test results of the first and second self-diagnostic test units; a self-diagnostic test execution instruction unit that outputs a self-diagnostic test start signal; the first self-diagnostic test unit includes a request control unit that issues a self-diagnostic memory access request to the first address translation unit in response to the self-diagnostic test start signal; Equipped with The first and second address conversion units each include: a translation lookaside buffer for storing a plurality of page table entries that are part of a page table stored in memory; an address translation circuit that translates the virtual address into a physical address based on a search result of the translation lookaside buffer; Equipped with each of the first and second self-test units includes a translation lookaside buffer control unit that rewrites the plurality of page table entries included in the corresponding translation lookaside buffer to self-test page table entries in response to the self-test start signal; Semiconductor device.

2. The semiconductor device according to claim 1 further comprises a CPU, the CPU reads out the first and second self-diagnostic test results from the result storage unit, issues a first reset signal to the primary memory management unit based on the first self-diagnostic test result, and issues a second reset signal to the secondary memory management unit based on the second self-diagnostic test result; Semiconductor device.

3. a plurality of self-test page table entries stored in the translation lookaside buffer of the first address translation unit and a plurality of self-test page table entries stored in the translation lookaside buffer of the second address translation unit are different from each other; The semiconductor device according to claim 1 .

4. a CPU serving as the self-diagnostic test execution instruction unit; the CPU outputs the self-diagnostic test start signal according to a software program; The semiconductor device according to claim 1 .

5. the self-diagnostic test start signal includes information specifying a memory management unit that is to be subjected to the self-diagnostic test; The semiconductor device according to claim 1 .

6. a timer module that functions as the self-diagnostic test execution instruction unit; the timer module outputs the self-diagnostic test start signal at a predetermined interval; The semiconductor device according to claim 1 .

7. The semiconductor device according to claim 6 further comprises a sensor for detecting an operating environment of the semiconductor device, The semiconductor device, wherein the cycle at which the timer module outputs the self-diagnostic test start signal is controlled in accordance with the detection result of the sensor.

8. 8. The semiconductor device according to claim 7, wherein the sensor is a temperature sensor.

9. The semiconductor device according to claim 7 , wherein the sensor is a voltage sensor.

10. A processing unit that issues a memory access request using a virtual address; a primary memory management unit provided corresponding to the processing unit; a secondary memory management unit that forms a hierarchical structure with the primary memory management unit and is connected to the primary memory management unit; Equipped with the primary memory management unit includes a first address translation unit that translates the virtual address of the memory access request into a physical address, and a first self-diagnostic test unit that performs a self-diagnostic test on the first address translation unit; the secondary memory management unit comprises: a second address translation unit that translates the virtual address of the memory access request into a physical address when the memory access request has not been address-translated by the primary memory management unit; and a second self-diagnostic test unit that performs a self-diagnostic test on the second address translation unit; a result storage unit for storing first and second self-diagnostic test results, which are the self-diagnostic test results of the first and second self-diagnostic test units; a self-diagnostic test execution instruction unit that outputs a self-diagnostic test start signal; the first self-diagnostic test unit includes a request control unit that issues a self-diagnostic memory access request to the first address translation unit in response to the self-diagnostic test start signal; an interrupt request unit that requests the self-diagnostic test execution instruction unit to output the self-diagnostic test start signal when the address translation results of the first and second address translation units in response to a memory access request from the processing unit indicate an address translation error; Equipped with The first and second address conversion units each include: a translation lookaside buffer that stores a portion of the page table stored in memory; an address translation circuit that translates the virtual address into a physical address based on a search result of the translation lookaside buffer; Equipped with the first self-diagnostic test unit issues, based on the self-diagnostic test start signal, a memory access request for a self-diagnostic test that hits a page table entry in the translation lookaside buffer for which the address translation result of the first or second address translation unit results in the address translation error; Semiconductor device.

11. A processing unit that issues a memory access request using a virtual address; a primary memory management unit provided corresponding to the processing unit; a secondary memory management unit that forms a hierarchical structure with the primary memory management unit and is connected to the primary memory management unit; Equipped with the primary memory management unit includes a first address translation unit that translates the virtual address of the memory access request into a physical address, and a first self-diagnostic test unit that performs a self-diagnostic test on the first address translation unit; the secondary memory management unit comprises: a second address translation unit that translates the virtual address of the memory access request into a physical address when the memory access request has not been address-translated by the primary memory management unit; and a second self-diagnostic test unit that performs a self-diagnostic test on the second address translation unit; a result storage unit for storing first and second self-diagnostic test results, which are the self-diagnostic test results of the first and second self-diagnostic test units; Equipped with The first and second address conversion units each include: a translation lookaside buffer for storing a plurality of page table entries that are part of a page table stored in memory; an address translation circuit that translates the virtual address into a physical address based on a search result of the translation lookaside buffer; Equipped with Each of the plurality of page table entries has translation information from a virtual address to a physical address and enable information that is set to be enabled or disabled based on the result of a self-diagnostic test. Semiconductor device.

12. a memory access request issuing unit that issues a memory access request in which a virtual address is set; a primary memory management unit having a first address translation unit including a first translation lookaside buffer that holds a first portion of a page table stored in the memory, and a first self-test unit that performs a self-test on the first address translation unit; a secondary memory management unit including a second address translation unit that holds a second portion of a page table stored in the memory and includes a second translation lookaside buffer that is accessed when a page table entry corresponding to the virtual address does not exist in the first translation lookaside buffer, and a second self-test unit that performs a self-test on the second address translation unit; a result storage unit for storing first and second self-diagnostic test results obtained by the first and second self-diagnostic test units; A semiconductor device comprising:

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