Comparators and Analog-to-Digital Converters

Abstract

[Problem] To suppress kickback currents, and to prevent deviations in a signal for outputting a comparison result. [Solution] This comparator comprises: a first input terminal and a second input terminal into which a first pair of differential input signals are input; a third input terminal and a fourth input terminal into which a second pair of differential input signals are input; a first comparison circuit that outputs a signal according to a difference signal of the first pair of differential input signals that is generated upon connecting the first input terminal to a positive side and connecting the second input terminal to a negative side, and a difference signal of the second pair of differential input signals that is generated upon connecting the third input terminal to the positive side and connecting the fourth input terminal to the negative side; and a second comparison circuit that outputs a signal according to a difference signal of the first pair of differential input signals that is generated upon connecting the first input terminal to the negative side and connecting the second input terminal to the positive side, and a difference signal of the second pair of differential input signals that is generated upon connecting the third input terminal to the positive side and connecting the fourth input terminal to the negative side.

Description

[Technical Field]

[0001] The present disclosure relates to comparators and analog-to-digital converters. [Background technology]

[0002] A successive approximation type analog-to-digital converter (hereinafter referred to as successive approximation type ADC) is known that includes a sampling switch, a comparator to which two differential input signal pairs are input, and a digital-to-analog converter (hereinafter referred to as DAC) (see Non-Patent Document 1). This type of comparator holds a signal corresponding to the difference signal between one differential input signal pair and the difference signal between the other differential input signal pair. The DAC is controlled by the signal held by the comparator, and two differential input signal pairs are generated based on the output signal of the DAC. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS”(IEEE Journal of Solid-State Circuit, 2016) Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the signal level of the difference signal between these differential input signal pairs changes significantly, that change can cause a current (hereafter referred to as a kickback current) to flow through the gate of the transistor to which the differential input signal pair is input, which can result in fluctuations in the signal level of the difference signal. If the signal level of the difference signal changes, a deviation occurs in the output signal of the comparator, and the ADC will not operate normally.

[0005] Therefore, the present disclosure provides a comparator and an analog-to-digital converter that suppress the above-mentioned kickback current and prevent deviation from occurring in the signal that outputs the comparison result. [Means for solving the problem]

[0006] In order to solve the above problem, according to the present disclosure, there is provided a first input terminal and a second input terminal to which a first differential input signal pair is input; a third input terminal and a fourth input terminal to which the second differential input signal pair is input; a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and the second input terminal to a negative side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side; a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to the negative side and the second input terminal to the positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to the positive side and the fourth input terminal to the negative side.

[0007] The amplifier may include a first output terminal and a second output terminal for outputting a pair of differential output signals according to the signal output from the first comparison circuit.

[0008] The voltage level of the difference signal of the first differential input signal pair may be greater than the voltage level of the difference signal of the second differential input signal pair.

[0009] The first comparison circuit and the second comparison circuit may have a common circuit configuration and common electrical characteristics.

[0010] the first comparison circuit has a first output node and a second output node that differentially output signals according to a difference signal of the first differential input signal pair and a difference signal of the second differential input signal pair; The amount of voltage fluctuation at the third input terminal caused in response to a voltage fluctuation at the first output node may be equal to the amount of voltage fluctuation at the fourth input terminal caused in response to a voltage fluctuation at the second output node.

[0011] The first comparison circuit a first comparator that outputs a first differential output signal pair to the first output node and the second output node, the first input terminal of which is connected to a positive side and the second input terminal of which is connected to a negative side, and that corresponds to a difference signal of the first differential input signal pair; a second comparator that outputs, from the first output node and the second output node, a second differential output signal pair corresponding to a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side, The second comparison circuit a third comparator that outputs a third differential output signal pair to a first internal node and a second internal node, the third differential output signal pair corresponding to a difference signal of the first differential input signal pair generated by connecting the second input terminal to a positive side and the first input terminal to a negative side; and a fourth comparator that outputs a fourth differential output signal pair from the first internal node and the second internal node according to a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side.

[0012] a first voltage setting circuit that sets the first output node and the second output node to a predetermined voltage level during a period in which the first comparison circuit does not perform a comparison operation; The input / output circuit may further include a second voltage setting circuit that sets the first internal node and the second internal node to a predetermined voltage level during a period in which the second comparison circuit does not perform a comparison operation.

[0013] each of the first comparator, the second comparator, the third comparator, and the fourth comparator includes an N-type transistor; Each of the first voltage setting circuit and the second voltage setting circuit may include a P-type transistor.

[0014] each of the first comparator, the second comparator, the third comparator, and the fourth comparator includes a P-type transistor; Each of the first voltage setting circuit and the second voltage setting circuit may include an N-type transistor.

[0015] the first comparator, the second comparator, the third comparator, and the fourth comparator perform a comparison operation when a predetermined signal is a first logic, and stop a comparison operation when the predetermined signal is a second logic; the first voltage setting circuit sets the first output node and the second output node to the predetermined voltage level when the predetermined signal is at the second logic level; The second voltage setting circuit may set the first internal node and the second internal node to the predetermined voltage level when the predetermined signal is at the second logic level.

[0016] The digital signal processing circuit may further include a latch circuit for holding the signal output from the first comparison circuit.

[0017] a waveform shaping circuit for shaping the waveform of the signal output from the first comparison circuit; The latch circuit may hold the signal whose waveform has been shaped by the waveform shaping circuit.

[0018] The waveform shaping circuit may be an inverter.

[0019] a first latch circuit that holds the signal output from the first comparison circuit; The digital signal processing device may further include a second latch circuit that holds the signal output from the second comparison circuit.

[0020] According to the present disclosure, a first sampling switch that switches whether or not one signal of a differential input signal pair is sampled; a first digital-to-analog converter that converts the sampled one signal into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits; a second sampling switch that switches whether or not the other signal of the differential input signal pair is sampled; a second digital-to-analog converter that converts the sampled other signal into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits; a filter circuit that samples and outputs the output signal of the first digital-to-analog converter and the output signal of the second digital-to-analog converter; a comparator that outputs a signal according to a difference signal of a first differential input signal pair, which is a pair of the output signal of the first digital-analog converter and the output signal of the second digital-analog converter, and a difference signal of a second differential input signal pair output from the filter circuit; a control circuit that controls the first digital-to-analog converter and the second digital-to-analog converter based on an output signal of the comparator. The comparator a first input terminal and a second input terminal to which the first differential input signal pair is input; a third input terminal and a fourth input terminal to which the second differential input signal pair is input; a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and the second input terminal to a negative side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side; and a second comparison circuit that outputs a signal according to a difference signal of the first differential input signal pair that is generated by connecting the first input terminal to the negative side and the second input terminal to the positive side, and a difference signal of the second differential input signal pair that is generated by connecting the third input terminal to the positive side and the fourth input terminal to the negative side. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a circuit diagram of a comparator 1 according to a first embodiment. [Figure 2A]Waveform diagram of Vgm_p and Vgm_n during the comparison operation of comparator 1. [Figure 2B] Waveform diagram when Vin_p + Vns_p < Vin_n + Vns_n. [Figure 3] Circuit diagram of successive approximation type ADC11 equipped with comparator 1 in FIG. 1. [Figure 4] Voltage waveform diagram of the output node voltage Vin_p of the first DAC14 and the output node voltage Vin_n of the second DAC15 in FIG. 3. [Figure 5] Circuit diagram of comparator 100 according to a comparative example. [Figure 6A] Signal waveform diagram of each part in comparator 1 in FIG. 1 by simulation. [Figure 6B] Signal waveform diagram of each part in comparator 100 in FIG. 5 by simulation. [Figure 7] Circuit diagram of comparator 1a according to the second embodiment. [Figure 8] Circuit diagram of comparator 1b according to the third embodiment. [Figure 9] Circuit diagram of comparator 1c according to the fourth embodiment.

Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments of a comparator and an analog-digital converter will be described with reference to the drawings. Hereinafter, the main components of the comparator and the analog-digital converter will be mainly described, but there may be components and functions not shown or described in the comparator and the analog-digital converter. The following description does not exclude components and functions not shown or described.

[0023] (First Embodiment) FIG. 1 is a circuit diagram of a comparator 1 according to a first embodiment. The comparator 1 of FIG. 1 is used in, for example, a successive approximation register ADC, as will be described later. However, the use of the comparator 1 of FIG. 1 is not necessarily limited to ADCs. Two differential input signal pairs (hereinafter referred to as a first differential input signal pair and a second differential input signal pair) Vin_p, Vin_n, Vns_p, and Vns_n are input to the comparator 1 of FIG. 1. The comparator 1 outputs a differential output signal pair Vout_p and Vout_n corresponding to the difference signal between the first differential input signal pair Vin_p and Vin_n and the difference signal between the second differential input signal pair Vns_p and Vns_n. Thus, the comparator 1 of FIG. 1 is a dynamic comparator 1 that performs a comparison operation between the two differential input signal pairs Vin_p, Vin_n, Vns_p, and Vns_n.

[0024] The comparator 1 in FIG. 1 includes a first input terminal TL1 and a second input terminal TL2 to which a first differential input signal pair Vin_p and Vin_n are input, a third input terminal TL3 and a fourth input terminal TL4 to which a second differential input signal pair Vns_p and Vns_n are input, a first comparison circuit 2, and a second comparison circuit 3.

[0025] The first comparison circuit 2 outputs a signal corresponding to a difference signal of the first differential input signal pair Vin_p, Vin_n generated by connecting the first input terminal TL1 to the positive side and the second input terminal TL2 to the negative side, and a difference signal of the second differential input signal pair Vns_p, Vns_n generated by connecting the third input terminal TL3 to the positive side and the fourth input terminal TL4 to the negative side.

[0026] The second comparison circuit 3 outputs a signal corresponding to a difference signal of the first differential input signal pair Vin_p, Vin_n generated by connecting the first input terminal TL1 to the negative side and the second input terminal TL2 to the positive side, and a difference signal of the second differential input signal pair Vns_p, Vns_n generated by connecting the third input terminal TL3 to the positive side and the fourth input terminal TL4 to the negative side.

[0027] The first comparison circuit 2 and the second comparison circuit 3 have a common circuit configuration and common electrical characteristics. More specifically, corresponding transistors in the first comparison circuit 2 and the second comparison circuit 3 have a common gate width and gate length.

[0028] The first comparison circuit 2 has the first input terminal TL1 connected to the positive side and the second input terminal TL2 connected to the negative side, and outputs a first differential output signal pair from the first output node n1 and the second output node n2 in response to the difference signal between the first differential input signal pair Vin_p and Vin_n. The amount of voltage fluctuation at the third input terminal TL3 caused by the voltage fluctuation at the first output node n1 is equal to the amount of voltage fluctuation at the fourth input terminal TL4 caused by the voltage fluctuation at the second output node n2. In contrast, the second comparison circuit 3 is not directly involved in the comparison operation of the comparator 1 and acts as a dummy circuit.

[0029] The first comparison circuit 2 includes a first comparator 4 and a second comparator 5 .

[0030] The first comparator 4 has the first input terminal TL1 connected to the positive side and the second input terminal TL2 connected to the negative side, and outputs a first differential output signal pair from the first output node n1 and the second output node n2 according to the difference signal of the first differential input signal pair Vin_p, Vin_n generated by connecting the first input terminal TL1 to the positive side and the second input terminal TL2 to the negative side.

[0031] The second comparator 5 has the third input terminal TL3 connected to the positive side and the fourth input terminal TL4 connected to the negative side, and outputs a second differential output signal pair from the first output node n1 and the second output node n2 according to the difference signal of the second differential input signal pair generated by connecting the third input terminal TL3 to the positive side and the fourth input terminal TL4 to the negative side.

[0032] The first comparator 4 has N-type MOS transistors Q1 and Q2. The first differential input signal Vin_p is input to the gate of the transistor Q1. The gate of the transistor Q1 is the positive side. The first differential input signal Vin_n is input to the gate of the transistor Q2. The gate of the transistor Q2 is the negative side.

[0033] An N-type MOS transistor Q3 is connected between the sources of the transistors Q1 and Q2 and the ground node. A clock signal Clk is input to the gate of the transistor Q3. When the clock signal Clk is at a high level, the transistors Q1 and Q2 compare the first differential input signal pair Vin_p and Vin_n, and when the clock signal Clk is at a low level, the comparison operation is stopped. The drain of the transistor Q1 is connected to a first output node n1, and the drain of the transistor Q2 is connected to a second output node n2.

[0034] The second comparator 5 has N-type MOS transistors Q4 and Q5. The first differential input signal Vns_p is input to the gate of the transistor Q4. The gate of the transistor Q4 is the positive side. The second differential input signal Vns_n is input to the gate of the transistor Q5. The gate of the transistor Q5 is the negative side.

[0035] An N-type MOS transistor Q6 is connected between the sources of the transistors Q4 and Q5 and the ground node. A clock signal Clk is input to the gate of the transistor Q6. When the clock signal Clk is at a high level, the transistors Q1 and Q2 compare the first differential input signal pair Vin_p and Vin_n, and when the clock signal Clk is at a low level, the comparison operation is stopped. The drains of the transistors Q4 and Q5 are connected to a first output node n1 and a second output node n2.

[0036] A pull-up circuit (first voltage setting circuit) 6 is connected to the first output node n1 and the second output node n2. When the clock signal Clk is at a low level, that is, during a period when the first comparison circuit 2 is not performing a comparison operation, the pull-up circuit 6 pulls up the first output node n1 and the second output node n2 to a high level. The pull-up circuit 6 has a P-type MOS transistor Q7 connected to the first output node n1 and a P-type MOS transistor Q8 connected to the second output node n2. The clock signal Clk is input to the gates of the transistors Q7 and Q8.

[0037] The second comparison circuit 3 includes a third comparator 7 and a fourth comparator 8 .

[0038] The third comparator 7 has the second input terminal TL2 connected to the positive side and the first input terminal TL1 connected to the negative side, and outputs a third differential output signal pair from the first internal node n3 and the second internal node n4 according to the difference signal of the first differential input signal pair Vin_p, Vin_n generated by connecting the second input terminal TL2 to the positive side and the first input terminal TL1 to the negative side.

[0039] The fourth comparator 8 has the third input terminal TL3 connected to the positive side and the fourth input terminal TL4 connected to the negative side, and outputs a fourth differential output signal pair from the first internal node n3 and the second internal node n4 according to the difference signal of the second differential input signal pair generated by connecting the third input terminal TL3 to the positive side and the fourth input terminal TL4 to the negative side.

[0040] The third comparator 7 has N-type MOS transistors Q9 and Q10. The first differential input signal Vin_n is input to the gate of the transistor Q9. The gate of the transistor Q9 is the positive side. The first differential input signal Vin_p is input to the gate of the transistor Q10. The gate of the transistor Q10 is the negative side.

[0041] An N-type MOS transistor Q11 is connected between the sources of the transistors Q9 and Q10 and the ground node. A clock signal Clk is input to the gate of the transistor Q11. When the clock signal Clk is at a high level, the transistors Q9 and Q10 compare the first differential input signal pair Vin_p and Vin_n, and when the clock signal Clk is at a low level, the comparison operation is stopped. The drain of the transistor Q9 is connected to a first internal node n3, and the drain of the transistor Q10 is connected to a second internal node n4.

[0042] The fourth comparator 8 has N-type MOS transistors Q12 and Q13. The second differential input signal Vns_p is input to the gate of the transistor Q12. The gate of the transistor Q12 is the positive side. The second differential input signal Vns_n is input to the gate of the transistor Q13. The gate of the transistor Q13 is the negative side.

[0043] An N-type MOS transistor Q14 is connected between the sources of the transistors Q12 and Q13 and the ground node. A clock signal Clk is input to the gate of the transistor Q14. When the clock signal Clk is at a high level, the transistors Q12 and Q13 compare the first differential input signal pair Vin_p and Vin_n, and when the clock signal Clk is at a low level, the comparison operation is stopped. The drains of the transistors Q12 and Q13 are connected to a first internal node n3 and a second internal node n4.

[0044] A pull-up circuit 9 (second voltage setting circuit) is connected to the first internal node n3 and the second internal node n4. When the clock signal Clk is at a low level, the pull-up circuit 9 pulls up the first internal node n3 and the second internal node n4 to a high level. The pull-up circuit 9 has a P-type MOS transistor Q15 connected to the first internal node n3 and a P-type MOS transistor Q16 connected to the second internal node n4. The clock signal Clk is input to the gates of the transistors Q15 and Q16.

[0045] The first internal node n3 and the second internal node n4 of the second comparison circuit 3, which acts as a dummy circuit, are connected to nothing but the dummy circuit. Meanwhile, the first output node n1 and the second output node n2 of the first comparison circuit 2 are connected to a latch circuit 10. The latch circuit 10 holds a signal indicating the comparison result output from the first comparison circuit 2 at the timing when the clock signal Clk transitions from high level to low level.

[0046] The latch circuit 10 includes P-type MOS transistors Q17 to Q20 and N-type MOS transistors Q21 to Q26. The first output node n1 is connected to the gates of transistors Q17, Q21, and Q22. The second output node n2 is connected to the gates of transistors Q18, Q24, and Q25. The gates of transistors Q20 and Q26 and the drains of transistors Q19 and Q23 are connected to an output terminal TL5 that outputs the differential output voltage Vout_p of comparator 1. The gates of transistors Q19 and Q23 and the drains of transistors Q25 and Q26 are connected to an output terminal TL6 that outputs the differential output voltage Vout_n of comparator 1.

[0047] Comparator 1 in FIG. 1 starts the comparison operation when the clock signal Clk transitions from the low level to the high level. While the clock signal Clk is at the low level, the first output node n1 and the second output node n2 are pulled up to the power supply voltage level. When the clock signal Clk transitions to the high level, the voltage levels of the first output node n1 and the second output node n2 decrease as transistors Q1, Q2, Q4, and Q5 turn on. When Vin_p + Vns_p > Vin_n + Vns_n, the discharge rate of Vgm_p > the discharge rate of Vgm_n. Conversely, when Vin_p + Vns_p < Vin_n + Vns_n, the discharge rate of Vgm_p < the discharge rate of Vgm_n.

[0048] Thus, a difference occurs in the discharge rates of the first output node n1 and the second output node n2 according to the input voltage Vin (= (Vin_p + Vns_p) - (Vin_n + Vns_n)) of comparator 1.

[0049] FIGS. 2A and 2B are waveform diagrams of Vgm_p and Vgm_n during the comparison operation of comparator 1. FIG. 2A is the waveform diagram when Vin_p + Vns_p > Vin_n + Vns_n, and FIG. 2B is the waveform diagram when Vin_p + Vns_p < Vin_n + Vns_n.

[0050] Due to the difference in discharge speed, the logic of the latch output of the latch circuit 10 on the subsequent stage side of the comparator 1 is determined. If the discharge speed of Vgm_p > the discharge speed of Vgm_n, then Vout_p = High / Vout_n = Low. If the discharge speed of Vgm_p < the discharge speed of Vgm_n, then Vout_p = Low / Vout_n = High.

[0051] In the comparator 1 of FIG. 1, the positive-phase signal Vin_p of the first differential input signal pair Vin_p, Vin_n is connected to the gate of the positive-phase transistor Q1 of the first comparator 4 in the first comparison circuit 2, and also connected to the gate of the negative-phase transistor Q10 of the third comparator 7 in the second comparison circuit 3. Further, the negative-phase signal Vin_n of the first differential input signal pair Vin_p, Vin_n is connected to the gate of the negative-phase transistor Q2 of the first comparator 4 in the first comparison circuit 2, and also connected to the gate of the positive-phase transistor Q9 of the fourth comparator 8 in the second comparison circuit 3. Thus, in the first comparison circuit 2 and the second comparison circuit 3, the connection destinations of the first differential input signal pair Vin_p, Vin_n are reversed.

[0052] The voltage levels of the first output node n1 and the second output node n2 where the comparison result of the first comparison circuit 2 is output vary greatly depending on the comparison result of the first comparison circuit 2. When the transistor Q1 or Q2 in FIG. 1 is turned on, the voltage levels of the first output node n1 or the second output node n2 decrease due to discharge. As will be described later, when the voltage levels of the first output node n1 or the second output node n2 decrease due to discharge, there is a possibility that a so-called kickback current, in which current flows through the gate of the transistor Q1 or Q2 via the parasitic capacitance of the MOS of the transistor Q1 or Q2 in the first comparison circuit 2, will occur. When a kickback current flows through the gate, the gate voltage fluctuates, and the first comparison circuit 2 cannot output a normal comparison result. As a countermeasure against the kickback current, in FIG. 1, in the first comparison circuit 2 and the second comparison circuit 3, the connection destinations of the first differential input signal pair Vin_p, Vin_n are reversed. Thereby, the influence of the kickback current can be suppressed, and the reason for this will be described later.

[0053] FIG. 3 is a circuit diagram of a successive approximation register ADC 11 including the comparator 1 of FIG. 1. The successive approximation register ADC 11 of FIG. 3 shows an example in which a differential input signal pair is converted into a 5-bit digital signal. Note that the number of bits of the successive approximation register ADC 11 is arbitrary. Furthermore, the circuit configuration of the successive approximation register ADC 11 is not limited to that shown in FIG. 3.

[0054] 3 includes a first sampling switch 12, a second sampling switch 13, a first digital-to-analog converter (hereinafter referred to as first DAC) 14, a second digital-to-analog converter (second DAC 15), a filter circuit 16, a comparator 1, and a control circuit (SAR logic) 17. In this specification, the first DAC 14 and the second DAC 15 are collectively referred to as a capacitive DAC 18.

[0055] The first sampling switch 12 switches whether to sample one signal Vad_p of the differential input signal pair Vad_p, Vad_n, and the second sampling switch 13 switches whether to sample the other signal Vad_n of the differential input signal pair Vad_p, Vad_n.

[0056] The first DAC 14 converts one of the sampled signals Vad_p into a digital signal consisting of multiple bits one bit at a time, and outputs a signal at a voltage level corresponding to the unconverted bits.

[0057] The first DAC14 has five capacitors C1 to C5 whose capacitances differ by a power of two, and three switches (first to third switches) SW1 to SW3 connected to the capacitors C1 to C5, respectively. The first switch SW1 switches whether one end of each capacitor is set to 0 V. The second switch SW2 switches whether one end of each capacitor is set to a common voltage Vcom. The third switch SW3 switches whether one end of each capacitor is set to a reference voltage Vref. The common voltage Vcom is, for example, half the voltage level of the reference voltage Vref.

[0058] The first to third switches SW1 to SW3 are switched on or off based on a control signal from the control circuit 17. The control circuit 17 turns on the second switch SW2 at the start of the comparison operation. Thereafter, the control circuit 17 turns on the first switch SW1 when it is desired to lower the output node voltage Vin_p of the first DAC 14, and turns on the third switch SW3 when it is desired to raise the output node voltage Vin_p of the first DAC 14.

[0059] The second DAC 15 converts the other sampled signal into a digital signal consisting of multiple bits one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits. The second DAC 15 has the same configuration as the first DAC 14, and switches the first to third switches SW1 to SW3 based on a control signal from the control circuit 17, just like the first DAC 14.

[0060] The filter circuit 16 samples the output signal of the first DAC 14 and the output signal of the second DAC 15 and outputs the sampled signal.

[0061] The comparator 1 has the configuration shown in Fig. 1. The comparator 1 receives a first differential input signal pair Vin_p, Vin_n, which is a pair of the output signal of the first DAC 14 and the output signal of the second DAC 15, and a second differential input signal pair Vns_p, Vns_n output from the filter circuit 16. The comparator 1 outputs a signal corresponding to the difference signal between the first differential input signal pair Vin_p, Vin_n and the difference signal between the second differential input signal pair Vns_p, Vns_n.

[0062] The control circuit 17 controls the switching of the first to third switches SW1 to SW3 in the first DAC 14 and the second DAC 15 based on the output signal of the comparator 1.

[0063] FIG. 4 is a voltage waveform diagram of the output node voltage Vin_p of the first DAC 14 and the output node voltage Vin_n of the second DAC 15 in FIG. 3. First, the first sampling switch 12 and the second sampling switch 13 are both turned on to sample the differential input signal pair Vad_p and Vad_n. At this time, one end of each of the capacitors C1 to C5 is set to the common voltage Vcom via the second switch SW2. As a result, a charge corresponding to the difference signal between the differential input signal pair Vad_p and Vad_n is accumulated in the capacitive DAC 18. The output signals of the first DAC 14 and the output signals of the second DAC 15 that constitute the capacitive DAC 18 are the first differential input signal pair Vin_p and Vin_n that are input to the comparator 1. Furthermore, the differential output signal of the filter circuit 16 is the second differential input signal pair Vns_p and Vns_n that are input to the comparator 1.

[0064] Thereafter, both the first sampling switch 12 and the second sampling switch 13 are turned off, and the comparison operation by the comparator 1 is started. The output of the capacitive DAC 18 is controlled so that the output voltage decreases in order from the above bits according to the difference signal between the sampled differential input signal pair Vad_p and Vad_n, and the output voltage gradually approaches zero.

[0065] When control is completed, the voltage remaining in the capacitive DAC 18 is sampled by the filter circuit 16, causing the output voltage of the filter circuit 16 to change. Normally, the residual voltage of the capacitive DAC 18 upon completion of control is at a very low voltage level, and the filter circuit 16 continues to output a signal at this low voltage level. In other words, the difference signal (Vns_p-Vns_n) between the second differential input signal pair Vns_p and Vns_n remains approximately equal to 0. Therefore, when the comparator 1 of FIG. 1 is used with the ADC 11 of FIG. 3, the difference in discharge rate between the voltage Vgm_p at the first output node n1 and the voltage Vgm_n at the second output node n2 of FIG. 1 is determined almost entirely by the difference signal between the first differential input signal pair Vin_p and Vin_n.

[0066] 1, when the voltage Vgm_p at the first output node n1 and the voltage Vgm_n at the second output node n2 are discharged, a kickback current flows to the gates of the transistors Q1 and Q2 in the first comparator 4 and the gates of the transistors Q4 and Q5 in the second comparator 5. The waveform of the kickback current changes significantly depending on the discharge speed of the voltage Vgm_p at the first output node n1 and the voltage Vgm_n at the second output node n2.

[0067] 3, the first differential input signal pair Vin_p, Vin_n input to the comparator 1 is connected to the output node of the capacitive DAC 18, which includes multiple capacitors C1 to C5. Therefore, even if a kickback current flows to the gates of the transistors Q1, Q2 in the first comparator 4 of FIG. 1, the voltage fluctuation of the first differential input signal pair Vin_p, Vin_n is not large. On the other hand, since no large capacitor exists at the output node of the filter circuit 16 to which the second differential input signal pair Vns_p, Vns_s is connected, if a kickback current flows to the gates of the transistors Q4, Q5 in the second comparator 5 of FIG. 1, the voltage fluctuation of the second differential input signal pair Vns_p, Vns_s may become relatively large.

[0068] In this way, the discharge of the differential output voltage pair Vgm_p, Vgm_n of the first and second output nodes n1, n2 causes a kickback to the second differential input signal pair Vns_p, Vns_n. If Vin_p = Vin_n, the discharge speed of the differential output voltage pair Vgm_p, Vgm_n of the first and second output nodes n1, n2 is the same, and the kickback current waveform is also the same. Therefore, when Vin_p = Vin_n, the voltage fluctuation of the second differential input signal pair Vns_p, Vns_n is the same, and the difference signal (Vns_p - Vns_n) between the second differential input signal pair Vns_p, Vns_n does not fluctuate. On the other hand, if Vin_p ≠ Vin_n, the discharge speed is different, and the kickback current waveform to the second differential input signal pair Vns_p, Vns_n also differs. This appears as a change in the difference signal (Vns_p - Vns_n) between the second differential input signal pair Vns_p, Vns_n. The larger the difference signal (Vin_p-Vin_n) between the first differential input signal pair Vin_p and Vin_n, the greater the difference in discharge rate, and therefore the greater the difference in the kickback current waveforms to the second differential input signal pair Vns_p and Vns_n, resulting in a greater change in the difference signal (Vns_p-Vns_n) between the second differential input signal pair Vns_p and Vns_n.

[0069] As mentioned above, the output signal level of the filter circuit 16 is essentially a small voltage level. If the output signal level of the filter circuit 16 fluctuates due to kickback, the ADC 11 may not operate as intended, degrading the characteristics of the ADC 11. Furthermore, lowering the output impedance of the filter circuit 16 to reduce voltage fluctuations increases current consumption, making the design of the filter circuit 16 more difficult.

[0070] As described above, the first comparison circuit 2 and the second comparison circuit 3 in the comparator 1 in Fig. 1 have the first differential input signal pair Vin_p, Vin_n connected to opposite terminals. This makes it possible to equalize the voltage fluctuation due to the kickback of one signal Vns_p of the second differential input signal pair Vns_p, Vns_n and the voltage fluctuation due to the kickback of the other signal Vns_n of the second differential input signal pair Vns_p, Vns_n, and thus cancel out the voltage fluctuation due to the kickback of the gates of the transistors Q4 and Q5 in the second comparator 5. This will be explained in more detail below.

[0071] In the comparator 1 of Figure 1, if the kickback current from the voltage Vgm_p of the first output node n1 to the second differential input signal Vns_p is Iα and the kickback current from the voltage Vgm_n of the second output node n2 to the second differential input signal Vns_n is Iβ, the difference in kickback current between the second differential input signal pair Vns_p, Vns_n when the second comparison circuit 3, which is a dummy circuit, does not exist is Iα-Iβ.

[0072] The discharge rate of the second internal node n4 voltage Vgm_dmy_n in the second comparison circuit 3, which is a dummy circuit, is the same as the discharge rate of the first internal node n3 voltage Vgm_dmy_p. Therefore, the kickback current from the second internal node n4 voltage Vgm_dmy_n to the second differential input signal Vns_n is Iα. Similarly, the kickback current from the first internal node n3 voltage Vgm_dmy_p to the second differential input signal Vns_p is Iβ. Considering the first comparison circuit 2 and the second comparison circuit 3 together, the kickback current to the second differential input signal Vns_p is Iα+Iβ, and the kickback current to the second differential input signal Vns_n is Iα+Iβ. Therefore, the difference in kickback current between the second differential input signals Vns_p and Vns_n is (Iα+Iβ)-(Iα+Iβ)=0. The difference in kickback current is zero, which means that the second differential input signals Vns_p and Vns_n of the comparator 1 do not fluctuate due to kickback.

[0073] In this way, in the comparator 1 of FIG. 1, the connections of the positive and negative phase signals of the first differential input signal pair Vin_p, Vin_n are reversed between the first comparator 4 in the first comparison circuit 2 and the third comparator 7 in the second comparison circuit 3. Therefore, even if a kickback current flows to the gates of the transistors Q4, Q5 in the second comparator 5 due to the discharge of the first output node n1 and the second output node n2, the kickback currents flowing to the gates of the transistors Q4, Q5 can be made equal. Therefore, the voltage fluctuations due to the kickback currents cancel each other out, and the first output node n1 and the second output node n2 are no longer affected by the kickback current.

[0074] 5 is a circuit diagram of a comparator 100 according to a comparative example. The comparator 100 in FIG. 5 includes the first comparison circuit 2 and latch circuit 10 of FIG. 1, but does not include the second comparison circuit 3. In the comparator 100 in FIG. 5, if the kickback current from the voltage Vgm_p of the first output node n1 to the second differential input signal Vns_p is Iα and the kickback current from the voltage Vgm_n of the second output node n2 to the second differential input signal Vns_n is Iβ, then because the second comparison circuit 3, which is a dummy circuit, is not present, the difference in kickback current between the gates of the transistors Q4 and Q5 in the second comparator 5 is Iα-Iβ, which is not zero. Therefore, in the comparator 100 of Figure 5, when the voltage levels of the voltage Vgm_p at the first output node n1 and the voltage Vgm_n at the second output node n2 fluctuate depending on the discharge rate, a difference in kickback current (Iα-Iβ) corresponding to the amount of fluctuation occurs, and the differential output voltages Vgm_p, Vgm_n of the comparator 100 fluctuate according to this difference.

[0075] Fig. 6A is a simulated signal waveform diagram of each part in the comparator 1 of Fig. 1, and Fig. 6B is a simulated signal waveform diagram of each part in the comparator 100 of Fig. 5. Figs. 6A and 6B show the voltage waveform of the clock signal Clk, the voltage waveform of the difference signal (Vin_p-Vin_n) between the first differential input signal pair Vin_p and Vin_n, and the voltage waveform of the difference signal (Vns_p-Vns_n) between the second differential input signal pair Vns_p and Vns_n.

[0076] 6A and 6B, the comparators 1 and 100 start a comparison operation at time t1. The control circuit 17 determines the charge of the capacitors of the capacitive DAC 18, starting from the most significant one, so that the output voltage (Vin_p-Vin_n) of the capacitive DAC 18 becomes zero. The output signal (Vns_p-Vns_n) of the filter circuit 16 is approximately 0V in FIG. 6A, whereas in FIG. 6B, a large spike-like voltage fluctuation occurs each time the comparator 100 performs a comparison operation. More specifically, in the simulation results of FIG. 6A, the output voltage of the filter circuit 16 is a minute DC voltage of approximately 300 μV, whereas in FIG. 6B, a very large spike-like voltage fluctuation occurs, sometimes exceeding 1 mV at most.

[0077] The larger the voltage of the output voltage Vin_p-Vin_n of the capacitive DAC 18, the greater the difference in discharge speed between the voltage Vgm_p of the first output node n1 and the voltage Vgm_n of the second output node n2, and the greater the voltage fluctuation of Vns_p-Vns_n due to the kickback current.

[0078] On the other hand, when the voltage of the output voltage Vin_p-Vin_n of the capacitive DAC 18 is small, the difference in discharge rate between the voltage Vgm_p of the first output node n1 and the voltage Vgm_n of the second output node n2 becomes small, and voltage fluctuations of Vns_p-Vns_n due to kickback current are less likely to occur.

[0079] In the case of a successive approximation ADC 11 using noise shaping technology, it is desirable to maintain a constant output voltage from the filter circuit 16 during the comparison operation. If the output voltage of the filter circuit 16 fluctuates, there is a risk that the analog-to-digital conversion operation will not be performed properly, and the characteristics of the ADC 11 itself will be degraded.

[0080] 6A, which shows the simulation results of comparator 1 in Fig. 1, shows that no spike-like voltage fluctuations are observed in the voltage waveform of output voltage Vin_p-Vin_n of capacitive DAC 18, and that the output voltage of filter circuit 16 is able to stably maintain a DC voltage of about 200 μV during comparison operation. Therefore, by using comparator 1 in Fig. 1 for ADC 11 in Fig. 2, the performance of ADC 11 can be improved.

[0081] As described above, the comparator 1 according to the first embodiment includes a second comparison circuit 3, which is a dummy circuit having the same circuit configuration and electrical characteristics as the first comparison circuit 2, separate from the first comparison circuit 2 to which the first differential input signal pair Vin_p, Vin_n and the second differential input signal pair Vns_p, Vns_n are input, and the connections of the first differential input signal pair Vin_p, Vin_n are reversed between the first comparison circuit 2 and the second comparison circuit 3. More specifically, in the first comparator 4 in the first comparison circuit 2, the positive-phase signal of the first differential input signal pair Vin_p, Vin_n is input to the gate of the positive-phase transistor, whereas in the third comparator 7 in the second comparison circuit 3, the positive-phase signal of the first differential input signal pair Vin_p, Vin_n is input to the gate of the negative-phase transistor. As a result, even if a kickback current flows to the gates of the transistors Q4 and Q5 in the second comparator 5 due to voltage fluctuations in the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2 of the first comparison circuit 2, it is possible to equalize the voltage fluctuations at the gates of the transistors Q4 and Q5 due to the kickback current. Therefore, voltage fluctuations due to the kickback current do not occur in the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2, the output voltage of the comparator 1 can be stabilized, and performance degradation of the ADC 11 can be suppressed.

[0082] (Second embodiment) In the comparator 1 of FIG. 1, the first comparator 4 and the second comparator 5 in the first comparison circuit 2 and the third comparator 7 and the fourth comparator 8 in the second comparison circuit 3 are configured with N-type MOS transistors, but they may also be configured with P-type MOS transistors.

[0083] FIG. 7 is a circuit diagram of a comparator 1a according to a second embodiment. The comparator 1a in FIG. 7 has transistors Q31 to Q38, Q41 to Q46, and Q51 to Q56, with the conductivity types of the transistors in the comparator 1 in FIG. 1 reversed. For example, the first comparator 4 and the second comparator 5 in the first comparison circuit 2 in the comparator 1a in FIG. 7 are composed of P-type MOS transistors Q31 to Q36. The same is true for the third comparator 7 and the fourth comparator 8 in the second comparison circuit 3. The pull-up circuit 6 is composed of N-type MOS transistors Q37 and Q38. Furthermore, the conductivity types of the transistors Q51 to Q56 in the latch circuit 10 are also reversed compared to the latch circuit 10 in FIG. 1.

[0084] In the comparator 1a of FIG. 7, the connection order of the transistors connected between the power supply node and the ground node is reversed from that of the comparator 1 of FIG. 1, but the operating principle is the same.

[0085] 7, similar to the comparator 1 in Fig. 1, the connections of the positive and negative signals of the first differential input signal pair Vin_p and Vin_n are reversed in the first comparator 4 in the first comparison circuit 2 and the third comparator 7 in the second comparison circuit 3. Therefore, similar to the comparator 1 in Fig. 1, in the comparator 1a in Fig. 7, even if a kickback current flows to the gates of the transistors Q4 and Q5 in the second comparator 5 due to voltage fluctuations in the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2, voltage fluctuations due to the kickback current do not occur in the voltages Vgm_p and Vgm_n, and performance degradation of the ADC 11 can be suppressed.

[0086] (Third embodiment) The third embodiment differs from the first embodiment in the configuration of the latch circuit 10.

[0087] Fig. 8 is a circuit diagram of a comparator 1b according to the third embodiment. The comparator 1b in Fig. 8 includes a first comparison circuit 2 and a second comparison circuit 3 having the same circuit configuration as the comparator 1 in Fig. 1. The comparator 1b in Fig. 8 includes a first latch circuit 21 connected to the first output node n1 and the second output node n2 of the first comparison circuit 2, and a second latch circuit 22 connected to the first internal node n3 and the second internal node n4 of the second comparison circuit 3.

[0088] The first latch circuit 21 has P-type MOS transistors Q61 to Q64 and N-type MOS transistors Q65 and Q66. A clock signal Clk is input to the gates of transistors Q61 and Q63. The gates of transistors Q62 and Q65 and the drains of transistors Q63 and Q64 are connected to the output node voltage Vout_p. The gates of transistors Q64 and Q66 and the drains of transistors Q62 and Q65 are connected to the output node voltage Vout_n. The source of transistor Q65 is connected to the voltage Vgm_p of the first output node n1, and the source of transistor Q66 is connected to the voltage Vgm_n of the second output node n2.

[0089] The second latch circuit 22 has P-type MOS transistors Q71 to Q74 and N-type MOS transistors Q75 and Q76, and is configured similarly to the first latch circuit .

[0090] 8 starts a comparison operation when the clock signal Clk transitions from low to high. After that, when the clock signal Clk transitions from high to low, the first latch circuit 21 holds the comparison result from the first comparison circuit 2, and the second latch circuit 22 holds the comparison result from the second comparison circuit 3.

[0091] 8, like the comparator 1 in Fig. 1, the connections of the positive and negative signals of the first differential input signal pair Vin_p and Vin_n are reversed in the first comparator 4 in the first comparison circuit 2 and the third comparator 7 in the second comparison circuit 3. Therefore, in the comparator 1b in Fig. 8, like the comparator 1 in Fig. 1, even if a kickback current flows to the gates of the transistors Q4 and Q5 in the second comparator 5 due to voltage fluctuations in the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2, voltage fluctuations due to the kickback current do not occur in the voltages Vgm_p and Vgm_n, and performance degradation of the ADC 11 can be suppressed.

[0092] As with the comparator 1a of FIG. 7, the conductivity types of the transistors in the comparator 1b of FIG. 8 may be reversed.

[0093] (Fourth embodiment) The comparator 1c according to the fourth embodiment shapes the waveform of the signal output from the first comparison circuit 2 and then inputs the signal to the latch circuit 10.

[0094] 9 is a circuit diagram of a comparator 1c according to a fourth embodiment. The comparator 1c of FIG. 9 includes a first comparison circuit 2, a second comparison circuit 3, and a latch circuit 10, which are configured similarly to the comparator 1 of FIG. 1. In addition, the comparator 1c of FIG. 9 includes inverters 23 and 24. The inverters 23 and 24 are connected to a first output node n1 and a second output node n2, which are connected to the first comparison circuit 2, respectively.

[0095] The inverters 23 and 24 invert the logic of the input signal and output it, and in doing so, perform waveform shaping to make the output signal waveform steeper. In this way, the inverters 23 and 24 function as waveform shaping circuits. Various logical operation elements (e.g., NAND elements, NOR elements, etc.) may be used instead of the inverters 23 and 24.

[0096] The voltage levels of the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2 decrease due to discharging by the transistors Q1, Q2, Q4, and Q5 in the first comparator 4 and the second comparator 5. The inverters 23 and 24 are charged as the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2 are discharged. The latch circuit 10 performs a holding operation using logic that corresponds to the difference in charging speed of the output voltages of the inverters 23 and 24.

[0097] 9, similar to the comparator 1 in Fig. 1, the connections of the positive and negative signals of the first differential input signal pair Vin_p and Vin_n are reversed in the first comparator 4 in the first comparison circuit 2 and the third comparator 7 in the second comparison circuit 3. Therefore, similar to the comparator 1 in Fig. 1, in the comparator 1b in Fig. 8, even if a kickback current flows to the gates of the transistors Q4 and Q5 in the second comparator 5 due to voltage fluctuations in the voltages Vgm_p and Vgm_n at the first output node n1 and the second output node n2, voltage fluctuations due to the kickback current do not occur in the voltages Vgm_p and Vgm_n, and performance degradation of the ADC 11 can be suppressed.

[0098] The waveform shaping circuit including the inverters 23, 24 and the like in FIG. 9 may be provided in the comparators 1a, 1b in FIG. 7 or FIG.

[0099] As described above, in the fourth embodiment, the output signal of the first comparison circuit 2 is first waveform-shaped by the inverters 23, 24, etc., and then held by the latch circuit 10. This allows the latch circuit 10 to quickly perform the holding operation, thereby improving the operating speed of the comparator 1c in FIG. 9.

[0100] A common technical feature of the comparators 1, 1a, 1b, and 1c according to the first to fourth embodiments described above is that a second comparison circuit 3 having the same circuit configuration and electrical characteristics as the first comparison circuit 2 is provided, and the connections of the first differential input signal pair Vin_p and Vin_n are reversed between the first comparison circuit 2 and the second comparison circuit 3. This makes it possible to suppress fluctuations in the voltages Vgm_p and Vgm_n of the first output node n1 and the second output node n2 of the first comparison circuit 2 caused by kickback current.

[0101] The present technology can be configured as follows: (1) a first input terminal and a second input terminal to which a first differential input signal pair is input; a third input terminal and a fourth input terminal to which the second differential input signal pair is input; a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and the second input terminal to a negative side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side; a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to the negative side and the second input terminal to the positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to the positive side and the fourth input terminal to the negative side. (2) The comparator according to (1), comprising a first output terminal and a second output terminal that output a differential output signal pair according to the signal output from the first comparison circuit. (3) The comparator according to (1) or (2), wherein the voltage level of the difference signal of the first differential input signal pair is greater than the voltage level of the difference signal of the second differential input signal pair. (4) The comparator according to any one of (1) to (3), wherein the first comparison circuit and the second comparison circuit have a common circuit configuration and common electrical characteristics. (5) the first comparison circuit has a first output node and a second output node that differentially output signals according to a difference signal of the first differential input signal pair and a difference signal of the second differential input signal pair; A comparator according to any one of (1) to (4), wherein the amount of voltage fluctuation at the third input terminal occurring in response to the voltage fluctuation at the first output node is equal to the amount of voltage fluctuation at the fourth input terminal occurring in response to the voltage fluctuation at the second output node. (6) The first comparison circuit a first comparator that outputs a first differential output signal pair to the first output node and the second output node, the first input terminal of which is connected to a positive side and the second input terminal of which is connected to a negative side, and that corresponds to a difference signal of the first differential input signal pair; a second comparator that outputs, from the first output node and the second output node, a second differential output signal pair corresponding to a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side, The second comparison circuit a third comparator that outputs a third differential output signal pair to a first internal node and a second internal node, the third differential output signal pair corresponding to a difference signal of the first differential input signal pair generated by connecting the second input terminal to a positive side and the first input terminal to a negative side; The comparator according to (5), further comprising: a fourth comparator that outputs a fourth differential output signal pair from the first internal node and the second internal node according to a difference signal of the second differential input signal pair generated by connecting the third input terminal to the positive side and the fourth input terminal to the negative side. (7) a first voltage setting circuit that sets the first output node and the second output node to a predetermined voltage level during a period in which the first comparison circuit does not perform a comparison operation; The comparator according to (6), further comprising: a second voltage setting circuit that sets the first internal node and the second internal node to a predetermined voltage level during a period in which the second comparison circuit does not perform a comparison operation. (8) each of the first comparator, the second comparator, the third comparator, and the fourth comparator includes an N-type transistor; The comparator according to (7), wherein the first voltage setting circuit and the second voltage setting circuit each have a P-type transistor. (9) Each of the first comparator, the second comparator, the third comparator, and the fourth comparator has a P-type transistor; The comparator according to (7), wherein the first voltage setting circuit and the second voltage setting circuit each have an N-type transistor. (10) The first comparator, the second comparator, the third comparator, and the fourth comparator perform a comparison operation when a predetermined signal is a first logic, and stop the comparison operation when the predetermined signal is a second logic; the first voltage setting circuit sets the first output node and the second output node to the predetermined voltage level when the predetermined signal is at the second logic level; The comparator according to any one of (7) to (9), wherein the second voltage setting circuit sets the first internal node and the second internal node to the predetermined voltage level when the predetermined signal is the second logic. (11) The comparator according to any one of (1) to (10), further comprising a latch circuit that holds the signal output from the first comparison circuit. (12) The comparator according to (11), further comprising a waveform shaping circuit that shapes the waveform of the signal output from the first comparison circuit, wherein the latch circuit holds the signal whose waveform has been shaped by the waveform shaping circuit. (13) The comparator according to (12), wherein the waveform shaping circuit is an inverter. (14) a first latch circuit that holds the signal output from the first comparison circuit; The comparator according to any one of (1) to (10), further comprising: a second latch circuit that holds the signal output from the second comparison circuit. (15) a first sampling switch that switches whether or not one of the differential input signal pair is sampled; a first digital-to-analog converter that converts the sampled one signal into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits; a second sampling switch that switches whether or not the other signal of the differential input signal pair is sampled; a second digital-to-analog converter that converts the sampled other signal into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits; a filter circuit that samples and outputs the output signal of the first digital-to-analog converter and the output signal of the second digital-to-analog converter; a comparator that outputs a signal according to a difference signal of a first differential input signal pair, which is a pair of the output signal of the first digital-analog converter and the output signal of the second digital-analog converter, and a difference signal of a second differential input signal pair output from the filter circuit; a control circuit that controls the first digital-to-analog converter and the second digital-to-analog converter based on an output signal of the comparator. The comparator a first input terminal and a second input terminal to which the first differential input signal pair is input; a third input terminal and a fourth input terminal to which the second differential input signal pair is input; a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and the second input terminal to a negative side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side; a second comparison circuit that outputs a signal according to a difference signal of the first differential input signal pair that is generated by connecting the first input terminal to a negative side and the second input terminal to a positive side, and a difference signal of the second differential input signal pair that is generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side.

[0102] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0103] 1, 1a, 1b, 1c comparators, 2 first comparison circuit, 3 second comparison circuit, 4 first comparator, 5 second comparator, 6 pull-up circuit, 7 third comparator, 8 fourth comparator, 9 pull-up circuit, 10 latch circuit, 11 ADC, 12 first sampling switch, 13 second sampling switch, 14 first DAC, 15 second DAC, 16 filter circuit, 17 control circuit, 18 capacitance DAC, 21 first latch circuit, 22 second latch circuit,

Claims

1. a first input terminal and a second input terminal to which a first differential input signal pair is input; a third input terminal and a fourth input terminal to which the second differential input signal pair is input; a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and the second input terminal to a negative side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side; a second comparison circuit that outputs a signal according to a difference signal of the first differential input signal pair that is generated by connecting the first input terminal to a negative side and the second input terminal to a positive side, and a difference signal of the second differential input signal pair that is generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side, comparator.

2. a first output terminal and a second output terminal for outputting a differential output signal pair according to the signal output from the first comparison circuit; 2. The comparator of claim 1.

3. a voltage level of the difference signal of the first differential input signal pair is greater than a voltage level of the difference signal of the second differential input signal pair; 3. A comparator according to claim 1 or 2.

4. the first comparison circuit and the second comparison circuit have a common circuit configuration and common electrical characteristics; A comparator according to any one of claims 1 to 3.

5. the first comparison circuit has a first output node and a second output node that differentially output signals according to a difference signal of the first differential input signal pair and a difference signal of the second differential input signal pair; a voltage fluctuation amount of the third input terminal caused in response to a voltage fluctuation of the first output node is equal to a voltage fluctuation amount of the fourth input terminal caused in response to a voltage fluctuation of the second output node; A comparator according to any one of claims 1 to 4.

6. The first comparison circuit a first comparator that outputs a first differential output signal pair to the first output node and the second output node, the first input terminal of which is connected to a positive side and the second input terminal of which is connected to a negative side, and that corresponds to a difference signal of the first differential input signal pair; a second comparator that outputs, from the first output node and the second output node, a second differential output signal pair corresponding to a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side, The second comparison circuit a third comparator that connects the second input terminal to a positive side and the first input terminal to a negative side and outputs a third differential output signal pair to a first internal node and a second internal node, the third differential output signal pair corresponding to a difference signal of the first differential input signal pair generated by connecting the second input terminal to a positive side and the first input terminal to a negative side; a fourth comparator that outputs a fourth differential output signal pair from the first internal node and the second internal node according to a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and the fourth input terminal to a negative side, 6. The comparator of claim 5.

7. a first voltage setting circuit that sets the first output node and the second output node to a predetermined voltage level during a period in which the first comparison circuit does not perform a comparison operation; a second voltage setting circuit that sets the first internal node and the second internal node to a predetermined voltage level during a period in which the second comparison circuit does not perform a comparison operation; 7. The comparator of claim 6.

8. each of the first comparator, the second comparator, the third comparator, and the fourth comparator includes an N-type transistor; each of the first voltage setting circuit and the second voltage setting circuit includes a P-type transistor; 8. The comparator of claim 7.

9. each of the first comparator, the second comparator, the third comparator, and the fourth comparator includes a P-type transistor; each of the first voltage setting circuit and the second voltage setting circuit includes an N-type transistor; 8. The comparator of claim 7.

10. the first comparator, the second comparator, the third comparator, and the fourth comparator perform a comparison operation when a predetermined signal is a first logic, and stop the comparison operation when the predetermined signal is a second logic; the first voltage setting circuit sets the first output node and the second output node to the predetermined voltage level when the predetermined signal is at the second logic level; the second voltage setting circuit sets the first internal node and the second internal node to the predetermined voltage level when the predetermined signal is at the second logic level. A comparator according to any one of claims 7 to 9.

11. a latch circuit for holding the signal output from the first comparison circuit; A comparator according to any one of claims 1 to 10.

12. a waveform shaping circuit for shaping the waveform of the signal output from the first comparison circuit; a latch circuit for holding the signal waveform-shaped by the waveform shaping circuit. A comparator according to any one of claims 1 to 10.

13. the waveform shaping circuit is an inverter; 13. The comparator of claim 12.

14. a first latch circuit that holds the signal output from the first comparison circuit; a second latch circuit that holds the signal output from the second comparison circuit; A comparator according to any one of claims 1 to 10.

15. a first sampling switch that switches whether one signal of the differential input signal pair is sampled; a first digital-to-analog converter that converts the sampled one signal into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits; a second sampling switch that switches whether or not the other signal of the differential input signal pair is sampled; a second digital-to-analog converter that converts the sampled other signal into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits; a filter circuit that samples the output signal of the first digital-to-analog converter and the output signal of the second digital-to-analog converter and outputs the second differential input signal pair; a comparator according to any one of claims 1 to 14, which outputs a signal according to a difference signal of the first differential input signal pair, which is a pair of an output signal of the first digital-analog converter and an output signal of the second digital-analog converter, and a difference signal of the second differential input signal pair; a control circuit that controls the first digital-to-analog converter and the second digital-to-analog converter based on an output signal of the comparator. Analog-to-digital converter.

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