Power- and area-efficient digital-to-time converter with improved stability

Abstract

To provide a power efficiency of which a stability is improved and provide a digital-time converter with a good area efficiency.SOLUTION: A digital-time converter (DTC) 100 converts a digital code dtc_code into a time delay by using a capacitor digital-analog converter (C-DAC) that functions as a charging capacitor. The DTC contains a switched capacitor voltage-current converter 135 for forming a charging current or a discharge current for charging or discharging a charging capacitor in the C-DAC in response to a trigger edge of an input clock signal clk_in for starting the time delay. A comparator 115 determines a termination of the time delay by comparing a voltage of the charging capacitor with a threshold voltage.SELECTED DRAWING: Figure 1

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]

[0001] This application claims priority to and benefit of U.S. patent application Ser. No. 17 / 111,208, filed December 3, 2020, and U.S. patent application Ser. No. 17 / 449,250, filed September 28, 2021, the entire contents of which are incorporated herein by reference. [Technical Field]

[0002] This application relates to digital-to-time converters, and more particularly to power- and area-efficient digital-to-time converters that are robust to process, voltage, and temperature variations. [Background technology]

[0003]

[0003] Fractional-N phase-locked loops (PLLs) are important building blocks for frequency synthesizers and for low-jitter clock applications using fixed frequency or spread spectrum. To provide performance improvements over phase noise and fractional spurs while achieving low power, digital-to-time converters (DTCs) are used in fractional-N PLLs. The DTC converts a digital code or word into a time delay, functioning as a true fractional divider with high resolution in the PLL. The DTC is also a fundamental building block suitable for other applications, including sampling oscilloscopes, direct digital frequency synthesis (DDFS), polar transmitters, radar, phased array systems, and time-interleaved ADC timing calibration.

[0004] It is known to use complementary metal-oxide semiconductor (CMOS) delay cells to form DTCs. However, CMOS delay cells are sensitive to process, voltage, and temperature (PVT) variations. Therefore, improved power supply noise robustness can be achieved by implementing a DTC with a capacitor charging circuit. The capacitor charging circuit charges a capacitor according to a digital word converted into a time delay by the DTC. A digital-to-analog converter (DAC), such as a resistor-DAC (R-DAC), converts the digital word into an initial voltage (Vinit) for the charging capacitor. The charging capacitor, charged to Vinit, is then further charged with a constant current until the charging capacitor voltage reaches a threshold voltage (Vtrip). The time delay is equal to the delay due to charging the charging capacitor, charged to Vinit, from Vinit to Vtrip. However, the DAC consumes power and semiconductor die area. Furthermore, the DTC may be affected by process, voltage, and temperature variations. Summary of the Invention

[0005]

[0005] A circuit is provided that includes a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors, a first current source configured to charge the plurality of capacitors with a charging current via the common terminal, and a comparator having a first input terminal coupled to the common terminal.

[0006]

[0006] Further, a method for a digital-to-time converter is provided, the method including charging an array of capacitors in a capacitive digital-to-analog converter in response to a digital code to form an array of charged capacitors, further charging the array of charged capacitors with a charging current via a common terminal in response to a timing signal to form an increased voltage for the common terminal, and determining when the increased voltage is equal to a trip voltage.

[0007]

[0007] Further provided is a circuit including a voltage-to-current switched capacitor converter configured to convert a reference voltage into a first current, a charging capacitor, a current mirror configured to mirror the first current to become a charging current for charging the charging capacitor, and a comparator having a first input coupled to the charging capacitor and a second input configured to receive a trip voltage.

[0008]

[0008] Finally, a circuit is provided that includes a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors, a first current source configured to discharge the plurality of capacitors with a discharge current conducted through the common terminal, and a comparator having a first input terminal coupled to the common terminal.

[0009]

[0009] These and other advantageous features can be better understood through the following detailed description. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram of an exemplary DTC in which a capacitive DAC (CDAC) functions as a charging capacitor that is charged during a time delay, according to one aspect of the present disclosure. [Figure 2]

[0011] 2 illustrates several exemplary voltage waveforms for charging the charge capacitor in the DTC of FIG. 1; [Figure 3]

[0012] FIG. 2 is a circuit diagram of a binary-weighted CDAC for a DTC according to one embodiment of the present disclosure. [Figure 4]

[0013] FIG. 1 is a circuit diagram of a switched capacitor voltage-to-current converter and current mirror according to one embodiment of the present disclosure. [Figure 5]

[0014] FIG. 1 is a diagram of an example DTC in which a switched capacitor voltage-current functions to generate a charging current for a charging capacitor, according to one embodiment of the disclosure. [Figure 6]

[0015] 1 is a flowchart of an exemplary method of operation of a DTC according to one embodiment of the present disclosure. [Figure 7]

[0016] 1 illustrates several exemplary electronic systems, each containing a DTC, according to one embodiment of the present disclosure. [Figure 8]

[0017] FIG. 10 is a diagram of an exemplary DTC in which the CDAC acts as a charging capacitor that is discharged during a time delay, according to one embodiment of the disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0018] Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

[0012]

[0019] A digital-to-time converter (DTC) is disclosed in which a capacitor DAC (CDAC) functions as both a digitally controlled voltage generator for a charging capacitor and as the charging capacitor itself. Compared to conventional charging capacitor DTC architectures, the resulting DTC has improved power efficiency and occupies reduced semiconductor die area. This reduced die space improves density because more circuitry can be integrated into the same die space due to the reduced area resulting from the implementation of the digital-to-time converter. A switched-capacitor voltage-to-current converter is also disclosed for generating a charging current to the charging capacitor to improve stability over process, voltage, and temperature variations.

[0013]

[0020] An exemplary DTC 100 is shown in FIG. 1. The CDAC 105 includes an array of capacitors sharing a common terminal 145 that is charged to an initial voltage Vinit in response to a digital DTC code (dtc_code). As described further herein, the CDAC 105 functions such that Vinit is a fraction of a DAC reference voltage (Vref_dac). The number of different fractions depends on the resolution of the CDAC 105 and its encoding. For example, in a 3-bit binary encoding implementation, the CDAC 105 can convert the DTC code dtc_code to one of eight possible settings for Vinit: 0 V, ⅛ Vref_dac, ¼ Vref_dac, ⅜ Vref_dac, ½ Vref_dac, ⅝ Vref_dac, ¾ Vref_dac, and ⅝ Vref_dac.

[0014]

[0021] After the multiple capacitors in CDAC 105 are charged to Vinit, they are all connected in parallel to a common terminal 145, so that they function as a single charging capacitor. Once the capacitors in CDAC 105 are charged to Vinit, an edge (which can be a rising or falling edge) of a timing signal, such as an input clock signal (clk_in), triggers switch S1 to close, causing a current source, such as current mirror 110, to begin charging the capacitors with a constant charging current Ichg. Comparator 115 functions to compare the common terminal voltage within CDAC 105 with a threshold voltage Vtrip. The output signal from comparator 115 may be inverted by inverter 120 to form the output clock signal (clk_dtc_out) of DTC 100, which is asserted to the power supply voltage at the end of a time delay. Thus, the time delay from DTC 100 is equal to the delay between the triggering edge of the input clock edge and the assertion of the output clock signal. In an alternative implementation, comparator 115 may be configured such that the output clock signal has a falling edge (discharging to ground) at the end of the time delay.

[0015]

[0022] Several example waveforms for charging the capacitors in CDAC 105 are shown in FIG. 2. In the following description, the multiple capacitors in CDAC 105 are collectively referred to as charging capacitors because they are connected in parallel to common terminal 145 during a charge redistribution phase in which the capacitors are charged to Vinit. In first waveform 200, the charging capacitors are charged to an initial voltage Vinit1 that is greater than the initial voltage Vinit2 of second waveform 205. A trigger edge of the input clock signal occurs at time t0. Both waveforms increase linearly from a constant charging current Ichg. However, waveform 200 reaches Vtrip at time t1, earlier than waveform 205 reaches Vtrip at time t2, due to Vinit1 being greater than Vinit2. Therefore, the time delay Δt1 from time t0 to time t1 of waveform 200 is shorter than the time delay Δt2 from time t0 to time t2 of waveform 205.

[0016]

[0023] Referring again to FIG. 1 , any suitable current source may be used to charge the charge capacitor with a constant charging current Ichg when switch S1 is closed. A particularly advantageous current source is formed by a switched-capacitor voltage-to-current converter 135, which functions to make DTC 100 robust to process, voltage, and temperature variations, as described further herein. The switched-capacitor voltage-to-current converter 135 converts an input reference voltage Vrefp into a first current I. A current source, such as current mirror 110, mirrors the first current I into a charging current Ichg that charges the charge capacitor. To generate the input reference voltage Vrefp, current source 125 drives a reference current Iref into a resistor biased by a bias voltage Vbias. In DTC 100, current source 125 drives the reference current Iref into a pair of resistors R2 and R1, although it should be understood that a single resistor (or more than two resistors) may be used in alternative implementations. In an alternative implementation, a voltage reference circuit with a voltage buffer may be used instead of the current source 125 to generate the input reference voltage Vrefp.

[0017]

[0024] Resistors R2 and R1 are placed in series between current source 125 and ground. Resistors R1 and R2 form a voltage divider, such that a voltage divider node 140 between resistors R1 and R2 is charged to a reference voltage Vref_dac that is equal to a divided down version of the input reference voltage Vrefp, depending on the resistance of resistors R1 and R2. By appropriately adjusting these resistors, the output voltage range of CDAC 105 can be set relative to the input reference voltage Vrefp.

[0018]

[0025] In some implementations, resistor R2 can be shorted or removed so that the reference voltage Vref_dac is equal to the input reference voltage Vrefp, thereby compensating for the offset of comparator 115 as follows: If comparator 115 were perfect, it would discharge its output signal when its negative terminal input voltage Vn equaled Vtrip at its positive input terminal. However, due to nonidealities, comparator 115 may instead discharge its output signal when the negative terminal input voltage Vn equals Vtrip plus some offset voltage, which may be positive or negative. To compensate for this offset voltage, auto-zero sampling switch S3, coupled between the output and the negative input terminal of comparator 115, is closed during the auto-zero phase before charging the charging capacitor. During the auto-zero phase, switch S2, which couples from voltage divider node 140 through auto-zero capacitor Caz to the negative input terminal of comparator 115, is also closed to couple the reference voltage Vref_dac to a first terminal of auto-zero capacitor Vac, which has a second terminal connected to the negative input terminal of comparator 115. Due to feedback through auto-zero switch S3 in the auto-zero phase, auto-zero capacitor C is charged with the offset voltage during the auto-zero phase. During normal operation, switches S2 and S3 are then open. Due to pre-charging auto-zero capacitor C to cancel the offset voltage, comparator 115 then discharges its output signal and toggles the output of inverter 120 when common terminal 145 is charged to trip voltage V regardless of the offset voltage of comparator 115.

[0019]

[0026] The CDAC 105 can be formed using any suitable encoding of its capacitors. An exemplary binary-encoded CDAC 300 is shown in more detail in FIG. 3. A reference voltage Vref_dac flows through switch S2 during an initial charging stage to charge the common terminal 145 of the array of capacitors 305. The CDAC 300 responds to a 3-bit wide digital code dtc_code, such that the array of capacitors has four capacitors, including capacitor 4C, capacitor 2C, capacitor 1C, and a second (or dummy) capacitor 1C'. As the name implies, there is a binary progression for the capacitance of the capacitors, such that capacitor 4C has twice the capacitance of capacitor 2C, and capacitor 2C has twice the capacitance of each of the 1C / 1C' capacitors. Each capacitor has a first plate coupled to the common terminal 145 or ground via a corresponding single-pole double-throw (SPDT) switch. For example, capacitor 4C has a first plate coupled to SPDT switch S4, capacitor 2C has a first plate coupled to SPDT switch S5, capacitor 1C has a first plate coupled to SPDT switch S6, and capacitor 1C' has a first plate coupled to SPDT switch S7. During the initial charging phase, bottom switch S8, which couples the second plate for each capacitor to ground, is closed. The setting of each SPDT switch during the initial charging phase depends on the DTC code. As mentioned above, a 3-bit DTC code corresponds to eight different values ​​of Vinit, ranging from 0V to 7 / 8Vref_dac, for example. For the 0V setting, each SPDT switch selects ground rather than common terminal 145. However, as the DTC code increases, more SPDT switches select common terminal 145 rather than ground to charge their respective capacitors with the DAC reference voltage Vref_dac. For example, the maximum value of the 3-bit DTC code may cause switches S4, S5, and S6 to select the common terminal, while switch S7 selects ground.In that case, capacitors S4, S5, and S6 are all charged to the DAC reference voltage during the initial charging phase.

[0020]

[0027] Once the appropriate capacitors have been charged in response to the DTC code during the initial charging phase, a charge redistribution phase occurs. The charge redistribution phase begins by opening bottom switch S8. This advantageously prevents the charge on the capacitors in capacitor array 305 from changing during the charge redistribution phase because the second plate for each capacitor is floating. More generally, ground may be replaced with a constant voltage source, with bottom switch S8 coupled between the second plate of each capacitor and the constant voltage source. It will be appreciated that switch S8 may be replaced with multiple switches S8 in alternative implementations. Once bottom switch S8 is opened, switch S2 is also opened to isolate the common terminal from the DAC reference voltage Vref at voltage divider node 140. All SPDT switches are then configured to select common terminal 145 so that the first plate for each capacitor is connected to common terminal 145. Thus, the charge on the first plate is redistributed from the capacitors that were charged during the initial charging phase to the capacitors that were grounded during the initial charging phase. Note that although the switching of the SPDT switches may be alternating or asynchronous due to nonidealities, no charge injection occurs due to the opening of bottom switch S8, which "locks" the total charge on all capacitors due to the floating second plates for each of the capacitors. The redistribution phase is then completed by closing bottom switch S8. Common terminal 145 is then charged to Vinit, which allows the input clock to be asserted to trigger the charging of the charge capacitors charged to Vinit by closing switch S1.

[0021]

[0028] An exemplary switched-capacitor voltage-to-current converter 135 with a current mirror 110 is shown in FIG. 4. A differential amplifier 405 has a feedback capacitor C3 coupled between the output of the differential amplifier 405 and its negative input terminal, forming an error integrator that integrates the difference between an input reference voltage Vrefp and the voltage at its negative input terminal. The amplifier 405 drives the gate of an NMOS transistor M4, which has its source connected to a degeneration resistor Rdg (or ground in other implementations) and its drain connected to the drain and gate of a diode-connected PMOS transistor M3. Transistor M3 forms a current mirror with current mirror PMOS transistor M2. Similarly, transistor M3 forms a current mirror 110 with current mirror PMOS transistor M1. The sources of transistors M1, M2, and M3 connect to a power supply terminal for the power supply voltage. The gates of transistors M1 and M2 connect to the gate of diode-connected transistor M3. Amplifier 405 causes transistor M4 to conduct current, which is mirrored through transistors M3 and M1 to form a first current I, which is mirrored by current mirror 110 to form a charging current Ichg. Transistor M1 is sized relative to transistor M2 so that the charging current Ichg is a factor K times the first current I. The drain of transistor M1 is coupled to a first plate of capacitor C1 through switch S11 and to ground through switch S9. The second plate of capacitor C1 is connected to ground. The first plate of capacitor C1 is also coupled to ground through switch S10. The first plate of capacitor C1 is further coupled to a first plate of capacitor C2 through switch S12. The second plate of capacitor C2 is connected to ground. The first plate of capacitor C2 is coupled to the negative input terminal of amplifier 405 through switch S13.

[0022]

[0029] A clock source, such as a crystal oscillator (not shown), generates a clock signal to control switches S9, S10, S11, S12, and S13. The clock signal has a frequency F CLK The clock signal oscillates between two phases at a frequency of 1 / f. For example, the first phase φ1 of the clock signal may correspond to when the clock signal is charging to the supply voltage, and the second phase φ2 may correspond to when the clock signal is discharging, although in alternative implementations, these two phases may be reversed. Switches S11 and S12 are closed when the clock signal is in phase φ1. During phase φ1, current I charges capacitors C1 and C2 through closed switches S11 and S12. Switches S9, S10, and S13 are open during phase φ1. During phase φ2, switches S9, S10, and S13 are closed, and switches S11 and S12 are open. During phase φ2, the charge on capacitor C2 drives the negative input terminal of amplifier 405. Capacitor C1 is discharged during phase φ2, and a first current I discharges to ground through closed switch S9. Given the clocking of this switch, the first current I is 2*F. CLK *Vrefp*C1. The current mirror transistor M1 mirrors the first current I so that the charging current Ichg is equal to a proportionality constant K times the first current I. Therefore, the charging current Ichg is equal to K*2*F CLK To demonstrate that this relationship for charging current Ichg is highly advantageous in reducing process, voltage, and temperature variations in timing delay from the DTC disclosed herein, the maximum timing delay for the DTC disclosed herein is equal to C DAC *(Vtrip / Ichg) where C DAC is the capacitance of the CDAC capacitor array (the capacitance of the charging capacitor). As mentioned above, when Vtrip and Vrefp are equal, the maximum delay is (1 / K)*(1 / F CLK )*(C DAC / C1). These coefficients are easily controlled accurately in the integrated circuit that contains the DTC 100, as opposed to conventional DTCs that rely on the precision of resistors or capacitors.

[0023]

[0030] Mismatch errors among transistors M1, M2, and M3 can be improved by using dynamic element matching (DEM) techniques via the switching matrix 410. The switching matrix 410 dynamically switches the drain connections of transistors M1, M2, and M3 to dynamically swap the roles of transistors M1, M2, and M3 but leave the relative mirror ratios between them unchanged. For example, in a first configuration of the switching matrix 410, the drain of transistor M3 is connected to the drain of transistor M4, as shown in FIG. 4. However, in a second configuration of the switching matrix 410, the drain of transistor M3 is instead connected to switch S11. In this second configuration, the drain of current mirror transistor M2 can then be connected to the drain of transistor M4 via the switching matrix 410. Similarly, the drain of current mirror transistor M1, which is normally coupled to switch S1 (FIG. 1), can be dynamically switched in other switching configurations via the switching matrix 410 to instead connect to either switch S11 or the drain of transistor M4. The resulting swapping of current mirror elements can be triggered in phase φ2 without affecting the capacitor charging operation.

[0024]

[0031] Referring again to FIG. 4 , the offset of amplifier 405 can be removed by auto-zeroing techniques similar to those described with respect to comparator 115. During clock phase φ1, switch Saz1, which connects between the negative input of amplifier 405 and the output of amplifier 405, and switch Saz2, which connects between the node of reference voltage Vrefp and the first plate of auto-zero capacitor Caz1, are closed. The second plate of auto-zero capacitor Caz2 is connected to the negative input of amplifier 405. Auto-zero switch Saz3, which connects between capacitor C3 and the negative input of amplifier 405, is open during clock phase φ1 to preserve the charge stored on capacitor C3. Thus, the offset voltage of amplifier 405 is sampled on auto-zero capacitor Caz1 during clock phase φ2. During phase φ2, switches Saz1 and Saz2 are open and switch Saz3 is closed, resulting in the offset in amplifier 405 being canceled by pre-charged capacitor Caz1. The error signal from capacitor C2 is transferred by closing switch S13 during clock phase φ2, while switch Saz3 is also closed to form an integrator with amplifier 405 and capacitor C3. Thus, the use of switched capacitor voltage-to-current converter 135 in generating charging current Ichg is highly advantageous in ensuring that the timing delays produced by the DTC are robust to process, voltage, and temperature variations.

[0025]

[0032] 5, an exemplary DTC 500 is shown in which a switched-capacitor voltage-to-current converter 135 and a current mirror 110 function to generate a charging current Ichg as described with respect to DTC 100. In DTC 500, a charging capacitor 505 is not integrated within a CDAC but instead is separately charged with an initial voltage Vinit set by a DAC 510. The remaining components of DTC 500 function as described with respect to DTC 100. If a single CDAC were used to form the charging capacitor 505 and the DAC 510, DTC 500 would decompose into DTC 100. However, even without the power and die space savings afforded by the use of a CDAC, DTC 500 remains robust to process, voltage, and temperature variations due to the use of a switched-capacitor voltage-to-current converter 135 to generate the charging current Ichg.

[0026]

[0033] An exemplary method of operation of a DTC including a CDAC will now be described with reference to the flowchart of FIG. 6 . The method includes an operation 600 of charging an array of capacitors in a capacitive digital-to-analog converter in response to a digital code to form an array of charged capacitors. Charging a common terminal 145 for the array of capacitors to an initial voltage Vinit is an example of operation 600. The method further includes an operation 605, performed in response to an edge of a timing signal, which includes further charging the charged array of capacitors with a charging current via the common terminal to form an increased voltage for the common terminal. Charging the CDAC capacitors via the common terminal 145 after a triggering edge of the input clock signal is an example of operation 605. Finally, the method includes an operation 610 of determining when the increased voltage equals a trip voltage. The comparison in comparator 115 is an example of operation 610.

[0027]

[0034] The DTCs disclosed herein may be advantageously incorporated into any suitable mobile device or electronic system. For example, as shown in Figure 7, a cellular telephone 700, a laptop computer 705, and a tablet PC 710 may all include a DTC according to the present disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, may also be configured with a DTC constructed in accordance with the present disclosure.

[0028]

[0035] Referring again to DTC 100, the same advantageous density and power improvements, as well as robustness to process, voltage, and temperature variations, may be provided in an alternative implementation in which the charge capacitor formed by CDAC 105 is discharged instead of charged during the time delay. An exemplary discharge DTC 800 is shown in FIG. 8. CDAC 105 functions, as described with respect to DTC 100, to convert the digital code to an initial voltage V stored by the CDAC capacitor to common terminal 145 during the redistribution phase of CDAC 105. Current mirror 810 mirrors a first current from switched capacitor voltage-to-current converter 805 to form a discharge current Idischarge. Current mirror 810 connects to common terminal 145 through switch S1, similar to that described with respect to DTC 100, such that when switch S1 is closed in response to a trigger clock signal edge to initiate the time delay, the discharge current Idischarge discharges the CDAC capacitor and the voltage Vinit begins to discharge.

[0029]

[0036] Comparator 815 also functions in a similar manner as described with respect to comparator 115 to determine when the initial voltage Vinit has decreased to equal the trip voltage Vtrip1, except that the trip voltage Vtrip of DTC 100 was greater than the initial voltage Vinit, but the trip voltage Vtrip1 is less than the initial voltage Vinit. Because the output of comparator 815 (clk_dtc_out) goes high at the end of the time delay when the CDAC capacitor has discharged to less than the trip voltage Vtrip1, no inverter equivalent to inverter 120 is needed within DTC 800. The remainder of DTC 800 functions as described with respect to DTC 100.

[0030]

[0037] It will be understood that numerous modifications, substitutions, and variations may be made in and to the materials, arrangements, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In this regard, the scope of the present disclosure should not be limited to the specific implementations illustrated and described herein, as these are only some examples thereof, but rather should be commensurate with the scope of the following appended claims and their functional equivalents. The inventions described in the claims of the present application as originally filed are set forth below. [C1] a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to charge the plurality of capacitors with a charging current via the common terminal; a comparator having a first input terminal coupled to the common terminal; A circuit comprising: [C2] further comprising a first switch coupled between the first current source and the common terminal, the first switch configured to be responsive to a timing signal. The circuit described in C1. [C3] at least one resistor; a second current source configured to drive a reference current through the at least one resistor to generate a reference voltage; The circuit of C1 further comprising: [C4] a switched-capacitor voltage-to-current converter configured to convert the reference voltage into a first current, the first current source comprising a current mirror configured to generate the charging current based on the first current. The circuit shown in C3. [C5] The circuit of C4, wherein the at least one resistor comprises a voltage divider having a voltage divider node for a digital-to-analog (DAC) reference voltage for the capacitive digital-to-analog converter. [C6] The circuit of C5, further comprising a second switch coupled between the voltage divider node and the common terminal. [C7] The circuit of C5, wherein a second input terminal of the comparator is coupled to the voltage divider node. [C8] The circuit is a digital-to-time converter, the digital-to-time converter comprising: an inverter configured to invert the output signal from the comparator to form an output clock signal for the digital-to-time converter; The circuit described in C7. [C9] The voltage divider is a first resistor coupled between the voltage divider node and the second current source; a second resistor coupled between the voltage divider node and ground; 3. The circuit of claim 2, comprising: [C10] further comprising a second capacitor coupled between the first input terminal and the common terminal of the comparator. The circuit described in C1. [C11] further comprising a switch connected between the output terminal of the comparator and the first input terminal; The circuit described in C1. [C12] The capacitive digital-to-analog converter further comprising a plurality of first switches corresponding to the plurality of capacitors, each first switch in the plurality of first switches being coupled between a first plate for a corresponding capacitor in the plurality of capacitors and the common terminal, and the first plurality of first switches being configured to be responsive to a digital code. The circuit described in C1. [C13] The circuit of C12, wherein a second plate of each capacitor in the plurality of capacitors is switchably coupled to ground. [C14] The circuit of C12, wherein the plurality of capacitors comprises a series of capacitors having a binary sequence of capacitances. [C15] 1. A method for operating a digital-to-time converter, comprising: charging an array of capacitors within the capacitive digital-to-analog converter in response to the digital code to form an array of charged capacitors; further charging the array of charged capacitors with a charging current via the common terminal in response to a timing signal to create an increased voltage for the common terminal; determining when the increased voltage equals a trip voltage; A method comprising: [C16] converting a reference voltage to a first current in a switched capacitor voltage-to-current converter; mirroring the first current in a current mirror to form the charging current, wherein a time delay of the digital-to-time converter is equal to a delay from a triggering edge of the timing signal to when the increasing voltage equals the trip voltage; The method of C15, further comprising: [C17] generating a reference current; driving the reference current through a resistor to form the reference voltage; The method of C16, further comprising: [C18] generating the trip voltage from the reference current. The method described in C17. [C19] Charging the array of capacitors in the capacitive digital-to-analog converter to form the array of charged capacitors includes: In a first stage, charging the subset of capacitors in the array of capacitors to the trip voltage to provide charge to the subset of capacitors; In a second step, redistributing the charge from the subset of capacitors to all of the capacitors in the array of capacitors to form the array of charged capacitors; The method of claim 18, comprising: [C20] The method of C19, further comprising isolating the array of capacitors from the constant voltage source during the charge redistribution by opening one or more switches coupled between the array of capacitors and the constant voltage source. [C21] further comprising closing a switch in response to the timing signal to couple a current source configured to provide the charging current to the common terminal. Method according to C15. [C22] a voltage-to-current switched capacitor converter configured to convert a reference voltage into a first current; a charging capacitor; a current mirror configured to mirror the first current to become a charging current for charging the charging capacitor; a comparator having a first input coupled to the charge capacitor and a second input configured to receive a trip voltage; A circuit comprising: [C23] a switch configured to close in response to a timing signal to couple the current mirror to the charging capacitor; The circuit described in C22. [C24] a capacitive digital-to-analog converter including an array of capacitors to form the charging capacitor; The circuit described in C22. [C25] The circuit of C21, wherein the circuit is contained within a cellular telephone. [C26] a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to discharge the plurality of capacitors with a discharge current conducted through the common terminal; a comparator having a first input terminal coupled to the common terminal; A circuit comprising: [C27] further comprising a first switch coupled between the first current source and the common terminal, the first switch configured to close in response to a timing signal. The circuit described in C26. [C28] at least one resistor; a second current source configured to drive a reference current through the at least one resistor to generate a reference voltage; The circuit of C26, further comprising: [C29] a switched-capacitor voltage-to-current converter configured to convert the reference voltage into a first current, wherein the first current source comprises a current mirror configured to mirror the first current to become the discharge current. Circuit described in C28. [C30] The circuit of C29, wherein the at least one resistor comprises a voltage divider having a voltage divider node for a digital-to-analog (DAC) reference voltage for the capacitive digital-to-analog converter.

Claims

1. 1. A method for operating a digital-to-time converter, comprising: charging an array of capacitors in a capacitive digital-to-analog converter (CDAC) in response to a digital code to form an array of charged capacitors, wherein the digital code corresponds to one of different values ​​for the initial voltage; converting a reference voltage to a first current in a switched capacitor voltage-to-current converter; mirroring the first current in a current mirror to form a charging current, wherein the current mirror mirrors the first current such that the charging current is equal to a proportionality constant K times the first current; further charging the array of charged capacitors with the charging current via the common terminal in response to a timing signal to form an increased voltage for a common terminal; wherein the array of charged capacitors is further charged so that the increased voltage is equal to a trip voltage. Equipped with Charging the array of capacitors in the capacitive digital-to-analog converter (CDAC) to form the array of charged capacitors includes: in a first step, charging the subset of capacitors in the array of capacitors to a DAC reference voltage to provide charge to the subset of capacitors, wherein the subset of capacitors is selected based on the digital code; in a second step, redistributing the charge from the subset of capacitors to all of the capacitors in the array of capacitors to form the array of charged capacitors such that the common terminal is charged to the initial voltage corresponding to the digital code; Equipped with the initial voltage is a fractional multiple of the DAC reference voltage, and the capacitors of the charged capacitor array are connected in parallel to the common terminal; method.

2. The time delay of the digital-to-time converter is equal to the delay from a triggering edge of the timing signal to when the increasing voltage equals the trip voltage. The method of claim 1 further comprising:

3. generating a reference current; driving the reference current through at least one resistor to form the reference voltage; The method of claim 1 further comprising:

4. generating the trip voltage from the reference current. The method of claim 3.

5. 10. The method of claim 1, further comprising isolating the array of capacitors from the constant voltage source during the charge redistribution by opening one or more switches coupled between the array of capacitors and the constant voltage source.

6. further comprising closing a switch in response to the timing signal to couple a current source configured to provide the charging current to the common terminal. The method of claim 1.

7. a voltage-to-current switched capacitor converter configured to convert a reference voltage into a first current; a capacitive digital-to-analog converter (CDAC) including an array of capacitors to form charge capacitors, wherein the capacitive digital-to-analog converter is configured to charge the array of capacitors in response to a digital code to form the charge capacitors, the digital code corresponding to one of different values ​​for an initial voltage; a current mirror configured to mirror the first current to become a charging current for further charging the charging capacitor, wherein the current mirror mirrors the first current such that the charging current is equal to a proportionality constant K times the first current; a switch configured to close in response to a timing signal to couple the current mirror to the charging capacitor; a comparator having a first input terminal coupled to the charging capacitor and a second input terminal configured to receive a trip voltage, the charging capacitor being charged to the trip voltage with the charging current in response to the timing signal; Equipped with Charging the array of capacitors comprises: in a first step, charging the subset of capacitors in the array of capacitors to a DAC reference voltage to provide charge to the subset of capacitors, wherein the subset of capacitors is selected based on the digital code; in a second step, redistributing the charge from the subset of capacitors to all of the capacitors in the array of capacitors to form the charging capacitors such that the common terminal is charged to the initial voltage corresponding to the digital code; Equipped with the initial voltage is a fractional multiple of the DAC reference voltage, and the capacitors of the charged capacitor array are connected in parallel to the common terminal; circuit.

8. The circuit of claim 7 , wherein the circuit is included within a cellular telephone.

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