Apparatus and method for changing stored data

Abstract

The requesting master processing device (205) has an associated private cache store (215) that stores data for access by the requesting master processing device. The requesting master processing device is configured to issue requests to modify data associated with a given memory address and stored in a private cache store (220) associated with the receiving master processing device (210). The private cache store associated with the receiving master processing device is configured to store the data for access by the receiving master processing device. The receiving master processing device and one of its associated private cache stores are configured to perform the requested modification of the data while the data is stored in the cache store associated with the receiving master processing device.

Description

[Technical Field]

[0001] The present technology relates to the field of processing devices, and more particularly to processing data modification requests in a system comprising a plurality of such processing devices.

[0002] Some data processing systems, such as multi-core processors, include multiple processing devices, such as processing cores, that may be implemented within the same chip. Such multiple processing devices can operate in parallel, thereby improving processing performance.

[0003] In at least some embodiments, a requesting master processing device having an associated private cache store that stores data for access by the requesting master processing device, the requesting master processing device being configured to issue a request that modifies data associated with a given memory address and stored in the private cache store associated with the receiving master processing device, the private cache store associated with the receiving master processing device being configured to store the data for access by the receiving master processing device; and a receiving master processing device having a private cache store, wherein the receiving master processing device and one of its associated private cache stores are configured to perform requested modifications of data while the data is stored in a cache store associated with the receiving master processing device.

[0004] Further embodiments include: a receiving circuit for receiving a request from a requesting master processing device to modify data associated with a given memory address; and a forwarding circuit that forwards a request to a private cache storage associated with the receiving master processing device to perform the requested modification to the data while the data is stored in a unique coherency state in the private cache storage associated with the receiving master processing device.

[0005] Further embodiments include: a receiving master processing device; a private cache store for storing data for access by a receiving master processing device, a private cache storage configured to receive a forwarded request from a home node device to modify data associated with a given memory address, the forwarded request originating from a request master processing device; An apparatus is provided in which one of the receiving master processing device and the private cache store is configured to perform a requested modification of data in the cache store when the data is stored in the private cache store in a unique coherency state.

[0006] A further embodiment provides a method in a home node device, the method comprising: receiving a request from a requesting master processing device to modify data associated with a given memory address; and forwarding a request to a private cache storage associated with the receiving master processing device to perform the requested modification to the data while the data is stored in a unique coherency state in the private cache storage associated with the receiving master processing device.

[0007] Further aspects, features, and advantages of the present technology will become apparent from the following description of examples, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows a schematic diagram of a comparative processing system; [Figure 2] 1 illustrates a schematic diagram of a processing system according to an embodiment of the present disclosure. [Figure 3] FIG. 1 is a flow diagram of a method according to an embodiment of the present disclosure. [Figure 4] FIG. 10 is a flow diagram illustrating a method in a home node device according to an embodiment of the present disclosure.

[0009] As described above, some data processing systems include multiple processing devices operating in parallel. In some such systems, each such processing device has an associated private cache store that stores data for access by that processing device. The latency associated with accessing data in the private cache is typically lower than the latency associated with accessing data stored in other storage devices, such as a shared cache accessible to all processing devices and / or main memory. Thus, a given processing device can fetch required data into its private cache and perform processing operations on the data while it is stored in the private cache, thereby experiencing lower latency than if the data were maintained in shared store during the execution of the processing operations.

[0010] However, while the use of private caches provides performance improvements, problems arise when data stored in a first processing device's private cache is modified by a second processing device. When the first device relinquishes control of the data and makes it available by providing it to shared storage or the second device's private cache, the data is no longer immediately available to the first device. This results in higher latency if the first device subsequently modifies the data again. Furthermore, this can result in an inefficient "ping-pong" effect, where data is constantly passed between the caches of the first and second devices.

[0011] Additionally, a performance penalty arises both from waiting for the first device to relinquish control of the data and from waiting for the data to become available in a private cache of the shared store or the second store. This effect is magnified when the data is modified at least intermittently by both the first and second processing devices, and whenever control of the data changes, it must either be passed between private caches (resulting in the aforementioned "ping-pong" performance inefficiencies as a result of the time required to transfer the data between caches) or must be maintained in the shared cache (preventing use of the private cache, thereby not providing its attendant benefits).

[0012] One embodiment of the present disclosure addresses this with an apparatus comprising a requesting master processing device and a receiving master processing device, each having an associated private cache configured to store data for access by the corresponding master processing device. "Requesting" and "receiving" are labels for specific functions described herein, and both devices may generally be specific devices of a set of similar devices, such that any pair of devices can assume the roles of "requesting" and "receiving" at a given time.

[0013] The requesting master processing device is configured to issue a request to modify data associated with a given memory address and stored in a private cache storage of a receiving master processing device. The request may be issued specifically to the private cache storage of the receiving master processing device. Alternatively, the request may be broadcast and then detected by the receiving master processing device. In an embodiment, the requested modification is one that can be performed without caching the data in the private cache storage associated with the requesting master device.

[0014] The receiving master processing device and one of its associated private cache stores are configured to perform the requested modification of the data while the data is stored in the cache store associated with the receiving master processing device.

[0015] In comparative systems that do not implement aspects of the present disclosure, requested modifications are performed either by providing the target data to a private cache of the requesting device in which the modifications are performed, or by providing the target data to a shared location, such as a shared cache or main memory, in which the modifications are performed. This data movement can be relatively time-consuming, especially when the on-chip network is congested. This data movement also increases power requirements. The apparatus described herein avoids the need for this time-consuming data movement by allowing the requested modifications to be performed without providing the target data to a private cache or shared memory of the requesting master processing device.

[0016] Some systems provide for data to be stored in different coherency states. For example, a given data item may be stored in a device's private cache in a unique coherency state, where the device can modify the data locally without notifying its home node or other devices that may cache data from the same address. Alternatively, a given data item may be stored in a private cache in a shared coherency state, where changes to the data in the private cache are signaled to other devices that may cache data from the same address, allowing the other devices to invalidate now-outdated versions of the data as needed. The coherency state may be managed by an additional device communicatively coupled to the master processing device. Providing coherency states in this manner enables data coherency to be maintained when access to the data is shared among devices.

[0017] In a comparative system that implements such coherency states, if the data to be modified is in exclusive coherency state in the private cache of the receiving device, the unique state must be relinquished to perform the modification requested by the requesting device. The data must then be moved to the private cache of the requesting device or to a shared location. As noted above, such a move can take time and increase power requirements.

[0018] In one embodiment of the present disclosure, the receiving master processing device and one of its associated private cache stores are configured to perform the requested modification of the data while the data is stored in a unique coherency state in the cache store associated with the receiving master processing device. Thus, the modification can be performed without the receiving device having to relinquish the exclusive coherency state so that the data can remain in the private cache of the receiving device, thereby improving performance, for example, the next time the receiving device accesses the data.

[0019] In one embodiment, the request is a request to perform an atomic update operation that includes the requested changes. An atomic update is an indivisible set of actions, such as a read followed by a write, where the data to be written and / or whether the write occurs depends on the read data, performed as a single, uninterrupted operation. By way of example, the atomic operation may include a comparison and / or arithmetic operation on the read value, based on which the value to be written is determined. While the atomic update is being performed, other accesses to the target data are prevented as a result of performing the read and write as a single operation. Performing these actions based on a single request can provide performance improvements over systems where multiple requests must be used and / or where the actions are performed in a central location in a private cache of the receiving device.

[0020] In this example, the private cache storage associated with the receiving master processing device may include an arithmetic logic unit that performs the requested atomic operation. Thus, the operation may be performed entirely within the private cache of the receiving device, as opposed to being performed by the receiving device itself, thereby improving processing efficiency. Alternatively, the receiving device itself (as opposed to its associated private cache) may include an arithmetic logic unit that performs the requested atomic operation. For example, an arithmetic unit within the receiving device's own data path or processing pipeline may be used to perform the arithmetic operations used in the atomic operation to calculate the value to be written.

[0021] In an alternative embodiment, the request is a request to perform a non-transitory store operation that includes the requested changes. The non-transitory store operation is a store instruction that includes a "hint" that the subject data will not be needed again by the requesting device in the near future. Performance degradation caused by invalidating copies of data in the private caches of receiving devices is avoided in this technique, in which such invalidation is not performed.

[0022] In some embodiments, the apparatus comprises a home node device. The home node device is configured to receive a request from a requested master processing device and forward the request to a private cache storage associated with the receiving master processing device. Thus, control of data access (e.g., maintaining cache coherency) can be managed by a central home node device. The requesting device can therefore issue a request to the home node device without any need to specifically identify the receiving device. Thus, the requesting device does not need to maintain a record of which other device actually stores the given data. For example, the home node device may be configured to perform the forwarding in response to determining that the data is stored in a unique coherency state in a private cache storage associated with the receiving master processing device.

[0023] The apparatus may include a shared cache associated with the home node device for storing data for access by the requesting master processing device and the receiving master processing device. Thus, in addition to allowing modifications to be performed in the receiving cache, the system may also allow modifications to be performed in the shared cache.

[0024] Alternatively or additionally, the private cache storage associated with the receiving master may be configured to determine, based on information associated with the request, whether to provide the data to the home node device and transition the data to a non-unique coherency state. Upon determining to provide the data to the home node device, the private cache storage associated with the receiving master processing device may be configured to refrain from performing the requested modifications in the private cache storage. The requested modifications may then be performed in the shared cache described above.

[0025] Alternatively, a private cache store associated with the receiving master processing device may be configured to perform the determination after making the requested modification.

[0026] Similarly, the home node device may be configured to determine, based on information related to the request, whether to trigger execution of the requested changes in the private cache storage of the receiving master processing device or in a shared storage location, such as the aforementioned shared cache shared between the requesting master processing device and the receiving storage device.

[0027] These determinations allow data to be provided to a shared store, such as a shared cache, in situations where it is generally advantageous to do so, even if the receiving processing device still requires access to the data.

[0028] Illustratively, to perform a change in the private cache of a receiving device, a request is sent from the requesting device to the home node and from there to the receiving device, the change is then performed, and then a response is sent from the receiving device to the requesting device. From the receiving device's perspective, this approach is more efficient because it means that the data can be kept in a unique coherency state at the receiving device even if the data is modified as requested by the requesting device.

[0029] Conversely, in this implementation, when a change is made in shared storage (which would be possible if the data were not stored in a unique coherency state in the private cache of the receiving device), a request is sent from the requesting device to the home node, the change is then made, and then a response is sent to the requesting device. Thus, fewer transmissions are made than if the change were made in the private cache of the receiving device, and therefore there is a shorter time delay (from the perspective of the requesting device) between the requesting device issuing the request and receiving the response.

[0030] Thus, there may be a trade-off between performing the modifications in the private cache of the receiving device (which is better for overall performance if the receiving device is more likely to need the data again than the requesting device or other processing devices in the system) and performing the modifications in shared storage (which is better for overall performance if the requesting device or other processing devices are more likely to need the data than the receiving device). In the following examples, information about the potential use of the data by the receiving device and other processing devices may be used to determine whether it is preferable for the receiving device to perform the requested modifications locally, or whether to relinquish control and allow the modifications to be performed in a shared location.

[0031] The determination of where to perform a given requested modification may be performed in various ways. For example, the request-related information on which the determination is based may include a count of the number of modification requests received from the home node device for the data. The counter may be a single bit, such that data is returned to the shared cache after a single request is received from a different processing device to modify that data. Alternatively, a multi-bit counter may be used to track the number of modification requests. When the number of modification requests specifying the same address reaches a threshold (e.g., 1 for a 1-bit counter), the modification request may trigger the recipient to relinquish a unique coherency state (if necessary) and provide control to the shared location or the requesting device's cache to perform the modification.

[0032] Alternatively or additionally, the information related to the request may include the occupancy of a queue of pending requests for data modifications received from the home node device. Similar to a counter of received requests, a queue occupancy above a threshold may indicate that the request would be more efficiently served by returning the subject data to the shared cache.

[0033] Alternatively or additionally, the information associated with the request may include cache replacement policy information, such as recency of accesses to the subject data item. For example, if the data item was recently accessed by the receiving device, the data item may be maintained in the receiving device's private cache storage. Conversely, if the data item was not recently accessed by the receiving device, the data item may be returned to the shared cache or provided to the requesting device's cache. This takes advantage of the fact that data recently accessed by the receiving device may be more likely to be needed again by the receiving device in the near future, and as a result, may be an indication that overall system performance may be better if the receiving device can perform the requested changes locally and maintain a unique coherency state, even if this results in slower servicing of the change request from the requesting device's perspective.

[0034] In another embodiment, if neither the requesting device nor the receiving device is expected to use the data item in the near future, the data item may be returned to the sharing device.

[0035] In an embodiment, the private cache storage associated with the receiving master processing device comprises a first level cache and a second level cache, such that lower access latency is associated with the first level cache rather than the second level cache. The aforementioned information associated with the request may then include an indication of whether the data is in the first level cache or the second level cache. For example, when the data is in the first level cache, it may be assumed that the data is likely to be needed again by the receiving device, and the requested modifications may be performed in the private cache of the receiving device. Conversely, when the data is in the second level cache, it may be assumed that the data is less likely to be needed again by the receiving device (e.g., by being evicted from the first level cache), and therefore the performance gain for the requesting device associated with performing the modifications (and similar future modification requests) in the shared cache exceeds the performance gain at the receiving device associated with performing the modifications in its private cache. Therefore, the data may be returned to the shared cache.

[0036] In one embodiment, the receiving master processing device is configured to buffer an invalidation request to execute after the request is executed if a cache line containing the data is invalidated while the request is pending. If such invalidation is accepted immediately, in some embodiments the data is placed in an intermediate coherence state indicating that it is being updated and invalidated; A failure notification is issued to the home node regarding this request. The failed request can then be handled appropriately, for example, by implementing the changes in the shared cache or by forwarding the failure notification to the requesting device.

[0037] In another embodiment, no failure notification is issued, and instead the invalidation is buffered until the request is fulfilled. Alternatively, the receiving device can use the invalidation to determine that the data item should be returned to the shared cache to fulfill the request.

[0038] In one embodiment, the private cache storage associated with the receiving master device is configured to, after performing the requested modification, update replacement policy information associated with the cache line containing the modified data to increase the probability that the cache line will be selected for eviction in future cache evictions. Updating the replacement policy may include designating the cache line as a least recently used cache line. Subsequent cache misses can then evict the data from the cache, thereby returning the data to the shared cache if it is not frequently needed by the receiving device.

[0039] In one embodiment, a private cache store associated with the receiving master processing device is configured to provide a return value in response to the request to at least one of the requesting master processing device and the home node device. When sent to the home node device, the home node device may forward the return value to the requesting master processing device and / or mark the corresponding cache line as not dirty. The requested modification may be part of an operation, such as an atomic operation, that requires a return value. The return value may be a size smaller than the cache line size of the private cache store. By sending Thus, bandwidth is reduced relative to a comparable system in which a cache line containing data is provided to a device requesting access to the data.

[0040] Embodiments of the present disclosure will now be described with reference to the drawings.

[0041] 1 illustrates a schematic diagram of a comparative processing system 100 that does not implement the above-described embodiments of the present disclosure. The system 100 includes a requesting master processing device 105 and a receiving master processing device 110. The system 100 may be, for example, a multi-core processor, with the devices 105, 110 being processing cores. Each device 105, 110 has an associated private cache store 115, 120. The private cache is a multi-level cache having a first level cache L1 and a second level cache L2.

[0042] The system 100 further includes a home node device 125 that communicates with the devices 105, 110 and their associated private caches 115, 120 via an interface 130, such as an on-chip network interface. The home node device 125 has an associated shared cache 135. Data may be retrieved from a main memory 140 and cached in the shared cache 135 for access by the requesting device 105 and the receiving device 110.

[0043] As described above, if only one of the devices 105, 110 needs to access cached data for a particular address, that device 105, 110 can reduce overhead by granting exclusive access to the data and storing a copy of the data in its private cache 115, 120. When data is cached in exclusive coherency, changes to the data by that device do not need to be communicated to the home node or other devices until the data is evicted from that device's private cache. In contrast, when data is cached in shared coherency, changes by one device 105, 110 are signaled to the home node device 125, which may trigger other devices that cache the same data to invalidate any (now stale) local copies of data from the same address.

[0044] We now describe an operational flow whereby a requesting device 105 can request that an operation be performed on data to which a receiving device 110 has been granted exclusive access, and which data is stored in its private cache 120.

[0045] The requesting device 105 issues a request for the operation to its private cache 115. If it is determined that the data is not present in its private cache 115, the request is forwarded to the home node device 125 via the interface 130.

[0046] At the home node device, it is determined that the data is stored in the private cache 120 of the receiving device 110 (alternatively, if the home node does not keep track of which caches store which addresses, the home node can simply broadcast an invalidation request to all other devices that can cache data from the requested address). The invalidation request for the data is issued from the home node device 125 to the private cache 120 of the receiving device 110. The cache line containing the data is then invalidated in the private cache 120 and (if dirty) written back to the shared cache 135.

[0047] The requested operation is then performed by the arithmetic logic unit 145 of the home node device 125 on the data in the shared cache 135. Finally, a return value of the operation is sent to the requesting device 105. Alternatively, the data may be sent to the private cache 115 of the requesting device 105 for the requesting device 105 to perform the operation.

[0048] As mentioned above, the described operational flows within system 100 incur performance penalties by invalidating data and writing it back from the private cache 120 of the receiving device 110 before the operations can be performed. These penalties are exacerbated in situations where the receiving device 110 later needs access to the data, and as a result, the data must be returned to its private cache 120 or must remain in the shared cache 135 (thereby increasing access latency for the receiving master device 110 if the same data is needed again). As mentioned above, this can cause an inefficient "ping-pong" effect in which data is passed back and forth between the private cache 120 of the requesting device 105 and the private cache 120 of the receiving device 110.

[0049] FIG. 2 illustrates a schematic diagram of an exemplary system 200 according to an embodiment of the present disclosure in which the above-mentioned performance penalty is mitigated.

[0050] System 200 comprises a requesting master processing device 205, a receiving master processing device 210, their associated private caches 215, 220, a home node device 225 associated with a shared cache 235, an interface 230, and a main memory 240, each of which operates in a manner similar to the like-named components of system 100 described above, except as noted below.

[0051] We now describe an operational flow whereby a requesting device 205 can request that an operation be performed on data to which a receiving device 210 has been granted exclusive access, and which data is stored in its private cache 220. As can be seen, this flow mitigates the performance penalty mentioned above associated with system 100.

[0052] For an operation, the requesting device 205 issues a request to its private cache 215. If it is determined that the data of interest is not stored in the private cache 215, the request is forwarded to the home node device 225 via interface 230, as described above in connection with FIG.

[0053] The home node device determines that the data is stored in the receiving device's private cache 220. The request is then forwarded to that private cache 220 where the requested operation is performed by the arithmetic logic unit 245 of the private cache 220. The forwarding function may be implemented through the use of a network-on-chip or an interconnect communication protocol configured to support such forwarding. The return value of the operation is then returned to the requesting device 205 via interface 230.

[0054] As described above, system 200 allows operations to be requested by a requesting master processing device on data stored in the private cache of the receiving master processing device and then executed in the private cache of the receiving master processing device, thereby mitigating the aforementioned performance penalty associated with invalidating and writing back target data in system 100. Specifically, the aforementioned "ping-pong" inefficiency is avoided. The configuration described herein is particularly efficient in situations where the requesting master device 205 requires intermittent access to data and the receiving master device 210 requires more frequent access to data.

[0055] Furthermore, the home node device 225 only needs to forward the request and does not need to perform the requested operation or process the return value, thereby improving the performance of the home node device 225. This approach is unique when, as always, data is cached in a unique coherency state in the private cache 220 of a particular master device 210, and the only device permitted to modify that data is the master device 210 itself. However, in this operational flow shown in FIG. 2, the requesting master device 205 can trigger a modification of the data while the data remains in a unique coherency state in the receiving master device 210. This approach can be useful not only for atomic requests, but also for non-transient store operations, or other operations in which the requesting master device 205 requests a modification of data associated with a particular address, but does not require the data to be returned to its own private cache 215.

[0056] FIG. 3 is a flow diagram illustrating a method according to an embodiment of the present disclosure.

[0057] In block 305, a request to modify the data is sent from the requesting device to its private cache.

[0058] In block 310, it is determined whether there is a cache hit in the private cache for the data, and if so, whether the data has a unique coherency state. As described above, a unique coherency state is a coherency state that allows a device holding the cached data to locally modify the data without notifying the home node or other devices in the system that may potentially hold cached data for the same address. If there is a cache hit and the data has a unique coherency state, the requested modification is performed in the private cache in block 315.

[0059] If not, flow proceeds to block 320 where the request is forwarded to the home node device.

[0060] At block 325, it is determined whether the data is stored in a unique coherency state in a private cache associated with the receiving device. If not, flow proceeds to block 330 where the requested changes are made to the data in the shared cache associated with the home node device.

[0061] If not, flow continues to block 335 where the request is forwarded to the receiving device.

[0062] At block 340, a determination is made whether to implement the changes at the receiving device or return the data to a central location, such as the home node described above. As noted above, this determination may be based on various factors, such as the value of a counter of received requests and / or the occupancy of a request queue.

[0063] If it is determined that the request should be fulfilled at the central location, flow proceeds to block 345 where the data is returned to the central location.

[0064] If it is determined that the changes should be made at the receiving device, flow proceeds to block 350 where the requested changes are made in the private cache of the receiving device.

[0065] 4 is a flow diagram illustrating a method in a home node device according to an embodiment of the present disclosure. As described above, the home node device is communicatively coupled to various master processing devices.

[0066] At block 405, a request to modify data is received that was forwarded from a requesting master processing device.

[0067] At block 420, information associated with the request is determined. The information may include one or more of a count of the number of modification requests received for the data, the occupancy of a queue of pending requests to modify the data, and cache replacement policy information, such as the recency of accesses to the data item of interest.

[0068] At block 425, a determination is made based on the aforementioned information associated with the request to execute the request in the shared cache or in the private cache in which the data is stored. For example, as described above, the determination to execute the request in the shared cache may be responsive to a count of received requests exceeding a threshold. The determination may alternatively or additionally be responsive to the occupancy of a queue of pending requests exceeding a threshold. The determination may be responsive to a last access of the target data being out of date. The determination may be responsive to a particular cache level in which the data is stored, e.g., a first level cache or a second level cache.

[0069] If it is determined that the request should be executed in the shared cache, flow proceeds to block 430, where the data is brought to the shared cache, including, for example, invalidating the data in any private caches in which the data was stored. The request is then executed in the shared cache.

[0070] If it is determined that the request should be executed in the private cache, flow proceeds to block 435, where the request is forwarded for execution in the private cache. For example, the request may be unicast to the private cache. Alternatively, the request may be broadcast to the private caches of all master processing devices and ignored by all devices except the device where the data is stored.

[0071] In this application, the term "configured to" is used to mean that an element of an apparatus has a configuration that allows it to perform a defined operation. In this context, "configuration" refers to an arrangement or method of interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element must be modified in any way to provide the defined operation.

[0072] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. 1. An apparatus comprising: a requesting master processing device having an associated private cache store that stores data for access by the requesting master processing device, the requesting master processing device being configured to issue a request that modifies data associated with a given memory address and stored in a private cache store associated with a receiving master processing device, the private cache store associated with the receiving master processing device being configured to store data for access by the receiving master processing device; a receiving master processing device having the private cache store of the receiving master processing device, the receiving master processing device and one of the receiving master processing device's associated private cache store configured to perform the requested modification of the data while the data is stored in the private cache store associated with the receiving master processing device; a home node device that receives the request from the requesting master processing device and forwards the request to the private cache storage associated with the receiving master processing device; the private cache storage associated with the receiving master processing device is configured to provide the data to the home node device based on information associated with the request.

2. 2. The apparatus of claim 1, wherein the one of the receiving master processing device and the private cache store associated with the receiving master processing device is configured to perform the requested modification of the data while the data is stored in a unique coherency state in the private cache store associated with the receiving master processing device.

3. 3. The apparatus of claim 1, wherein the requested modification is a modification that can be performed without caching the data in the private cache store associated with the requesting master processing device.

4. The apparatus of any one of claims 1 to 3, wherein the request is a request to perform an atomic update operation that includes the requested changes.

5. 5. The apparatus of claim 4, wherein the private cache store associated with the receiving master processing device comprises an arithmetic logic unit that performs the atomic update operation.

6. The apparatus of any one of claims 1 to 3, wherein the request is a request to perform a non-transitory storage operation that includes the requested modification.

7. The apparatus of any preceding claim, comprising a shared cache associated with the home node device that stores data for access by the requesting master processing device and the receiving master processing device.

8. 2. The apparatus of claim 1, wherein, upon determining to provide the data to the home node device, the private cache storage associated with the receiving master processing device is configured to inhibit performing the requested modification in the private cache storage.

9. The apparatus of any preceding claim, wherein the private cache associated with the receiving master processing device is configured to perform the determination after performing the requested modification.

10. 10. The apparatus of claim 1, wherein the home node device is configured to determine, based on information related to the request, whether to trigger execution of the requested changes in the private cache storage of the receiving master processing device or in a shared storage location shared between the requesting master processing device and the receiving master processing device.

11. the information relating to the request is: a count of the number of change requests received from the home node device regarding the data; the occupancy of a queue of pending requests for data modifications received from the home node device; and and cache replacement policy information.

12. the private cache storage associated with the receiving master processing device includes a first level cache and a second level cache; 12. The apparatus of claim 10 or 11, wherein the information associated with the request includes an indication of whether the data is in the first level cache or the second level cache.

13. the home node device: determining that the data is stored in a unique coherency state in the private cache storage associated with the receiving master processing device; The device according to any one of claims 1 to 12, configured to perform said forwarding in response to a determination.

14. 14. The apparatus of claim 1, wherein the private cache store associated with the receiving master processing device is configured to, after performing the requested modification, update replacement policy information associated with a cache line containing the modified data to increase the probability that the cache line will be selected for eviction in a future cache eviction.

15. 15. The apparatus of claim 14, wherein said updating said replacement policy information comprises designating said cache line as a least recently used cache line.

16. 16. The apparatus of claim 1, wherein the private cache storage associated with the receiving master processing device is configured to provide a return value in response to the request to at least one of the requesting master processing device and a home node device.

17. 17. The apparatus of claim 16, wherein the private cache store associated with the receiving master processing device is configured to provide the return value in a transmission of a size smaller than a cache line size of the private cache store.

18. 1. An apparatus comprising: a receiving master processing device; a private cache store for storing data for access by the receiving master processing device; a private cache storage configured to receive a forwarded request from a home node device to modify data associated with a given memory address, the forwarded request originating from a request master processing device; When the data is stored in the private cache store in a unique coherency state, one of the receiving master processing device and the private cache store is configured to perform the requested modification of the data in the private cache store, and the private cache store provides the data to the home node device based on information associated with the forwarded request.

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