Display device and manufacturing method thereof

Abstract

To provide a display device with improved reliability.SOLUTION: A display device is provided, comprising: a substrate having a display area and a pad area located on one side of the display area; a pad electrode disposed in the pad area on the substrate; a protective insulating layer disposed on the substrate and the pad electrode to expose at least a part of a top surface of the pad electrode; an inorganic encapsulation layer disposed on the protective insulating layer; and a conductive layer disposed in the pad area between an end of the inorganic encapsulation layer adjacent to the pad electrode and the protective insulating layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device including a pad electrode and a manufacturing method thereof. [Background technology]

[0002] Flat panel displays are being used as a replacement for cathode ray tube displays due to their light weight and thinness, etc. Representative examples of such flat panel displays include liquid crystal displays (LCDs) and organic light emitting display (OLED) displays.

[0003] The display device includes a display region where pixel structures are disposed and a pad region where pad electrodes are disposed. An encapsulation layer is disposed on the pixel structures to protect the pixel structures. The pad electrodes are electrically connected to an external device that generates image signals to be provided to the pixel structures. In order to deposit the encapsulation layer so as not to overlap with the pad electrodes, a deposition process using a mask structure is required, which increases process costs. Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide a display device with improved reliability.

[0005] Another object of the present invention is to provide a method for manufacturing a display device with reduced process costs.

[0006] However, the present invention is not limited to the above-mentioned objects, and can be variously expanded within the scope of the present invention. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object of the present invention, a display device according to an exemplary embodiment of the present invention includes a substrate having a display area and a pad area located on one side of the display area, a pad electrode arranged in the pad area on the substrate, a protective insulating layer arranged on the substrate and the pad electrode and exposing at least a portion of the upper surface of the pad electrode, an inorganic sealing layer arranged on the protective insulating layer, and a conductive layer arranged in the pad area between an end of the inorganic sealing layer adjacent to the pad electrode and the protective insulating layer.

[0008] In one embodiment, the inorganic sealing layer and the conductive layer are each spaced apart from at least a portion of the pad electrode on a plane.

[0009] In one embodiment, the conductive layer has an undercut shape relative to the edge of the inorganic sealing layer.

[0010] In one embodiment, the conductive layer has a first etching rate for a first etching step, and the inorganic sealing layer has a second etching rate for the first etching step that is higher than the first etching rate.

[0011] In one embodiment, the first etching step is a dry etching step.

[0012] In one embodiment, the conductive layer has a third etching rate for the second etching process, and the pad electrode has a fourth etching rate for the second etching process that is lower than the third etching rate.

[0013] In one embodiment, the protective insulating layer has a fifth etching rate for the second etching step that is lower than the third etching rate, and the inorganic sealing layer has a sixth etching rate for the second etching step that is lower than the third etching rate.

[0014] In one embodiment, the second etching step is a wet etching step.

[0015] In one embodiment, the display device further includes a transistor disposed in the display region on the substrate, and a pixel electrode disposed on the transistor and electrically connected to the transistor. The conductive layer is disposed in the same layer as the pixel electrode.

[0016] In order to achieve another object of the present invention described above, a manufacturing method of a display device according to an exemplary embodiment of the present invention includes the steps of: preparing a substrate having a display area and a pad area located on one side of the display area; forming a pad electrode in the pad area on the substrate; forming a protective insulating layer on the substrate and the pad electrode; forming a contact hole in the protective insulating layer to expose at least a portion of the upper surface of the pad electrode; forming a conductive layer covering the contact hole in the pad electrode and the pad area on the protective insulating layer; forming an inorganic sealing layer on the protective insulating layer and the conductive layer; removing a portion of the inorganic sealing layer overlapping at least a portion of the pad electrode by a first etching process; and removing a portion of the conductive layer overlapping at least a portion of the pad electrode by a second etching process. [Effects of the Invention]

[0017] In a method for manufacturing a display device according to an exemplary embodiment of the present invention, a conductive layer is formed in a pad region on a pad electrode and a protective insulating layer. Then, an inorganic encapsulation layer is deposited over the entire display region and pad region without using a mask structure. A first etching process is then performed without using a mask structure to remove a portion of the inorganic encapsulation layer overlapping the pad electrode. The conductive layer is not etched during the first etching process, thereby preventing damage to the pad electrode during the first etching process. A second etching process is then performed without using a mask structure to remove a portion of the conductive layer overlapping the pad electrode. This reduces the number of mask structures used in the manufacturing process of the display device, thereby reducing process costs. Furthermore, damage to the pad electrode is prevented, thereby improving the reliability of the display device.

[0018] However, the effects of the present invention are not limited to the above-mentioned effects, and can be variously expanded within the scope of the present invention. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing an external device electrically connected to the display device of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line II' of the display device of FIG. [Figure 4] FIG. 4 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 5] FIG. 5 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 7] FIG. 7 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 8]FIG. 8 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings, in which the same or similar reference numerals are used to refer to the same components throughout the drawings.

[0021] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an external device electrically connected to the display device of FIG.

[0022] 1 and 2, the display device 10 (e.g., the substrate 110 in FIG. 3) includes a display area (DA) and a pad area (PA). Pixel structures (PX) are arranged in the display area (DA). For example, the pixel structures (PX) are arranged as a whole in the display area (DA) along a first direction (D1) and a second direction (D2) perpendicular to the first direction (D1).

[0023] Each pixel structure (PX) includes a light-emitting element that generates light and a transistor that drives the light-emitting element. For example, the light-emitting element includes an organic light-emitting diode. Also, the light-emitting element includes a nano-light-emitting diode. For example, the transistor is a thin film transistor (TFT). An image is displayed in the display area (DA) of the display device 10 by the pixel structure (PX) including the light-emitting element and the transistor.

[0024] In one embodiment, the pad area (PA) is located on at least one side of the display area (DA). For example, as shown in FIG. 1, the pad area (PA) is located in a first direction (D1) of the display area (DA). However, this is merely an example, and embodiments of the present invention are not limited thereto. For example, the pad area (PA) may be located in both the first direction (D1) and the second direction (D2) of the display area (DA).

[0025] The pad electrodes (PE) are arranged in the pad region (PA). For example, the pad electrodes (PE) are arranged along the second direction (D2). The pad electrodes (PE) are electrically connected to the external device 20. That is, the pad electrodes (PE) electrically connect the external device 20 and the pixel structure (PX).

[0026] The external device 20 is electrically connected to the display device 10 via a flexible printed circuit board or a printed circuit board. For example, one side of the flexible printed circuit board may be in direct contact with the pad electrode (PE), and the other side of the flexible printed circuit board may be in direct contact with the external device 20. The external device 20 provides data signals, gate signals, light emission control signals, gate initialization signals, initialization voltages, power supply voltages, etc. to the display device 10. In addition, a driving integrated circuit is mounted on the flexible printed circuit board. In another exemplary embodiment, the driving integrated circuit may be mounted on the display device 10 adjacent to the pad electrode (PE).

[0027] 1 shows an example in which the display area (DA) and the pad area (PA) each have a rectangular planar shape, but the embodiment of the present invention is not limited thereto. For example, the display area (DA) and the pad area (PA) each may have a triangular, rhombic, polygonal, circular, or elliptical planar shape.

[0028] 1 shows the width of the pad area (PA) in the second direction (D2) as being the same as the width of the display area (DA) in the second direction (D2), but the embodiment of the present invention is not limited thereto. For example, the width of the pad area (PA) in the second direction (D2) may be smaller than the width of the display area (DA) in the second direction (D2).

[0029] FIG. 3 is a cross-sectional view taken along line II' of the display device of FIG.

[0030] 3, a display device 10 according to an embodiment of the present invention includes a substrate 110, a gate insulating layer 120, an interlayer insulating layer 130, a transistor (TR), a pad electrode (PE), a protective insulating layer 140, a pixel defining film 150, a light emitting element 160, an encapsulating layer 170, and a conductive layer 180. The transistor (TR) includes an active layer (AL), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). The light emitting element 160 includes a pixel electrode 161, a light emitting layer 162, and a counter electrode 163. The encapsulating layer 170 includes a first inorganic encapsulating layer 171, an organic encapsulating layer 172, and a second inorganic encapsulating layer 173.

[0031] The substrate 110 has a display area (DA) and a pad area (PA). For example, the pad area (PA) is located on one side of the display area (DA). In one embodiment, the substrate 110 is a transparent insulating substrate. For example, the substrate 110 is made of glass, quartz, plastic, etc.

[0032] The active layer (AL) is disposed in the display region (DA) on the substrate 110. For example, the active layer (AL) may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The active layer (AL) includes a source region and a drain region doped with impurities, and a channel region disposed between the source region and the drain region. The source region and the drain region are doped with P-type or N-type impurities, and the channel region is doped with a different type of impurity than the impurities doped in the source region and the drain region.

[0033] In one embodiment, although not shown in the drawings, a buffer layer is disposed between the substrate 110 and the active layer (AL). That is, the active layer (AL) is disposed in the display area (DA) on the buffer layer. The buffer layer can prevent impurities from diffusing from the substrate 110 to the active layer (AL). In addition, the buffer layer can improve the flatness of the surface of the substrate 110 if the surface of the substrate 110 is uneven. The buffer layer can include an organic or inorganic material. For example, the buffer layer can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0034] The gate insulating layer 120 is disposed on the substrate 110. For example, the gate insulating layer 120 is disposed over the entire display area (DA) and pad area (PA) on the substrate 110. The gate insulating layer 120 disposed in the display area (DA) covers the active layer (AL) on the substrate 110. For example, the gate insulating layer 120 includes an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. Alternatively, the gate insulating layer 120 may have a multi-layer structure including multiple insulating layers made of different materials.

[0035] The gate electrode (GE) is disposed in the display area (DA) on the gate insulating layer 120. The gate electrode (GE) overlaps the channel region of the active layer (AL). The gate electrode (GE) includes a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, etc. For example, the gate electrode (GE) includes molybdenum (Mo), copper (Cu), etc. Optionally, the gate electrode (GE) may have a multi-layer structure including multiple conductive layers.

[0036] The interlayer insulating layer 130 is disposed on the gate insulating layer 120. For example, the interlayer insulating layer 130 is disposed over the entire display area (DA) and pad area (PA) on the gate insulating layer 120. The interlayer insulating layer 130 disposed in the display area (DA) covers the gate electrode (GE) on the gate insulating layer 120. For example, the interlayer insulating layer 130 includes an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. Alternatively, the interlayer insulating layer 130 may have a multi-layer structure including multiple insulating layers made of different materials.

[0037] The source electrode (SE) and the drain electrode (DE) are disposed in the display area (DA) on the interlayer insulating layer 130. The source electrode (SE) and the drain electrode (DE) are connected to the source region and the drain region of the active layer (AL), respectively. The source electrode (SE) and the drain electrode (DE) each include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, etc. For example, the source electrode (SE) and the drain electrode (DE) each include aluminum (AL), titanium (Ti), copper (Cu), etc., which may be used alone or in combination with each other. Optionally, the source electrode (SE) and the drain electrode (DE) each have a multi-layer structure including multiple conductive layers. For example, the source electrode (SE) and the drain electrode (DE) each have a multi-layer structure in which Ti, Al, and Ti are sequentially stacked. The active layer (AL), the gate electrode (GE), the source electrode (SE), and the drain electrode (DE) form a transistor (TR).

[0038] The pad electrode (PE) is disposed in a pad region (PA) on the interlayer insulating layer 130. That is, the pad electrode (PE) is disposed in the pad region (PA) on the substrate 110. In one embodiment, the pad electrode (PE) may be disposed in substantially the same layer as the source electrode (SE) and the drain electrode (DE). That is, the pad electrode (PE) may include the same material as the source electrode (SE) and the drain electrode (DE) and may be formed substantially simultaneously with the source electrode (SE) and the drain electrode (DE). The pad electrode (PE) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, etc. For example, the pad electrode (PE) may include Al, Ti, Cu, etc., which may be used alone or in combination with each other. Alternatively, the pad electrode (PE) may have a multi-layer structure including multiple conductive layers. For example, the pad electrode (PE) may have a multi-layer structure in which Ti, Al, and Ti are sequentially stacked.

[0039] The protective insulating layer 140 is disposed on the interlayer insulating layer 130. For example, the protective insulating layer 140 is disposed over the entire display area (DA) and pad area (PA) on the interlayer insulating layer 130. The protective insulating layer 140 protects the transistors (TR) and may provide a flat surface on the top of the transistors (TR). The protective insulating layer 140 may include an organic or inorganic material. For example, the protective insulating layer 140 may include an organic insulating material such as polyimide (PI). Alternatively, the protective insulating layer 140 may have a multi-layer structure including multiple insulating layers made of different materials.

[0040] For example, the protective insulating layer 140 arranged in the display area (DA) has a first contact hole 145 that exposes at least a portion of the upper surface of the drain electrode (DE). The pixel electrode 161 is electrically connected to the drain electrode (DE) through the first contact hole 145. For example, the protective insulating layer 140 arranged in the pad area (PA) has a second contact hole 147 that exposes at least a portion of the upper surface of the pad electrode (PE). That is, the protective insulating layer 140 arranged in the pad area (PA) on the substrate 110 and the pad electrode (PE) exposes at least a portion of the upper surface of the pad electrode (PE). The external device 20 is electrically connected to the pad electrode (PE) through the second contact hole 147.

[0041] The pixel electrode 161 is disposed in the display area (DA) on the protective insulating layer 140. The pixel electrode 161 is disposed on the transistor (TR) and electrically connected to the transistor (TR). For example, the pixel electrode 161 is electrically connected to the drain electrode (DE) through the first contact hole 145. The pixel electrode 161 may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, or the like. For example, the pixel electrode 161 may include silver (Ag), indium tin oxide (ITO), or the like. These may be used alone or in combination. Alternatively, the pixel electrode 161 may have a multi-layer structure including multiple conductive layers. For example, the pixel electrode 161 may have a multi-layer structure in which ITO, Ag, and ITO are sequentially stacked.

[0042] The conductive layer 180 is disposed in the pad area (PA) on the protective insulating layer 140. In an exemplary embodiment, as shown in FIGS. 10 and 11 , during the manufacturing process of the display device 10, a first etching process (e.g., a dry etching process using plasma) is performed to remove portions of the first and second inorganic sealing layers 171 and 173 overlapping the pad electrode (PE). After the first etching process, the conductive layer 180 covers the upper surface of the pad electrode (PE) exposed by the second contact hole 147 and a portion of the protective insulating layer 140 located in the pad area (PA). For example, a first etching rate of the conductive layer 180 during the first etching process is lower than a second etching rate of the first and second inorganic sealing layers 171 and 173 during the first etching process. That is, during the first etching process, the first and second inorganic sealing layers 171 and 173 are etched relatively more than the conductive layer 180. Therefore, the conductive layer 180 can prevent or reduce damage to the pad electrode (PE) and the protective insulating layer 140 due to the first etching process, as will be described in detail later.

[0043] In one embodiment, as shown in FIG. 3 , the conductive layer 180 is disposed in the pad area (PA) between the protective insulating layer 140 and an end of the sealing layer 170 adjacent to the pad electrode (PE). For example, the conductive layer 180 is disposed in the pad area (PA) between the side end of the first inorganic sealing layer 171 in the first direction (D1) and the protective insulating layer 140. For example, the conductive layer 180 does not directly contact the pad electrode (PE). For example, the conductive layer 180 is separated from at least a portion of the pad electrode (PE) on a plane. That is, the conductive layer 180 exposes all or a portion of the pad electrode (PE) on a plane. In other words, all or a portion of the pad electrode (PE) does not overlap the conductive layer 180 on a plane. 12 and 13, in the manufacturing process of the display device 10, after the first etching step is performed, a second etching step is performed to remove a portion of the conductive layer 180 overlapping the pad electrode (PE). The second etching step causes the conductive layer 180 to expose the upper surface of the pad electrode (PE) exposed by the second contact hole 147.

[0044] In one embodiment, the conductive layer 180 has an undercut (UC) shape with respect to the end of the sealing layer 170 adjacent to the pad electrode (PE). That is, the conductive layer 180 has an undercut (UC) shape with respect to the side ends of the first and second inorganic sealing layers 171 and 173 in the first direction (D1). For example, the second etching process is a wet etching process using an etching solution. Furthermore, a third etching rate of the conductive layer 180 in the second etching process is higher than a fourth etching rate of the pad electrode (PE) in the second etching process, a fifth etching rate of the protective insulating layer 140 in the second etching process, and a sixth etching rate of the first and second inorganic sealing layers 171 and 173 in the second etching process. Therefore, the pad electrode (PE), the protective insulating layer 140, and the first and second inorganic sealing layers 171 and 173 are hardly etched by the second etching process. Furthermore, the conductive layer 180 has an undercut (UC) shape with respect to the side edges in the first direction (D1) of the first and second inorganic sealing layers 171 and 173. This will be described in detail later.

[0045] In one embodiment, the conductive layer 180 is disposed in substantially the same layer as the pixel electrode 161. That is, the conductive layer 180 includes the same material as the pixel electrode 161 and is formed substantially simultaneously with the pixel electrode 161. The conductive layer 180 may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, or the like. For example, the conductive layer 180 may include Ag, ITO, or the like. These may be used alone or in combination with each other. Alternatively, the conductive layer 180 may have a multi-layer structure including multiple sub-layers. For example, the conductive layer 180 may have a multi-layer structure in which ITO, Ag, and ITO are sequentially stacked.

[0046] The pixel defining layer 150 is disposed in the display area (DA) on the protective insulating layer 140. The pixel defining layer 150 may partially cover the pixel electrode 161 on the protective insulating layer 140. The pixel defining layer 150 has a pixel opening that exposes at least a portion of the pixel electrode 161. For example, the pixel opening exposes a central portion of the pixel electrode 161, and the pixel defining layer 150 covers a peripheral portion of the pixel electrode 161. For example, the pixel defining layer 150 includes an organic insulating material such as polyimide (PI).

[0047] The light-emitting layer 162 is disposed on the pixel electrode 161 exposed by the pixel opening of the pixel defining film 150. That is, the light-emitting layer 162 is disposed within the pixel opening. The light-emitting layer 162 includes at least one of an organic light-emitting material and quantum dots.

[0048] The counter electrode 163 is disposed on the light-emitting layer 162 and overlaps the pixel electrode 161. In one embodiment, the counter electrode 163 is also disposed on the pixel defining layer 150. The counter electrode 163 may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, or the like. For example, the counter electrode 163 may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), or the like, which may be used alone or in combination with each other. The pixel electrode 161, the light-emitting layer 162, and the counter electrode 163 form a light-emitting element 160.

[0049] The sealing layer 170 is disposed on the counter electrode 163 and covers the light emitting element 160. The sealing layer 170 can seal the display area (DA) and protect the light emitting element 160 from external impurities.

[0050] The sealing layer 170 includes at least one inorganic sealing layer and at least one organic sealing layer. For example, as shown in FIG. 3 , the sealing layer 170 includes a first inorganic sealing layer 171, a second inorganic sealing layer 173 disposed on the first inorganic sealing layer 171, and an organic sealing layer 172 disposed between the first inorganic sealing layer 171 and the second inorganic sealing layer 173. However, this is merely an example, and the embodiments of the present invention are not limited thereto and may include various combinations.

[0051] The first inorganic sealing layer 171 is disposed on the counter electrode 163. For example, the first inorganic sealing layer 171 has a substantially uniform thickness due to the profile of the counter electrode 163.

[0052] The organic sealing layer 172 is disposed on the first inorganic sealing layer 171. The organic sealing layer 172 has a substantially flat upper surface without creating a step around the periphery of the first inorganic sealing layer 171.

[0053] The second inorganic sealing layer 173 is disposed on the organic sealing layer 172. That is, the first and second inorganic sealing layers 171, 173 are disposed on the protective insulating layer 140. The second inorganic sealing layer 173 has a substantially uniform thickness and a substantially flat upper surface.

[0054] In one embodiment, as shown in FIG. 3 , portions of the first and second inorganic sealing layers 171 and 173 extend into the pad region (PA). That is, the side ends of the first and second inorganic sealing layers 171 and 173 in the first direction (D1) are located in the pad region (PA). For example, the first and second inorganic sealing layers 171 and 173 do not directly contact the pad electrode (PE). For example, the first and second inorganic sealing layers 171 and 173 are separated from at least a portion of the pad electrode (PE) in a planar view. That is, the first and second inorganic sealing layers 171 and 173 expose all or a portion of the pad electrode (PE) in a planar view. In other words, all or a portion of the pad electrode (PE) does not overlap the first and second inorganic sealing layers 171 and 173 in a planar view. Therefore, a conductive member (for example, an anisotropic conductive film) is in direct contact with the upper surface of the pad electrode (PE) exposed by the second contact hole 147. The conductive member electrically connects the pad electrode (PE) and the external device 20.

[0055] 4 to 13 are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0056] As shown in Figure 4, a substrate 110 having a display area (DA) and a pad area (PA) is prepared. For example, the pad area (PA) is located on one side of the display area (DA). In one embodiment, the substrate 110 is a transparent insulating substrate. For example, the substrate 110 is made of glass, quartz, plastic, etc.

[0057] An active layer (AL) is formed in the display area (DA) on the substrate 110. For example, the active layer (AL) is formed using amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like. The active layer (AL) includes the source region, the drain region, and the channel region. The source region and the drain region are doped with P-type or N-type impurities, and the channel region is doped with impurities of a type different from the impurities doped in the source region and the drain region.

[0058] A gate insulating layer 120 is formed on the substrate 110 and the active layer (AL). For example, the gate insulating layer 120 is formed over the entire display area (DA) and pad area (PA) on the substrate 110. The gate insulating layer 120 formed in the display area (DA) covers the active layer (AL) on the substrate 110. For example, the gate insulating layer 120 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0059] A gate electrode (GE) is formed in the display area (DA) on the gate insulating layer 120. The gate electrode (GE) is formed so as to overlap the channel area of ​​the active layer (AL). For example, the gate electrode (GE) is formed using a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, or the like.

[0060] An interlayer insulating layer 130 is formed on the gate insulating layer 120 and the gate electrode (GE). For example, the interlayer insulating layer 130 is formed over the entire display area (DA) and pad area (PA) on the gate insulating layer 120. The interlayer insulating layer 130 formed in the display area (DA) covers the gate electrode (GE) on the gate insulating layer 120. For example, the interlayer insulating layer 130 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0061] 5, contact holes are formed in the gate insulating layer 120 and the interlayer insulating layer 130 so as to overlap the source region and the drain region of the active layer (AL), respectively. Furthermore, a source electrode (SE) and a drain electrode (DE) are formed on the interlayer insulating layer 130 so as to overlap the contact holes, respectively. The source electrode (SE) and the drain electrode (DE) are connected to the source region and the drain region of the active layer (AL), respectively, through the contact holes. The active layer (AL), the gate electrode (GE), the source electrode (SE), and the drain electrode (DE) form a transistor (TR).

[0062] A pad electrode (PE) is formed in the pad region (PA) on the interlayer insulating layer 130. That is, the pad electrode (PE) is formed in the pad region (PA) on the substrate 110. The pad electrode (PE) is formed using a material having an etching rate lower than that of the conductive layer 180 in the second etching process (e.g., a wet etching process using an etchant). That is, in the second etching process shown in FIGS. 12 and 13, the conductive layer 180 is etched relatively more than the pad electrode (PE). In an exemplary embodiment, the pad electrode (PE) is formed to have a multi-layer structure including multiple conductive layers. In this case, the uppermost layer of the conductive layers is formed using a material having an etching rate lower than that of the conductive layer 180 in the second etching process. Alternatively, each of the conductive layers may be formed using a material having an etching rate lower than that of the conductive layer 180 in the second etching process.

[0063] In one embodiment, each of the source electrode (SE), drain electrode (DE), and pad electrode (PE) is formed using a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, or the like. For example, each of the source electrode (SE), drain electrode (DE), and pad electrode (PE) is formed using Al, Ti, Cu, or the like. These may be used alone or in combination with each other. Optionally, each of the source electrode (SE), drain electrode (DE), and pad electrode (PE) is formed to have a multi-layer structure including multiple conductive layers. For example, each of the source electrode (SE), drain electrode (DE), and pad electrode (PE) may have a multi-layer structure in which Ti, Al, and Ti are sequentially stacked.

[0064] In one embodiment, the source electrode (SE), the drain electrode (DE), and the pad electrode (PE) may be formed substantially simultaneously. For example, a first preliminary electrode layer is formed over the entire display area (DA) and the pad area (PA) on the interlayer insulating layer 130. Then, the first preliminary electrode layer is partially etched to simultaneously form the source electrode (SE), the drain electrode (DE), and the pad electrode (PE).

[0065] As shown in FIG. 6 , a protective insulating layer 140 is formed on the interlayer insulating layer 130, the source electrode (SE), the drain electrode (DE), and the pad electrode (PE). That is, the protective insulating layer 140 is formed on the substrate 110 and the pad electrode (PE). For example, the protective insulating layer 140 is formed over the entire display area (DA) and pad area (PA) on the interlayer insulating layer 130. The protective insulating layer 140 is formed using a material having a lower etching rate than the conductive layer 180 in the second etching process (e.g., a wet etching process using an etchant). That is, in the second etching process shown in FIGS. 12 and 13 , the conductive layer 180 is etched relatively more than the protective insulating layer 140. For example, the protective insulating layer 140 is formed using an organic insulating material such as polyimide (PI).

[0066] A first contact hole 145 and a second contact hole 147 are formed in the protective insulating layer 140. The first contact hole 145 exposes at least a portion of the upper surface of the drain electrode (DE). The second contact hole 147 exposes at least a portion of the upper surface of the pad electrode (PE). The first and second contact holes 145 and 147 are formed substantially simultaneously.

[0067] 7, a pixel electrode 161 is formed in the display area (DA) on the protective insulating layer 140. The pixel electrode 161 is electrically connected to the drain electrode (DE) through the first contact hole 145.

[0068] Furthermore, a conductive layer 180 covering the second contact hole 147 is formed in the pad electrode (PE) and the pad region (PA) on the protective insulating layer 140. For example, as shown in Fig. 7, the conductive layer 180 covers the upper surface of the pad electrode (PE) exposed by the second contact hole 147 and a part of the protective insulating layer 140 located in the pad region (PA). That is, the conductive layer 180 is formed entirely in the pad region (PA) on the pad electrode (PE) and the protective insulating layer 140.

[0069] The conductive layer 180 is formed using a material having a lower etching rate in the first etching process (e.g., a dry etching process using plasma) than the first and second inorganic sealing layers 171 and 173. That is, in the first etching process shown in FIGS. 10 and 11 , the first and second inorganic sealing layers 171 and 173 are etched relatively more than the conductive layer 180. In an exemplary embodiment, the conductive layer 180 is formed to have a multi-layer structure including multiple sub-layers. In this case, the uppermost layer of the sub-layers is formed using a material having a lower etching rate in the first etching process than the first and second inorganic sealing layers 171 and 173. Alternatively, each of the sub-layers may be formed using a material having a lower etching rate in the first etching process than the first and second inorganic sealing layers 171 and 173.

[0070] The conductive layer 180 is formed using a material having a higher etching rate in the second etching process (e.g., a wet etching process using an etchant) than the etching rate of the pad electrode (PE), the etching rate of the protective insulating layer 140, and the etching rate of the first and second inorganic sealing layers 171 and 173. That is, in the second etching process shown in FIGS. 12 and 13, the conductive layer 180 is etched relatively more than the pad electrode (PE), the protective insulating layer 140, and the first and second inorganic sealing layers 171 and 173. In an exemplary embodiment, the conductive layer 180 is formed to have a multi-layer structure including a plurality of sub-layers. In this case, each of the sub-layers is formed using a material having a higher etching rate in the second etching process than the etching rate of the pad electrode (PE), the etching rate of the protective insulating layer 140, and the etching rate of the first and second inorganic sealing layers 171 and 173.

[0071] Each of the pixel electrode 161 and the conductive layer 180 may be formed using a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, or the like. For example, each of the pixel electrode 161 and the conductive layer 180 may include silver (Ag), indium tin oxide (ITO), or the like. These may be used alone or in combination with each other. Alternatively, each of the pixel electrode 161 and the conductive layer 180 may have a multi-layer structure including multiple conductive layers. For example, each of the pixel electrode 161 and the conductive layer 180 may have a multi-layer structure in which ITO, Ag, and ITO are sequentially stacked.

[0072] In one embodiment, the pixel electrode 161 and the conductive layer 180 may be formed substantially simultaneously. For example, a second preliminary electrode layer is formed over the entire display area (DA) and pad area (PA) on the protective insulating layer 140 and the pad electrode (PE). Then, the second preliminary electrode layer is partially etched to simultaneously form the pixel electrode 161 and the conductive layer 180.

[0073] 8, a pixel defining layer 150 is formed in the display area (DA) on the protective insulating layer 140. The pixel defining layer 150 partially covers the pixel electrode 161 on the protective insulating layer 140. The pixel defining layer 150 has the pixel opening that exposes at least a portion of the pixel electrode 161. For example, the pixel defining layer 150 is formed using an organic insulating material such as polyimide (PI).

[0074] An emitting layer 162 may be formed in the display area (DA) on the pixel electrode 161. For example, the emitting layer 162 is formed on the pixel electrode 161 exposed by the pixel opening of the pixel defining film 150. The emitting layer 162 is formed using at least one of an organic emitting material and quantum dots.

[0075] A counter electrode 163 is formed in the display area (DA) on the light-emitting layer 162. For example, the counter electrode 163 is also formed in the display area (DA) on the pixel defining film 150. The counter electrode 163 is formed using a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, etc. The pixel electrode 161, the light-emitting layer 162, and the counter electrode 163 form a light-emitting element 160.

[0076] 9, a sealing layer 170 is formed on the counter electrode 163. For example, a first inorganic sealing layer 171, an organic sealing layer 172, and a second inorganic sealing layer 173 are formed in this order.

[0077] The first inorganic sealing layer 171 is formed entirely in the display area (DA) and the pad area (PA) on the counter electrode 163 and the conductive layer 180. The organic sealing layer 172 is formed in the display area (DA) on the first inorganic sealing layer 171. The second inorganic sealing layer 173 is formed entirely in the display area (DA) and the pad area (PA) on the first inorganic sealing layer 171 and the organic sealing layer 172. That is, the first inorganic sealing layer 171 and the second inorganic sealing layer 173 are sequentially formed in the pad area (PA) on the conductive layer 180. The organic sealing layer 172 is formed in the display area (DA) on the counter electrode 163.

[0078] The first and second inorganic encapsulation layers 171 and 173 are formed entirely in the display area (DA) and the pad area (PA) on the protective insulating layer 140 and the conductive layer 180. For example, each of the first and second inorganic encapsulation layers 171 and 173 is deposited entirely on the substrate 110 without using a mask structure.

[0079] The first and second inorganic sealing layers 171, 173 are formed using a material having a higher etching rate in the first etching process (e.g., a dry etching process using plasma) than the etching rate of the conductive layer 180. That is, in the first etching process shown in FIGS. 10 and 11, the first and second inorganic sealing layers 171, 173 are etched relatively more than the conductive layer 180.

[0080] The first and second inorganic sealing layers 171 and 173 are formed using a material having a lower etching rate than the conductive layer 180 during the second etching process. That is, in the second etching process shown in FIGS. 12 and 13, the conductive layer 180 is etched relatively more than the first and second inorganic sealing layers 171 and 173. For example, the second etching process is a wet etching process using an etching solution. Therefore, the second etching process may cause the conductive layer 180 to have an undercut (UC) shape at the side edges of the first direction (D1) of the first and second inorganic sealing layers 171 and 173.

[0081] 10 and 11, the first etching process removes portions of the first and second inorganic sealing layers 171 and 173 that overlap at least a portion of the pad electrode (PE). The first etching process separates each of the first and second inorganic sealing layers 171 and 173 from at least a portion of the pad electrode (PE) in a plan view. That is, each of the first and second inorganic sealing layers 171 and 173 exposes all or a portion of the pad electrode (PE) in a plan view. In other words, all or a portion of the pad electrode (PE) does not overlap each of the first and second inorganic sealing layers 171 and 173 in a plan view.

[0082] In one embodiment, the first etching process may be performed without using a mask structure. For example, the first etching process may be a dry etching process using atmospheric pressure plasma. A dry etching process using atmospheric pressure plasma may selectively provide an etching gas to a portion of a substrate. Therefore, compared to a general dry etching process, a dry etching process using atmospheric pressure plasma may selectively etch a portion of a substrate without using a mask structure. For example, the first etching process may be performed by providing an etching gas from a side edge of the substrate 110 in a first direction (D1) in a direction opposite to the first direction (D1). That is, the etching gas is provided only from a side edge of the substrate 110 in the first direction (D1) to a region overlapping the pad electrode (PE) (e.g., the region indicated by the arrow in FIG. 10). As a result, the first etching process removes portions of the first and second inorganic sealing layers 171 and 173 overlapping the pad electrode (PE) without using a mask structure.

[0083] The conductive layer 180 has a first etching rate in the first etching process. The first and second inorganic sealing layers 171 and 173 have a second etching rate in the first etching process that is higher than the first etching rate. For example, the etching gas contains a fluorine-containing fluorocompound. For example, the conductive layer 180 may have a multilayer structure in which ITO, Ag, and ITO are sequentially stacked. Because the ITO contained in the top layer of the conductive layer 180 has a relatively low etching rate in the fluorocompound, the conductive layer 180 is hardly etched in the first etching process. Therefore, when the portions of the first and second inorganic sealing layers 171 and 173 are removed in the first etching process, the conductive layer 180 covers the pad electrode (PE) and the protective insulating layer 140 to prevent them from being exposed to the etching gas. Therefore, damage to the pad electrode (PE) and the protective insulating layer 140 in the first etching process can be prevented or reduced.

[0084] 12 and 13, the second etching process removes a portion of the conductive layer 180 that overlaps at least a portion of the pad electrode (PE). For example, the second etching process causes the conductive layer 180 not to be in direct contact with the pad electrode (PE). For example, the second etching process causes the conductive layer 180 to be separated from at least a portion of the pad electrode (PE) on a plane. That is, the conductive layer 180 exposes all or a portion of the pad electrode (PE) on a plane. In other words, all or a portion of the pad electrode (PE) does not overlap the conductive layer 180 on a plane.

[0085] For example, the second etching process is a wet etching process using an etching solution. For example, the second etching process can be performed without using a mask structure. The conductive layer 180 has a third etching rate for the second etching process. The pad electrode (PE) has a fourth etching rate for the second etching process that is lower than the third etching rate. The protective insulating layer 140 has a fifth etching rate for the second etching process that is lower than the third etching rate. The first and second inorganic sealing layers 171 and 173 have a sixth etching rate for the second etching process that is lower than the third etching rate. For example, the conductive layer 180 may have a multilayer structure in which ITO, Ag, and ITO are sequentially stacked. The pad electrode (PE) may have a multilayer structure in which Ti, Al, and Ti are sequentially stacked. Ti included in the uppermost layer of the pad electrode (PE) and the protective insulating layer 140 have a relatively lower etching rate for the etching solution than ITO and Ag. Therefore, the pad electrode (PE) and the protective insulating layer 140 are hardly etched by the second etching process. Furthermore, the first and second inorganic sealing layers 171, 173 have a relatively lower etching rate with respect to the etching solution than ITO and Ag. Therefore, the first and second inorganic sealing layers 171, 173 are hardly etched by the second etching process. As a result, the conductive layer 180 can have an undercut (UC) shape with respect to the side ends of the first and second inorganic sealing layers 171, 173 in the first direction (D1).

[0086] In conventional display device manufacturing methods, depositing an inorganic encapsulation layer so as not to overlap with the pad electrode requires a deposition process using a mask structure, which increases costs. However, it is possible to deposit the inorganic encapsulation layer entirely over the display area and pad area without using a mask structure, and then remove the portion of the inorganic encapsulation layer overlapping the pad electrode using a dry etching process without using a mask structure. For example, an etching gas can be supplied to only a portion of the substrate (e.g., the region overlapping the pad electrode) to etch the portion of the inorganic encapsulation layer. However, when the portion of the inorganic encapsulation layer is etched, the etching gas can damage the pad electrode and the protective insulating layer located around the pad electrode. This can result in poor electrical contact between the pad electrode and an external device.

[0087] In a method for manufacturing a display device 10 according to an exemplary embodiment of the present invention, a conductive layer 180 is formed in the pad electrode (PE) and the pad region (PA) on the protective insulating layer 140. The conductive layer 180 covers the upper surface of the pad electrode (PE) exposed through the second contact hole 147 and a portion of the protective insulating layer 140 located in the pad region (PA). The conductive layer 180 may be formed simultaneously with the pixel electrode 161 formed in the display region (DA) on the protective insulating layer 140. Then, first and second inorganic encapsulation layers 171 and 173 may be deposited over the entire display region (DA) and pad region (PA) without using a mask structure. Then, a first etching process is performed to remove portions of the first and second inorganic encapsulation layers 171 and 173 overlapping the pad electrode (PE). For example, the first etching process may be performed by providing an etching gas only to a portion of the substrate 110 (e.g., the arrow region in FIG. 10 ) without using a mask structure. The conductive layer 180 has a relatively low etching rate compared to the first etching process, and is therefore hardly etched by the first etching process. Therefore, the conductive layer 180 can prevent the pad electrode (PE) and the protective insulating layer 140 from being damaged by the first etching process. After the first etching process is performed, a second etching process is performed to remove a portion of the conductive layer 180 overlapping the pad electrode (PE). The pad electrode (PE) and the protective insulating layer 140 have a relatively low etching rate compared to the second etching process. Therefore, the pad electrode (PE) and the protective insulating layer 140 are hardly etched by the second etching process, and only the portion of the conductive layer 180 overlapping the pad electrode (PE) is etched. This reduces the number of mask structures used in the manufacturing process of the display device 10, thereby reducing manufacturing costs. Furthermore, poor electrical contact between the pad electrode (PE) of the display device 10 and the external device 20 can be prevented, thereby improving the reliability of the display device 10.

[0088] Although the present invention has been described with reference to exemplary embodiments thereof, those skilled in the art will recognize that various modifications and variations of the present invention may be made without departing from the spirit and scope of the present invention as set forth in the following claims. [Industrial Applicability]

[0089] The present invention is applicable to various display devices, such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices. [Explanation of symbols]

[0090] 10: Display device 110: Circuit board AL: active layer 120: Gate insulating layer GE: gate electrode 130: Interlayer insulating layer SE: Source electrode DE: Drain electrode TR: Transistor PE: Pad electrode 140: Protective insulating layer 160: Light-emitting element 161: Pixel electrode 162: Emitting layer 163: Counter electrode 170: Sealing layer 171, 173: First and second inorganic sealing layers 172: Organic sealing layer 180: Conductive layer

Claims

1. a substrate having a display area and a pad area located on one side of the display area; a pad electrode disposed in the pad region on the substrate; a protective insulating layer disposed on the substrate and the pad electrode, the protective insulating layer defining a contact hole exposing at least a portion of an upper surface of the pad electrode; an inorganic sealing layer disposed on the protective insulating layer; a conductive layer disposed in the pad region between an end of the inorganic sealing layer adjacent to the pad electrode and the protective insulating layer, the pad region includes a first region between the contact hole and the display region, and a second region on an opposite side of the contact hole from the first region; The display device, characterized in that the conductive layer is disposed in the first region and is not disposed in the second region.

2. 2. The display device according to claim 1, wherein the inorganic sealing layer and the conductive layer are each spaced apart from at least a portion of the pad electrode in a plan view.

3. 3. The display device according to claim 1, wherein the conductive layer has an undercut shape relative to the end portion of the inorganic sealing layer.

4. the conductive layer has a first etch rate with respect to a first etching step; 4. The display device according to claim 1, wherein the inorganic sealing layer has a second etching rate in the first etching step that is higher than the first etching rate.

5. a substrate having a display area and a pad area located on one side of the display area; a pad electrode disposed in the pad region on the substrate; a protective insulating layer disposed on the substrate and the pad electrode, exposing at least a portion of an upper surface of the pad electrode; an inorganic sealing layer disposed on the protective insulating layer; a conductive layer disposed in the pad region between an end of the inorganic sealing layer adjacent to the pad electrode and the protective insulating layer, the conductive layer has a third etch rate with respect to the second etching step; The display device, wherein the pad electrode has a fourth etching rate in the second etching step that is lower than the third etching rate.

6. the protective insulating layer has a fifth etching rate in the second etching step that is lower than the third etching rate; 6. The display device according to claim 5, wherein the inorganic sealing layer has a sixth etching rate in the second etching step that is lower than the third etching rate.

7. a substrate having a display area and a pad area located on one side of the display area; a transistor disposed in the display region on the substrate; a pixel electrode disposed on the transistor and electrically connected to the transistor; a pad electrode disposed in the pad region on the substrate; a protective insulating layer disposed on the substrate and the pad electrode, exposing at least a portion of an upper surface of the pad electrode; an inorganic sealing layer disposed on the protective insulating layer; a conductive layer disposed in the pad region between an end of the inorganic sealing layer adjacent to the pad electrode and the protective insulating layer, The display device, wherein the conductive layer is disposed in the same layer as the pixel electrodes.

8. providing a substrate having a display area and a pad area located on one side of the display area; forming a pad electrode in the pad region on the substrate; forming a protective insulating layer on the substrate and the pad electrode; a contact hole is formed in the protective insulating layer to expose at least a portion of an upper surface of the pad electrode; forming a conductive layer covering the contact hole in the pad electrode and the pad region on the protective insulating layer; forming an inorganic sealing layer on the protective insulating layer and the conductive layer; a first etching step of removing a portion of the inorganic sealing layer that overlaps at least a portion of the pad electrode; a second etching step for removing a portion of the conductive layer that overlaps at least a portion of the pad electrode;

9. A method for manufacturing a display device as described in Claim 8, characterized in that the first etching process is a dry etching process.

10. A method for manufacturing a display device as described in Claim 8, characterized in that the second etching process is a wet etching process.

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