Audio circuit, electronic device using the same, and in-vehicle audio system

Abstract

An analog voltage VFILA can be input into a volume setting pin FILA of an audio circuit 300. A power supply pin VCC accepts a power supply voltage VCC. A bias circuit 310 generates a first reference voltage VFIL corresponding to the analog voltage VFILA. A D / A converter 320 converts a digital audio signal SDIG into an analog audio signal VDAC. The full scale voltage range of the D / A converter 320 can be varied in accordance with the first reference voltage VFIL. A class D amplifier circuit 200 has a duty cycle corresponding to the analog audio signal VDAC output by the D / A converter 320, and outputs an output pulse signal SOUT having an amplitude corresponding to the power supply voltage VCC.

Description

[Technical Field]

[0001] The present disclosure relates to an audio amplifier circuit that drives a speaker or a headphone. [Background technology]

[0002] A highly efficient class-D amplifier is used as a power amplifier for driving an electroacoustic transducer such as a speaker or a headphone. FIG. 1 is a block diagram of an audio system 100R using a class-D amplifier. The audio system 100R mainly includes a speaker 102, a low-pass filter 104, a sound source 106, and a class-D amplifier circuit 900R. The sound source 106 outputs a digital audio signal D IN Generate.

[0003] The class-D amplifier circuit 900R receives the digital input audio signal D IN An output pulse signal S having a duty cycle according to OUT The low-pass filter 104 generates the output pulse signal S of the class-D amplifier circuit 900R. OUT The high frequency components are removed and the signal is supplied to the speaker 102.

[0004] The class-D amplifier circuit 900R in FIG. 1 includes an audio interface circuit 902, a serial interface circuit 904, an output stage 930, an integrator 910, and a PWM (Pulse Width Modulation) comparator 920.

[0005] The audio interface circuit 902 receives a digital audio signal D IN Receives PWM signal D PWM The level shift circuit 906 outputs the PWM signal D PWM The amplitude of the input audio signal S is level-shifted to a PWM signal with a voltage level (for example, 5V) that matches the input voltage range of the subsequent circuit. IN Output.

[0006] The integrator 910 converts the input audio signal S INand the output pulse signal S OUT The feedback signal S according to FB Integrate the difference of

[0007] The PWM comparator 920 compares the output of the integrator 910 with a reference voltage and generates a pulse signal S PWM Output.

[0008] The output stage 930 includes a driver 932 and a half-bridge circuit (inverter circuit) 934. The driver 932 outputs a pulse signal S PWM In response to this, the half-bridge circuit 934 is driven.

[0009] 2 is a block diagram of an audio system 100S using a class-D amplifier. IN A digital audio signal (e.g., a PCM signal) corresponding to PCM The D / A converter 908 converts the digital audio signal S output by the audio interface circuit 903 into PCM the analog input audio signal S IN Convert to.

[0010] The integrator 910 converts the input audio signal S IN and the output pulse signal S OUT The feedback signal S according to FB The triangular wave generating circuit 940 generates a periodic signal V having a pulse width modulated carrier frequency. OSC The PWM comparator 920 generates the output of the integrator 910 and the periodic signal V OSC and the pulse signal S PWM Output. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Patent No. 5618776 Summary of the Invention [Problem to be solved by the invention]

[0012] The output pulse signal S of the class-D amplifier circuits 900R and 900S in Fig. 1 and Fig. 2 OUT The amplitude (time average) of this, in other words, the volume of the speaker 102, is determined by the power supply voltage Vcc of the half-bridge circuit 934. In an in-vehicle application, if Vcc=14.4 V and the load impedance is 4 Ω, the output is fixed at 26 W.

[0013] If you want to change the output, i.e., the volume, you need to use a digital volume. For audio product applications that require high sound quality, a digital volume function is implemented in the SoC (System On Chip) or DSP (Digital Signal Processor / Digital Sound Processor), which corresponds to the sound source 106, so you can use that.

[0014] On the other hand, in applications where warning sounds or simple audio signals are to be reproduced, the sound source 106 often does not have a digital volume function. To address this, specifically, in the class-D amplifier circuit 900R of FIG. 1, a digital volume function is implemented in the audio interface circuit 902. The serial interface circuit 904 receives a volume setting value from the microcontroller 108, which is the host processor, and sets the volume gain of the audio interface circuit 902. The audio interface circuit 902 outputs a PWM signal D whose duty cycle is scaled according to the volume. PWM Output.

[0015] 2, a digital volume function is implemented in the audio interface circuit 903. The audio interface circuit 903 outputs a digital audio signal S whose amplitude is adjusted according to the volume. PCM Output.

[0016] As described above, in the conventional technology, it is necessary to implement a digital volume function in the audio interface circuit 903, which is a factor in increasing costs.

[0017] Furthermore, for this control, it is necessary to send a volume setting command from the microcontroller 108.

[0018] The present disclosure has been made in view of the above-mentioned problems, and it is an exemplary purpose of an embodiment thereof to provide an audio circuit with a variable volume. [Means for solving the problem]

[0019] The audio circuit according to the present disclosure includes a volume setting pin that receives an analog voltage, a power supply pin that receives a power supply voltage, a bias circuit that generates a first reference voltage according to the analog voltage, a D / A converter that converts a digital audio signal into an analog audio signal, the D / A converter having a full-scale voltage range that is variable according to the first reference voltage, and a class D amplifier circuit that outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal output by the D / A converter and an amplitude that corresponds to the power supply voltage.

[0020] Any combination of the above components, and any transformation of the present invention into a method, device, or the like, are also valid aspects of the present invention. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Effects of the Invention]

[0021] According to an aspect of the present disclosure, the volume can be set. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a block diagram of an audio system using a class-D amplifier. [Figure 2] FIG. 2 is a block diagram of an audio system using a Class D amplifier. [Figure 3] FIG. 3 is a block diagram of an audio system including an audio circuit according to an embodiment. [Figure 4] FIG. 4 is an operational waveform diagram of the audio circuit of FIG. [Figure 5] FIG. 5 is a circuit diagram showing an example of an audio circuit. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of the bias circuit of FIG. [Figure 7] FIG. 7 is a block diagram of an example of the configuration of a D / A converter. [Figure 8] 8(a) and 8(b) are diagrams showing the input / output characteristics of the D / A converter of FIG. [Figure 9] 9(a) to 9(c) are operational waveform diagrams of the D / A converter. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of the upper conversion unit and the lower conversion unit. [Figure 11] FIG. 11 is a circuit diagram showing a specific example of the configuration of the upper conversion unit and the lower conversion unit. [Figure 12] FIG. 12 is a circuit diagram of the upper selector and the lower selector of FIG. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of the first amplifier and the second amplifier. [Figure 14] FIG. 14 is a diagram showing another example of the configuration of a D / A converter and a bias circuit. [Figure 15] FIG. 15 is a diagram illustrating another example of the configuration of the D / A converter. [Figure 16] FIG. 16 is a block diagram of an in-vehicle audio system that uses the audio circuit according to the embodiment. [Figure 17] 17(a) and 17(b) are diagrams showing electronic devices that use the audio circuit according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0023] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0024] An audio circuit according to one embodiment includes a volume setting pin that receives an analog voltage, a power supply pin that receives a power supply voltage, a bias circuit that generates a first reference voltage according to the analog voltage, a D / A converter that converts a digital audio signal into an analog audio signal, the D / A converter having a full-scale voltage range that is variable according to the first reference voltage, and a class D amplifier circuit that outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal output by the D / A converter and an amplitude that corresponds to the power supply voltage.

[0025] According to this configuration, the duty cycle of the output pulse signal generated by the class-D amplifier is scaled in accordance with the first reference voltage, so that the volume can be controlled.

[0026] In one embodiment, the bias circuit may include a first resistor connected between the volume setting pin and the power supply pin, and a second resistor connected between the volume setting pin and ground. When no external analog voltage is applied to the volume setting pin, a voltage determined by the voltage division ratio of the first resistor and the second resistor is generated at the volume setting pin, and the volume corresponding to this voltage level can be set as the default.

[0027] In one embodiment, the class D amplifier circuit may include an integrator that receives an analog audio signal and an output pulse signal, a periodic voltage generating circuit that generates a periodic voltage of a triangular wave or a sawtooth wave, a PWM (Pulse Width Modulation) comparator that compares the output of the integrator with the periodic voltage, a bridge circuit, and a driver that drives the bridge circuit according to the output of the PWM comparator.

[0028] In one embodiment, the bias circuit may further generate a second reference voltage obtained by dividing the first reference voltage and the power supply voltage, and the second reference voltage may be supplied to the integrator.

[0029] In one embodiment, the periodic voltage generating circuit may generate a periodic voltage whose midpoint level is the second reference voltage.

[0030] In one embodiment, the audio circuit may be monolithically integrated on a single substrate. "Monolithically integrated" includes cases where all of the circuit components are formed on the substrate, or where the main circuit components are monolithically integrated, and some resistors, capacitors, etc. may be provided outside the substrate to adjust the circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniformly.

[0031] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0032] In this specification, "a state in which component A is connected to component B" includes cases in which component A and component B are directly physically connected, and cases in which component A and component B are indirectly connected via other components that do not affect the electrical connection state or inhibit function.

[0033] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not affect the electrical connection state or impede function.

[0034] 3 is a block diagram of an audio system 100 including an audio circuit 300 according to an embodiment. The audio system 100 includes a speaker 102, a low-pass filter 104, a sound source 106, and the audio circuit 300. The audio circuit 300 is configured as a functional IC (Integrated Circuit) integrated on a single semiconductor chip.

[0035] The audio circuit 300 includes a bias circuit 310, a D / A converter 320, a digital audio interface circuit 330, a class-D amplifier circuit 200, a volume setting pin FILA, and a power supply pin VCC. The volume setting pin FILA receives an external analog voltage V FILA The power supply pin VCC can be used to input the power supply voltage V CC is supplied.

[0036] The digital audio interface circuit 330 receives the digital audio signal D IN Receives digital audio signal D IN The format of is not particularly limited, but 2 S(I 2 Examples include Inter IC Sound (S).

[0037] The bias circuit 310 supplies an analog voltage V FILA The first reference voltage V FILGenerates the first reference voltage V FIL is the analog voltage V FILA or may have the same voltage level as the analog voltage V FILA may have a voltage level obtained by multiplying the voltage by a predetermined coefficient.

[0038] The D / A converter 320 converts the digital audio signal S DIG , the analog audio signal V DAC The D / A converter 320 is supplied with a first reference voltage V FIL is supplied, and the first reference voltage V FIL Depending on the full-scale voltage range V FULL In other words, a voltage width of 1 LSB can be set.

[0039] The class-D amplifier circuit 200 converts the analog audio signal V output from the D / A converter 320 into DAC and an output pulse signal S having a duty cycle corresponding to the power supply voltage Vcc. OUT The class D amplifier circuit 200 may be configured using known technology or circuits that can be used in the future, and the configuration is not particularly limited.

[0040] The above is the configuration of the audio circuit 300. Next, the operation thereof will be described.

[0041] 4 is an operation waveform diagram of the audio circuit 300 of FIG. 3. In FIG. 4, the digital audio signal S DIG , the output signal V of the D / A converter 320 DAC and the output pulse signal S of the class D amplifier circuit 200 OUT In this example, a digital audio signal S DIG is a sine wave. The setting voltage of the volume setting pin FILA is V FILA The different states are shown as (i) to (iii), and the set voltage V FILA becomes higher.

[0042] The output pulse signal S of the class D amplifier circuit 200 OUTThe amplitude of the set voltage V FILA Regardless of the supply voltage V CC However, the duty cycle (duty) is equal to the analog audio signal V output by the D / A converter 320. DAC It depends on the set voltage V FILA is scaled accordingly.

[0043] The driving voltage V supplied to the speaker 102 DRV is the output pulse S OUT is the effective voltage (time average) of duty(t)×V CC The gain of the class D amplifier circuit 200 is g D When g D ×V DAC It can be expressed as (t).

[0044] The above is the operation of the audio circuit 300. According to this audio circuit 300, a volume setting pin FILA is provided, and a setting voltage V FILA The driving voltage V applied to the speaker 102 in response to DRV The amplitude of the signal can be changed, enabling volume control.

[0045] In this audio circuit 300, the circuit configuration can be simplified and the chip area can be reduced because there is no need to implement a digital volume function in the digital audio interface circuit 330. In addition, there is no need for an interface with the microcontroller 108 in Figures 1 and 2, and the microcontroller 108 itself is also not required.

[0046] The present disclosure covers various devices and circuits that can be understood as the circuit diagram in Figure 3 or derived from the above description, and is not limited to any particular configuration. Below, more specific configuration examples will be described not to narrow the scope of the present invention, but to facilitate and clarify understanding of the essence of the invention and circuit operation.

[0047] 5 is a circuit diagram showing one embodiment (300A) of the audio circuit 300. In this embodiment, the class-D amplifier circuit 200A is configured as a class-D amplifier with feedback. The class-D amplifier circuit 200A includes an integrator 210, a periodic voltage generating circuit 220, a PWM comparator 230, a bridge circuit 240, and a driver 250.

[0048] The bridge circuit 240 is a push-pull inverter and includes a high-side transistor MH and a low-side transistor ML. The high-side transistor MH may be a PMOS transistor or an NMOS transistor.

[0049] The integrator 210 includes resistors R11 and R12, a capacitor C11, and an error amplifier 212. An input voltage V is input to an inverting input terminal (-) of the error amplifier 212 via a first resistor R11. DAC is output through the second resistor R12 as an output pulse signal S OUT Feedback voltage V according to FB The capacitor C11 is provided between the output and the inverting input terminal of the error amplifier 212, and the second reference voltage V FILP is input. The gain g D is given by R12 / R11. Also, the second reference voltage V FILP The output pulse signal S OUT The midpoint level of the time-averaged waveform is defined.

[0050] The periodic voltage generating circuit 220 generates a periodic voltage V OSC Generates a periodic voltage V OSC is the carrier wave of the pulse width modulation. The periodic voltage V OSC The frequency of this signal is a PWM frequency, which is higher than the audio frequency band (20 Hz to 20 kHz) and is set in the range of several hundred kHz to several MHz. INT and the periodic voltage V OSC and the PWM signal S is set to high or low depending on the comparison result. PWMGenerate.

[0051] The configuration of the periodic voltage generating circuit 220 is not particularly limited. The periodic voltage generating circuit 220 has a bottom voltage of 0V and a power supply voltage V CC The periodic voltage V OSC Alternatively, the periodic voltage generating circuit 220 may generate a periodic voltage V OSC may be generated.

[0052] The driver 250 generates a PWM signal S PWM In response to this, the high-side transistor MH and the low-side transistor ML of the bridge circuit 240 are switched on in a complementary manner. The driver 250 inserts a dead time so that the high-side transistor MH and the low-side transistor ML are not turned on at the same time.

[0053] The bias circuit 310A controls the voltage V FILA The first reference voltage V FIL and supplies it to the D / A converter 320. The bias circuit 310A also generates the voltage V FILA A second reference voltage V FILP and supplies it to the error amplifier 212 of the integrator 210.

[0054] Fig. 6 is a circuit diagram showing an example of the configuration of the bias circuit 310A of Fig. 5. The bias circuit 310A includes a first resistor R21 to a sixth resistor R26, a first buffer 312, a second buffer 314, and a third buffer 313.

[0055] The volume setting pin FILA accepts an external setting voltage V FILA The first resistor R21 is connected between the power supply terminal (power supply line) VCC and the volume setting pin FILA, and the second resistor R22 is connected between the volume setting pin FILA and the ground. If the volume setting pin FILA is left non-connected (NC), the external setting voltage V FILA If not given, the voltage V of the volume setting pin FILAFILA(NC) teeth, V FILA(NC) =R22 / (R21+R22)×Vcc This becomes:

[0056] The first buffer 312 has a high input impedance and a low output impedance, and outputs a set voltage V FILA The first reference voltage V FILA Output.

[0057] The fifth resistor R25, the sixth resistor R26 and the third buffer 313 are connected to the power supply voltage V CC When R25=R26, the voltage divider circuit 316 divides the power supply voltage V CC The midpoint voltage V CC / 2 is generated. Midpoint voltage V CC / 2 is output via buffer 313 .

[0058] The third resistor R23 and the fourth resistor R24 ​​are provided between the output of the voltage divider circuit 316 and the output of the first buffer 312. The ratio of the resistance values ​​of the third resistor R23 and the fourth resistor R24 ​​is determined by the gain g D That is, it may be determined in accordance with the resistance values ​​of the first resistor R11 and the second resistor R12 in FIG. R24:R23=R11:R12

[0059] The connection node Nx between the third resistor R23 and the fourth resistor R24 ​​is connected to a voltage V CC / 2 and voltage V FIL A voltage Vx is generated by dividing this internally. Vx=(V FIL ×R23+V CC / 2×R24) / (R23+R24)

[0060] The second buffer 314 has a high input impedance and a low output impedance, and outputs a second reference voltage V FILP Output.

[0061] The above is the configuration of the audio circuit 300A. In this audio circuit 300A, the full-scale output, i.e., the volume, is set by the voltage V of the volume setting pin FILA. FILA It can be controlled according to the

[0062] The second reference voltage V generated by the bias circuit 310 of FIG. FILP may be supplied to the periodic voltage generating circuit 220. The periodic voltage generating circuit 220 may generate a periodic voltage having a center level equal to the second reference voltage V FILP and V CC A periodic voltage V with half amplitude of / N (N is a constant) OSC For example, if N=8, the periodic voltage V OSC The bottom is V FILP -V CC / 8, peak is V FILP +V CC / 8. Note that N is not limited to 8. For example, if N=2, the periodic voltage V OSC The bottom is 0V and the peak is 2×V FILP This becomes:

[0063] In this case, the periodic voltage V OSC The amplitude of the output voltage V of the D / A converter 320 DAC and the power supply voltage V CC As a result, even in a configuration in which the total gain of the audio circuit 300 is set low, it is possible to ensure a full-scale output level within the operating power supply voltage range, thereby reducing the noise level.

[0064] Furthermore, in the bias circuit 310A of Figure 6, by providing resistors R21 and R22, the circuit can operate even when the volume setting pin FILA is disconnected (NC). In this case, it is recommended to determine the resistance values ​​of resistors R25 and R26 so as to obtain the volume value that is expected to be used most frequently. When using the audio circuit 300A at the volume value expected, the designer of the audio system 100A does not need to apply an external signal to the volume setting pin FILA.

[0065] Also, the reference voltage V of the integrator 210 can be appropriately set by the resistors R23 and R24. FILP

[0066] Next, a configuration example of the D / A converter 320 will be described.

[0067] FIG. 7 is a block diagram of a configuration example (400) of the D / A converter 320. The D / A converter 400 includes an upper conversion unit 410, a lower conversion unit 420, a first amplifier 430, and a second amplifier 440.

[0068] The D / A converter 400 converts an n-bit (n≧2) digital signal D IN into differential analog signals V DAC_P , V DAC_N . Here, the subscript P indicates the positive phase and N indicates the negative phase.

[0069] The upper conversion unit 410 generates first upper voltages V IN and second upper voltages V [[ID=二十八]] U_P that monotonically change with opposite polarities with respect to the upper m bits (1≦m<n) of the digital signal D U_N . Hereinafter, m = 9.

[0070] The lower conversion unit 420 generates first lower voltages V IN and second lower voltages V L_P that monotonically change with opposite polarities with respect to the lower (n - m) bits of the digital signal D L_N .

[0071] In the following description, it is assumed that n = 16, m = 9, and m - n = 7 bits. That is, the upper 9 bits D IN [15:7] of the digital signal are supplied to the upper conversion unit 410, and the lower 7 bits D IN [6:0] of the digital signal are supplied to the lower conversion unit 420.

[0072] Also, in the present embodiment, the first upper voltage V U_P monotonically increases with respect to the upper m bits, and the second upper voltage V U_Nare assumed to be monotonically decreasing with respect to the upper m bits, and they are in a complementary relationship.

[0073] On the other hand, the first lower voltage V L_P decreases monotonically for the lower (nm) bits, and the second lower voltage V L_N is assumed to be monotonically increasing with respect to the lower (nm) bits, and they are in a complementary relationship.

[0074] The first amplifier 430 outputs a first upper voltage V U_P and the second higher voltage V U_N On the other hand, V U_P and the first lower voltage V L_P and the second lower voltage V L_N On the other hand, V L_P and receives one side of the differential analog signal, V DAC_P Output.

[0075] The second amplifier 440 has the same configuration as the first amplifier 430 and outputs the first higher voltage V U_P and the second higher voltage V U_N On the other hand, V U_L and the first lower voltage V L_P and the second lower voltage V L_N On the other hand, V L_N and receives the other side of the differential analog signal, V DAC_N Output.

[0076] The first amplifier 430 outputs a first upper voltage V U_P to the non-inverting input terminal (+), and the first lower voltage V L_P is input to the inverting input terminal (-), and its output voltage V DAC_P is expressed by equation (1). V DAC_P =g×(V U_P -V L_P ) …(1)

[0077] The second amplifier 440 outputs a second upper voltage V U_N to the non-inverting input terminal (+), and the second lower voltage V L_N is input to the inverting input terminal (-), and its output voltage V DAC_P is expressed by equation (2). V DAC_N =g×(V U_N -V L_N ) …(2)

[0078] The above is the configuration of the D / A converter 400. Next, its operation will be described. FIGS. 8(a) and 8(b) are diagrams showing the input / output characteristics of the D / A converter 400 of FIG. 7. The horizontal axis represents the digital signal D IN The vertical axis represents the value of m, and the vertical axis represents the voltage. For simplicity, let n=16 and m=4.

[0079] In Figure 8(a), the upper voltage V U_P , lower voltage V L_P and the output voltage V DAC_P In FIG. 8(b), the upper voltage V U_N , lower voltage V L_N and the output voltage V DAC_N is shown. The lower voltage V L_P ,V L_N The range is the upper voltage V U_P ,V U_N is equal to the step size.

[0080] Output voltage V DAC_P is the digital signal D IN It increases monotonically with the output voltage V DAC_N is the digital signal D IN The two output voltages V DAC_P ,V DAC_N is a differential signal.

[0081] Next, we will explain the improvement of noise characteristics in the D / A converter 400. Figures 9(a) to 9(c) are operational waveform diagrams of the D / A converter 400.

[0082] Here, the digital signal D IN The first upper voltage V U_P and the second higher voltage V U_N are generated by the same up-conversion unit 410, they contain common-mode noise. L_Pand the second lower voltage V L_N are generated by the same down-conversion unit 420, they contain common-mode noise. DAC_P and the output voltage V of the second amplifier 440 DAC_N contains a signal component of opposite phase and common mode noise.

[0083] The two output voltages V DAC_P ,V DAC_N are used as differential signals, so their difference V DIFF =V DAC_P -V DAC_N This signal component V DIFF does not include noise that is superimposed in the upper conversion section 410 and the lower conversion section 420.

[0084] This completes the operation of the D / A converter 400. This D / A converter 400 can improve noise characteristics.

[0085] The waveform diagram in FIG. 9 shows the cancellation of noise components during playback of an audio signal, but the effect of noise cancellation is more pronounced in a small signal state or in a no signal state.

[0086] The noise components generated in the upper conversion unit 410 and the lower conversion unit 420 are expressed as V X_Y (where X=U, L, Y=P, N). In a small signal state, V U_P ≒V U_N ,V L_P ≒V L_N In this way, the noise components generated by the resistance of the conversion section are cancelled out at the BTL output. U_P =V U_N ,V L_P =V L_N As a result, the noise components generated by the resistance of the conversion section are cancelled out at the BTL output.

[0087] 10 is a circuit diagram showing an example of the configuration of the upper conversion unit 410 and the lower conversion unit 420. The upper conversion unit 410 includes an upper resistor string RSTR1, an upper selector 412, and an upper decoder 414. The upper resistor string RSTR1 is a series-connected m The upper resistor string RSTR1 includes 511 resistor elements (-1=511), and a tap is provided at the connection node between adjacent resistor elements. A first reference voltage Vr1 is applied to one end of the upper resistor string RSTR1, and a second reference voltage Vr2 is applied to the other end. The upper selector 412 is connected to the multiple taps of the upper resistor string RSTR1, and includes multiple switches therein. The upper decoder 414 controls the upper selector 412 and outputs the upper m bits D IN The voltage V generated at the two taps based on [15:7] U_P ,V U_N Specifically, two taps located symmetrically with respect to the center are selected.

[0088] Similarly, the lower conversion unit 420 includes a lower resistor string RSTR2, a lower selector 422, and a lower decoder 424. The lower resistor string RSTR2 is a plurality of resistors connected in series. nーm The lower resistor string RSTR2 includes 127 resistor elements, and a tap is provided at the connection node between adjacent resistor elements. A third reference voltage Vr3 is applied to one end of the lower resistor string RSTR2, and a fourth reference voltage Vr4 is applied to the other end. The lower selector 422 is connected to the plurality of taps of the lower resistor string RSTR2, and includes a plurality of switches therein. The lower decoder 424 controls the lower selector 422 and selects the lower (nm) bits D IN Voltage V of two taps based on [6:0] L_P ,V L_N Specifically, two taps located symmetrically with respect to the center are selected.

[0089] Although not limited to this, Vr2=Vr3 may also be set.

[0090] 11 is a circuit diagram showing a specific example of the configuration of the upper conversion unit 410 and the lower conversion unit 420. The upper conversion unit 410 and the lower conversion unit 420 include a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4 in addition to an upper resistor string RSTR1 and a lower resistor string RSTR2. The first resistor R1 to the third resistor R3 are connected to a reference voltage terminal V REG and ground. The fourth resistor R4 is connected in parallel with the lower resistor string RSTR2.

[0091] If R1 to R4 were not present, the resistance value of the resistance elements of the lower resistor string RSTR2 would need to be designed to be 1 / 127 times the resistance value of the resistance elements of the upper resistor string RSTR1. In this configuration, by appropriately determining the resistors R1, R2, R3, and R4, it is possible to configure the resistance elements of the upper resistor string RSTR1 and the lower resistor string RSTR2 with the same resistance value.

[0092] It is preferable to pair the first resistor R1, the second resistor R2, and the third resistor R3, and it is also preferable to pair the upper resistor string RSTR1, the lower resistor string RSTR2, and the fourth resistor R4, which can cancel the influence of resistance variations and improve characteristics such as integral nonlinearity and differential nonlinearity.

[0093] The configuration of the upper selector 412 and the lower selector 422 will be described with reference to Fig. 12. Fig. 12 is a circuit diagram of the upper selector 412 and the lower selector 422 of Fig. 11.

[0094] The upper resistor string RSTR1 is 2 m It contains 512 resistor elements, formed in a meandering pattern, with multiple taps arranged in a matrix of A rows and B columns. Specifically, a bar containing B=32 resistor elements is arranged in the X direction and then folded back, so in this example, A=16 and B=32. The resistor element on the lowest potential (Vr3) side is short-circuited.

[0095] The upper selector 412 is a plurality of (2) m The circuit includes 512 upper switches SWu (1≦i≦A), A row lines Lr, B column lines Lc, A first output switches SWo_p, and A second output switches SWo_n. One end of the upper switches SWu is connected to the corresponding tap, and the other end of the multiple upper switches SWu in the ith row (1≦i≦A) is connected to the ith row line Lr, and the control terminals of the multiple upper switches SWu in the jth column (1≦j≦B) are connected to the jth column line Lc.

[0096] One end of each of the A first output switches SWo_p is connected to a first output line Lo_p, and the other end of each is connected to a corresponding one of the A row lines Lr. One end of each of the A second output switches SWo_n is connected to a second output line Lo_n, and the other end of each is connected to a corresponding one of the A row lines Lr. The multiple upper switches are preferably configured using CMOS (Complementary Metal Oxide Semiconductor) switches.

[0097] The upper decoder 414 generates 32-bit data HINB[31:0] to be applied to a plurality of column lines Lc.

[0098] The upper decoder 414 also generates a control signal HINA[15:0] to be applied to the plurality of first output switches SWo_p. The control signals HINA[15:0] are assigned to the plurality of second output switches SWo_n in the reverse order.

[0099] The lower resistor string RSTR2 and the lower selector 422 are configured in a similar manner. n-m It contains 128 resistor elements, formed in a meandering pattern, with multiple taps arranged in a matrix of C rows and D columns. Specifically, a bar containing D=32 resistor elements is arranged in the X direction and then folded back, so in this example, C=4 and D=32. The resistor element on the lowest potential (Vr4) side is short-circuited.

[0100] The lower selector 422 is a plurality of (2) n-m = 256) lower switches SWl, C row lines Lr, D column lines Lc, C third output switches SWo_p, and C second output switches SWo_n. One end of the lower switch SWl is connected to the corresponding tap, and the other end of the plurality of lower switches SWl in the ith row (1≦i≦C) is connected to the ith row line Lr. In addition, the control terminals of the plurality of lower switches SWl in the jth column (1≦j≦B) are connected to the jth column line Lc.

[0101] One end of each of the C third output switches SWo_p is connected to the third output line Lo_p, and the other end of each is connected to a corresponding one of the C row lines Lr. One end of each of the C fourth output switches SWo_n is connected to the fourth output line Lo_n, and the other end of each is connected to a corresponding one of the C row lines Lr. The multiple lower switches are preferably configured with NMOS (N-channel Metal Oxide Semiconductor) switches, which allows for a smaller chip area.

[0102] The lower decoder 424 generates 32-bit data LINC[31:0] to be applied to a plurality of column lines Lc.

[0103] The lower-order decoder 424 also generates a control signal LIND[15:0] to be applied to the plurality of third output switches SWo_p. The control signals HIND[15:0] are applied to the plurality of fourth output switches SWo_p in the reverse order.

[0104] According to this configuration, the upper resistor string RSTR1 and the lower resistor string RSTR2 are arranged in a meandering pattern, and the switches are arranged in a matrix pattern, thereby making it possible to reduce the number of control lines.

[0105] If the upper selector 412 selects the first upper voltage V U_P and a selector for extracting the second higher voltage V U_NIf a separate selector is provided to extract the , the number of switches becomes enormous. Specifically, A × B × 2 = 512 × 2 = 1024 switches are required. In contrast, with the configuration of FIG. 12, the number of switches can be reduced to A × B + A × 2 = 512 + 32 = 544. A similar effect can be obtained with the lower selector 422.

[0106] 13 is a circuit diagram showing an example of the configuration of the first amplifier 430 and the second amplifier 440. As described above, the first amplifier 430 and the second amplifier 440 have the same configuration, and include operational amplifiers OA11 and OA12 and resistors R11 and R12. The operational amplifier OA1 forms a buffer (voltage follower) and outputs the lower voltage V L_# (#=P, N). The operational amplifier OA2 and resistors R11 and R12 form a subtraction amplifier (subtraction circuit), and two input voltages V U_# , V L_# Voltage V according to the difference DAC# Output.

[0107] Next, a modification of the D / A converter 400 will be described.

[0108] In the embodiment, the first lower voltage V U_P is the digital signal D IN The second lower voltage V U_N is the digital signal D IN The first lower voltage V U_P is the digital signal D IN The second lower voltage V U_N is the digital signal D IN In this case, the first amplifier 430 and the second amplifier 440 may be configured as an adder circuit instead of a subtracter circuit. V DAC_P =g×(V U_P +V L_P ) V DAC_N =g×(V U_N +V L_N )

[0109] In the embodiment, the upper conversion unit 410 and the lower conversion unit 420 are configured as resistor voltage dividers, but this is not limitative and they may be configured as other D / A converters.

[0110] The reference voltage V in Figure 11 REG As a result, the voltage V of the volume setting pin FILA FILA Reference voltage V according to FIL Just give it the following.

[0111] 14 is a diagram showing another example configuration (400B) of the D / A converter 320 and a bias circuit 310B. This D / A converter 400B is an inverter type. Differential thermometer codes D1_P to Dn_P and D1_N to Dn_N are input to the D / A converter 400B. Therefore, the audio signal D received by the digital audio interface circuit 330 in FIG. 3 is input to the D / A converter 400B in the stage preceding the D / A converter 400B. IN A converter (not shown) is provided to convert the signal into thermometer code.

[0112] The D / A converter 400B includes a plurality of level shifters LSP1 to LSPn, LSN1 to LSNn, a plurality of inverters INVP1 to INVPn, INVN1 to INVNn, resistors RP1 to RPn, RN1 to RNn, capacitors C41 to C43, and resistors R41 to R46.

[0113] The bias circuit 310B controls the voltage V FILA Reference voltage V according to FIL In this example, the bias circuit 310B includes a non-inverting amplifier 318 and generates a set voltage V FILA The reference voltage V has a voltage level that is multiplied by the gain (×(R27+R28) / R27). FIL Output.

[0114] Reference voltage V FILis supplied to a plurality of inverters INVP1 to INVPn, INVN1 to INVNn. Positive thermometer codes D1_P to Dn_P are input to the gates of the inverters INVP1 to INVPn via level shifters LSP1 to LSPn. When the ith bit Di_P of the thermometer code is high, the corresponding inverter INVPi is set to a high voltage, i.e., a reference voltage V FIL Conversely, when the ith bit Di_P of the thermometer code is low, the corresponding inverter INVPi outputs a low voltage, i.e., 0V.

[0115] A voltage Vp generated at a connection node Np of the plurality of resistors RP1 to RPn is proportional to the values ​​(the number of 1s) of the thermometer codes D1_P to Dn_P.

[0116] Negative thermometer codes D1_N to Dn_N are input to the gates of inverters INVN1 to INVNn via level shifters LSN1 to LSNn. A voltage Vn generated at a connection node Nn between multiple resistors RN1 to RNn is proportional to the value (the number of 1s) of the thermometer codes D1_N to Dn_N.

[0117] An operational amplifier OA41 and resistors R42 and R43 form an inverting amplifier, which inverts the voltage Vn to generate a voltage Vn_b.

[0118] Resistors R41, R44, and R45 and operational amplifier OA42 form an inverting adder that adds and inverts and amplifies voltages Vn_b and Vp, and outputs output voltage V DAC Generate.

[0119] 15 is a diagram showing another example configuration (400C) of the D / A converter 320. The D / A converter 400 is a current summing type, and includes a bias transistor M0, multiple current sources CS1 to CSn, resistors R51 and R52, and an output stage 470. Differential thermometer codes D1 to Dn are input to the D / A converter 400C.

[0120] The i-th current source CS includes a differential pair and a transistor Mi serving as a tail current source. The transistors M1 to Mn form a current mirror circuit with the transistor M0 as its input. The drain of the transistor M0 is connected to a volume setting terminal FILA. A bias signal VBIAS is supplied to the volume setting terminal FILA. The current flowing through the transistors M0 to Mn can be set according to the bias signal VBIAS.

[0121] The first terminals of resistors R51 and R52 are connected to a reference voltage V FILP is supplied. One drain (on the left side in the drawing) of the differential pair of current sources CS1 to CSn is connected to the second end of resistor R51, and the other drain (on the right side in the drawing) of the differential pair is connected to the second end of resistor R52.

[0122] The output stage 470 outputs a voltage V corresponding to the difference between the voltages Vn and Vp at the second terminals of the resistors R51 and R52. DAC The configuration of output stage 470 is not particularly limited, but may include, for example, a capacitor C51, resistors R53 to R7, a reference voltage source 472, and operational amplifiers OA51 and OA52.

[0123] The operational amplifier OA51 and resistors R53 and R54 form an inverting amplifier, which inverts and amplifies the voltage Vn and outputs the voltage Vn_b.

[0124] The operational amplifier OA52 and resistors R55 to R57 form an inverting summing amplifier, which sums and inverts and amplifies the voltages Vp and Vn_b, resulting in the output voltage V of the D / A converter 400C. DAC Generate.

[0125] (Application) The following describes the use of the audio circuit 300. Fig. 16 is a block diagram of an in-vehicle audio system that uses the audio circuit according to the embodiment.

[0126] The in-car audio system 500 includes four speakers 502. FL ,502 FR ,502 RL ,502RR , 4 filters 504 FL ,504 FR ,504 RL ,504 RR , a sound source 506 and an audio circuit 300 .

[0127] The sound source 106 outputs a two-channel (left and right) or multi-channel digital audio signal. The audio circuit 300 includes a four-channel class-D amplifier circuit 200 and an interface circuit 301 with the sound source 106. The interface circuit 301 can be associated with the digital audio interface circuit 330 and the D / A converter 320 in FIG. 3.

[0128] The filter 504, the sound source 506, and the audio circuit 300 are built into an audio head unit or a car navigation device, or the audio circuit 300 may be a product independent of the sound source 106.

[0129] 17(a) and 17(b) are diagrams showing electronic devices using the audio circuit according to the embodiment. The electronic device in Fig. 17(a) is a display device 600 such as a television. The display device 600 includes speakers 602L and 602R, filters 604L and 604R, a sound source 606, the audio circuit 300, and a display panel 610.

[0130] 17(b) is an audio component device 800. The audio component device 800 includes an audio signal processing circuit 806 corresponding to a sound source, an audio circuit 300, and a filter (not shown). The audio circuit 300 drives speakers 802L and 802R connected via a speaker cable.

[0131] The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of the components and the processing steps. Such modifications will be described below.

[0132] Although the embodiment has been described with reference to a half-bridge type Class D amplifier, the present invention can also be applied to a full-bridge type (BTL: Bridge-Tied Load) Class D amplifier, in which case the DC blocking capacitor of the low-pass filter 104 is not required. Furthermore, a full-bridge type Class D amplifier may employ a filterless modulation method in which the low-pass filter 104 is omitted. [Industrial Applicability]

[0133] The present disclosure can be used in audio devices. [Explanation of symbols]

[0134] 100 Audio System 102 Speaker 104 filters 106 sound sources 300 Audio Circuit VCC power pin FILA volume setting pin 200 Class D amplifier circuits 210 Integrator 212 Error Amplifier 220 Periodic Voltage Generator Circuit 230 PWM Comparator 240 Bridge Circuit 250 Driver 310 Bias Circuit 320 D / A converter 330 Digital Audio Interface Circuit 400 D / A converter

Claims

1. A volume setting pin that receives an analog voltage; a power supply pin for receiving a power supply voltage; a bias circuit that generates a first reference voltage according to the analog voltage; a D / A converter that converts a digital audio signal into an analog audio signal, wherein a voltage width of the analog audio signal corresponding to 1 LSB (Least Significant Bit) of the digital audio signal is variable in accordance with the first reference voltage; a class D amplifier circuit that outputs an output pulse signal having a duty cycle corresponding to the analog audio signal output by the D / A converter and having an amplitude corresponding to the power supply voltage; Equipped with The class D amplifier circuit comprises: an integrator receiving the analog audio signal and the output pulse signal; a periodic voltage generating circuit that generates a periodic voltage of a triangular wave or a sawtooth wave; a PWM (Pulse Width Modulation) comparator that compares the output of the integrator with the periodic voltage; A bridge circuit; a driver that drives the bridge circuit in response to an output of the PWM comparator; Equipped with the bias circuit further generates a second reference voltage obtained by dividing the first reference voltage and the power supply voltage; The second reference voltage is supplied to the integrator.

2. The bias circuit a first resistor provided between the volume setting pin and the power supply pin; a second resistor provided between the volume setting pin and ground; 2. The audio circuit of claim 1, comprising:

3. 2. The audio circuit according to claim 1, wherein the periodic voltage generating circuit generates the periodic voltage with the second reference voltage as a midpoint level.

4. 4. The audio circuit according to claim 1, wherein the audio circuit is monolithically integrated on a single substrate.

5. A speaker and an audio circuit according to any one of claims 1 to 4 that drives the speaker; An in-car audio system comprising:

6. An electronic device comprising the audio circuit according to any one of claims 1 to 4.

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