Analog-to-Digital Converter

Abstract

To improve sensitivity while suppressing quantization errors.SOLUTION: An AD converter (1) comprises: a charging circuit (2) that has a capacitance (C1) charged with electric charges depending on an input current (Iin); a discharging circuit (3) for discharging the electric charges charged in the capacitance (C1); a counting circuit (4) that counts the number of times of charging / discharging the capacitance (C1); and a random PWM circuit (6) that generates a random PWM signal (S1) for changing an opening and closing time of a switch (SW2) of the discharging circuit (3).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an integral analog-to-digital converter circuit. [Background technology]

[0002] Liquid crystal panels in mobile phones, digital cameras, and the like are equipped with illuminance sensors to control the amount of light emitted by the liquid crystal backlight according to the illuminance of ambient light. Liquid crystal panels mounted on mobile phones and the like use proximity sensors to turn off the display when a face approaches, in order to reduce power consumption. These mobile devices are designed with a filter over the sensor to make it invisible from the outside, reducing the amount of light incident on the sensor. Therefore, there is a need for illuminance sensors that can measure even lower illuminance levels, and proximity sensors that can detect with a very small input signal. Therefore, there has been a demand for analog-to-digital converters, such as those described in Patent Document 1, that can measure current with high accuracy and have a small circuit scale.

[0003] FIG. 10 is a circuit diagram of a conventional analog-to-digital converter 91.

[0004] The analog-to-digital converter 91 generally includes a charging circuit 92, a comparing circuit 95, a counting circuit 94, and a discharging circuit 93. The charging circuit 92 includes a capacitor C1 and a differential amplifier AMP1. The comparing circuit 95 includes a comparator CMP1, a switch SW1, and a voltage source 85. The voltage source 85 outputs a reference voltage Vref. The counting circuit 94 includes a D flip-flop 81 and a counter 82. The discharging circuit 93 includes a current source 83 and a switch SW2.

[0005] FIG. 11 is a waveform diagram showing the operation timing of the analog-to-digital converter 91. At the start of operation, a low-level signal is input to switch SW1, closing it. As a result, the output signal Vsig of the charging circuit 92, which is an integrating circuit, is equal to the reference voltage vref. During the conversion period tconv, a high-level signal is input to switch SW1, turning it off, causing the input current Iin to charge the capacitor C1, and analog-to-digital conversion is performed. The detailed operation of the analog-to-digital converter 91 is described below.

[0006] First, in synchronization with the rising edge of the clock signal clk, the precharge signal to the switch SW2 of the discharge circuit 93 is set to high (precharge) to turn on the switch SW2, thereby discharging the fixed charge in the capacitance C1 and performing a precharge operation in which the output signal Vsig decreases.

[0007] Then, in synchronization with the next rising edge of the clock signal clk, the precharge signal goes low and the switch SW2 turns off. Thereafter, the charging circuit 92 (integrator), which is an integrating circuit, is charged by the input current Iin, and when the output signal Vsig of the charging circuit 92 increases and exceeds the reference voltage vref, the comparison signal comp output from the comparison circuit 95 goes high. The comparison signal comp is sampled by the D flip-flop 81, and the charge signal charge output from the D flip-flop 81 to the switch SW2 and counter 12 goes high.

[0008] While the charge signal charge output to the switch SW2 is high, the switch SW2 is turned on, discharging the charge stored in the capacitor C1 of the charging circuit 92. As a result, the output signal vsig of the charging circuit 25 decreases.

[0009] When the charge signal charge output to switch SW2 goes low, switch SW2 turns off, the input current Iin charges, and the output signal Vsig rises. When the output signal Vsig exceeds the reference voltage Vref, the comparison signal comp and charge signal charge go high, turning on switch SW2 and lowering the output signal Vsig.

[0010] The analog-to-digital converter 91 repeats the above-described operation, and during the conversion period tconv when the switch SW1 is turned off, the counter 82 counts the number of discharges count of the discharge circuit 93, thereby making it possible to output a digital value ADCOUT corresponding to the input current Iin.

[0011] The analog-to-digital converter 91 operates so that the amount of charge charged by the input current Iin is equal to the amount of charge discharged by the current I flowing through the discharge circuit 93. Therefore, the amount of charge charged = the amount of charge discharged is expressed by the following equation (2): Iin×tconv=I×tclk×count…(2) It is shown as follows. From the above equation (2), the following equation (3) count=(Iin×tconv) / (I×tclk)…(3) is derived.

[0012] Here, tclk is the cycle of the clock signal clk, tconv is the conversion period during which charging is performed by the input current Iin, I is the reference current value, and count is the number of times the discharge circuit 93 discharges.

[0013] The minimum resolution is determined by (I x tclk).

[0014] The conversion period tconv is calculated using the following equation (4): tconv=tclk×2 n (n is resolution)…(4) If we set it so that count=Iin / I×2 n …(5) is derived.

[0015] For example, when the resolution n=16 bits, the counter 82 outputs a value corresponding to the input current Iin in the range of 0 to 65535. This allows the integral analog-to-digital converter 91 to perform analog-to-digital conversion with a wide dynamic range and high resolution.

[0016] Furthermore, in order to reduce quantization errors when performing signal processing using an n-bit quantized signal obtained by quantizing a continuous signal using an analog-to-digital converter, a method for reducing quantization errors is known in which a noise signal of an arbitrary number of bits m is randomly added within a predetermined region using an adding means within the gradation width of the quantized signal quantized by the analog-to-digital converter (Patent Document 2). [Prior art documents] [Patent documents]

[0017] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-104656 [Patent Document 2] Japanese Patent Application Publication No. 05-75862 Summary of the Invention [Problem to be solved by the invention]

[0018] In recent years, smartphones have tended to have larger screens, with full-screen displays becoming more common. Also, the adoption of OLED (Organic Light Emitting Diode) displays is increasing. Because OLED displays have the property of transmitting light (typically a transmittance of about 3-5%), installing a light sensor on the back of the display can contribute to full-screen displays.

[0019] Optical sensors used in applications such as being installed on the back of a display must detect subtle changes in illuminance caused by external light passing through the back of the display, so they require higher sensitivity than conventional sensors. Possible ways to improve the sensitivity of optical sensors are to increase the area of ​​the optical sensor's photodiode (PD) or the sensitivity of the optical sensor's AD converter circuit, but increasing the PD area increases the optical sensor's chip size, raising the issue of increased costs. Increasing the sensitivity of the AD converter circuit also increases noise components, which, combined with the suppression of signal components by the display's transmittance, leads to the issue of a worsening S / N ratio.

[0020] To solve these problems, the measurement results of the optical sensor can be added sequentially. For example, adding the results of two measurements makes it possible to achieve twice the sensitivity.

[0021] However, simply adding up the measurement results of the optical sensors poses a problem in that the error that occurs during quantization (quantization error) is also amplified.

[0022] In the configuration of Patent Document 2, it is necessary to provide a separate adding means to reduce quantization errors, which makes the configuration complicated.

[0023] An object of one embodiment of the present invention is to provide an analog-to-digital converter that can provide an optical sensor that can suppress quantization errors and improve sensitivity with a simple configuration. [Means for solving the problem]

[0024] In order to solve the above problem, an analog-digital converter according to one embodiment of the present invention is an integral type analog-digital converter comprising: a charging circuit having a capacitance to which an electric charge corresponding to an input current is charged; a discharging circuit for discharging the electric charge charged to the capacitance; and a counting circuit for converting the current value of the input current into a digital value by counting the number of times the capacitance is charged and discharged in a first conversion period and a second conversion period, wherein the first conversion period includes a first pre-charge period and a first count period, and the second conversion period includes a second pre-charge period and a second count period, and further comprising a phase changing circuit for changing a first phase of an output signal of the charging circuit in the first count period to a second phase in the second count period.

[0025] In order to solve the above problem, another analog-digital converter according to one embodiment of the present invention is an integral type analog-digital converter including: a charging circuit having a capacitance to which an electric charge corresponding to an input current is charged; a discharging circuit for discharging the electric charge charged to the capacitance; and a counting circuit for converting the current value of the input current into a digital value by counting the number of times the capacitance is charged and discharged during a first conversion period and a second conversion period, wherein the first conversion period includes a first pre-charge period and a first count period, the second conversion period includes a second pre-charge period and a second count period, the discharging circuit has a switch provided for discharging the electric charge charged to the capacitance, and further includes a random pulse width modulation circuit provided for generating a random pulse width modulation signal for changing the opening and closing times of the switch during the first and second pre-charge periods. [Effects of the Invention]

[0026] According to one embodiment of the present invention, it is possible to realize an analog-to-digital converter that can provide an optical sensor that can suppress quantization errors and improve sensitivity with a simple configuration. [Brief explanation of the drawings]

[0027] [Figure 1]1 is a circuit diagram of an analog-to-digital converter according to a first embodiment. [Figure 2] FIG. 10 is a waveform diagram for explaining an output signal of a charging circuit according to a comparative example. [Figure 3] 5 is a waveform diagram for explaining an output signal of a charging circuit provided in the analog-to-digital converter. FIG. [Figure 4] FIG. 2 is a circuit diagram of a random pulse width modulation circuit provided in the analog-to-digital converter. [Figure 5] FIG. 2 is a circuit diagram of a random pulse width modulation signal generating circuit provided in the random pulse width modulation circuit. [Figure 6] 4 is a waveform diagram showing the operation timing of the random pulse width modulation signal generating circuit. FIG. [Figure 7] 10 is a graph showing simulation results of the random pulse width modulation signal. [Figure 8] FIG. 10 is a circuit diagram of an analog-to-digital converter according to a second embodiment. [Figure 9] 5 is a waveform diagram for explaining an output signal of a charging circuit provided in the analog-to-digital converter. FIG. [Figure 10] FIG. 1 is a circuit diagram of a conventional analog-to-digital converter. [Figure 11] 3 is a waveform diagram showing operation timings of the analog-to-digital converter. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] [Embodiment 1] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described in detail. Fig. 1 is a circuit diagram of an analog-to-digital converter 1 according to the first embodiment.

[0029] The integral analog-to-digital converter 1 includes a charging circuit 2 having a capacitance C1 that is charged with an electric charge corresponding to the input current Iin, a discharging circuit 3 for discharging the electric charge stored in the capacitance C1, and a counting circuit 4 that converts the current value of the input current Iin into a digital value by counting the number of times the capacitance C1 is charged and discharged during a first conversion period and a second conversion period.

[0030] The first conversion period includes a first precharge period and a first count period, and the second conversion period includes a second precharge period and a second count period.

[0031] The analog-to-digital converter 1 further includes a random pulse width modulation circuit 6 (phase change circuit) that changes the first phase of the output signal Vsig of the charging circuit 2 in the first count period to a second phase in the second count period.

[0032] The random pulse width modulation circuit 6 randomly changes the first phase of the output signal Vsig to the second phase.

[0033] The count circuit 4 converts the current value of the input current Iin into a digital value by performing arithmetic processing on the count value in the first conversion period and the count value in the second conversion period. The arithmetic processing includes averaging, root-mean-square processing, and addition processing.

[0034] The discharge circuit 3 has a switch SW2 provided to discharge the charge stored in the capacitor C1. The random pulse width modulation circuit 6 is provided to generate a random pulse width modulation signal S1 for changing the opening and closing times of the switch SW2 during the first precharge period and the second precharge period.

[0035] The random pulse width modulation signal S1 randomly changes the opening and closing times of the switch SW2.

[0036] The charging circuit 2 includes a differential amplifier 18. The analog-to-digital converter 1 includes a comparison circuit 5. The comparison circuit 5 includes a comparator 19, a voltage source 15, and a switch control circuit 16.

[0037] In the analog-digital converter 1 according to the first embodiment, similarly to the analog-digital converter 91 described in the conventional example, a precharge signal is applied to the switch SW2 during the precharge period to turn on the switch SW2, thereby discharging a certain amount of charge in the capacitor C1 and performing a precharge operation to decrease the output signal Vsig. Thereafter, during the count period, charging is performed with the input current Iin to be measured, and the count circuit 4 counts the number of discharges by the discharge circuit 3.

[0038] Generally, analog-to-digital converters contain quantization errors. The occurrence of quantization errors in the analog-to-digital converter 1 according to the first embodiment will be briefly described below.

[0039] FIG. 2 is a waveform diagram for explaining the output signal Vsig of the charging circuit according to the comparative example.

[0040] FIG. 2 shows the waveform of the output signal Vsig when the value of the input current Iin is changed. The waveform Vsig_a is the waveform when the input current Iin=Iin1 flows, and is shown by a solid line in FIG.

[0041] The conversion period tconv includes a precharge period tpre and a count period tcnt.

[0042] Since the waveform Vsig_a exceeds the reference voltage Vref four times within the count period tcnt, the count by the count circuit 4 becomes four.

[0043] The waveform Vsig_c is the waveform when an input current Iin3 smaller than Iin1 flows, and is shown by the dashed line in Figure 2. The count is 3 because the reference voltage vref is exceeded three times within the count period tcnt.

[0044] Here, the dashed line shows the waveform vsig_b when the input current is Iin2, which is smaller than Iin1 but larger than Iin3 (Iin1>Iin2>Iin3). The waveform vsig_b exceeds the reference voltage vref four times within the count period tcnt, so the count is 4, just like in the case of Iin1.

[0045] In this way, there are cases where the count value does not decrease even though the input current Iin is decreasing. This is the quantization error of the analog-to-digital converter.

[0046] The analog-to-digital converter 1 according to this embodiment includes a random pulse width modulation circuit 6 that randomly changes the pulse width of the precharge signal applied to the switch SW2 during the precharge period tpre (first precharge period, second precharge period) in order to reduce quantization error and improve resolution.

[0047] 3 is a waveform diagram for explaining the output signal Vsig of the charging circuit 2 provided in the analog-to-digital converter 1. This Fig. 3 corresponds to a timing diagram when the duty of the random pulse width modulation signal S1 during the count period tcnt is set to 100%.

[0048] The timing when the pulse width of the precharge signal is changed is shown in Figure 3. For simplicity, three timings will be explained.

[0049] Figure 3 shows waveforms charge_sw2_bb·charge_sw2_bf obtained by changing the pulse width of the precharge signal waveform charge_sw2_b corresponding to the waveform Vsig_b shown in Figure 2, which has a count of 4. The precharge signal charge_sw2_bb is a signal obtained by shortening the pulse width and advancing the timing of the precharge signal waveform charge_sw2_b of the waveform Vsig_b shown in Figure 3, while the precharge signal charge_sw2_bf is a signal obtained by lengthening the pulse width and delaying the timing. The waveform Vsig_bb of the output signal Vsig corresponding to the precharge signal charge_sw2_bb is shown by a solid line. The waveform Vsig_b of the output signal Vsig corresponding to the precharge signal charge_sw2_b is shown by a dashed line. The waveform Vsig_bf of the output signal Vsig corresponding to the precharge signal charge_sw2_bf is shown by a dashed line.

[0050] While the count of the waveform Vsig_b is 4, the count of the waveform Vsig_bb remains at 4. In contrast, the count of the waveform Vsig_bf becomes 3. From this, it can be seen that the count value of the waveform Vsig_b is 4, which is close to 3.

[0051] Since 1 clock = 1 count, by controlling the pulse width of the precharge signals charge_sw2_b, charge_sw2_bb, and charge_sw2_bf to 1 clock of the clock signal CLK or less, a phase shift of 1 count or less can be generated.

[0052] In this way, the pulse width of the precharge signal applied to switch SW2 during the precharge period tpre is changed to change the timing (changing the phase of the output signal Vsig), and the measurement operation is repeated during the count period tcnt (first count period, second count period). For example, the timing of the precharge signal is changed and measurements are performed during 10 conversion periods tconv (first conversion period, second conversion period). If the count is 3 all 10 times, the count value is 3. However, if 8 out of 10 times are 3 and 2 out of 10 times are 4, the count value is 3.2. If 5 out of 10 times are 3 and 5 out of 10 times are 4, the count value can be 3.5. This makes it possible to reduce the quantization error to 1 / 10 and increase the resolution by 10 times.

[0053] It is desirable to change the timing of the precharge signal randomly. By changing it randomly, it is possible to prevent the measurement results from tending to shift in a certain direction depending on the number of measurements of the conversion period tconv and the change in the timing of the precharge signal. In this way, by changing the sampling timing of the precharge signal randomly, it is possible to reduce quantization errors.

[0054] The analog-to-digital converter 1 includes a selector 17. The selector 17 is configured by a logical product circuit (AND circuit) and outputs a signal charge_sw2 for connecting the switch SW2 when the charge signal charge=1 and the random pulse width modulation signal S1=1.

[0055] Fig. 4 is a circuit diagram of the random pulse width modulation circuit 6 provided in the analog-to-digital converter 1. Fig. 5 is a circuit diagram of the clock signal and random pulse width modulation signal generation circuit 8 provided in the random pulse width modulation circuit 6. Fig. 6 is a waveform diagram showing the operation timing of the clock signal and random pulse width modulation signal generation circuit 8. Fig. 7 is a graph showing the simulation results of the random pulse width modulation signal S1.

[0056] The random pulse width modulation circuit 6 is composed of a random generation circuit 14 that generates a random signal, a selection circuit 10 that selects one of a plurality of reference voltage setting signals based on the random signal generated by the random generation circuit 14, a PWM (pulse width modulation) reference voltage generation circuit 9 that generates a pulse width reference voltage VREF_PWM based on the reference voltage setting signal selected by the selection circuit 10, and a clock signal and random pulse width modulation signal generation circuit 8 that generates a clock signal CLK and a random pulse width modulation signal S1 based on the pulse width reference voltage VREF_PWM generated by the reference voltage generation circuit 9. The random generation circuit 14, the selection circuit 10, and the PWM reference voltage generation circuit 9 (DA converter) are general circuits, so detailed description thereof will be omitted here.

[0057] The random pulse width modulation circuit 6 configured as above operates as follows.

[0058] 6, at time t1, a pre-charge signal Pre-Charge is input to the selection circuit 10, causing one of the reference voltage setting signals to be randomly selected by the selection circuit 10. Then, the reference voltage generation circuit 9 generates a pulse width reference voltage VREF_PWM based on the reference voltage setting signal selected by the selection circuit 10, and supplies the generated voltage to the clock signal and random pulse width modulation signal generation circuit 8.

[0059] In the example shown in FIGS. 5 and 6, a pulse width reference voltage VREF_PWM of 0.2 V is supplied to the clock signal and random pulse width modulation signal generating circuit 8.

[0060] After the signal EN goes high at time t1, the charge signals Charge1 and Charge2 are repeatedly output. The high period (pulse width W1) of the random pulse width modulation signal S1 occurs between time t2 when the charge signal Charge1 reaches the reference voltage VREF (0.4 V in this case) of the comparator CMP1 and time t3 when the charge signal Charge2 reaches the pulse width reference voltage VREF_PWM (0.2 V in this case) selected above.

[0061] The clock signal and random pulse width modulation signal generation circuit 8 outputs a clock signal CLK with a duty of 50%. When the reference voltage VREF of the clock unit that outputs the clock signal CLK is 0.4 V, the duty of the random pulse width modulation signal S1 is Duty = VREF_PWM / VREF × 50% when Duty_100 = 0. When Duty_100 = 1, Duty = 100% (independent of the pulse width reference voltage VREF_PWM).

[0062] The period of the random pulse width modulation signal S1 is the same as the period of the clock signal CLK. The pulse width (duty) of the random pulse width modulation signal S1 is adjusted by the pulse width reference voltage VREF_PWM.

[0063] The random pulse width modulation signal S1 generated by the clock signal and random pulse width modulation signal generation circuit 8 becomes the precharge signal applied to the switch SW2 during the precharge period tpre1, and the counting operation of the number of times the capacitor C1 is charged and discharged is started during the count period tcnt1 following the precharge period tpre1.

[0064] In the example shown in FIG. 6, after multiple measurements are performed during the count period tcnt1 of the conversion period tconv1, the pre-charge signal Pre-Charge is input again to the selection circuit 10 at time t4 to change the pulse width reference voltage VREF_PWM (for example, from 0.2 V to 0.10 V), and the pulse width of the random pulse width modulation signal S1 is shortened from pulse width W1 to pulse width W2.

[0065] In the example of FIG. 6, two conversion periods, tconv1 and tconv2, are performed consecutively, and the measurement results in the conversion period tconv1 and the measurement results in the conversion period tconv2 are added together to improve measurement sensitivity.

[0066] However, if the conversion periods tconv1 and tconv2 are measured under the same conditions, a quantization error occurs. Therefore, the pulse width of the random pulse-width modulation signal S1 is changed randomly by randomly changing the pulse width reference voltage VREF_PWM during the precharge periods tpre1 and tpre2, thereby reducing the quantization error.

[0067] Only the pulse width of the random pulse width modulation signal S1 changes between the conversion period tconv1 and the conversion period tconv2, and it is necessary to operate under the same conditions between the count period tcnt1 and the count period tcnt2.

[0068] FIG. 6 shows the relationship between the pulse width reference voltage VREF_PWM and the duty of the random pulse width modulation signal S1. Precharge period tpre1: pulse width reference voltage VREF_PWM=0.15V → duty of random pulse width modulation signal S1=18.75%, Count period tcnt1: Pulse width reference voltage VREF_PWM = 0.40V → Duty of random pulse width modulation signal S1 = 50%, Precharge period tpre2: Pulse width reference voltage VREF_PWM=0.10V → Duty of random pulse width modulation signal S1=12.5%, Count period tcnt2: Pulse width reference voltage VREF_PWM = 0.04V → Duty of random pulse width modulation signal S1 = 50%, This is an explanatory diagram of what happens when the signal changes as shown below.

[0069] 5 and 6 show examples of circuits for outputting a signal in which the pulse width of the random pulse width modulation signal S1 is set to 50% or less of the pulse width of the clock with the same period.

[0070] In this way, by changing the pulse width of the random pulse width modulation signal S1, measuring multiple times, and averaging the count values, it is possible to improve the accuracy of the analog-to-digital converter 1. Instead of averaging, root mean square processing or addition processing may be performed.

[0071] [Embodiment 2] Other embodiments of the present invention will be described below. For ease of explanation, the same reference numerals will be used to designate components having the same functions as those described in the above embodiment, and the description thereof will not be repeated.

[0072] Fig. 8 is a circuit diagram of an analog-digital converter 1A according to embodiment 2. Fig. 9 is a waveform diagram for explaining the output signal Vsig of the charging circuit 2 provided in the analog-digital converter 1A. Components similar to those described above are given the same reference numerals, and detailed description of these components will not be repeated.

[0073] In the first embodiment, the quantization error is reduced by changing the pulse width of the random pulse width modulation signal S1 applied to the switch SW2 during the precharge period tpre. However, what actually contributes to the reduction of the quantization error is that the period of the output signal Vsig remains the same but the phase changes randomly.

[0074] When this point is taken into consideration, it is possible to produce a similar effect by changing the voltage of the reference voltage Vref, as shown in FIGS.

[0075] The analog-to-digital converter 1A includes a comparison circuit 5A. The comparison circuit 5A includes a voltage source 15A including a variable power supply, and a reference voltage value change circuit 7 that changes the value of the reference voltage supplied to the comparator 19 from the voltage source 15A.

[0076] The waveform Vsig_vref1 is a waveform when the value of the reference voltage Vref is set to a voltage value Vref1 (first voltage value), the waveform Vsig_vref2 is a waveform when the value of the reference voltage Vref is set to a voltage value Vref2 (second voltage value), and the waveform Vsig_vref3 is a waveform when the value of the reference voltage Vref is set to a voltage value Vref3 (Vref3 <Vref2<Vref1)。

[0077] The precharge signal is a random pulse width modulation signal S1, which is common to the waveforms Vsig_vref1, Vsig_vref2, and Vsig_vref3, so the voltage drop caused by the discharge circuit 3 is the same for all three waveforms. The voltage rise is caused by the common current Iin, so the rising angle is also the same for all three waveforms.

[0078] The waveform Vsig_vref3 (solid line) falls after exceeding the voltage value Vref3. The waveform Vsig_vref2 (dashed line) falls after exceeding the voltage value Vref2. The waveform Vsig_vref1 (dashed line) falls after exceeding the voltage value Vref1.

[0079] The voltage falls during the count period tcnt when the signal charge_sw2 based on the charge signal charge is applied to the switch SW2. Since this time is common to all three waveforms, the voltage drop is the same, and since the discharged charge is also the same for all three waveforms, the time it takes to charge again is also the same.

[0080] In this way, since the charging and discharging periods are the same after the reference voltage Vref is exceeded once, the waveforms Vsig_vref1, Vsig_vref2, and Vsig_vref3 have the same cycle.

[0081] In this way, the analog-to-digital converter 1A further includes a comparison circuit 5A that compares the output signal V-sig of the charging circuit 2 with the reference voltage Vref. The reference voltage value change circuit 7 (phase change circuit) of the comparison circuit 5A changes the voltage value Vref1 (first voltage value) of the reference voltage Vref in the count period tcnt (first count period) to a voltage value Vref2 (second voltage value) in another count period tcnt (second count period).

[0082] 〔summary〕 An analog-digital converter 1·1A according to a first aspect of the present invention is an integral analog-digital converter 1·1A comprising: a charging circuit 2 having a capacitance C1 to which an electric charge corresponding to an input current Iin is charged; a discharging circuit 3 for discharging the electric charge stored in the capacitance C1; and a counting circuit 4 for converting the current value of the input current Iin into a digital value by counting the number of times the capacitance C1 is charged and discharged during a first conversion period and a second conversion period (conversion period tconv), wherein the first conversion period (conversion period tconv) includes a first pre-charge period (pre-charge period tpre) and a first count period (count period tcnt), the second conversion period (conversion period tconv) includes a second pre-charge period (pre-charge period tpre) and a second count period (count period tcnt), and the converter further comprises a phase changing circuit (random pulse width modulation circuit 6, reference voltage value changing circuit 7) for changing the first phase of the output signal Vsig of the charging circuit 2 during the first count period (count period tcnt) to a second phase during the second count period (count period tcnt).

[0083] According to the above configuration, the first phase of the output signal of the charging circuit during the first count period is changed to the second phase during the second count period. As a result, the phase of the output signal of the charging circuit changes depending on the count period. Therefore, it is possible to improve sensitivity while suppressing quantization error of the analog-to-digital converter.

[0084] In the analog-to-digital converter 1·1A according to aspect 2 of the present invention, in the above aspect 1, it is preferable that the phase change circuit (random pulse width modulation circuit 6, reference voltage value change circuit 7) randomly changes the first phase to the second phase.

[0085] According to the above configuration, by changing the timing randomly, it is possible to prevent the measurement results from tending to shift in a certain direction due to the number of measurements in the conversion period and the change in the timing of the precharge signal.

[0086] In the analog-to-digital converter 1·1A according to aspect 3 of the present invention, in the above aspect 2, it is preferable that the count circuit 4 converts the current value of the input current Iin into a digital value by performing arithmetic processing on the count value in the first conversion period (conversion period tconv) and the count value in the second conversion period (conversion period tconv).

[0087] According to the above configuration, the accuracy of analog-to-digital conversion can be improved by performing arithmetic processing on the count values ​​counted multiple times.

[0088] It is preferable that the analog-to-digital converter 1A according to aspect 4 of the present invention, in any one of aspects 1 to 3 above, further includes a comparison circuit 5 that compares the output signal Vsig of the charging circuit 2 with a reference voltage Vref, and that the phase change circuit includes a reference voltage value change circuit 7 that changes a first voltage value (voltage value Vref1) of the reference voltage Vref during the first count period (tcnt) to a second voltage value Vref2 during the second count period (tcnt).

[0089] According to the above configuration, the phase of the output signal of the charging circuit can be changed by changing the voltage value of the reference voltage that is compared with the output signal of the charging circuit.

[0090] An analog-digital converter 1 according to a fifth aspect of the present invention is an integral analog-digital converter 1 including: a charging circuit 2 having a capacitance C1 to which an electric charge corresponding to an input current Iin is charged; a discharging circuit 3 for discharging the electric charge charged in the capacitance C1; and a counting circuit 4 for counting the number of times the capacitance C1 is charged and discharged in a first conversion period (conversion period tconv) and a second conversion period (conversion period tconv) to convert the current value of the input current Iin into a digital value, wherein the first conversion period (conversion period tconv) is a first pre-charge period (pre-charge period tpr the second conversion period (conversion period tconv) includes a second pre-charge period (pre-charge period tpre) and a second count period (count period tcnt), the discharge circuit 3 has a switch SW2 provided to discharge the charge stored in the capacitance C1, and further includes a random pulse width modulation circuit 6 provided to generate a random pulse width modulation signal S1 for changing the opening and closing times of the switch SW2 in the first and second pre-charge periods (pre-charge periods tpre).

[0091] According to the above configuration, the open / close times of the switch are changed during the first and second precharge periods. Therefore, the first phase of the output signal from the charging circuit during the first count period is changed to the second phase during the second count period. Therefore, the phase of the output signal from the charging circuit changes depending on the count period. Therefore, it is possible to improve sensitivity while suppressing quantization error of the analog-to-digital converter.

[0092] In the analog-to-digital converter 1 according to a sixth aspect of the present invention, in the fifth aspect, it is preferable that the random pulse width modulation signal S1 randomly changes the opening and closing times of the switch SW2.

[0093] According to the above configuration, by changing the timing randomly, it is possible to prevent the measurement results from tending to shift in a certain direction due to the number of measurements in the conversion period and the change in the timing of the precharge signal.

[0094] In the analog-to-digital converter 1 according to aspect 7 of the present invention, in the above-mentioned aspect 6, it is preferable that the count circuit 4 converts the current value of the input current Iin into a digital value by performing arithmetic processing on the count value in the first conversion period (conversion period tconv) and the count value in the second conversion period (conversion period tconv).

[0095] According to the above configuration, the accuracy of analog-to-digital conversion can be improved by performing arithmetic processing on the count values ​​counted multiple times.

[0096] An analog-to-digital converter 1 according to an eighth aspect of the present invention is preferably the same as in the fifth aspect, except that the random pulse width modulation circuit 6 includes a selection circuit 10 that selects one of the reference voltage setting signals based on a random signal, a reference voltage generation circuit 9 that generates a reference voltage based on the reference voltage setting signal selected by the selection circuit 10, and a random pulse width modulation signal generation circuit (clock signal and random pulse width modulation signal generation circuit 8) that generates the random pulse width modulation signal S1 based on the reference voltage generated by the reference voltage generation circuit 9.

[0097] According to the above configuration, a random pulse width modulation signal that randomly changes the opening and closing times of the switch can be generated based on the random signal.

[0098] In the analog-to-digital converter 1 according to aspect 9 of the present invention, in the above aspect 8, it is preferable that the random pulse width modulation signal generating circuit (clock signal and random pulse width modulation signal generating circuit 8) generates a random pulse width modulation signal having a pulse width according to the voltage value of the reference voltage.

[0099] According to the above configuration, the open / close times of the switch of the discharge circuit in the first and second precharge periods can be changed by a random pulse width modulation signal having a pulse width according to the voltage value of the reference voltage.

[0100] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment. [Explanation of symbols]

[0101] 1 Analog-to-Digital Converter 2 Charging circuit 3 Discharge circuit 4 Counting circuit 5 Comparison circuit 6 Random pulse width modulation circuit (phase change circuit) 7 Reference voltage value change circuit (phase change circuit) 8. Clock signal and random pulse width modulation signal generator (random pulse width modulation signal generator) 9 Reference voltage generation circuit 10 Selection circuit S1 Random pulse width modulated signal C1 capacity SW2 switch Iin Input current Vsig output signal tconv Conversion period (1st conversion period, 2nd conversion period) tpre Precharge period (first precharge period, second precharge period) tcnt Count period (1st count period, 2nd count period) Vref Reference voltage VREF_PWM Pulse width reference voltage W1 Pulse width W2 Pulse width Vref1 voltage value (first voltage value, second voltage value) Vref2 voltage value (first voltage value, second voltage value) Vref3 voltage value (first voltage value, second voltage value)

Claims

1. a charging circuit having a capacitance that is charged with an electric charge according to an input current; a discharge circuit for discharging the charge stored in the capacitor; a count circuit that converts a current value of the input current into a digital value by counting the number of times the capacitance is charged and discharged during a first conversion period and a second conversion period, the first conversion period includes a first precharge period and a first count period; the second conversion period includes a second precharge period and a second count period; a phase change circuit that changes a first phase of an output signal of the charging circuit in the first count period to a second phase in the second count period; The analog-to-digital converter, wherein the phase change circuit randomly changes the first phase to the second phase.

2. An analog-to-digital converter as described in Claim 1, wherein the counting circuit converts the current value of the input current into a digital value by performing arithmetic processing on the count value in the first conversion period and the count value in the second conversion period.

3. A charging circuit having a capacity to be charged with an electric charge according to an input current; a discharge circuit for discharging the charge stored in the capacitor; a count circuit that converts a current value of the input current into a digital value by counting the number of times the capacitance is charged and discharged during a first conversion period and a second conversion period, the first conversion period includes a first precharge period and a first count period; the second conversion period includes a second precharge period and a second count period; a phase change circuit that changes a first phase of an output signal of the charging circuit in the first count period to a second phase in the second count period; an analog-to-digital converter, characterized in that the phase change circuit includes a reference voltage value change circuit that changes a first voltage value of a reference voltage to be compared with the output signal of the charging circuit during the first count period to a second voltage value during the second count period.

4. 4. The analog-to-digital converter according to claim 3, further comprising a comparison circuit that compares the output signal of the charging circuit with the reference voltage.

5. a charging circuit having a capacitance that is charged with an electric charge according to an input current; a discharge circuit for discharging the charge stored in the capacitor; a count circuit that converts a current value of the input current into a digital value by counting the number of times the capacitance is charged and discharged during a first conversion period and a second conversion period, the first conversion period includes a first precharge period and a first count period; the second conversion period includes a second precharge period and a second count period; the discharge circuit has a switch provided for discharging the charge stored in the capacitor, 10. An analog-to-digital converter, further comprising: a random pulse width modulation circuit configured to generate a random pulse width modulation signal for varying the opening and closing times of the switch during the first and second precharge periods.

6. 6. The analog-to-digital converter according to claim 5, wherein the random pulse width modulation signal randomly varies the opening and closing times of the switch.

7. 7. The analog-to-digital converter according to claim 6, wherein the count circuit converts the current value of the input current into a digital value by performing arithmetic processing on the count value in the first conversion period and the count value in the second conversion period.

8. a selection circuit for selecting one of the reference voltage setting signals based on a random signal; a reference voltage generating circuit that generates a reference voltage based on the reference voltage setting signal selected by the selection circuit; 6. The analog-to-digital converter according to claim 5, further comprising a random pulse width modulation signal generating circuit that generates the random pulse width modulation signal based on the reference voltage generated by the reference voltage generating circuit.

9. 9. The analog-to-digital converter according to claim 8, wherein the random pulse width modulation signal generating circuit generates a random pulse width modulation signal having a pulse width corresponding to the voltage value of the reference voltage.

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