Nanosheet transistors with body contacts

Abstract

The semiconductor nanosheet device includes vertically aligned and stacked semiconductor channel layers separated by a work function metal, and a gate dielectric partially surrounding and physically separating the work function metal from each other, with a first portion of the work function metal in direct contact with a vertical sidewall of each layer. The semiconductor device includes first and second sets of vertically aligned and stacked semiconductor channel layers separated by a work function metal, and a gate dielectric partially surrounding and physically separating the work function metal from each other, with a first portion of the work function metal between the first and second sets in direct contact with a sidewall of each layer. The method includes forming a first stack of vertically aligned and stacked alternating layers of a sacrificial layer and a semiconductor channel layer, forming vertical openings to create a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing the vertical sidewalls of the alternating layers of both stacks.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor manufacturing, and more particularly to fabricating nanosheet field effect transistors with dynamic threshold voltage control. [Background technology]

[0002] Complementary metal-oxide semiconductor (CMOS) technology is commonly used for field-effect transistors (hereinafter "FETs") as part of advanced integrated circuits (hereinafter "ICs") such as central processing units (hereinafter "CPUs"), memories, and storage devices. With the continuing demand for reducing transistor device dimensions, nanosheet FETs help achieve a reduced FET device footprint while maintaining FET device performance. A nanosheet FET comprises multiple nanosheets extending between a pair of source / drain epitaxial regions. The device may be a gate-all-around transistor, in which a gate surrounds at least a portion of the nanosheet channel.

[0003] The threshold voltage of an FET is typically determined by the nature of the work function metal composition used in the FET, in conjunction with various other device / material characteristics, including, but not limited to, channel doping, growth conditions of the high-k dielectric, charge distribution within the high-k dielectric, spacing at the high-k / channel interface, and the presence and nature of an interfacial oxide formed between the high-k and the channel. It would be advantageous to fabricate nanosheet FET devices with dynamic threshold voltage control. Summary of the Invention

[0004] According to one embodiment, a semiconductor nanosheet device is provided, comprising vertically aligned semiconductor channel layers stacked on top of each other, the semiconductor channel layers separated from each other by a work function metal, and a gate dielectric layer partially surrounding each of the semiconductor channel layers and physically separating the work function metal from each of the semiconductor channel layers, wherein a first portion of the work function metal is in direct contact with a vertical sidewall of each of the semiconductor channel layers.

[0005] According to one embodiment, a semiconductor device is provided, comprising: a first set of semiconductor channel layers vertically aligned and stacked on top of each other and separated by a work function metal; a second set of semiconductor channel layers adjacent to the first set of semiconductor channel layers, the second set of semiconductor channel layers vertically aligned and stacked on top of each other and separated by a work function metal; and a gate dielectric layer partially surrounding each of the semiconductor channel layers and physically separating the work function metal from each of the semiconductor channel layers, wherein a first portion of the work function metal between the first set of semiconductor channel layers and the second set of semiconductor channel layers is in direct contact with a sidewall of each of the semiconductor channel layers in both the first set of semiconductor channel layers and the second set of semiconductor channel layers.

[0006] According to one embodiment, a method is provided, comprising: forming an initial stack of nanosheet layers on a substrate, the stack of nanosheet layers including alternating layers of vertically aligned sacrificial layers and semiconducting channel layers stacked on top of one another; and forming vertical openings along the length of the initial stack of nanosheet layers to create a first stack of nanosheet layers and a second stack of nanosheet layers, the vertical openings exposing vertical sides of the alternating sacrificial layers and semiconducting channel layers of both the first stack and the second stack.

[0007] Preferred embodiments of the invention will now be described, by way of example only, with reference to the following drawings: [Brief explanation of the drawings]

[0008] [Figure 1] 1A-1C are top views of semiconductor structures at intermediate stages of fabrication in accordance with illustrative embodiments. [Figure 2] 1 along cross section X1-X1, parallel to FIG. 3, according to an exemplary embodiment. [Figure 3] 2 is a cross-sectional view of the semiconductor structure of FIG. 1 along cross section X2-X2, parallel to FIG. 2, according to an exemplary embodiment. [Figure 4] 2 and 3. FIG. 3 is a cross-sectional view of the semiconductor structure of FIG. 1 taken along cross section YY, perpendicular to FIGS. 2 and 3, according to an exemplary embodiment. [Figure 5] 1A-1C are cross-sectional views of semiconductor structures along cross section X1-X1 illustrating selective removal of a layer of semiconductor material according to example embodiments. [Figure 6] 2A-2C are cross-sectional views of semiconductor structures along cross section X2-X2 illustrating selective removal of semiconductor material layers according to example embodiments. [Figure 7] 1A is a cross-sectional view of a semiconductor structure along cross section YY illustrating selective removal of a semiconductor material layer according to an exemplary embodiment. [Figure 8] 1A-1C are cross-sectional views of semiconductor structures along cross section X1-X1 illustrating the formation of a dielectric according to example embodiments. [Figure 9] 2A-2C are cross-sectional views of semiconductor structures along cross section X2-X2 illustrating the formation of a dielectric according to example embodiments. [Figure 10] 3A is a cross-sectional view of a semiconductor structure along cross section YY illustrating the formation of a dielectric according to an exemplary embodiment. FIG. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor structure along cross section X1-X1 illustrating removal of a hard mask, according to an example embodiment. [Figure 12]FIG. 10 is a cross-sectional view of a semiconductor structure along cross section X2-X2 illustrating removal of a hard mask, according to an example embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor structure along cross section YY illustrating removal of a hard mask according to an example embodiment. [Figure 14] 1A-1C are cross-sectional views of a semiconductor structure along cross section X1-X1 illustrating the formation of a sacrificial gate according to an exemplary embodiment. [Figure 15] 2A-2C are cross-sectional views of semiconductor structures along cross section X2-X2 illustrating the formation of a sacrificial gate according to example embodiments. [Figure 16] 1A is a cross-sectional view of a semiconductor structure along cross section YY illustrating the formation of a sacrificial gate according to an exemplary embodiment. [Figure 17] 1A-1C are cross-sectional views of semiconductor structures along cross section X1-X1 illustrating the formation of inner spacers according to example embodiments. [Figure 18] 2A-2C are cross-sectional views of the semiconductor structure along cross section X2-X2 illustrating the formation of inner spacers according to example embodiments. [Figure 19] 1A-1C are cross-sectional views of semiconductor structures along cross section YY illustrating the formation of inner spacers according to example embodiments. [Figure 20] 1A is a cross-sectional view of a semiconductor structure along cross section X1-X1 illustrating removal of a sacrificial gate according to an exemplary embodiment. FIG. [Figure 21] FIG. 2 is a cross-sectional view of a semiconductor structure along cross section X2-X2 illustrating removal of a sacrificial gate according to an exemplary embodiment. [Figure 22] FIG. 10 is a cross-sectional view of a semiconductor structure along cross section YY illustrating removal of a sacrificial gate according to an exemplary embodiment. [Figure 23] 1A-1C are cross-sectional views of a semiconductor structure along cross section X1-X1 illustrating the formation of a high-k liner according to an example embodiment. [Figure 24] 2A-2C are cross-sectional views of semiconductor structures along cross section X2-X2 illustrating the formation of a high-k liner according to example embodiments. [Figure 25] 1A is a cross-sectional view of a semiconductor structure along cross section YY illustrating the formation of a high-k liner according to an example embodiment. [Figure 26] 1A-1C are cross-sectional views of semiconductor structures along cross section X1-X1 illustrating the formation of a work function metal layer according to example embodiments. [Figure 27] 2A-2C are cross-sectional views of semiconductor structures along cross section X2-X2 illustrating the formation of a work function metal layer according to example embodiments. [Figure 28] 3A is a cross-sectional view of a semiconductor structure along cross section YY illustrating the formation of a work function metal layer according to an exemplary embodiment. FIG. [Figure 29] 1A is a cross-sectional view of a semiconductor structure along cross section X1-X1 illustrating partial removal of a work function metal layer according to an example embodiment. [Figure 30] FIG. 2 is a cross-sectional view of a semiconductor structure along cross section X2-X2 illustrating partial removal of a work function metal layer according to an example embodiment. [Figure 31] FIG. 2 is a cross-sectional view of a semiconductor structure along cross section YY illustrating partial removal of a work function metal layer according to an example embodiment. [Figure 32] 1A is a cross-sectional view of a semiconductor structure along cross section X1-X1 illustrating partial removal of a dielectric according to an example embodiment. FIG. [Figure 33] FIG. 2 is a cross-sectional view of a semiconductor structure along cross section X2-X2 illustrating partial removal of a dielectric according to an exemplary embodiment. [Figure 34] FIG. 2 is a cross-sectional view of a semiconductor structure along cross section YY illustrating partial removal of a dielectric according to an example embodiment. [Figure 35] 1A-1C are cross-sectional views of semiconductor structures along cross section X1-X1 illustrating the formation of additional work function metal materials according to example embodiments. [Figure 36] FIG. 10 is a cross-sectional view of a semiconductor structure along cross section X2-X2 illustrating the formation of an additional work function metal material according to an example embodiment. [Figure 37]FIG. 10 is a cross-sectional view of a semiconductor structure along cross section YY illustrating the formation of an additional work function metal material according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to refer to corresponding or analogous features.

[0010] Although detailed embodiments of the claimed structures and methods are disclosed herein, it will be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Throughout the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0011] References in the specification to "one embodiment," "an embodiment," "exemplary embodiment," etc. mean that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in the context of an embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to affect that feature, structure, or characteristic in the context of other embodiments, whether or not explicitly stated.

[0012] When an element, such as a layer, region, or substrate, is referred to as being "on" or "on" another element, it is understood that it may be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly on" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it is understood that it may be directly "connected" or "coupled" to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0013] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of illustration and description, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on the distinctive features or elements of various embodiments of the present invention.

[0014] Nanosheet field-effect transistors (hereafter "FETs") can be formed from alternating layers of silicon and silicon-germanium, which are then formed into nanosheets. Gate-all-around structures can be formed on all vertical sides and the top horizontal surface of the nanosheet cross section. Source-drain structures can be formed at the opposite ends of the nanosheet structure.

[0015] The present invention relates generally to the field of semiconductor manufacturing, and more particularly to fabricating nanosheet FETs with dynamic threshold voltage control.

[0016] The threshold voltage of a nanosheet FET is determined by the nature of the work function metal composition used in the FET, along with various other device / material characteristics, including, but not limited to, channel doping, growth conditions of the high-k dielectric, charge distribution within the high-k dielectric, high-k / channel interfacial spacing, and the presence and nature of interfacial oxides formed between the high-k and channel. In one embodiment, when fabricating a nanosheet FET, all parts of the nanosheet FET may be fabricated simultaneously with the same material, and control of the threshold voltages corresponding to different nanosheet FETs may be managed by using different work function metals for different voltage thresholds.

[0017] Alternating layers of sacrificial semiconductor material and semiconductor channel material may be formed and then formed into a parallel nanosheet stack. A longitudinal opening may be formed in the nanosheet stack, spanning the length of the nanosheet stack and exposing an inner side of the alternating layers of sacrificial semiconductor material and semiconductor channel material of the nanosheet stack. The longitudinal opening divides the nanosheet stack into two nanosheet stacks, each of which is then formed into a transistor. The longitudinal opening is filled with a dielectric. A sacrificial gate may be formed on the nanosheet stack perpendicular to the length of the nanosheet stack. Portions of the nanosheet stack may be removed between adjacent sacrificial gates. Portions of the sacrificial semiconductor material layer of the nanosheet stack, along with lateral portions of the dielectric, may be removed adjacent to where the portions of the nanosheet stack were removed. Internal spacers may be formed where the portions of the sacrificial semiconductor material layer were removed. Sources and drains may be formed at each end of the nanosheet stack. The sacrificial gate may be removed, and the remaining portions of the sacrificial semiconductor material layer of the nanosheet stack may be removed. A gate dielectric or high-k liner may be formed on the exposed surface of the dielectric, surrounding the opening where the sacrificial material layer was removed. A work function metal may be formed to fill the opening where the sacrificial material layer and sacrificial gate were removed. The work function metal may be recessed. A portion of the high-k liner may be removed, exposing the dielectric, and an opening may be formed in the dielectric. The opening in the dielectric may be where the longitudinal opening formed between two adjacent stacks of nanosheets intersects with the location of the gate extending perpendicular to the longitudinal opening. An additional work function metal may be formed within the opening in the dielectric and where the work function metal was recessed. The additional work function metal will have direct contact with the sidewalls of the semiconductor channel material. This direct contact may be referred to as a body contact. The resulting structure may be a gate in direct contact with the nanosheet, extending vertically from the gate over the nanosheet to the separation layer below the nanosheet. This provides direct contact of the nanosheets with the semiconductor channel material layer without a high-k liner between the work function metal and the semiconductor channel material layer.

[0018] This direct contact forms a variable threshold voltage field effect transistor (VTFET), also known as a dynamic threshold voltage FET. As explained above, the threshold voltage of a transistor is set by various device and material characteristics during device fabrication. This threshold voltage is sometimes referred to as the as-fabricated threshold voltage or unbiased threshold voltage. During operation of a variable (dynamic) threshold voltage FET, as the gate potential (and therefore the body potential) is increased, the threshold voltage is lowered below its as-fabricated value. As a result, the drive current of the transistor increases.

[0019] Other advantages of direct contact include maintaining the compactness of the nanosheet design without increasing the device area. Body contacts can also mitigate the floating-body effect associated with partially depleted nanosheet channels.

[0020] Embodiments of the present invention disclose structures and methods for forming nanosheet FETs with dynamic threshold voltage control, which are described in detail below with reference to the accompanying drawings of FIGS. 1-37, according to exemplary embodiments.

[0021] 1-4, a semiconductor structure 100 (hereafter "structure") is shown at an intermediate stage of fabrication, according to an exemplary embodiment. FIG. 1 is a top view of structure 100. FIGS. 2 and 3 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to each other. FIG. 4 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2. Section line YY is parallel to a gate line that will be formed later. Structure 100 of FIGS. 1-4 may be formed or prepared.

[0022] Structure 100 may include alternating layers of sacrificial semiconductor material and semiconductor channel material stacked on top of each other and covered by a hard mask 22 on substrate 10. It should be noted that although a limited number of alternating layers are depicted, any number of alternating layers may be formed.

[0023] Substrate 10 may be a bulk substrate, which may be made from any of several known semiconductor materials, such as, for example, silicon, germanium, silicon-germanium alloys, and composite (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of composite semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium arsenide. Typically, substrate 10 may be, but is not limited to, on the order of several hundred microns thick. In other embodiments, substrate 10 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer separates the base substrate from the top semiconductor layer.

[0024] The alternating layers of sacrificial semiconductor material and semiconductor channel material may include a nanosheet stack sacrificial layer 12 (hereinafter "stack sacrificial layer") on a substrate 10, which is covered by a sacrificial semiconductor material layer 16 (hereinafter "sacrificial layer"), which is covered by a semiconductor channel material layer 18 (hereinafter "channel layer"), which is covered by the sacrificial layer 16, which is covered by the channel layer 18, which is covered by the sacrificial layer 16, which is covered by the channel layer 18, which is covered by the sacrificial layer 16. A hard mask 22 may cover the top sacrificial layer 16.

[0025] The sacrificial stack layer 12 may be, for example, silicon-germanium with a germanium concentration of approximately 60 atomic percent, although percentages higher and lower than 60 percent may also be used. The sacrificial stack layer 12 may be formed using epitaxial growth techniques. The sacrificial stack layer 12 is later removed selectively relative to the remaining alternating layers, as described below.

[0026] The terms "epitaxially grown and / or deposited" and "epitaxially grown and / or deposited" refer to the growth of a semiconductor material on a deposition surface of a semiconductor substrate, where the grown semiconductor material has the same liquid crystalline properties as the semiconductor material on the deposition surface. In epitaxial deposition techniques, chemical reactants provided by source gases are controlled, and system parameters are set such that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to migrate and orient themselves on the deposition surface to the liquid crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same liquid crystalline properties as the deposition surface on which it is formed.

[0027] Examples of various epitaxial growth techniques include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultrahigh vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from approximately 550°C to approximately 900°C. Higher temperatures typically result in faster deposition, but faster deposition can lead to liquid crystal defects and film cracking. Epitaxial growth of the first and second semiconductor materials, which result in the sacrificial and semiconductor channel material layers, respectively, can be performed using any well-known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0028] Each sacrificial layer 16 is composed of a first semiconductor material that is compositionally different from at least the upper portion of substrate 10, channel layer 18, and stack sacrificial layer 12. In one embodiment, each sacrificial layer 16 may be a silicon-germanium semiconductor alloy and may have a germanium concentration of less than 50 atomic percent. In another example, each sacrificial layer 16 may have a germanium concentration ranging from about 20 atomic percent to about 40 atomic percent. Each sacrificial layer 16 may be formed using known deposition or epitaxial growth techniques, such as those described above.

[0029] Each channel layer 18 is made of a second semiconductor material that is compositionally different from at least the upper portion of the substrate 10, the sacrificial layer 16, and the stack sacrificial layer 12. Each channel layer 18 has a different etch rate than the first semiconductor material of the sacrificial layer 16 and a different etch rate than the stack sacrificial layer 12. The sacrificial layer 16 has a different etch rate than the stack sacrificial layer 12. The second semiconductor material may be, for example, silicon. The second semiconductor material may be formed for each channel layer 18 using known deposition or epitaxial growth techniques, such as those described above.

[0030] The alternating layers of sacrificial layers 16 and channel layers 18 and the stack sacrificial layer 12 can be formed by sequential epitaxial growth of alternating layers of nanosheet stack sacrificial layer material and first and second semiconductor materials.

[0031] The stack sacrificial layer 12 may have a thickness in the range of about 5 nm to about 15 nm. The sacrificial layers 16 may each have a thickness in the range of about 5 nm to about 12 nm, and the channel layers 18 may each have a thickness in the range of about 3 nm to about 12 nm. Each sacrificial layer 16 may have a thickness that is the same as or different from the thickness of each channel material layer 18. In one embodiment, each sacrificial layer 16 has the same thickness. In one embodiment, each channel layer 18 has the same thickness.

[0032] A hard mask 22 may be formed on the horizontal upper surfaces of the stack sacrificial layers 12 and alternating layers of sacrificial layers 16 and channel layers 18 by methods known in the art.

[0033] The stack sacrificial layer 12, alternating layers of sacrificial layers 16 and channel layers 18, and hard mask 22 may be formed as a nanosheet stack, with each stack covered by hard mask 22 by patterning the hard mask 22 and then removing portions of each layer to form vertical trenches (not shown). The trenches may be formed between each nanosheet stack by an anisotropic etching technique, such as reactive ion etching (RIE), and stopping the etching of portions of the substrate 10 to subsequently form shallow trench isolation regions (hereinafter "STI") 24 between each nanosheet stack.

[0034] 4, the STI 24 may be formed between adjacent nanosheet stacks in a trench (not shown) between adjacent nanosheet stacks. The STI 24 may be formed on a portion of the vertical side surface of the nanosheet stack.

[0035] The STIs 24 may be a dielectric material and may be formed between adjacent nanosheet stacks using known patterning and deposition techniques. Adjacent nanosheet stacks are separated from each other by the STIs 24. The lower horizontal surface and portions of the side surfaces of the STIs 24 may be adjacent to the lower horizontal surface and vertical side surfaces of the substrate 10. The lower horizontal surface of the STIs 24 may be below the lower horizontal surface of the stack sacrificial layer 12. The vertical side surfaces of the STIs 24 may be adjacent to the vertical side surfaces of the nanosheet stacks, including the vertical side surfaces of the stack sacrificial layer 12, the sacrificial layer 16, the channel layer 18, and the hard mask 22.

[0036] After forming the STIs 24, a chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 100 so that the horizontal top surfaces of the STIs 24 and the hard mask 22 are coplanar.

[0037] Each nanosheet stack may include a stack sacrificial layer 12 covered by alternating layers of sacrificial layers 16 and channel layers 18, which are in turn covered by a hard mask 22. In Figures 1-4, by way of example only, the nanosheet stack includes four sacrificial layers 16 alternating with three channel layers 18. Material stacks that can be used in embodiments of the present invention are not limited to the specific embodiment shown in Figures 1-4. There may be any number of nanosheet stacks on the structure 100.

[0038] The nanosheet stack can include any number of sacrificial layers 16 and channel layers 18. The nanosheet stack is used to fabricate gate-all-around devices containing vertically stacked nanosheets of semiconducting channel material for positive channel field effect transistor (hereinafter "p-FET") or negative channel field effect transistor (hereinafter "n-FET") devices.

[0039] 5-7, structure 100 is shown in accordance with an exemplary embodiment. Figures 5 and 6 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 7 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0040] As shown in Figures 5-7, an organic planarization layer (hereinafter "OPL") 26 may be formed and a first opening 27 formed.

[0041] The OPL 26 is deposited on the hard mask 22 on the nanosheet stack and on the STI 24 surrounding the nanosheet stack. The OPL 26 may be formed by blanket deposition using a typical deposition technique, such as spin-on coating. The OPL 26 may be a self-planarizing organic material containing carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. The first OPL 26 is deposited using a standard C x H yNon-limiting examples of materials include, but are not limited to, CHM701B available from Cheil Chemical Co., Ltd., HM8006 and HM8014 available from JSR Corporation, and ODL-102 or ODL-401 available from Shin-Etsu Chemical Co., Ltd.

[0042] Conventional lithography processes are then used to define the cut-out opening 27. The opening 27 may be made by removing portions of the OPL 26, the hard mask 22, and portions of the nanosheet stack, including portions of the sacrificial layer 16, the channel layer 18, and the stack sacrificial layer 12. The opening 27 may be formed by selectively removing portions of the OPL 26 selective to the hard mask 22 using a combination of etching techniques, which may be performed in multiple steps. The additional removal to form the opening 27 may include removal using an anisotropic etching technique, such as reactive ion etching (RIE), and stopping on the stack sacrificial layer 12 for later formation of a direct contact between the semiconductor channel material and a work function metal within the nanosheet stack. In one embodiment, the lower horizontal portion of the opening 27 includes the remaining portion of the stack sacrificial layer 12.

[0043] An opening 27 may be made along the length of the nanosheet stack along the cross-sectional line of X2-X2, essentially dividing the nanosheet stack in two for later forming direct contact between the semiconducting channel material and the work function metal within the opening 27.

[0044] 8-10, structure 100 is shown in accordance with an exemplary embodiment. Figures 8 and 9 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 10 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0045] As shown in Figures 8-10, a dielectric 28 may be formed within opening 27. Dielectric 28 may be formed by conformally depositing or growing a dielectric within opening 27. Dielectric 28 may include any dielectric material, such as silicon carbide, silicon oxide carbide, or silicon oxide carbon nitride, and may include a single layer or multiple layers of dielectric material. The material used for dielectric 28 may be selected to be capable of being selectively removed relative to both silicon oxide and silicon nitride.

[0046] The dielectric 28 may fill the opening 27. A horizontal lower surface of the dielectric 28 may be adjacent to a horizontal upper surface of the sacrificial stack layer 12 in the opening 27. A vertical side surface of the dielectric 28 may be adjacent to a vertical side surface of a portion of the sacrificial stack layer 12, a vertical side surface of the sacrificial layer 16, a vertical side surface of the channel layer 18, and a vertical side surface of the hard mask 22. A portion of the dielectric 28 may be removed by standard etching so that the horizontal upper surfaces of the dielectric 28 and the hard mask 22 are coplanar.

[0047] 11-13, structure 100 is shown in accordance with an exemplary embodiment. Figures 11 and 12 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 13 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0048] 11-13, the hard mask 22 and portions of the STI 24 may be removed. The hard mask 22 and portions of the STI 24 may be selectively removed using a combination of etching techniques to selectively remove the hard mask 22 and the STI 24 selective to the dielectric 28, the sacrificial stack layer 12, the channel layer 18, and the sacrificial stack layer 16, and may be performed in multiple steps. The remaining portions of the STI 24 may be recessed in the substrate 10. The top surfaces of the remaining portions of the STI 24 may be flush with the horizontal lower surface of the sacrificial stack layer 12.

[0049] Removal of the hard mask 22 and the STI 24 may expose the horizontal top surface of the topmost sacrificial layer 16 of the nanosheet stack and may also expose a portion of the vertical side surface of the dielectric 28 above the nanosheet stack. The vertical side surfaces of the nanosheet stack may be exposed, including the vertical side surfaces of the stack sacrificial layer 12, the channel layer 18, and the stack sacrificial layer 16.

[0050] 14-16, structure 100 is shown in accordance with an exemplary embodiment. Figures 14 and 15 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 16 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0051] 14-16, a sacrificial gate 30 and a gate hard mask 32 may be formed. The sacrificial stack layer 12 may be removed. An isolation layer 36 and side spacers 34 may be formed.

[0052] The sacrificial gate 30 may comprise a single sacrificial material or a stack of one or more sacrificial materials. At least one sacrificial material may be formed by forming a blanket layer(s) of one material (or various materials) and then patterning the material (or various materials) using lithography and etching. The sacrificial gate 30 may comprise any material, including, for example, polysilicon, amorphous silicon, or multilayer combinations thereof. The sacrificial gate 30 may be formed using any deposition technique, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), high-density plasma (HDP) deposition, and spin-on techniques. Optionally, a gate dielectric layer and a gate cap may be formed as part of the sacrificial gate 30 according to known techniques. As shown in FIGS. 14 and 15, there are three sacrificial gates 30. In one embodiment, there may be any number of sacrificial gates 30 formed.

[0053] In one embodiment, the sacrificial gate 30 is deposited to a thickness sufficient to fill or substantially fill the spaces between adjacent nanosheet structures, cover the top and exposed side surfaces of the dielectric 28, and cover the top surface of the top sacrificial layer 16 of the nanosheet stack, as shown in Figure 16. The sacrificial gate 30 may be adjacent to the vertical sides of the nanosheet stack, including the vertical sides of the stack sacrificial layer 12, the channel layer 18, and the stack sacrificial layer 16. The height of the sacrificial gate 30 may be much thicker than the underlying structures and may have a height of between 100 nm and 150 nm around the periphery of the nanosheet stack.

[0054] A gate hard mask 32 may be formed on the upper horizontal surface of the sacrificial gate 30 by methods known in the art. The gate hard mask 32 may have vertical sides that align with the vertical sides of the sacrificial gate 30.

[0055] The sacrificial stack layer 12 may be removed selectively with respect to the sacrificial layer 16, the channel layer 18, the dielectric 28, the sacrificial gate 30, and the gate hard mask 32. For example, a dry etching technique may be used to selectively remove the sacrificial stack layer 12, such as using a gas phase HCl dry etch.

[0056] An isolation layer 36 and side spacers 34 may be formed. The isolation layer 36 may be formed in an opening (not shown) where the stack sacrificial layer 12 has been removed. The isolation layer 36 may be formed between the bottom sacrificial layer 16 of the nanosheet stack and the substrate 10, and between the dielectric 28 and the substrate 10. The side spacers 34 may be formed on both sides of the sacrificial gate 30 and the gate hard mask 32.

[0057] The isolation layer 36 and the side spacers 34 may each be formed after several steps, including, for example, conformally depositing or growing a dielectric and performing an anisotropic etching step. The isolation layer 36 and the side spacers 34 may comprise any dielectric material, such as silicon nitride, and may include a single layer or multiple layers of dielectric material. In one embodiment, the isolation layer 36 and the side spacers 34 may be the same material. The isolation layer 36 and the side spacers 34 may be formed simultaneously or separately.

[0058] 17-19, structure 100 is shown in accordance with an exemplary embodiment. Figures 17 and 18 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 19 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0059] 17-19, vertical portions of each nanosheet stack may be removed, and additional portions of each sacrificial layer 16 and the laterally recessed portions of dielectric 28 may be removed using methods known in the art. Inner spacers 38 may be formed on either side of sacrificial layer 16. Source-drain regions 40 may be formed in the partially recessed locations where the vertical portions of each nanosheet stack have been removed. An inner layer dielectric (hereinafter "ILD") 42 may be formed above source-drain regions 40. The gate hard mask 32 may be removed.

[0060] The vertical portion of the nanosheet stack that is removed may be between two adjacent sacrificial gates 30, the gate hard mask 32, and the side spacers 34 surrounding each sacrificial gate 30. The vertical portion of the nanosheet stack may be formed by removing the vertical portion of the nanosheet stack, including a portion of each channel layer 18 and a portion of each sacrificial layer 16.

[0061] Vertical portions of the nanosheet stack are removed from the nanosheet stack between adjacent sacrificial gates 30 and gate hard masks 32, each with a side spacer 34 surrounding the sacrificial gate 30 and gate hard mask 32. The sacrificial gates 30, gate hard masks 32, and side spacers 34 protect the remaining portions of the nanosheet stack. The vertical portions of the nanosheet stack may be removed by etching using an anisotropic etching technique, such as reactive ion etching (RIE), and stopping at the separation layer 36. As shown in FIGS. 17 and 18, there are two vertical portions of the nanosheet stack removed, but there may be any number of vertical portions removed in the structure 100.

[0062] Further portions of each sacrificial layer 16 on either side of where the vertical portion of the nanosheet stack was removed may be recessed simultaneously with the lateral recessing of the dielectric 28, and the same amount of recessing may be performed on both.

[0063] Inner spacers 38 may be formed on either side of the sacrificial layer 16. The outer vertical sides of the inner spacers may be vertically aligned with the channel layer 18, and the inner vertical sides of the inner spacers may be vertically aligned with the remainder of the sacrificial layer 16.

[0064] The inner spacers 38 may each be formed after several steps including, for example, conformally depositing or growing a dielectric and performing an anisotropic etching step. The inner spacers 38 may comprise any dielectric material, such as silicon nitride, and may comprise a single layer or multiple layers of dielectric material.

[0065] In the location where the vertical portions of the nanosheet stack have been removed and partially recessed, a source-drain 40 may be formed using methods known in the art. An interlayer dielectric (hereinafter "ILD") 42 may be formed above the source-drain 40.

[0066] The source-drain 40 may be epitaxially grown in the region between adjacent sacrificial gates 30, gate hard masks 32, and side spacers 34. The source-drain 40 may be in direct contact with the edge of the channel layer 18 of the nanosheet stack and the edge of the inner spacer 38 surrounding the sacrificial layer 16. The source-drain 40 may be formed on the isolation layer 36. Portions of the source-drain 40 may be removed so that the top surfaces of the source-drain 40 are above the nanosheet stack, and an ILD 42 may be formed above the source-drain 40 between adjacent sacrificial gates 30, gate hard masks 32, and side spacers 34.

[0067] After forming the ILD 42, the gate hard mask 32 may be removed, for example, by wet etching techniques as described above, followed by chemical mechanical polishing (CMP) techniques to remove excess material and polish the top surface of the structure 100 until the top surface of the structure 100 is coplanar with the sacrificial gate 30, the side spacers 34, and the ILD 42.

[0068] 20-22, structure 100 is shown in accordance with an exemplary embodiment. Figures 20 and 21 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 22 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0069] As shown in FIGS. 20-22, the sacrificial gate 30 may be removed, and the sacrificial layer 16 may be removed.

[0070] The sacrificial gate 30 may be removed by methods known in the art. The sacrificial gate 30 may be removed selectively to the side spacers 34 and the top sacrificial layer 16 of the nanosheet stack.

[0071] The sacrificial material layer 16 is removed selectively to the channel layer 18, the inner spacer 38, the dielectric 28, and the separation layer 36. As shown in Figure 20, the remaining channel layer 18 of the nanosheet stack is shown suspended and supported at both ends by source and drain electrodes 40. For example, a dry etching process can be used to selectively remove the sacrificial layer 16, such as using a vapor phase HCl dry etch.

[0072] 23-25, structure 100 is shown in accordance with an exemplary embodiment. Figures 23 and 24 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 25 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0073] 23-25, a high-k liner 44 may be formed. Materials for the high-k liner 44 include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfO x N y , ZrO x N y , LaO x N y , AlO x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y2O x N y , SiON, SiN x, their silicates, and alloys thereof. The high-k liner 44 may be referred to as a gate dielectric 44. The high-k liner 44 may be formed on the exposed surfaces of the structure 100. The high-k liner 44 may be chamfered selectively to the side spacers 34, the ILD 42, the channel layer 18, and the dielectric 28. The high-k liner 44 may surround the opening where the sacrificial layer 16 was removed, along the exposed portions of the isolation layer 36, the exposed portions of the upper and lower surfaces of the channel layer 18, the exposed surfaces of the inner spacers 38, and part of the inner surfaces of the side spacers 34. As shown in FIG. 25 , the high-k liner 44 may cover the upper horizontal surfaces of the STI 24. The high-k liner 44 may cover the exposed horizontal and vertical surfaces of the dielectric 28.

[0074] 26-28, structure 100 is shown in accordance with an exemplary embodiment. Figures 26 and 27 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 28 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0075] 26-28, a work function metal (hereinafter "WFM") 46 may be formed. The WFM 46 may be conformally formed on the structure 100 according to an exemplary embodiment. The WFM 46 is formed within each cavity of the nanosheet stack, surrounding the suspended portion of the channel layer 18.

[0076] The WFM 46 forms a layer surrounding the exposed portion of the nanosheet stack. The WFM 46 may cover the exposed portion of the STI 24, the exposed surface between the side spacers 34 above the nanosheet stack, and the exposed surface of the dielectric 28. The WFM 46 may fill the remnants of the opening in the high-k liner 44 where the sacrificial layer 16 was removed. The WFM 46 may fill the remnants of the opening between the side spacers 34 above the nanosheet stack where the sacrificial gate 30 was removed, with the high-k liner 44 between the WFM 46 and a portion of the side spacers 34 above the nanosheet stack.

[0077] The WFM 46 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). The materials selected for the WFM 46 and high-k liner 44 may be selected based on the desired threshold voltage, combined with other materials and properties as described above for the nanosheet stack in which the WFM 46 surrounds the channel layer 18, and whether the device is a p-FET or n-FET. In one embodiment, the work function metal for a p-FET device may include a metal nitride, such as titanium nitride or tantalum nitride, titanium carbide, titanium aluminum carbide, or other suitable material known in the art. In one embodiment, the work function metal for an n-FET device may include, for example, titanium aluminum carbide, or other suitable material known in the art. In one embodiment, the work function metal may include one or more layers to achieve the desired device characteristics.

[0078] After forming the WFM 46, a chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 100 so that the horizontal top surfaces of the WFM 46, side spacers 34, and ILD 42 are coplanar.

[0079] 29-31, structure 100 is shown in accordance with an exemplary embodiment. Figures 29 and 30 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 31 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0080] 29-31, WFM 46 may be selectively recessed relative to dielectric 28, side spacers 34, and ILD 42 using methods known in the art. As shown in FIG. 31, a portion of high-k liner 44 may be removed along the top surface of dielectric 28 to expose dielectric 28.

[0081] 32-34, structure 100 is shown in accordance with an exemplary embodiment. Figures 32 and 33 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 34 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0082] As shown in FIGS. 32-34 , portions of the high-k liner 44 may be removed to form openings 48 in the dielectric 28. An anisotropic etching technique, such as reactive ion etching (RIE), may be used to remove portions of the dielectric 28 to form the openings 48. The openings 48 may be formed between the side spacers 34 and the ILD 42. Although three openings 48 are shown, any number of openings may be formed between adjacent rows of gates. A portion of the dielectric 28 may remain on the horizontal lower surface of each opening 48. The opposing vertical side surfaces of each opening 48 may include the vertical side surfaces of the dielectric 28 and the vertical side surfaces of the side spacers 34. The alternating opposing vertical side surfaces of each opening 48 may include the vertical side surfaces of each channel layer 18 of the nanosheet stack and the high-k liner 44, and the spaced portions of the vertical side surfaces of the WFM 46 between the channel layers 18, above the nanosheet stack, and between the bottom channel layer 18 and the separation layer 36.

[0083] 35-37, structure 100 is shown in accordance with an exemplary embodiment. Figures 35 and 36 are cross-sectional views of structure 100 along section lines X1-X1 and X2-X2, respectively, which are parallel to one another. Figure 37 is a cross-sectional view of structure 100 along section line YY, which is perpendicular to section lines X1-X1 and X2-X2.

[0084] 35-37, additional formations of WFMs 46 may be deposited as described above. WFMs 46 may be deposited in each of the openings 48 and in the gate. The vertical sides of the WFMs 46 may be adjacent to the vertical sides of the dielectric 28 and the vertical sides of the side spacers 34. The alternating vertical sides of each WFM 46 may include the vertical sides of each channel layer 18 of the nanosheet stack and the high-k liner 44, as well as the spaced portions of the vertical sides of the WFMs 46 between the channel layers 18, above the nanosheet stack, and between the bottom channel layer 18 and the separation layer 36.

[0085] After forming WFM 46, a chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of structure 100 so that the horizontal top surfaces of WFM 46, side spacers 34, and ILD 42 are coplanar.

[0086] 37, the portion of the WFM 46 formed in the opening 48 directly contacts the vertical sidewall of the channel layer 18, as identified by region 52. Within region 52, an area within the nanosheet stack provides increased contact area between the WFM 46 and the channel layer 18. Therefore, the gate of the nanosheet device directly contacts the sidewall of the channel layer 18. In other words, the WFM 46 directly contacts the sidewall of each channel layer 18 without the high-k liner 44. This direct contact is sometimes referred to as a body contact, since the WFM / gate contacts the body of the channel.

[0087] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the present invention. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. vertically aligned semiconductor channel layers stacked on top of each other, said semiconductor channel layers separated from each other by a work function metal; a gate dielectric layer partially surrounding each of the semiconductor channel layers and physically separating the work function metal from each of the semiconductor channel layers such that a first portion of the work function metal is in direct contact with a vertical sidewall of each of the semiconductor channel layers; A semiconductor nanosheet device comprising:

2. 2. The semiconductor nanosheet device of claim 1, wherein a portion of the gate dielectric layer extends vertically above the semiconductor channel layer to separate the first portion of the work function metal and the second portion of the work function metal directly above the top semiconductor channel layer.

3. 2. The semiconductor nanosheet device of claim 1, wherein the gate dielectric layer extends vertically below the semiconductor channel layers to separate the first portion of the work function metal and the second portion of the work function metal directly below a lowest one of the semiconductor channel layers.

4. 2. The semiconductor nanosheet device of claim 1, wherein the gate dielectric layer extends vertically between each of the semiconductor channel layers to separate the first portion of the work function metal from a second portion of the work function metal located between two adjacent semiconductor channel layers.

5. The semiconductor nanosheet device of claim 1 , further comprising source and drain regions extending laterally from opposite ends of the semiconductor channel layer.

6. a first set of vertically aligned semiconductor channel layers stacked on top of each other and separated by a work function metal; a second set of semiconductor channel layers adjacent to the first set of semiconductor channel layers, the second sets of semiconductor channel layers being vertically aligned and stacked on top of each other separated by the work function metal; a gate dielectric layer partially surrounding each of the semiconductor channel layers and physically separating the work function metal from each of the semiconductor channel layers such that a first portion of the work function metal between the first set of semiconductor channel layers and the second set of semiconductor channel layers is in direct contact with a sidewall of each of the semiconductor channel layers of both the first set of semiconductor channel layers and the second set of semiconductor channel layers; A semiconductor device comprising:

7. 7. The semiconductor device of claim 6, wherein a first portion of the gate dielectric layer extends vertically above the first set of semiconductor channel layers to separate the first portion of the work function metal from a second portion of the work function metal immediately above a top semiconductor channel layer of the first set of semiconductor channel layers, and a second portion of the gate dielectric layer extends vertically above the second set of semiconductor channel layers to separate the first portion of the work function metal from a third portion of the work function metal immediately above a top semiconductor channel layer of the second set of semiconductor channel layers.

8. 7. The semiconductor device of claim 6, wherein the gate dielectric layer extends vertically below the first set of semiconductor channel layers to separate the first portion of the work function metal from the second portion of the work function metal immediately below a lowest semiconductor channel layer of the first set of semiconductor channel layers, and the gate dielectric layer extends vertically below the second set of semiconductor channel layers to separate the first portion of the work function metal from the third portion of the work function metal immediately below a lowest semiconductor channel layer of the second set of semiconductor channel layers.

9. 7. The semiconductor device of claim 6, wherein a second portion of the gate dielectric layer separates the first portion of the work function metal from a second portion of the work function metal, the second portion of the work function metal being located between two adjacent layers of the first set of semiconductor channel layers, and a third portion of the gate dielectric layer separates the first portion of the work function metal from a third portion of the work function metal, the third portion of the work function metal being located between two adjacent layers of the second set of semiconductor channel layers.

10. source and drain regions extending laterally from opposite ends of the first set of semiconductor channel layers; source-drain regions extending laterally from opposite ends of the second set of semiconductor channel layers; The semiconductor device of claim 6 further comprising:

11. forming an initial stack of nanosheet layers on a substrate, the initial stack of nanosheet layers comprising alternating layers of vertically aligned sacrificial layers and semiconducting channel layers stacked on top of each other; forming vertical openings along the length of the initial stack of nanosheet layers to create a first stack of nanosheet layers and a second stack of nanosheet layers, the vertical openings exposing vertical sides of the alternating sacrificial layers and the semiconducting channel layers of both the first stack and the second stack; forming a dielectric in the opening; forming a sacrificial gate spanning both the first stack and the second stack of nanosheet layers; forming source / drain regions extending laterally from either end of the semiconductor channel layer in the first stack and the second stack of nanosheet layers; removing the sacrificial gate; removing the sacrificial layers of the first stack and the second stack; forming a gate dielectric on the exposed surfaces of the dielectric surrounding the openings where the sacrificial layers of the first stack and the second stack were removed; conformally depositing a work function metal, the work function metal filling openings in the first stack and the second stack remaining after the sacrificial layer was removed; recessing the work function metal, the recessing exposing a portion of the gate dielectric on a horizontal upper surface of the dielectric; A method comprising:

12. removing the exposed portion of the gate dielectric from the upper horizontal surface of the dielectric; The method of claim 11 further comprising:

13. forming a vertical opening in the dielectric to expose a second vertical side of the first stack and a first vertical side of the second stack; The method of claim 12 further comprising:

14. forming an additional work function metal in the vertical openings of the dielectric, wherein the second vertical side of each of the semiconductor channel layers of the first stack contacts the work function metal without the gate dielectric between the semiconductor channel layer and the work function metal, and the first vertical side of each of the semiconductor channel layers of the second stack contacts the work function metal without the gate dielectric between the semiconductor channel layer and the work function metal; 14. The method of claim 13, further comprising:

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