Electronic device and control method

Abstract

To provide an electronic device and a control method thereof capable of improving DRAM access efficiency.SOLUTION: An electronic device 100 comprises: a first data processing unit 102 which processes image data; a second data processing unit 101 which processes data other than the image data; a DRAM 112 conforming to an LPDDR5; and a control unit which divides banks included in the DRAM into regions for the image data and data regions for the data other than the image data and controls, according to the divided regions, opening and closing of pages as of after DRAM access.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electronic device having a DRAM (Dynamic Random Access Memory) and a control method thereof. [Background technology]

[0002] The structure of DRAM (Dynamic Random Access Memory) allows interleaved access to each bank, making it possible to access another bank during a precharge period, thereby improving memory access efficiency.

[0003] When accessing data in DRAM, first select the bank to access by issuing an ACT command along with the row address. Next, activate the address to be accessed by specifying the column address. When accessing DRAM, if the access is to the same page in the same bank and row, access efficiency can be improved by leaving the page open after access. This is suitable for accessing general data other than image data.

[0004] However, when accessing a different page in the same bank, it takes time to precharge and close the open page, specify a new row address, and then open the page, resulting in a decrease in access efficiency.

[0005] On the other hand, information processing devices that handle images often reference adjacent image data to the left, right, top, and bottom. Therefore, access is characterized by frequent access both horizontally and vertically. To efficiently access data above and below, it is common to store adjacent data above and below in different banks. In this case, by opening the bank with the next address in advance while accessing data, the next data can be accessed without delay. The efficiency of the next access can be improved by closing and precharging the page of the bank that was accessing the data after the access is completed.

[0006] Patent Document 1 describes a method for controlling the opening and closing of pages to improve access efficiency based on the page hit rate of a DRAM for each initiator. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-213703 Summary of the Invention [Problem to be solved by the invention]

[0008] The method described in Patent Document 1 calculates the hit rate of page opens for each initiator and can switch the state of a bank after access probabilistically. However, the method described in Patent Document 1 performs control based on the hit rate of the target page, regardless of the type of data. Therefore, when general data and image data are mixed, even if a bank is opened based on the page hit rate, it will be closed if accessed by another initiator, resulting in a problem of reduced access efficiency.

[0009] Therefore, an object of the present invention is to improve the access efficiency of a DRAM. [Means for solving the problem]

[0010] The electronic device of the present invention has a first data processing unit that processes image data, a second data processing unit that processes data other than image data, a DRAM that complies with LPDDR5, and a control unit that divides a bank included in the DRAM into an area for image data and an area for data other than image data, and controls the opening or closing of pages after accessing the DRAM according to the divided areas. [Effects of the Invention]

[0011] According to the present invention, it is possible to improve the access efficiency of the DRAM. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a block diagram illustrating components of the electronic device 100. [Figure 2] 10 is a flowchart illustrating a memory access process. [Figure 3] FIG. 10 is a diagram for explaining the contents of an access request from an initiator. [Figure 4] FIG. 10 is a diagram for explaining the contents of a bank information holding unit. [Figure 5] FIG. 10 is a diagram for explaining the contents of a queue list. [Figure 6] 10 is a timing chart for explaining access to a DRAM. [Figure 7] 10 is a timing chart for explaining access to a DRAM. [Figure 8] 10 is a timing chart for explaining access to a DRAM. [Figure 9] 7 is a diagram illustrating components of an electronic device 700 that allows the contents of a bank information holding unit 105 to be rewritten when the mode is changed. [Figure 10] FIG. 10 is a diagram for explaining the contents of the bank information storage unit after a mode change. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

[0014] [Embodiment 1] First, we will explain the operation of a general DRAM (Dynamic Random Access Memory). Access to the DRAM is performed as follows by the memory controller issuing the following command: (1) Issue the ACT command along with the row address to activate the row address. (2) Issue a READ or WRITE command along with the column address to open the page to be accessed. (3) Reading and writing data In the case of a READ command, the data at the target address is read. In the case of a WRITE command, data is written to the target address. (4) PRECHARGE closes the page after data access is complete.

[0015] As mentioned above, accessing data from DRAM requires time to execute the ACT command, the READ or WRITE command, and the PRECHARGE command to close the page after the access is complete. Therefore, there are two access methods to speed up subsequent data accesses.

[0016] First, the first access method, a method for accessing general data, will be explained.

[0017] FIG. 6 is a timing chart of access to a DRAM in which a page is kept open and read after the READA data access is completed in order to speed up access.

[0018] T600 issues a READA ACT command, activating the bank and row address issued at the same time as issuing the command.T601 then issues a READA command along with the column address specification to open the page to be accessed.

[0019] After that, the memory controller issues a READB command to access the same page without PRECHARGE at T603. Data reading starts with reading the read data DoutA0 from the address specified by READA at T602. After reading up to DoutA7, it continues reading the read data DoutB0 to DoutB3 from the address specified by READB at T604.

[0020] By keeping the page open, the read time from DoutA0 to DoutB3 is 6 cycles.

[0021] On the other hand, FIG. 7 shows a timing chart of access to the DRAM in the case where access efficiency is reduced because the page is closed after READA is completed even when accessing the same page.

[0022] T600 issues a READA ACT command, activating the specified bank and row address at the same time as issuing the command.T601 then issues a READA command along with specifying the column address to open the page to be accessed.

[0023] After the access is completed, T603 issues a PRECHARGE command to close the page.

[0024] At T604, an ACT command is issued to read READB, and at T605, a READB command is issued together with the specification of a column address. At T606, reading READB is completed, and a PRECHARGE command is issued to close the page.

[0025] Data reading starts at T602 with reading of read data DoutA0 from the address specified by READA. Data reading for READB starts at T606. The data reading time when closing a page is 14 cycles.

[0026] The difference in read completion time between when the page is closed after access is complete and when the page is left open is 8 cycles, which indicates a decrease in access efficiency.

[0027] In this way, control of the page after access is completed affects access efficiency, and for general data access where the same page is frequently accessed, it is advantageous to leave the page open after data access.

[0028] Next, the second access method, a method for accessing image data, will be described.

[0029] A characteristic of image data is that access to adjacent data above, below, left, and right is required for processing. Since access to data above and below accesses different pages, as shown in Figure 7, it is necessary to close and open the page after the access is complete, which reduces access efficiency.

[0030] Therefore, it is common to first activate and access another bank as shown in FIG.

[0031] T600 issues an ACT command for bank A, activating the row address of bank A that was issued at the same time as the command was issued. After that, T601 issues a READA command together with the column address specification to open the page to be accessed.

[0032] At T602, an ACT command is issued for bank B, and the row address issued at the same time as the command is issued is activated for bank A. After that, at T604, a READB command is issued together with the specification of a column address to open the page to be accessed.

[0033] After that, the memory controller issues a PRECHARGE command for bank A at T605 when the read of READA is completed, and closes the page.

[0034] Data reading starts at T603 with reading of read data DoutA0 from the address specified by READA. After reading up to DoutA7, data DoutB0 to DoutB3 from the address specified by READB is read from T605. Here, after the access is complete, there is no access to the same page, so control is performed to close the page. The read time from DoutA0 to DoutB3 is 6 cycles.

[0035] In the case of image data that is intended to be accessed on a different page, it is more advantageous to have control that closes the page after access.

[0036] In this way, access efficiency can be improved by changing the control after access completion depending on the data type, such as general data, image data, etc. Therefore, in the first embodiment, the bank is divided into two areas, and post-DRAM access control is performed for each data type.

[0037] Next, a control method for improving access efficiency by dividing a bank into an image data area and a general data area will be described.

[0038] The electronic device 100 is an electronic device that has an LPDDR5 memory 112 and handles image data and general data other than image data. The LPDDR5 memory 112 is a DRAM (Dynamic Random Access Memory) that complies with the LPDDR5 (Low-Power Double Data Rate 5) standard.

[0039] The general data processing unit 101 is an information processing unit that handles general data like a CPU. The general data processing unit 101 has a function of transmitting and receiving address information to the access information processing unit 104, the address conversion unit 107, and general data to the memory controller unit 108 via the memory bus 103.

[0040] The image data processing unit 102 is an information processing unit that processes image data in a rectangular area. The image data processing unit 102 has a function of transmitting and receiving address information to an access information processing unit 104, an address conversion unit 107, and image data to a memory controller unit 108 via a memory bus 103.

[0041] A processing unit that accesses the DRAM, such as the general data processing unit 101 or the image data processing unit 102, is called an initiator.

[0042] The bank information holding unit 105 transmits to the access information processing unit 104 information on the bank that handles general data and the bank that handles image data.

[0043] The access information processing unit 104 identifies the bank to be accessed from the address information received from the general data processing unit 101 and the image data processing unit 102 via the memory bus 103 and the bank information received from the bank information holding unit 105. The access information processing unit 104 transmits the information on the identified bank via the bank information signal 106 to the address conversion unit 107 and the memory controller unit 108.

[0044] The address conversion unit 107 performs address conversion based on address information received from the general data processing unit 101 and the image data processing unit 102 via the memory bus 103 and bank information received via the bank information signal 106. The address conversion unit 107 transmits the generated address information to the memory controller unit 108.

[0045] The memory controller unit 108 includes a subsequent access queue list 109, a write data cache unit 110, and a read data cache unit 111. The memory controller unit 108 receives the bank information signal 106 from the access information processing unit 104 and address information from the address conversion unit 107 via the bank information signal 106. The memory controller unit 108 transmits the received bank information and address information to the subsequent access queue list 109. The memory controller unit 108 transmits and receives subsequent access information to and from the subsequent access queue list 109.

[0046] The write data cache unit 110 stores the data to be written to the DRAM received from the initiator. The memory controller unit 108 transmits the data stored in the write data cache unit 110 to the LPDDR5 memory 112 via a DRAM interface signal 113.

[0047] The read data cache unit 111 receives and stores data from the LPDDR5 memory 112 via a DRAM interface signal 113. The memory controller unit 108 transmits the data stored in the read data cache unit 111 to the initiator via the memory bus 103.

[0048] Next, a process of accessing the LPDDR5 memory 112 of the electronic device 100 will be described with reference to the flowchart of FIG.

[0049] In step S201, the general data processing unit 101 or the image data processing unit 102 transmits the DRAM access required by each processing unit as command and address information.

[0050] 3(a) shows an example of a command and address information transmitted from the general data processing unit 101. The general data processing unit 101 transmits information on the bank, row, column, and burst length as an ID No., command, and address.

[0051] 3(b) is an example of the command and address information transmitted from the image data processing unit 102. The image data processing unit 102 transmits information on the bank, row, column, and H burst length and V burst length that specify the rectangular area as the ID No., command, and address. After transmitting the command and address information, the process proceeds to step S202.

[0052] In step S202, the access information processing unit 104 and the address conversion unit 107 receive the command and address information, and the process proceeds to step S203.

[0053] In step S203, the access information processing unit 104 checks the command received from the general data processing unit 101 or the image data processing unit 102, and if it is a Write command, the process proceeds to step S204, whereas if it is a Read command, the process proceeds to step S206.

[0054] In step S204, the access information processing unit 104 requests the initiator to transmit data, and then the process proceeds to step S205.

[0055] In step S205, when the initiator receives a data transmission request from the access information processing unit 104, it transmits the data to the memory controller unit 108 via the memory bus 103, and proceeds to step S206.

[0056] In step S206, the access information processing unit 104 transmits bank information based on the address information received from the initiator to the bank information holding unit 105. For example, if the ID No. in FIG. 3 is ID1, the access information processing unit 104 transmits 8 as the bank No. If the ID No. is ID5, the access information processing unit 104 transmits 0 as the bank No. to the bank information holding unit 105. The bank information holding unit 105 internally holds bank information.

[0057] 4 shows an example of bank information stored in the bank information storage unit 105. In this example, eight banks with bank numbers 0 to 7 are set as banks for image data, and eight banks with bank numbers 8 to F are set as banks for general data. When the bank information storage unit 105 receives a request signal for information on bank number 8 from the access information processing unit 104, it transmits to the access information processing unit 104 a signal indicating that the bank to be accessed by the ID number is an image data area. The access information processing unit 104 then transmits to the address conversion unit 107 and the memory controller unit 108 a signal indicating that the bank to be accessed by the ID number is an image data area.

[0058] Similarly, when the bank information holding unit 105 receives an inquiry signal for information of ID No. 1 from the access information processing unit 104, it transmits to the access information processing unit 104 information that it is a general data area. The access information processing unit 104 transmits information that the bank accessed by the ID No. is a general data area to the address conversion unit 107 and the memory controller unit 108. After completing transmission of the bank type, the access information processing unit 104 proceeds to step S207.

[0059] In step S207, if the type of the bank received from the bank information holding unit 105 is general data, the address conversion unit 107 proceeds to step S209, and if it is image data, the address conversion unit 107 proceeds to step S208.

[0060] In step S208, the address conversion unit 107 converts the address received from the initiator into an address for the image area, and the process proceeds to step S210.

[0061] In step S209, address conversion unit 107 converts the address received from the initiator into an address for the general data area, and the process proceeds to step S210.

[0062] In step S210, the memory controller unit 108 stores the address received from the initiator in the subsequent access queue list 109. The memory controller unit 108 performs a round-robin check to see if an address matching the bank number of the address to be accessed next in the DRAM is listed in the subsequent access queue list 109, and then proceeds to step S211.

[0063] In step S211, if a matching bank is listed in the subsequent access queue list 109, the process proceeds to step S212, and if not, the process proceeds to step S214.

[0064] In step S212, the memory controller unit 108 checks whether a same-page access is listed in the subsequent access queue list 109. If it is listed, the process proceeds to step S213, and if it is not listed, the process proceeds to step S215.

[0065] In step S214, the memory controller unit 108 determines whether the bank to be accessed next is an image data area. The memory controller unit 108 determines the type of bank using the bank information from the access information processing unit 104, and if it is an image data area, the process proceeds to step S215, and if it is a general data area, the process proceeds to step S213.

[0066] In step S213, the memory controller unit 108 generates a command to keep the page open after the access is completed from the command information and address information, and proceeds to step S216.

[0067] In step S215, the memory controller unit 108 generates a command to close the page after the access is completed from the command information and address information, and proceeds to step S216. Here, as an example of the process of checking the subsequent access queue list, a process flow will be described in which the next access is ID1, which is an access to general data, as shown in Figure 5(a), and the subsequent access queue list lists accesses such as those shown in Figure 5(b).

[0068] The memory controller unit 108 performs a round-robin check to see if a bank matching bank No. 8 of the address to be accessed is listed in the subsequent access queue list 109. Here, it can be confirmed that ID2 is the same. Since a matching bank is found, the process proceeds to step S212.

[0069] In step S212, the memory controller unit 108 checks whether a same page access is listed in the subsequent access queue list 109. Since ID2 is the same page, the process proceeds to step S213.

[0070] In step S213, the memory controller unit 108 generates a command to keep the page open after the access is completed from the command information and address information of ID1, and proceeds to step S216. The above process makes it possible to confirm that the access is to the same page of ID1, and after the access of ID1 is completed, efficient access becomes possible by keeping the page open.

[0071] In step S216, if the generated DRAM access command is a READ command, the memory controller unit 108 proceeds to step S217, and if it is a WRITE command, the memory controller unit 108 proceeds to step S220.

[0072] In step S217, the memory controller unit 108 issues a command to the LPDDR5 memory 112 via the DRAM interface signal 113, receives data via the DRAM interface signal 113, and transitions the process to step S218.

[0073] In step S218, the memory controller unit 108 temporarily transmits the data received from the LPDDR5 memory 112 to the Read data cache unit 111, stores it, and then proceeds to step S219.

[0074] In step S219, the memory controller unit 108 transmits the data stored in the read data cache unit 111 to the initiator via the memory bus 103, and the process proceeds to step S219.

[0075] In step S220, the memory controller unit 108 reads the data from the write data cache unit 110, and the process proceeds to step S221.

[0076] In step S221, the memory controller unit 108 issues a command to the LPDDR5 memory 112 via the DRAM interface signal 113. After issuing the command, the memory controller unit 108 transmits the data read from the write data cache unit 110 to the LPDDR5 memory 112. After the transmission is completed, the process proceeds to step S222.

[0077] In step S222, the memory controller unit 108 checks whether there is next DRAM access data. If there is next DRAM access data, the process proceeds to step S206. If there is no next DRAM access data, the process ends and the DRAM transitions to low-consumption mode.

[0078] [Embodiment 2] The following describes an example of changing the classification of banks in the bank information storage unit in response to a change in mode of electronic device 700. In this example, due to increased access to image data, a change is made from the standard bank area configuration shown in Fig. 4 to an increased proportion of banks for image-oriented areas shown in Fig. 10.

[0079] FIG. 9 is a diagram illustrating components of electronic device 700 that allows the contents of bank information holding unit 105 to be rewritten when the mode is changed.

[0080] A CPU (Central Processing Unit) 701 is a control unit that controls each component of the electronic device 700. The CPU 701 accesses the access information processing unit 104 via the memory bus 103. The CPU 701 accesses the non-volatile memory 702. The components other than the CPU 701 are the same as the components shown in FIG. 1, and therefore, description thereof will be omitted.

[0081] Hereinafter, a method for updating the contents of bank information holding unit 105 in response to a mode change of electronic device 700 will be described with reference to the configuration of FIG.

[0082] When the CPU 701 detects a mode change of the electronic device by receiving a notification from the general data processing unit 101 or the image data processing unit 102, it acquires the data of the bank information holding unit 105 after the mode change into the nonvolatile memory 702. Thereafter, the CPU 701 transmits the data of the bank information holding unit 105 after the mode change to the access information processing unit 104 via the memory bus 103.

[0083] When the access information processing unit 104 receives the value of the bank information holding unit together with a command to update the value of the bank information holding unit from the CPU 701, it rewrites the contents of the bank information holding unit 105.

[0084] After the rewrite is complete, similar to the first embodiment, post-access control is executed, thereby enabling control with a bank configuration according to the mode change. [Explanation of symbols]

[0085] 100 Electronic equipment 101 General Data Processing Section 102 Image data processing unit 103 memory bus 104 Access information processing unit 105 Bank Information Storage Unit 106 Bank information signal 107 Address translation unit 108 Memory Controller 109 Subsequent Access Queue 110 Write data cache unit 111 Read data cache section 112 LPDDR5 memory 113 DRAM interface signals

Claims

1. a first data processing unit that processes image data; a second data processing unit that processes data other than image data; a DRAM compliant with LPDDR5; a control unit that divides a bank included in the DRAM into an area for image data and an area for data other than image data, and controls opening or closing of a page after accessing the DRAM according to the divided area; An electronic device comprising:

2. 2. The electronic device according to claim 1, wherein an address from the first data processing unit and an address from the second data processing unit are converted depending on whether the bank to be accessed is an area for image data or an area for data other than image data.

3. 3. The electronic device according to claim 1, wherein a bank included in the DRAM is divided into an area for image data and an area for data other than image data in response to a change in mode of the electronic device.

4. A method for controlling an electronic device having a first data processing unit that processes image data, a second data processing unit that processes data other than image data, and a DRAM that complies with LPDDR5, Dividing a bank included in the DRAM into an area for image data and an area for data other than image data; a step of controlling opening or closing of a page after accessing the DRAM according to the divided areas; A control method comprising:

Images