Automatic redistribution layer via generation

Abstract

Systems and methods are described for automatically generating placements of vias in a redistribution layer of a semiconductor package. In various embodiments, a user defines attributes to be used for automatic via generation in a redistribution layer of a semiconductor package. Circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator. The automatic via generator uses the attributes, data indicative of an RDL netlist of signal routes in the RDL, and RDL mask layout data representing signal masks for metal layers in the RDL. The processor generates placements of vias in the RDL based on the attributes and identification of areas of overlap between metal layers.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 228,552, entitled "VIA GENERATION FOR SILICON LAYOUT," filed August 2, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] Description of Related Art There is an increasing demand for semiconductor packages that provide communication between one or more integrated circuits within the chip package and external components on a motherboard located outside the chip package. Electronic products related to mobile computing, wearable electronics, and the Internet of Things (IoT) are driving the demand for miniature packages that utilize vertical signal interconnects. Examples of chip packages used in these products include ball grid arrays (BGA), chip scale packages (CSP), and system in package (SiP).

[0003] Semiconductor packages utilize controlled collapse chip connection (C4) interconnects, also known as flip-chip interconnects. For example, C4 bumps connect to vertical through silicon vias (TSVs) formed in a silicon package substrate that have connections to a printed circuit board using bump pads. A group of TSVs forming a through silicon bus is used as an interconnect between the base die, one or more additional integrated circuits, and routing on a printed circuit board (PCB), such as a motherboard or card. The demand for SiP and more signal interconnects between integrated circuits and printed circuit boards (PCBs) is also increasing the demand for package substrates and interposers.

[0004] The package substrate is the part of the chip package that provides mechanical base support and an electrical interface for signal interconnections. An interposer is an intermediate layer between one or more integrated circuits, either flip-chip bumps or other interconnects, and the package substrate. As used, an interposer provides an electrical interface for signal interconnections between a die assembled thereon (die-to-die interconnects) and the package substrate (die-to-package interconnects). Depending on the embodiment, the terms package substrate and interposer are used interchangeably.

[0005] One or more integrated circuits in a semiconductor package have signal routes connected between them and a motherboard (or printed circuit board) using a redistribution layer, which is a signal route located between microbumps that contact pads on the integrated circuit and through-silicon vias (TSVs) in the silicon package substrate.

[0006] While innovations bring improvements, modern technologies in processing and integrated circuit design still present design challenges that limit potential gains. One challenge is that one or more integrated circuits have tens of thousands of nodes for receiving one or more power voltage reference levels and one or more ground reference voltage levels, while there are hundreds of nodes in TSVs for transferring these voltage reference levels. Routing these power connections through redistribution layers becomes complex. Additionally, manually placing vias on mask layout representations of these signal routes before performing verification checks and subsequent manufacturing can take weeks or months.

[0007] In view of the above, an efficient method and system for creating vias for power connections in redistribution layers is desired. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a generalized diagram of a computing system. [Figure 2] FIG. 1 is a generalized diagram of a cross-sectional view of a semiconductor package metal layer scheme. [Figure 3] FIG. 2 is a generalized diagram of the metal layers of a redistribution layer. [Figure 4] FIG. 2 is a generalized diagram of the metal layers of a redistribution layer. [Figure 5] FIG. 2 is a generalized diagram of the metal layers of a redistribution layer. [Figure 6] FIG. 1 is a generalized diagram of a graphical user interface. [Figure 7] FIG. 1 is a generalized diagram of one embodiment of a method for automatic via creation in a redistribution layer. [Figure 8] FIG. 1 is a generalized diagram of one embodiment of a method for automatic via creation in a redistribution layer. [Figure 9] FIG. 1 is a generalized diagram of a computing system. DETAILED DESCRIPTION OF THE INVENTION

[0009] While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0010] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. Furthermore, it will be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements are exaggerated relative to other elements.

[0011] Systems and methods are contemplated for automatically generating vias in redistribution layers. As used herein, the terms "automatic generation" or "automatically generating" refer to performing generation or having the ability to perform a generation step without user intervention. As disclosed herein, a user defines attributes to be used for automatic via generation in a redistribution layer of a semiconductor package. In one embodiment, the user provides the attributes via a graphical user interface (GUI). In another embodiment, the user provides the attributes via a text file or executable file written in any of a variety of scripting languages. The computing device used by the user includes hardware, such as processor circuitry, for executing instructions for the automatic via generator. The automatic via generator uses the attributes, a copy of the RDL netlist of signal routes in the redistribution layer (RDL), and a copy of the RDL mask layout data representing signal masks for metal layers in the RDL.

[0012] When a processor of a computing device executes the instructions of the automatic via generator, the processor identifies a metal overlap region between metal layers of an RDL. The metal overlap region is also referred to as a metal overlap junction area or overlap junction area. In some embodiments, the metal overlap region is between adjacent metal layers of an RDL, such as metal layers RDL1 and RDL2. In other embodiments, the metal overlap region is between two non-adjacent metal layers of an RDL, such as metal layers RDL1 and RDL4, such as through-hole vias. In still other embodiments, the metal overlap region is between a pin of a surface mount device (SMD) pin layer and a metal layer of an RDL. In still further embodiments, the metal overlap region is between a metal layer of an RDL and an under-bump metallurgy (UBM) layer that provides electrical connection to a C4 bump. In some examples, the metal overlap region has a square or rectangular shape, such as the metal overlap region between two metal layers of an RDL. In other examples, the metal overlap region has a circular shape, such as the metal overlap region between a metal layer of an RDL and a pin of an SMD pin layer. For valid via creation, the metal overlap area between the two metal layers is equal to or greater than a minimum overlap junction area threshold. In some embodiments, based on the received attributes, the processor divides the overlap area in half to allow via layers to be placed both above and below the overlap area. Based on the attributes received from the user, the processor places different types of via layers in the overlap area.

[0013] The processor generates vias based on the sequence order indicated in the received attributes. The sequence order determines which via layer to use to start automatic via generation and which subsequent via layers to select for further automatic via generation. Vias are placed based on the size and pitch corresponding to the currently selected via layer to satisfy DRC rules. In addition, the processor does not change the dimensions of the metal layer of the signal route during via placement. If multiple sequences for a particular via layer are specified in the received attributes, the processor places additional vias in that via layer if possible. In some cases, via redundancy already exists, but the automatic via generator still increases the number of vias as much as possible. The processor then generates a report. The processor maintains a log file during automatic via generation and uses corresponding information to provide summarized results in a report. In various embodiments, the processor writes a file located at a known destination.

[0014] In the following description, a computing system for supporting the development of hardware products using semiconductor package substrates is shown in FIG. 1. The computing system supports the automatic generation of vias in a redistribution layer. FIG. 2 illustrates components of a semiconductor package, such as a redistribution layer using flip-chip technology. FIGS. 3-5 illustrate metal overlap areas between adjacent metal layers in a redistribution layer. FIG. 6 illustrates an example of a graphical user interface for a user to provide attributes to utilize during the automatic generation of vias in a redistribution layer. FIGS. 7-8 provide method steps implemented to support the automatic generation of vias in a redistribution layer. FIG. 9 illustrates an example of a manufactured chip package including automatically generated vias in a redistribution layer in a computing system.

[0015] Referring to FIG. 1, a generalized block diagram of one embodiment of a computing system 100 is shown. In the illustrated embodiment, computing system 100 includes a client computing device 150, servers 120A-120D that execute software and include hardware for supporting organization center 110, a network 140, and data storage 130 that includes one or more data stores supported and used by organization center 110. While a single client computing device 150 is shown, any number of client computing devices may utilize organization center 110 via network 140. Client computing device 150, also referred to as client device 150, includes hardware, such as processor circuitry, for executing instructions for a rewiring layer (RDL) automatic via generator 160. RDL automatic via generator 160 (or via generator 160) uses a copy of the data stored in data storage 130 and user-provided attributes 166. In one embodiment, the user provides attributes 166 via a graphical user interface (GUI) 162. Examples of data used by via generator 160 include RDL mask layout data 132 , an RDL netlist, and a copy of at least a portion of design rule check (DRC) 136 .

[0016] Client device 150 includes mobile computing devices such as desktop computers, laptops, tablet computers, etc. Client device 150 includes hardware circuitry such as processing unit 170 for processing instructions of a computer program. In some embodiments, processing unit 170 includes one or more homogeneous cores of a processor. In other embodiments, the processing unit includes heterogeneous cores, such as parallel-processing-architected cores and general-purpose cores such as those used in a central processing unit (CPU). The parallel-architected core may be a graphics processing unit (GPU), digital signal processing unit (DSP), etc.

[0017] Client device 150 includes a network interface (not shown) that supports one or more communication protocols for data and message transfer over network 140. Network 140 includes multiple switches, routers, cables, wireless transmitters, and the Internet for transferring messages and data. Thus, the network interfaces of organization center 110 and client device 150 support at least the Hypertext Transfer Protocol (HTTP) for communication over the World Wide Web. In addition to communicating with client device 150 over network 140, organization center 110 also communicates with data storage 130 for storing and retrieving data.

[0018] In various embodiments, organization center 110 is infrastructure for a vendor that produces one or more hardware products. Organization center 110 includes an intranet that provides a private network accessible only to the organization's staff. Intranet portals are used to provide access to resources with user-friendly interfaces, such as graphical user interfaces (GUIs) and dashboards. Information and services made available by organization center 110 are not available to the general public through direct access. Through user authentication, staff members can access resources through organization center 110 to communicate with other staff members, collaborate on projects, monitor product development, update products, documentation, and tools stored in a central repository, etc.

[0019] Servers 120A-120D used to support organization center 110 and the resources accessed through organization center 110 include various server types such as database servers, computing servers, application servers, file servers, mail servers, etc. In various embodiments, servers 120A-120D and client devices 150 operate in a client-server architecture model.

[0020] Client device 150 includes a copy of a particular version of a given software product or tool, such as via generator 160. In some embodiments, the version of via generator 160 is based at least on the operating system and processor used by client device 150. Via generator 160 includes engine 164 that, when executed by processor 170, causes processor 170 to automatically generate vias in a layout mask representation of signal routes in a redistribution layer. Signal routes in a redistribution layer are signal routes located between an integrated circuit and a printed circuit board. For example, signal routes in a redistribution layer are signal routes located between microbumps that contact pads on an integrated circuit and through-silicon vias (TSVs) in a silicon package substrate. Redistribution layers eliminate the need to have a set of input / output (I / O) pads wire-bonded to pins on the package, which facilitates chip-to-chip bonding.

[0021] As described above, organizational center 110 is an infrastructure for vendors that produce one or more hardware products. An integrated circuit is any of various types of integrated circuits being developed for production. When tens of thousands of metal layers may be used to provide signal routes within a redistribution layer, manually placing vias on these metal layers can take weeks or months. Via generator 160 performs this placement in a more efficient manner. While redistribution layers include control signal routes and data signal routes, in one embodiment, via generator 160 provides automatic via generation for signal routes in redistribution layers that provide either power supply voltage reference levels or ground reference voltage levels used by the integrated circuit. To do so, via generator 160 uses attributes 166 provided by the user.

[0022] In one embodiment, a user provides attributes 166 to via generator 160 via a graphical user interface (GUI) 162. In another embodiment, a user provides attributes 166 to via generator 160 via a text file or an executable file written in any of a variety of scripting languages. In one embodiment, when processor 170 executes the code of engine 164 of via generator 160, processor 170 automatically generates vias in the order of the sequences specified by attributes 166. Each sequence identifies a pair of adjacent metal layers within a redistribution layer. Via generator 160 additionally uses copies of RDL mask layout data 132 and RDL netlist 134 to identify the placement of metal layers within the redistribution layer. Via generator 160 also uses DRC 136 to verify that the placement of vias does not violate design rules for the layout. Via generator 160 or another tool also performs layout-to-schematic (LVS) checking. If the via placement passes the DRC and LVS checks, one or more copies of the updated version of RDL mask layout data 132 are stored on client device 150 and data storage 130. The integrated circuit under development is then subjected to a semiconductor chip tape-out process, and the semiconductor manufacturing process provides the integrated circuit hardware for testing.

[0023] Referring to FIG. 2 , a generalized block diagram of a semiconductor package metal layer scheme 200 (or metal layer scheme 200) is shown, which provides signal routing between integrated circuits and a printed circuit board. As shown, metal layer scheme 200 utilizes controlled-collapse chip connect (C4) interconnects, also known as flip-chip interconnects. Two integrated circuits 210 and 212 have signal routes connected between them and a motherboard (or printed circuit board), which is not shown for ease of illustration. The interconnects may be connected to vertical through-glass vias formed in a silicon package substrate that have connections to the printed circuit board using bump pads. In addition to signal routes between the motherboard and integrated circuits 210 and 212 via interconnects 240, signal routes to and from integrated circuits 210 and 212 are routed through redistribution layer 230. In some embodiments, metal layer scheme 200 additionally includes a separate interposer (not shown) between redistribution layer 230 and interconnects 240 (e.g., under-bump metallurgy). In one embodiment, the interposer includes through silicon vias, but the redistribution layer 230 does not include TSVs. In another embodiment, the interposer and the redistribution layer 230 each include one or more TSVs. In yet another embodiment, no separate interposer is used, as shown in FIG.

[0024] Here, the integrated circuit is a system on a chip (SoC). As shown, one SoC is used in the hardware product. However, other examples of integrated circuits, such as one or more of a CPU, GPU, multimedia engine, application specific integrated circuit (ASIC), digital signal processor (DSP), etc., are possible and contemplated. Interconnect 240 provides connections between multiple redistribution layers (RDLs) 1-4 and the package substrate and motherboard. In some embodiments, it is common to have hundreds of UBM layers and C4 bumps. Additionally, four metal layers (RDLs 1-4) are used in redistribution layer 230, although other embodiments use a different number of metal layers. Between adjacent metal layers (RDLs 1-4) of redistribution layer 230 are vias labeled Via 2-Via 4, which provide physical connections between adjacent layers of redistribution layer 230. Redistribution layer 230 also includes a via layer of vias between the pins of the SMD pin layer and metal layer RDL1. As shown, redistribution layer 230 further includes a via layer of vias between metal layer RDL4 and interconnect 240.

[0025] SoC 210 may have signals routed to and from both other SOCs (not shown) and the motherboard (printed circuit board) through at least interconnect 240. Signals are routed through metal layers of redistribution layer 230, such as a metal layer designated as redistribution layer 1 (RDL1) and a metal layer designated as redistribution layer 4 (RDL4). These metal layers are also referred to as conductor 1 and conductor 4, respectively. In addition to metal layers RDL1 through RDL4 of redistribution layer 230, signals are routed through pin and via 1 through via 5 layers of surface-mount device (SMD) pin layers. Redistribution layer 230 includes control signal and data signal routes, although the signal routes shown here route one or more of the power supply and ground reference voltage levels used by SoC 210 and SoC 212. Each of SoC 210 and SoC 212 may use one or more power supply and ground reference voltage levels. In some cases, SoC 210 and SoC 212 each have tens of thousands of nodes that use pads 220 to receive power supply voltage reference levels and one or more ground reference voltage levels, while there are hundreds of UBMs to transfer these voltage reference levels. Routing these signals can be complex. In some cases, layout mask data for signal routes within metal layers RDL1-RDL4 is already provided, but manually placing vias on these metal layers can take weeks or months.

[0026] To make via placement more efficient, the processor circuitry executes instructions in a software tool that follows an algorithm developed by a software programmer to automatically generate vias based on user-provided attributes. The tool, sometimes referred to as an RDL automatic via generator (or automatic via generator), uses copies of the RDL mask layout data and the RDL netlist to identify placements for metal layers within the redistribution layer. The automatic via generator also uses user-supplied attributes. In various embodiments, the automatic via generator takes into account design rule checks (e.g., spacing, etc.). In some embodiments, such other tools perform DRC and LVS checks. After passing the checks, the integrated circuit under development undergoes a semiconductor chip tape-out process, and the semiconductor manufacturing process provides the integrated circuit hardware for testing.

[0027] Referring to FIG. 3 , a generalized block diagram of metal layer 300 is shown. As shown, two horizontal signal routes in metal layer RDL1 302 are connected by a vertical signal route in metal layer RDL2 304. Side A and B cross sections are also provided to aid in viewing the layout in three dimensions. The metal layer of RDL1 302 physically connects with the metal layer of RDL2 304 using a via placement in Via 2 layer 306. The width of the metal layer of RDL2 304 places a single row of two vias in Via 2 layer 306. Thus, each of the two metal layers RDL1 302 and RDL2 304 are physically connected. In various embodiments, these metal layers 302 and 304 provide power supply or ground reference voltage levels used by the corresponding integrated circuits.

[0028] Although the orientations are described as horizontal and vertical, it is understood that the semiconductor package can be rotated and the redistribution layers rotated. The direction of current flow is used to describe the relationship between the metal layers and vias. Here, metal layer RDL2 304 is located above metal layer RDL1 302; therefore, the SoC or other integrated circuit would be located within the page of this figure, but the UBM and silicon package substrate are located off-page of this figure. The reverse orientation is possible and contemplated, but for the purposes of this description, the integrated circuit is located within the page.

[0029] Referring to FIG. 4, a generalized block diagram of metal layer 400 is shown. Materials and structures previously described are similarly numbered. As shown, two horizontal signal routes in metal layer RDL1 302 are connected by vertical signal routes in metal layer RDL2 304. Side A and B cross sections are also provided to aid in viewing the layout in three dimensions. The metal layer of RDL1 302 physically connects with the metal layer of RDL2 304 using a via placement in Via 2 layer 306. Due to the larger width of the metal layer of RDL2 304, two rows of two vias in Via 2 layer 306 are placed.

[0030] Turning to FIG. 5 , a generalized block diagram of metal layer 500 is shown. Materials and structures previously described are similarly numbered. As shown, two horizontal signal routes in metal layer RDL1 302 are connected by a vertical signal route in metal layer RDL2 304. Side A and B cross sections are also provided to aid in viewing the layout in three dimensions. The metal layer of RDL1 302 physically connects with the metal layer of RDL2 304 using the via placement of the vias in the via 2 layer 306. A cutaway of the top metal layer RDL3 502 reveals the single row placement of the two vias in the via 2 layer 306. Additionally, two horizontal signal routes in metal layer RDL3 502 are connected by the same vertical signal route in metal layer RDL2 304. Using the previous (FIGS. 3 and 4) orientation of metal layers 300-500, metal layer RDL3 502 is located above metal layer RDL2 304. Thus, the two metal layers RDL1 302, the single metal layer RDL2 304, and the two metal layers RDL3 502 are each physically connected.

[0031] In various embodiments, these metal layers 302, 304, 502 provide power supply or ground reference voltage levels used by the corresponding integrated circuit. The metal layer of RDL3 502 physically connects to the metal layer of RDL2 304 using the arrangement of vias in the Via 3 layer 504. Due to the width of the metal layer of RDL2 304 and the area required for the vias in the Via 2 layer 306, a single row of two vias in the Via 3 layer 504 is used by each of the metal layers of RDL3 502. Note that the vias in the Via 2 layer 306 and the Via 3 layer 504 have physical connections to only two adjacent layers, not three adjacent layers. In various embodiments, design rule checking (DRC) does not allow physical connections to the third metal layer. Thus, as shown, the vias in the Via 2 layer 306 are disposed between the metal layers of RDL1 302 and RDL2 304, but the vias in the Via 2 layer 306 are not vertically continuous to physically connect with the metal layer of RDL3 502. Similarly, the vias in the Via 3 layer 504 are disposed between the metal layers of RDL2 304 and RDL3 502, but the vias in the Via 3 layer 504 are not vertically continuous to physically connect with the metal layer of RDL1 302. However, in other embodiments, the DRC allows for the use of through-hole vias formed through more than two metal layers.

[0032] Note that in the above examples shown in Figures 3-5, the metal overlap region is between the metal layers of the RDL and has a rectangular shape. However, in other examples, the metal overlap region is between the pins of a surface-mount device (SMD) pin layer and the metal layers of the RDL. In these examples, it is possible and contemplated that the metal overlap region has a circular shape. In yet other examples, the metal overlap region is between the metal layers of the RDL and the under-bump metallurgy (UBM) layer that provides electrical connection to the C4 bumps.

[0033] Turning to FIG. 6 , a generalized block diagram of a graphical user interface (GUI) 600 is shown. As shown, GUI 600 includes multiple selections for customizing multiple attributes used for automatic via generation in a redistribution layer. A user can provide selections for multiple attributes using one or more of the following: provided drop-down menus, input boxes for receiving text, checkboxes or other shapes for changing color to indicate selections, etc. Box 602 allows a user to select a geographic area within a redistribution layer for automatic via generation. For example, a user can draw a shape with a boundary that defines the area for automatic via generation. Alternatively, a user can select an existing design outline.

[0034] In some embodiments, a table with multiple fields is provided. Field 604 indicates adjacent layers to be customized for automatic via generation. As shown, the first row indicates metal layer RDL1 and the SMD pin layer. The Via 1 layer is between these two layers (RDL1 and SMD pin). The second row indicates metal layer RDL1 and metal layer RDL2. The Via 2 layer is between these two metal layers (RDL1 and RDL2). The third and fourth rows follow this same rule for identifying via layers. The last row indicates a metal layer (RDL4) and a UBM that is physically connected to the C4 bump. The Via 5 layer is between these two layers (RDL4 and UBM). Field 606 indicates a via pad stack for each via layer. The via pad stack includes features that describe a single via definition or multiple via definitions, such as a metal layer on the edge of a via opening in a dielectric. The pad stack definition also describes the holes (via openings) in the redistribution layers that are used to create the vias. These characteristics include whether the holes are plated or non-plated. Additionally, these characteristics indicate the hole size (diameter), the finished hole size, the size of the pads formed on the inner and outer layers, and the size of the clearance around the holes. The user indicates the via pitch in field 608.

[0035] The via placement description field 610 includes three subfields. The first subfield indicates the reference metal. For example, the Via 2 layer is between two metal layers RDL1 and RDL2. The user selects one of these metal layers RDL1 and RDL2 as the reference metal to use to describe the placement of vias in the metal overlap region of the RDL1 and RDL2 layers. The user selects a starting point in the second subfield. The starting point refers to the selected reference metal and also indicates the edge of the selected reference metal that will be the automatic via placement. As an example, briefly referring back to metal layer 500 (of FIG. 5), for the Via 2 layer, the user selects "Top" as the reference metal, indicating metal layer RDL2. The user selects "Rail Right Edge" as the starting point, and the user selects "Vertical" for the direction in the third subfield. The vertical and horizontal directions are used to determine the placement of pad stacks for multiple vias placed in the metal overlap region. Examples of placing multiple vias in the metal overlap region are shown in FIGS.

[0036] In various embodiments, one of the subfields of field 610 or another field (not shown) in GUI 600 includes indicators that allow a user to specify a hole type and a corresponding via type. For example, a user can specify whether a via hole is a through-hole via hole, a multi-hole hole in a stack of microvias, a blind microvia hole, a buried hole hole, or a copper-filled microvia hole. In other embodiments, selection of the hole type and corresponding via type is not permitted by the user. Rather, the semiconductor manufacturing process already defines the hole types and corresponding via types between metal layers in the RDL. This information is provided by a separate file that is accessed by the RDL automatic via generator when generating vias based on attributes provided by the user.

[0037] Note that in some embodiments, a row in the table identifies one or more via layers that skip a metal layer. In one example, a row (not shown) indicates metal layers RDL2 and RDL4. One or more vias are between these two metal layers (RDL2 and RDL4) but do not cross metal layer RDL3. As described above, the hole types and corresponding via types between the metal layers of the RDLs are specified by the user, or they are already specified by the semiconductor manufacturing process. Another field or other indicator indicates the absence of metal layer RDL3 in these particular overlap regions. Therefore, in these particular overlap regions, no metal from metal layer RDL3 is present between RDL2 and RDL4; only dielectric is present. In some embodiments, one or more fields in the table in GUI 600 include a cross-section definition of a via layer that identifies the thickness (depth) of the corresponding via between the corresponding metal layers. The pad stack definition provides the via diameter, as described above. Additionally, in some embodiments, a field in the table of GUI 600 indicates via stacking rules, such as vias in the Via 1 and Via 3 layers are allowed to be placed (stacked) in the same vertically aligned overlapping region, but vias in the Via 2 layer are not allowed to be placed in this same vertically aligned overlapping region.

[0038] Field 620 indicates the sequence order to use for automatic via generation in the redistribution layers. Via layers do not need to be traversed consecutively adjacently. The user can customize the order of via layers used by the automatic via generator. Note that in some cases, the automatic via generator defaults to using the maximum number of vias in the Via 1 layer to fit inside the area of ​​the pins in the SMD pin layer while still meeting the DRC using the pitch of the Via 1 layer. In various embodiments, the pins in the SMD pin layer are significantly larger than the vias in the Via 1 layer.

[0039] Note also that one or more via layers (one or more rows in the table) have multiple sequence numbers indicating iterations are being performed for a particular via layer. For example, briefly referring again to metal layers 400-500 (in FIGS. 4 and 5), the first pass through the Via 2 layer adds only a single column of vias for the Via 2 layer to the right edge of vertical metal layer RDL2. For portions of the redistribution layer that also have metal layer RDL3 overlapping metal layer RDL1, such as shown in metal layer 500, placement of vias for Via 2 layer is complete. However, for portions of the redistribution layer that do not have metal layer RDL3 overlapping metal layer RDL1, such as shown in metal layer 400, more vias for the Via 2 layer can be added.

[0040] Field 630 allows the user to indicate whether DRC violations are allowed. For example, the user may want to stagger vias on two different layers, such as vias on via 1 layer and vias on via 3 layer, etc. This allows more vias to fit within a particular area while still meeting the DRC spacing on the same via layer. Field 630 also allows the user to indicate whether a report should be generated that provides information on the results of the automatic via generation using the attributes provided in multiple fields of GUI 600.

[0041] 7, one embodiment of a method 700 for automatic via creation in a redistribution layer is shown. For purposes of explanation, the steps in this embodiment (as well as in FIG. 8) are shown in sequence. However, in other embodiments, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0042] A user selects attributes to customize automatic via generation in the redistribution layer (block 702). In one embodiment, the user provides the attributes to the automatic via generator via a graphical user interface (GUI). GUI 600 (in FIG. 6) is an example. In another embodiment, the user provides the attributes to the automatic via generator via a text file or executable file written in any of a variety of scripting languages. The user initiates execution of the automatic via generator, and a processor in a corresponding computing device performs automatic via generation in the redistribution layer based on the attributes (block 704). In one embodiment, this automatic generation includes receiving attributes such as a reference metal identification, starting point, direction, and sequence. Additionally, overlap regions are identified as described above. Based on this information, data indicating the placement of one or more vias between metal layers is generated. In addition, the attributes may include pitch and size information for a given layer, which is used to determine the spacing between the vias. Furthermore, as described above, in one embodiment, the automatic process is configured to divide the overlap region in half and place vias both above and below the overlap region. The user then runs one or more tools to perform design rule check (DRC) verification and layout versus schematic (LVS) verification (block 706).

[0043] The user determines whether the results of the automatic via generation meet the design requirements, such as measuring via redundancy and measuring equivalent via resistance in a specific area of ​​the redistribution layer. If the results do not meet the design requirements (conditional block 708: "No"), the control flow of method 700 returns to block 702, where the user selects attributes. If the results meet the design requirements (conditional block 708: "Yes"), the semiconductor package design is taped out and manufactured (block 710).

[0044] If no potential is applied to the first node of the integrated circuit in the semiconductor package (conditional block 712: "No"), the semiconductor package waits for power-on (block 714). On the other hand, if a potential is applied to the first node that created a potential difference (conditional block 710: "Yes"), automatically generated vias in the metal layers and redistribution layers transmit current between the integrated circuit and the motherboard (block 716).

[0045] Referring to FIG. 8 , one embodiment of a method 800 for automatic via generation in a redistribution layer is shown. A user defines attributes for the automatic via generator to use for automatic via generation in the redistribution layer. In one embodiment, the user provides the attributes to the automatic via generator via a graphical user interface (GUI) (GUI 600 (of FIG. 6 )). In another embodiment, the user provides the attributes to the automatic via generator via a text file or executable file written in any of a variety of scripting languages. When a processor executes the instructions of the automatic via generator, the processor defines pads at the far end of the redistribution layer (block 802). For example, the user defines a pitch for using inner pads. In one example, the user defines the pitch of vias in the Via 1 layer to connect to pins in the SMD pin layer. The user selects the pitch to satisfy existing DRC rules and maximize the number of vias in the Via 1 layer that physically connect to corresponding pins in the SMD pin layer. Based on the attributes entered by the user, the processor defines pins of the SMD pin layer at the top of the stack of redistribution layers and vias of the Via 5 layer at the bottom of the stack of redistribution layers, where top and bottom are orientation indicators.

[0046] The processor calculates a metal overlap area (block 804). Examples of metal overlap areas between metal layers RDL1 and RDL2 are shown in metal layers 300-500 (FIGS. 3-5). An example of a metal overlap area between metal layers RDL2 and RDL3 is shown in metal layer 500 (FIG. 5). In another example, the processor calculates a metal overlap area between a pin of an SMD pin layer and a metal layer of an RDL. In yet another example, the processor calculates a metal overlap area between a metal layer of an RDL and an under bump metallurgy (UBM) layer that provides electrical connection to a C4 bump. The shape of the metal overlap area is square, rectangular, or circular based on the upper and lower layers used to define the metal overlap area. In some embodiments, based on the received attributes, the processor divides the overlap area in half to allow via layers to be placed both above and below the overlap area. An example of this type of via placement is shown in metal layer 500 (FIG. 5). Based on the attributes indicating the reference metal, starting point, and direction, the processor places vias of different via layer types (e.g., Via 2, Via 3) in the overlap region. In some embodiments, if a top (upper) via is already placed in the split region, the bottom (lower) via is placed in the other half. If two adjacent layer overlap regions are not co-located, the overlap region is fully utilized for the bottom via, and vice versa (e.g., RDL1 and RDL3 are not in the same plane). Such an approach may be used when DRC constraints do not allow via stacking.

[0047] The processor generates vias based on the indicated sequence (block 806). The indicated sequence is specified in the attributes received from the user. The sequence order determines which via layer to use to start automatic via generation and which subsequent via layers to select for further automatic via generation. Vias are placed based on the size and pitch corresponding to the currently selected via layer to satisfy DRC rules. In addition, the processor does not change the dimensions of the metal layer of the signal route. If multiple sequences for a particular via layer are specified in the received attributes, the processor places additional vias in that via layer if possible. In some cases, via redundancy already exists, but the automatic via generator still increases the number of vias as much as possible. The processor generates a report (block 808). The processor maintains a log file during automatic via generation and uses corresponding information to provide summarized results in a report. In various embodiments, the processor writes a file located at a known destination.

[0048] Referring to FIG. 9 , one embodiment of a computing system 900 utilizing a redistribution layer with automatically placed vias is shown. The computing system 900 utilizes a chip package 940 that includes automatically generated vias in the redistribution layer. The chip package 940 may use any of a ball grid array (BGA) surface mount package, a chip scale package (CSP), and a system-in-package (SiP) that communicates with other components on a motherboard (or printed circuit board). In one embodiment, the computing system 900 includes a processor 910 and memory 930 within the chip package 940. In another embodiment, only one of the processor 910 and memory 930 is included within the chip package 940. Interfaces such as a memory controller, a bus or communication fabric, one or more phase-locked loops (PLLs) and other clock generation circuits, a power management unit, and the like are not shown for ease of illustration. Additionally, in the illustrated embodiment, the chip package 940 is connected to a memory bus 950 and disk memory 954 via an input / output (I / O) controller and bus 952.

[0049] It is understood that in other embodiments, computing system 900 includes one or more of the following: another processor of the same or different type as processor 910, one or more peripheral devices, a network interface, one or more other memory devices, etc. In some embodiments, the functionality of computing system 900 is integrated onto a system-on-chip (SoC). In other embodiments, the functionality of computing system 900 is integrated onto a peripheral card inserted into a motherboard. Computing system 900 may be used in any of a variety of computing devices, such as a desktop computer, a tablet computer, a laptop, a smartphone, a smartwatch, a game console, a personal assistant device, etc.

[0050] The processor 910 includes hardware such as circuitry. In various embodiments, the processor 910 includes one or more processing units. In some embodiments, each of the processing units includes one or more processor cores capable of general-purpose data processing and associated cache memory subsystems. In such embodiments, the processor 910 is a central processing unit (CPU). In other embodiments, the processing cores are computational units, each having a highly parallel data microarchitecture with multiple parallel execution lanes and associated data storage buffers. In such embodiments, the processor 910 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0051] In some embodiments, memory 930 includes any of various types of dynamic random access memory (DRAM). Memory 930 stores at least a portion of an operating system (OS) 932, one or more applications represented by code 934, and at least source data 936. In various embodiments, memory 930 stores copies of these software components 932, 934, 936, with original copies stored on disk memory 954. Memory 930 may also store intermediate and final result data generated by processor 910 when executing a particular application of code 934.

[0052] In various embodiments, off-chip disk memory 954 includes one or more hard disk drives (HDDs) and solid-state disks (SSDs) comprising banks of flash memory. I / O controller and bus 952 supports communication protocols with off-chip disk memory 954. While a single operating system 932 and a single instance of code 934 and source data 936 are shown, in other embodiments, other numbers of these software components are stored in memory 930 and disk memory 954. Operating system 932 includes instructions for initiating the boot-up of processor 910, assigning tasks to hardware circuitry, managing resources of computing system 900, and hosting one or more virtual environments.

[0053] It should be noted that one or more of the above-described embodiments include software. In such embodiments, program instructions implementing the methods and / or mechanisms are transmitted to or stored on a computer-readable storage medium. Many types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Generally speaking, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media (e.g., disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, Blu-Rays), and the like. Examples of storage media include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory) accessible via a peripheral interface such as a Universal Serial Bus (USB) interface, etc. Examples of storage media include microelectromechanical systems (MEMS), and storage media accessible via a communication medium such as a network and / or wireless link.

[0054] Additionally, in various embodiments, the program instructions include a behavioral or register-transfer level (RTL) description of the hardware functionality in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDS II stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to generate a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the system. The netlist can then be placed and routed to generate a data set that describes the geometric shapes that are applied to a mask. The mask can then be used in various semiconductor manufacturing steps to generate a semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set, as appropriate. Additionally, the instructions are utilized for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0055] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated, and it is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. 1. A processor, comprising: A circuit is provided. The circuit comprises: receiving a plurality of attributes corresponding to an arrangement of a plurality of vias between adjacent ones of the plurality of metal layers; generating data indicative of a placement of the plurality of vias between the adjacent metal layers based at least in part on the attribute and an identification of an overlap region in the adjacent metal layers, the attribute specifying an order of via placement across the plurality of via layers; configured to: Processor.

2. The attributes include one or more of a reference metal identification, a starting point, a direction, and a sequence. The processor of claim 1 .

3. the circuitry is configured to determine a placement of the plurality of vias based at least in part on a size and pitch of a currently selected via layer. The processor of claim 2 .

4. the circuitry is configured to determine spacing between a plurality of vias disposed in the overlap region based at least in part on the size and pitch. The processor of claim 3.

5. the circuit is configured to divide the overlap region in half and place vias both above and below the overlap region. The processor of claim 1 .

6. the circuitry is configured to generate an arrangement of the plurality of vias in an order of sequences specified by the plurality of attributes, each sequence identifying a pair of metal layers; The processor of claim 1 .

7. The multiple levels of metal layers are redistribution layers between the integrated circuit and the printed circuit board. The processor of claim 1 .

8. A computer-implemented method comprising: receiving a plurality of attributes corresponding to an arrangement of a plurality of vias between adjacent ones of the plurality of metal layers; generating data indicative of a placement of the plurality of vias between the adjacent metal layers based at least in part on the attribute and an identification of an overlap region in the adjacent metal layers, the attribute specifying an order of via placement across the plurality of via layers. method.

9. The attributes include one or more of a reference metal identification, a starting point, a direction, and a sequence.

9. The method of claim 8.

10. determining a placement of the plurality of vias based at least in part on a size and pitch of a currently selected via layer; 10. The method of claim 9.

11. generating an arrangement of the plurality of vias in an order of sequences specified by the plurality of attributes, each sequence identifying a pair of metal layers; 9. The method of claim 8.

12. The multiple levels of metal layers are redistribution layers between the integrated circuit and the printed circuit board. The method of claim 11.

13. the one or more signal types include one or more of a power supply voltage reference level or a ground reference voltage level used by the integrated circuit; 13. The method of claim 12.

14. receiving the plurality of attributes via a graphical user interface; The method of claim 11.

15. A computer-readable storage medium storing program instructions, comprising: The program instructions, when executed by a computer, receiving data including a plurality of attributes corresponding to an arrangement of a plurality of vias between adjacent ones of a plurality of metal layers; generating data indicative of a placement of the plurality of vias between the adjacent metal layers based at least in part on the attribute and an identification of an overlap region in the adjacent metal layers, the attribute specifying an order of via placement across the plurality of via layers; causing the computer to perform A computer-readable storage medium.

16. The attributes include one or more of a reference metal identification, a starting point, a direction, and a sequence.

16. The computer-readable storage medium of claim 15.

17. the program instructions are executable to determine a placement of the plurality of vias based at least in part on a size and pitch of a currently selected via layer.

17. The computer-readable storage medium of claim 16.

18. the program instructions are executable to determine a spacing between a plurality of vias disposed in the overlap region based at least in part on the size and pitch.

20. The computer-readable storage medium of claim 17.

19. the program instructions are executable to divide the overlap region in half and place vias both above and below the overlap region.

16. The computer-readable storage medium of claim 15.

20. The program instructions are executable to generate an arrangement of the plurality of vias in an order of sequences specified by the plurality of attributes, each sequence identifying a pair of metal layers.

16. The computer-readable storage medium of claim 15.

Images