Lossless encoding / decoding modes for video encoding / decoding

Abstract

A method and apparatus for video encoding / decoding in a lossless encoding / decoding mode are provided, the method including: partitioning a video image into a plurality of CUs including a lossless CU; determining a residual encoding / decoding block size of the lossless CU; and, in response to determining that the residual encoding / decoding block size of the lossless CU is greater than a predetermined maximum value, splitting the residual encoding / decoding block into two or more residual blocks for residual encoding / decoding.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application No. 62 / 868,857, filed June 28, 2019, entitled "Lossless Encoding / Decoding Mode for Video Encoding / Decoding," and U.S. Provisional Application No. 62 / 871,134, filed July 6, 2019, entitled "Lossless Encoding / Decoding Mode for Video Encoding / Decoding," the entire specifications of which are incorporated herein by reference. [Technical Field]

[0002] This application relates generally to video encoding / decoding and compression. In particular, this disclosure relates to improving and simplifying lossless encoding / decoding for video encoding / decoding. [Background technology]

[0003] Various video encoding / decoding techniques can be used to compress video data. The video encoding / decoding is performed according to one or more video encoding / decoding standards. Exemplary video encoding / decoding standards include Versatile Video Coding (VVC), Joint Exploration Test Model (JEM), High Efficiency Video Coding / decoding (H.265 / HEVC), Advanced Video Coding / decoding (H.264 / AVC), and Moving Picture Experts Group (MPEG) encoding / decoding. Video encoding / decoding generally utilizes prediction methods (e.g., inter-prediction, intra-prediction, etc.) that rely on redundancy present in a video image or sequence. An important goal of video encoding / decoding techniques is to compress video data into a lower bitrate format while avoiding or minimizing degradation of video quality.

[0004] The first version of the HEVC standard was finalized in October 2013 and provides approximately 50% bitrate savings or equivalent visual quality compared to the previous generation video encoding / decoding standard, H.264 / MPEG AVC. While the HEVC standard offers significant encoding / decoding improvements over its predecessor, there is evidence that better coding efficiency than HEVC can be achieved by adding additional encoding / decoding tools on top of HEVC. Based on this, both ITU-TVECG and MPEG have begun exploring new encoding / decoding techniques for future video encoding / decoding standardization. The Joint Video Experts Team (JVET), formed by ITU-TVECG and ISO / IEC MPEG in October 2015, has begun significant research into advanced techniques that could significantly improve encoding / decoding efficiency. Reference software, called the Joint Exploration Model (JEM), integrates several additional coding tools on top of the HEVC Test Model (HM) and is maintained by the JVET.

[0005] A joint call for proposals (CfP) for video compression with capabilities beyond HEVC was issued by ITU-T and ISO / IEC in October 2017. In April 2018, 23 CfP responses were received and evaluated at the 10th JVET meeting, demonstrating an approximately 40% improvement in compression efficiency over HEVC. Based on these evaluation results, JVET launched a new project to develop a new generation of video coding and decoding standard called Versatile Video Coding and Decoding (VVC). In the same month, a reference software code base called the VVC Test Model (VTM) was established to demonstrate a reference implementation of the VVC standard. Summary of the Invention

[0006] This disclosure describes example techniques generally related to lossless encoding and decoding in video encoding and decoding.

[0007] According to a first aspect of the present disclosure, there is provided a lossless coding mode method for video coding, including: partitioning a video image into a plurality of lossless coding / decoding units (CUs), each CU including a lossless coding / decoding unit; determining a residual coding / decoding block size of the lossless CU; and, in response to determining that the residual coding / decoding block size of the lossless CU is greater than a predetermined maximum value, splitting the residual coding block into two or more residual blocks for residual coding.

[0008] According to a second aspect of the present disclosure, there is provided a lossless encoding / decoding mode method for video encoding / decoding, including partitioning a video image into a plurality of lossless encoding / decoding units (CUs), each CU comprising the lossless encoding / decoding units; and selecting for the lossless CUs a residual encoding / decoding scheme that is the same as that used for non-transform skip mode CUs.

[0009] According to a third aspect of the present disclosure, there is provided an apparatus for a lossless encoding / decoding mode for video encoding / decoding, comprising: one or more processors; and a memory configured to store instructions executable by the one or more processors, wherein the one or more processors, when executing the instructions, are configured to: partition a video image into a plurality of lossless encoding / decoding units (CUs), each CU including a CU; determine a residual encoding / decoding block size of the lossless CU; and, in response to determining that the residual encoding / decoding block size of the lossless CU is greater than a predetermined maximum value, divide the residual encoding / decoding block into two or more residual blocks for residual encoding / decoding.

[0010] According to a fourth aspect of the present disclosure, there is provided an apparatus for a lossless encoding / decoding mode for video encoding / decoding, comprising: one or more processors; and a memory configured to store instructions executable by the one or more processors, wherein the one or more processors, when executing the instructions, are configured to partition a video image into a plurality of lossless encoding / decoding units (CUs), each CU including a lossless encoding / decoding unit, and select for the lossless CUs a residual encoding / decoding scheme that is the same as that used for non-transform skip mode CUs.

[0011] According to a fifth aspect of the present disclosure, there is provided an apparatus for video encoding and decoding, comprising: one or more processors; and a non-transitory storage medium configured to store instructions executable by the one or more processors, the instructions, when executed, causing the one or more processors to perform operations such as partitioning a video image into a plurality of lossless encoding / decoding units (CUs), each CU including a CU; determining a residual encoding / decoding block size of the lossless CU; and, in response to determining that the residual encoding / decoding block size of the lossless CU is greater than a predetermined maximum value, dividing the residual encoding / decoding block into two or more residual blocks for residual encoding / decoding.

[0012] According to a sixth aspect of the present disclosure, there is provided an apparatus for video encoding and decoding, comprising one or more processors; and a non-transitory storage medium configured to store instructions executable by the one or more processors, the instructions, when executed, causing the one or more processors to perform operations such as partitioning a video image into a plurality of lossless encoding / decoding units (CUs), each CU including a lossless encoding / decoding unit, and selecting for the lossless CUs a residual encoding / decoding scheme that is the same as that used for non-transform skip mode CUs. [Brief explanation of the drawings]

[0013] A more particular description of examples of the present disclosure will be given by reference to specific examples illustrated in the accompanying drawings, which examples will be described with additional specificity and detail through the use of the accompanying drawings, which illustrate only some examples and are therefore not intended to be limiting in scope. [Figure 1] FIG. 1 is a block diagram illustrating an example video encoder according to an embodiment of this disclosure. [Figure 2A] FIG. 2A is a schematic diagram illustrating quaternary block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2B]FIG. 2B is a schematic diagram illustrating horizontal dual block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2C] FIG. 2C is a schematic diagram illustrating vertical dual block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2D] FIG. 2D is a schematic diagram illustrating horizontal ternary block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2E] FIG. 2E is a schematic diagram illustrating vertical ternary block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a block diagram illustrating an example video decoder according to an embodiment of this disclosure. [Figure 3A] FIG. 3A is a schematic diagram illustrating an example of decoder-side motion vector refinement (DMVR), according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram illustrating an example of an image divided into CTUs, tiles, and tile groups, according to one embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic diagram illustrating another example of an image divided into CTUs, and further into tiles and tile groups, according to an embodiment of the present disclosure. [Figure 6A] FIG. 6A is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6B] FIG. 6B is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6C] FIG. 6C is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6D] FIG. 6D is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6E] FIG. 6E is a schematic diagram illustrating examples of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6F] FIG. 6F is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6G] FIG. 6G is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 6H] FIG. 6H is a schematic diagram illustrating an example of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram illustrating an example apparatus for a lossless encoding / decoding mode for video encoding / decoding, according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a flowchart illustrating an example process of a lossless encoding / decoding mode for video encoding / decoding according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a flowchart illustrating another exemplary process of a lossless encoding / decoding mode for video encoding / decoding, according to an embodiment of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following detailed description, a number of non-limiting specific details are set forth to facilitate understanding of the concept described herein. However, it will be apparent to those skilled in the art that the present invention can be embodied in various modifications. For example, it will be apparent to those skilled in the art that the concept described herein can be embodied in many types of electronic devices having digital video capabilities.

[0015] As used herein, the singular or plural forms "one embodiment," "embodiment," "example," "an embodiment," "an example," or similar expressions mean that a particular feature, structure, or characteristic being described is included in at least one embodiment or example. A feature, structure, element, or characteristic described in connection with one or more embodiments may also be applicable to other embodiments, unless expressly stated otherwise.

[0016] Throughout this disclosure, all terms such as "first," "second," "third," etc. are used solely to refer to related elements, e.g., devices, components, configurations, steps, etc., and do not imply spatial or chronological order, unless the context clearly dictates otherwise. For example, "first device" and "second device" may refer to two separately formed devices or two parts, components, or operating states of the same device, which may be arbitrarily named.

[0017] As used herein, terms such as "if" or "if" or "if" can be understood to mean "when" or "depending on," depending on the context. When these terms appear in the claims, they do not imply that the associated limitation or feature is conditional or optional.

[0018] The terms "module," "sub-module," "circuit," "sub-circuit," "unit," or "sub-unit" include memory (shared, dedicated, or group) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits that may or may not store code or instructions. A module or circuit may include one or more components that are directly or indirectly connected. These components may be physically connected to each other, physically disconnected, or adjacent to each other.

[0019] A unit or module may be implemented entirely in software, entirely in hardware, or a combination of hardware and software. In an entirely software implementation, for example, a unit or module may include functionally related code blocks or software components that are directly or indirectly linked together to perform specific functions.

[0020] FIG. 1 shows a block diagram of an exemplary block-based hybrid video encoder 100 that can be used in combination with many video encoding / decoding standards that utilize block-based processing. VVC is built on a block-based hybrid video encoding / decoding framework. In the encoder 100, the input video signal is processed in blocks, which can be called coding / decoding units (CUs). In VTM-1.0, a CU can be up to 128x128 pixels. However, unlike HEVC, which partitions blocks based solely on quadtrees, VVC divides a single coding / decoding tree unit (CTU) into multiple CUs based on quadtrees / binary trees / ternary trees to adapt to various local characteristics. Just as the division of components into CTBs is a partition, a coding / decoding tree block (CTB) is, by definition, an NxN block of samples for some value of N. A CTU includes a CTB for luma samples for an image with a three-sample array, two corresponding CTBs for chroma samples, or a CTB for samples for a monochrome image or an image coded with three separate color planes, and the syntactic structures used for coding and decoding the samples. Furthermore, the concept of multiple partition unit types in HEVC has been removed, meaning that the separation of CUs, prediction units (PUs) and transform units (TUs) no longer exists in VVC. Instead, each CU is always used as the basic unit for both prediction and transformation, without further partitioning.

[0021] In the multi-type tree structure, a CTU is first partitioned using a quadtree structure. Then, each quadtree leaf node can be further partitioned using binary and ternary tree structures. As shown in Figures 2A-2E, there are five partition types: quadtree (Figure 2A), horizontal binary (Figure 2B), vertical binary (Figure 2C), horizontal ternary (Figure 2D), and vertical ternary (Figure 2E).

[0022] For a given video block, predictions are formed based on either an inter-prediction approach or an intra-prediction approach. In inter-prediction, one or more predictors are formed based on pixels from a previously reconstructed frame using motion estimation and motion compensation. In intra-prediction, predictors are formed based on reconstructed pixels in the current frame. A mode decision can select the best predictor for predicting the current block.

[0023] A prediction residual, which represents the difference between the current video block and its predictor, is sent to a transform circuit 102. The transform coefficients are then sent from the transform circuit 102 to a quantification circuit 104 for entropy reduction. The quantified coefficients are then provided to an entropy coding and decoding circuit 106 to generate a compressed video bitstream. As shown in FIG. 1, prediction-related information 110, such as video block partition information, motion vectors, reference picture indices, and intra-prediction modes from an inter-prediction circuit and / or an intra-prediction circuit 112, is also provided via the entropy coding and decoding circuit 106 and stored in the compressed video bitstream 114.

[0024] The encoder 100 also requires decoder-related circuitry to reconstruct pixels for prediction purposes. First, a prediction residual is reconstructed via an inverse quantification 116 and an inverse transform circuit 118. This reconstructed prediction residual is combined with a block predictor 120 to generate unfiltered reconstructed pixels for the current video block.

[0025] Spatial prediction (also called "intra prediction") predicts the current video block using pixels from samples (also called reference samples) of already coded and decoded neighboring blocks within the same video frame as the current video block.

[0026] Temporal prediction (also called "inter-prediction") predicts a current video block using reconstructed pixels from previously coded and decoded video images. Temporal prediction reduces the temporal redundancy inherent in video signals. The temporal prediction signal for a coding / decoding unit (CU) or coding / decoding block is typically signaled by one or more motion vectors (MVs), which indicate the amount and direction of motion between the current CU and its temporal references. Furthermore, if multiple reference images are supported, a reference image index is additionally transmitted to identify which reference image in the reference image store the temporal prediction signal comes from.

[0027] After spatial and / or temporal prediction is performed, an intra / inter mode decision circuit 121 in encoder 100 selects an optimal prediction mode based, for example, on a rate-distortion optimization method. Next, block predictor 120 is subtracted from the current video block, and the resulting prediction residual is decorrelated by transform circuit 102 and quantification circuit 104. The resulting quantification residual coefficients are inversely quantified by inverse quantification circuit 116 and inversely transformed by inverse transform circuit 118 to generate a reconstructed residual, which is then added to the prediction block to generate a reconstructed signal for this CU. Furthermore, an in-loop filter 115, such as a deblocking filter, sample adaptive offset (SAO), and / or adaptive in-loop filter (ALF), may be applied to this reconstructed CU before it is placed in a reference picture store in picture buffer 117 for use in encoding and decoding future video blocks. To generate the output video bitstream 114, the encoding / decoding mode (inter or intra), prediction mode information, motion information, and quantified residual coefficients are all sent to the entropy encoding / decoding unit 106, which further compresses and packs them to generate the bitstream.

[0028] For example, the current versions of AVC, HEVC, and VVC provide a deblocking filter. HEVC defines an additional in-loop filter called SAO (Sample Adaptive Offset) to further improve coding efficiency. For the current version of the VVC standard, another in-loop filter called ALF (Adaptive Loop Filter) is being actively researched and is likely to be included in the final standard.

[0029] These in-loop filter operations are selectable. Performing these operations contributes to improving encoding / decoding efficiency and visual quality. These operations can be turned off as determined by the encoder 100 to save computational complexity.

[0030] Note that when these filter options are turned on by the encoder 100, intra prediction is typically based on pixels of the unfiltered reconstruction, while inter prediction is based on pixels of the filtered reconstruction.

[0031] Figure 3 is a block diagram illustrating an exemplary block-based video decoder 200 that can be used in combination with many video encoding and decoding standards. This decoder 200 is similar to the reconstruction-related parts present in the encoder 100 of Figure 1. In the decoder 200, an input video bitstream 201 is first decoded via entropy decoding 202 to derive quantified coefficient levels and prediction-related information. The quantified coefficient levels are then processed by inverse quantification 204 and inverse transform 206 to obtain a reconstructed prediction residual. A block predictor mechanism implemented in an intra / inter mode selector 212 is configured to perform intra prediction 208 or motion compensation 210 based on the decoded prediction information. The reconstructed prediction residual from the inverse transform 206 and the prediction output generated by the block predictor mechanism are summed by a summing unit 214 to obtain a set of unfiltered reconstructed pixels.

[0032] The reconstructed blocks may further pass through an in-loop filter 209 before being stored in an image buffer 213, which acts as a reference image store. The reconstructed video in the image buffer 213 may be sent to drive a display device or used to predict future video blocks. If the in-loop filter 209 is on, it performs a filtering operation on these reconstructed pixels to derive the final reconstructed video output 222.

[0033] In general, the basic intra prediction scheme applied in VVC is kept the same as that of HEVC, except that some modules are further extended and / or improved, such as, for example, intra sub-partition (ISP) coding / decoding mode, intra prediction extended in wide-angle intra direction, position-dependent intra prediction combining (PDPC) and 4-tap intra interpolation. Images, Tile Groups, Tiles and CTU Partitions in VVC

[0034] In VVC, a tile is defined as a rectangular region of CTUs within a particular tile column and a particular tile row in a picture. A tile group is a group of an integer number of tiles in a picture that are exclusively contained in a single NAL unit. Essentially, the concept of a tile group is the same as that of a slice defined in HEVC. For example, a picture is divided into tile groups and tiles.

[0035] A tile is a set of CTUs that contain a rectangular region in an image. A tile group contains multiple tiles of an image. Two tile group modes are supported: raster scan tile group mode and rectangular tile group mode. In raster scan tile group mode, a tile group contains a set of tiles in the tile raster scan of an image. In rectangular tile group mode, it contains multiple tiles of an image that collectively form a rectangular region of the image. The tiles in a rectangular tile group are in the order of the tile raster scan of the tile group.

[0036] Figure 4 shows an example of a raster scan tile group partition of an image where the image is divided into 12 tiles and 3 raster scan tile groups.

[0037] Figure 5 shows an example of a rectangular tile group partition of an image where the image is divided into 24 tiles (6 tile columns and 4 tile rows) and 9 rectangular tile groups. Large block size transform with high frequency zeroing in VVC.

[0038] VTM4 allows for large block size transforms, up to 64x64 in size, primarily for high-resolution video, such as 1080p and 4K sequences. For transform blocks of size 64 (width or height, or both width and height), high-frequency transform coefficients are zeroed out, so only low-frequency coefficients are retained. For example, for an MxN transform block, where M is the block width and N is the block height, if M equals 64, only the left 32 columns of transform coefficients are retained. Similarly, if N equals 64, only the top 32 rows of transform coefficients are retained. Using transform skip mode for large blocks uses the entire block without zeroing any values. Virtual Pipeline Data Unit (VPDU) in VVC

[0039] A Virtual Pipeline Data Unit (VPDU) is defined as a non-overlapping unit within a picture. In a hardware decoder, consecutive VPDUs are processed simultaneously by multiple pipeline stages. It is important to keep the VPDU size small because it is roughly proportional to the buffer size in most pipeline stages. In most hardware decoders, the VPDU size can be set to the maximum transform block (TB) size. However, in VVC, ternary tree (TT) and binary tree (BT) partitioning can increase the VPDU size.

[0040] To keep the VPDU size as 64x64 luma samples, the following normative partition restrictions (with syntax notification changes) are applied to VTM5 as shown in Figures 6A-6H. For convenience, the examples in Figures 6A-6D are labeled from left to right for the upper example, and the examples in Figures 6E-6H are labeled from left to right for the lower example. For CUs where either width or height, or both width and height, are equal to 128, TT splitting is not allowed (Figs. 6A, 6B, 6E, 6F, 6G and 6H). For CUs with −128 × N (N ≤ 128, i.e., width equal to 128 and height less than or equal to 128), horizontal BT is not allowed (Figure 6D). For −N (N≦128, i.e., height equals 128 and width less than or equal to 128) × 128 CUs, vertical BT is not allowed (Figure 6C). Transform Coefficient Coding in VVC

[0041] Transform coefficient coding / decoding refers to the coding / decoding process of transform coefficient quantization level values ​​of a TU. In HEVC, the transform coefficients of a coding / decoding block are coded / decoded by non-overlapping coefficient groups (or sub-blocks), and each CG contains coefficients of a 4x4 block of the coding / decoding block. CGs within a coding / decoding block and the transform coefficients within the CG are coded / decoded in a predetermined scanning order. The coding / decoding of transform coefficient levels of CGs with at least one non-zero transform coefficient can be separated into multiple scanning passes. In the first pass, the first bin (denoted by bin0 and also called important_coeff_flag, which indicates that the coefficient magnitude is greater than 0) is coded / decoded. Next, two scanning passes can be applied to context-code the second / third bins (denoted by bin1 and bin2, respectively, also called coeff_abs_greater1_flag and coeff_abs_greater2_flag). Finally, two more scan passes are invoked to encode and decode the remaining values ​​of the sign information and coefficient levels (also called coeff_abs_level_remaining) if necessary. Note that only the bins in the first three scan passes are encoded and decoded in normal mode and are referred to as normal bins in the following description.

[0042] In VVC3, for each sub-block, the normal coded bins and the bypass coded bins are separated in coding / decoding order. First, all the normal coded bins of the sub-block are transmitted, followed by the bypass coded bins. The transform coefficient levels of the sub-block are coded in four passes at the scanning positions as follows: - Pass 1: The encoding and decoding of the importance (sig_flag), the greater than 1 flag (gt1_flag), the parity (par_level_flag), and the greater than 2 flag (gt2_flag) are processed in encoding and decoding order. If sig_flag is equal to 1, gt1_flag is encoded and decoded first (indicating whether the absolute level is greater than 1). If gt1_flag is equal to 1, par _level _flag is additionally encoded and decoded (specifies the parity at absolute level minus 2). Pass 2: The remaining absolute levels (residues) are coded at all scan positions where gt2_flag is 1 or gt1_flag is 1. Non-binary syntax elements are binarized with a Golomb-Rice code, and the resulting bins are coded and decoded in the bypass mode of the arithmetic coding / decoding engine. Pass 3: The absolute levels (absLevel) of coefficients whose sig_flag has not been coded in the first pass (because the limit of the normal coded bins has been reached) are fully coded in the bypass mode of the arithmetic coding / decoding engine using Golomb-Rice coding. Pass 4: Encoding and decoding of the sign (sign_flag) for all scan positions where sig_coeff_flag is equal to 1

[0043] For 4x4 sub-blocks, no more than 32 normal coded / decoded bins (sig_flag, par_flag, gt1_flag, and gt2_flag) are guaranteed to be coded or decoded. For 2x2 chroma sub-blocks, the number of normal coded / decoded bins is limited to 8.

[0044] The Rice parameter (ricePar) for encoding / decoding the remainder of a non-binary syntax element (pass 3) is derived in the same way as in HEVC. At the start of each sub-block, ricePar is set to 0. After encoding / decoding the remainder of a syntax element, the Rice parameter is modified according to a predetermined formula. To encode / decode the non-binary syntax element absLevel (pass 4), the sum of absolute values ​​of the local template, sumAbs, is determined. The variables ricePar and posZero are determined based on the dependent quantification by table lookup and sumAbs. The intermediate variable codeValue is derived as follows: If -absLevel[k] is equal to 0, then codeValue is set equal to posZero. - Otherwise, if absLevel[k] is less than or equal to posZero, codeValue is set equal to absLevel[k] -1. Otherwise (absLevel[k] is greater than posZero), codeValue is set equal to absLevel[k]. The value of codeValue is encoded and decoded using a Golomb-Rice code with the Rice parameter ricePar.

[0045] In the remainder of this disclosure, transform coefficient coding and decoding is also referred to as residual coding and decoding. Decoder-side Motion Vector Refinement (DMVR) in VVC

[0046] Decoder-side motion vector refinement (DMVR) is a technique for blocks coded and decoded in bi-predictive merge mode, controlled by the sps_dmvr_enabled_flag flag signaled by the SPS signal. In this mode, the two motion vectors (MVs) of a block can be further refined by bilateral matching (BM) prediction.

[0047] 3A is a schematic diagram illustrating an example of decoder-side motion vector refinement (DMVR). As shown in FIG. 3A, a bilateral matching method is used to refine the motion information of a current CU 322 in a current image 320 by searching for the closest match between its two reference blocks 302, 312 along the current CU's motion trajectory in its two associated reference images, i.e., refPic in List L0 300 and refPic in List L1 310. Pattern rectangular blocks 322, 302, and 312 indicate the current CU and its two reference blocks based on the initial motion information from the merge mode. Pattern rectangular blocks 304, 314 indicate a pair of reference blocks based on MV candidates used in the motion refinement search process, i.e., the motion vector refinement process.

[0048] The MV difference between the candidate MV and the initial MV (also called the original MV) is MV diff and -MV diff MV candidates and early Music Video Both are bidirectional motion vectors. During the DMVR process, the number of such MV candidates around the initial MV can be checked. Specifically, for each given MV candidate, its two associated reference blocks are located from its reference images in List0 and List1, respectively, and the difference between them is calculated. Such block differences are usually measured by SAD (or sum of absolute differences) or row-subsampled SAD (i.e., SAD calculated for every other row of the associated block). Finally, the MV candidate with the lowest SAD between the two reference blocks becomes the refined MV and is used as the actual prediction for the current CU to generate a bi-predicted signal.

[0049] In VVC, DMVR applies to CUs that meet the following conditions: Encoded and decoded in CU level merge mode (not sub-block merge mode) with bi-predictive MV. With respect to the current image, one reference image of the CU is in the past (i.e., POC is smaller than the current image POC) and the other reference image is in the future (i.e., POC is larger than the current image POC). · The POC distance (i.e., absolute POC difference) from both reference images to the current image is the same. A CU is greater than 64 luma samples in size and greater than 8 luma samples in height.

[0050] The refined MVs derived by the DMVR process are used to generate inter prediction samples and are also used for temporal motion vector prediction for future image encoding / decoding. The original MVs are also used for the deblocking process and for spatial motion vector prediction for future CU encoding / decoding. Some additional features of DMVR are presented in the following subsections. Bi-directional Optical Flow (BDOF) in VVC

[0051] The Bidirectional Optical Flow (BDOF) tool is included in VTM5. Formerly called BIO, BDOF is included in JEM. Compared to the JEM version, BDOF in VTM5 is a simpler version that requires much less computation, especially in terms of the number of multiplications and the size of the multipliers. BDOF is controlled by the SPS sps_bdof_enabled_flag flag.

[0052] BDOF is used to refine the bi-predictive signal of a CU at the 4x4 sub-block level. BDOF is applied to a CU when the following conditions are met: 1) the height of the CU is not 4 and the size of the CU is not 4x8; 2) the CU is not coded / decoded in affine mode or ATMVP merge mode; 3) the CU is coded / decoded in "true" bi-predictive mode, that is, one of the two reference pictures is before the current picture in display order, and the other is after the current picture in display order. BDOF is only applied to the luma component.

[0053] As the name suggests, BDOF mode is based on the concept of optical flow, which assumes smooth object motion. BDOF calculates the gradient of the current block and adjusts the predicted samples to improve coding efficiency. Decoder-side control for DMVR and BDOF in VVC

[0054] In current VVC, for normal merge candidates, BDOF / DMVR is always applied if the SPS flag is enabled and some bi-prediction and size constraints are met.

[0055] DMVR applies to normal merge mode when all of the following conditions are met: - sps_dmvr_enabled_flag equals 1 - general_merge_flag [xCb] [yCb] equals 1 - predFlagL0[0][0] and predFlagL1[0][0] are both equal to 1 - mmvd_merge_flag [xCb] [yCb] equals 0 -DiffPicOrderCnt(currPic, RefPicList [0] [refIdxL0]) is equal to DiffPicOrderCnt(RefPicList [1] [refIdxL1], currPic) - BcwIdx[xCb][yCb] equals 0 - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both equal to 0 - cbWidth is 8 or greater - cbHeight is 8 or greater - cbHeight * cbWidth is 128 or greater

[0056] BDOF is applied to bi-prediction when all of the following conditions are met: - sps_bdof_enabled_flag is equal to 1. - predFlagL0[xSbIdx][ySbIdx] and predFlagL1[xSbIdx][ySbIdx] are both equal to 1. - DiffPicOrderCnt(currPic, RefPicList [0] [refIdxL0]) * DiffPicOrderCnt(currPic, RefPicList [1] [refIdxL1]) is less than 0. - MotionModelIdc[xCb][yCb] is equal to 0. - merge_subblock_flag[xCb][yCb] is equal to 0. - sym_mvd_flag[xCb][yCb] is equal to 0. - BcwIdx[xCb][yCb] is equal to 0. - luma_weight_l0_flag[refIdxL0] and luma_weight_l1_flag[refIdxL1] are both 0. - cbHeight is 8 or greater. - cIdx is equal to 0. Residual coding for transform skip mode CUs in VVC Decryption

[0057] VTM5 allows the use of transform skip mode for luma blocks of up to 32x32 size (inclusive). When a CU is coded / decoded in transform skip mode, its prediction residual is quantized and coded / decoded by a transform skip residual coding / decoding process. This residual coding / decoding process is modified from the transform coefficient coding / decoding process described in the previous section. In transform skip mode, the residual of the CU is also coded / decoded in units of non-overlapping sub-blocks of 4x4 size. Unlike the normal transform coefficient coding / decoding process, in transform skip mode, instead of signaling the last coefficient position, coded_subblock_flag is signaled for all 4x4 sub-blocks in the CU in forward scan order, i.e., from the upper-left sub-block to the last sub-block.

[0058] For each sub-block, if coded_subblock_flag is equal to 1 (i.e., the sub-block has at least one non-zero quantified residual), the encoding and decoding of the quantified residual level is performed in three scan passes: - First scan pass: The significance flag (sig_coeff_flag), sign flag (coeff_sign_flag), absolute level flag greater than 1 (abs_level_gtx_flag[0]), and parity (par_level_flag) are coded / decoded. For a scan position, if coeff_sig_flag is equal to 1, coeff_sign_flag is coded / decoded, followed by abs_level_gtx_flag[0] (which specifies whether the absolute level is greater than 1). If abs_level_gtx_flag[0] is equal to 1, par_level_flag is additionally coded / decoded to specify the absolute level parity. - Scan passes greater than x: For each scan position where the absolute level is greater than 1, up to four abs_level_gtx_flag[i] (i = 1 ... 4) are encoded / decoded to specify whether the absolute level at a position is greater than 3, 5, 7, or 9. - Remaining scan pass: For all scan positions where abs_level_gtx_flag[4] is equal to 1 (i.e., the absolute level is greater than 9), the remaining absolute levels are encoded and decoded. The remaining absolute levels are binarized using the reduced Rice parameter derivation template.

[0059] Bins in scan passes #1 and #2 (the first scan pass and scan passes greater than x) are context-decoded until the maximum number of context-decoded bins in a CU is reached. The maximum number of context-decoded bins in a residual block is limited to 2*block_width*block_height, or equivalently, an average of two context-coded bins per sample position. Bins in the last scan pass (the remaining scan passes) are bypass-decoded. Lossless encoding in HEVC

[0060] The lossless encoding / decoding mode in HEVC is achieved by simply bypassing the transform, quantization, and in-loop filters (deblocking filter, sample adaptive offset, and adaptive loop filter). This design aims to enable lossless encoding / decoding with minimal changes required to implement regular HEVC encoders and decoders for mainstream applications.

[0061] In HEVC, the lossless encoding / decoding mode can be turned on or off at each CU level. This is done via the syntax cu_transquant_bypass_flag, which is signaled at the CU level. To reduce signaling overhead when the lossless encoding / decoding mode is not required, the cu_transquant_bypass_flag syntax is not always signaled. It is signaled only when another syntax called transquant_bypass_enabled_flag has a value of 1. In other words, the syntax transquant_bypass_enabled_flag is used to turn on the signaling of the cu_transquant_bypass_flag syntax.

[0062] In HEVC, the syntax transquant_bypass_enabled_flag is signaled in a Picture Parameter Set (PPS) to indicate whether the syntax cu_transquant_bypass_flag needs to be signaled for each CU in a picture that references this PPS. If this flag is set to 1, the syntax cu_transquant_bypass_flag is sent at the CU level to indicate whether the current CU is encoded or decoded in lossless mode. If this flag is set to 0 in the PPS, cu_transquant_bypass_flag is not sent and all CUs in the picture are encoded or decoded with the transform, quantization, and loop filter included in the process, which typically results in a certain level of video quality degradation. To encode and decode the entire picture losslessly, the flag transquant_bypass_enabled_flag in the PPS must be set to 1, and the CU-level flag cu_transquant_bypass_flag must be set to 1 for each CU in the picture. Detailed syntax signaling related to lossless mode in HEVC is shown as follows: - transquant_bypass_enabled_flag equal to 1 specifies that cu_transquant_bypass_flag is present. transquant_bypass_enabled_flag equal to 0 specifies that cu_transquant_bypass_flag is not present. - cu_transquant_bypass_flag equal to 1 specifies that the scale and transform processes specified in Section 8.6 and the in-loop filter processes specified in Section 8.7 are bypassed. If cu_transquant_bypass_flag is not present, it is inferred to be equal to 0. [Table 1]

[0063] In VVC, the maximum CU size is 64x64, and the VPDU is also set to 64x64. Due to the coefficient zeroing mechanism for widths / heights larger than 32, the maximum block size for coefficient encoding / decoding in VVC is 32x32. Under this constraint, the current transform skip only supports CUs up to 32x32, so that the maximum block size for residual encoding / decoding is 32x32 for coefficient encoding / decoding. However, VVC does not define a block size constraint for residual encoding / decoding of lossless CUs. As a result, currently, VVC can generate residual blocks larger than 32x32 in lossless encoding / decoding mode, which requires support for residual encoding / decoding for blocks larger than 32x32. This is undesirable for the codec. In this disclosure, several methods are proposed to solve this problem.

[0064] Another issue related to supporting lossless encoding / decoding in VVC is how to select a residual (or coefficient) encoding / decoding scheme. Currently, two different residual encoding / decoding schemes are available in VVC. For a given block (or CU), the selection of the residual encoding / decoding scheme is based on the transform skip flag of the given block (or CU). Therefore, in VVC, like HEVC, if the transform skip flag is assumed to be 1 in lossless mode, the residual encoding / decoding scheme used in transform skip mode is always used for the lossless mode CU. However, the current residual encoding / decoding scheme used when the transform skip flag is true is primarily designed for encoding / decoding screen content. It may not be optimal to use it for lossless encoding / decoding of normal content (i.e., non-screen content). This disclosure proposes several methods for selecting a residual encoding / decoding scheme for a lossless CU.

[0065] In the current VVC, two decoder-side tools, namely, BDOF and DMVR, refine the decoded pixels by filtering the current block, improving encoding / decoding performance. However, in lossless encoding / decoding, BDOF and DMVR do not contribute to encoding / decoding gain because the predicted pixels are already perfectly predicted. Therefore, decoder-side BDOF and DMVR do not benefit VVC, and these tools should not be applied to lossless encoding / decoding. However, in the current VVC, BDOF and DMVR are always applied for a typical merge candidate when the SPS flag is enabled and some bi-prediction and size constraints are satisfied. Therefore, for lossless VVC encoding / decoding, controlling DMVR and BDOF at lower levels, i.e., the slice level and CU level, can benefit the performance efficiency of VVC lossless encoding / decoding. Residual block partition of reversible CU

[0066] According to an example of the present disclosure, it is proposed to align the maximum residual encoding / decoding block size of a lossless CU with the maximum block size supported by the transform skip mode. In one example, the transform skip mode can be enabled only for residual blocks whose width and height are both 32 or less, meaning that the maximum residual encoding / decoding block size in the transform skip mode is 32x32. According to this example, the maximum width and / or height of the residual block for a lossless CU is also set to 32, and the maximum residual block size is set to 32x32. Whenever the width / height of a lossless CU is greater than 32, the CU residual block is divided into multiple smaller residual blocks of size 32xN and / or 32xN, with the width or height of the smaller residual block being 32 or less. For example, a 128x32 lossless CU is divided into four 32x32 residual blocks for residual encoding / decoding. In another example, a 64x64 lossless CU is divided into four 32x32 residual blocks.

[0067] According to another example of the present disclosure, it is proposed to align the maximum block size for residual encoding / decoding of a lossless CU with the size of a VPDU. In one example, the width / height of the largest residual block of a lossless CU is set to the VPDU size (e.g., 64x64 in the current VVC). Whenever the width / height of a lossless CU is greater than 64, the residual block of the CU is divided into multiple smaller residual blocks of size 64xN and / or Nx64, and the width or height of these smaller residual blocks is equal to or less than the width and / or height of the VPDU. For example, a 128x128 lossless CU is divided into four 64x64 residual blocks for residual encoding / decoding. In another example, a 128x32 lossless CU is divided into two 64x32 residual blocks. Residual coding / decoding scheme selection for lossless mode CU

[0068] In current VVC, different residual coding / decoding schemes are used by a CU depending on whether the CU is coding / decoding in transform skip mode. The current residual coding / decoding used in transform skip mode is generally more suitable for coding screen content.

[0069] According to one example of this disclosure, lossless CUs use the same residual encoding and decoding scheme used by transform skip mode CUs.

[0070] According to another example of this disclosure, lossless CUs use the same residual encoding and decoding scheme used by non-transform skip mode CUs.

[0071] According to another example of the present disclosure, a residual encoding / decoding scheme for a lossless CU is adaptively selected from existing residual encoding / decoding schemes based on certain conditions and / or predetermined procedures. Such conditions and / or predetermined procedures are followed by the encoder and decoder so that no signaling is required to indicate the selection in the bitstream. In one example, a simple screen content detection scheme can be specified and utilized in both the encoder and decoder. Based on this detection scheme, the current video block can be classified as screen content or normal content. If it is screen content, a residual encoding / decoding scheme to be used in transform skip mode is selected. Otherwise, another residual encoding / decoding scheme is selected.

[0072] According to another example of the present disclosure, a syntax is signaled in the bitstream to explicitly specify which residual encoding / decoding scheme is used by a lossless CU. Such a syntax is a binary flag, with each binary value indicating the selection of one of two residual encoding / decoding schemes. The syntax can be signaled at different levels. For example, it may be signaled in the sequence parameter set (SPS), picture parameter set (PPS), slice header, tile group header, or tile. It may also be signaled at the CTU or CU level. When such a syntax is signaled, all lossless CUs at the same or lower levels use the same residual encoding / decoding scheme indicated by this syntax. For example, if the syntax is signaled at the SPS level, all lossless CUs in the sequence use the indicated residual encoding / decoding scheme. If the syntax is signaled at the PPS level, all lossless CUs in the image use the residual encoding / decoding scheme indicated in the associated PPS. If there is a CU-level construct indicating whether a CU is encoded / decoded in lossless mode, such as cu_transquant_bypass_flag, the construct indicating the residual encoding / decoding scheme is conditionally signaled based on the lossless mode flag of this CU. For example, the construct indicating the residual encoding / decoding scheme is signaled for this CU only if the lossless mode flag cu_transquant_bypass_flag indicates that the current CU is encoded / decoded in lossless mode. If the construct is signaled by a slice header-level flag, all CUs in this slice that are encoded / decoded in lossless mode use the residual encoding / decoding scheme recognized based on the signaled flag. The residual encoding / decoding scheme for each of the multiple CUs is selected based on the first signaled flag, where the residual encoding / decoding scheme selected for the lossless CU by the signaled flag in the slice header is the residual encoding / decoding scheme used by the transform skip mode CU or the non-transform skip mode CU.

[0073] According to an example of the present disclosure, the transform skip mode flag is also signaled for a CU encoded and decoded in a lossless mode, and in this case, the selection of the residual encoding and decoding scheme for the CU is based on the transform skip mode flag, regardless of whether the CU is encoded and decoded in a lossless mode. Disable DMVR

[0074] In the current VVC, the on / off control of the DMVR is not defined for the lossless encoding / decoding mode. In one example of the present disclosure, it is proposed to control the turn-on / off of the DMVR at the slice level by a 1-bit signaling slice_disable_dmvr_flag flag. In one example, if the sps_dmvr_enabled_flag flag is set to 1 and the transquant_bypass_enabled_flag flag is set to 0, the slice_disable_dmvr_flag flag needs to be signaled. If the slice_disable_dmvr_flag flag is not signaled, it is inferred to be 1. If slice_disable_dmvr_flag is equal to 1, the DMVR is turned off. In this case, the signaling is as follows: [Table 2]

[0075] In another example, it is proposed to control the turn on / off of DMVR at the cu level by cu_transquant_bypass_flag. In one example, the cu level control for DMVR is as follows: DMVR applies to normal merge mode when all of the following conditions are met: - sps_dmvr_enabled_flag equals 1; - cu_transquant_bypass_flag is set to 0; - general_merge_flag[xCb][yCb] equals 1; - predFlagL0[0][0] and predFlagL1[0][0] are both equal to 1; - mmvd_merge_flag[xCb][yCb] equals 0; - DiffPicOrderCnt(currPic,RefPicList [0] [refIdxL0]) is the same as DiffPicOrderCnt(RefPicList [1] [refIdxL1],currPic); - BcwIdx[xCb][yCb] equals 0; - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both equal to 0; - cbWidth is greater than or equal to 8; - cbHeight is greater than or equal to 8; - cbHeight * cbWidth is 128 or greater. Disable BDOF

[0076] In the current VVC, the on / off control of BDOF is not defined for the lossless encoding / decoding mode. In one example of the present disclosure, it is proposed to control the turn-on / off of BDOF by a 1-bit signaling slice_disable_bdof_flag flag. In one example, if the sps_bdof_enabled_flag flag is set to 1 or the transquant_bypass_enabled_flag flag is set to 0, the slice_disable_bdof_flag flag needs to be signaled. If the slice_disable_bdof_flag flag is not signaled, it is presumed to be 1. If the slice_disable_bdof_flag flag is equal to 1, BDOF is turned off. In this case, the signaling is indicated as follows: [Table 3]

[0077] In another example of the present disclosure, it is proposed to control the turn on / off of BDOF at the cu level by cu_transquant_bypass_flag. In one example, the cu level control for BDOF is as follows: BDOF is applied to normal merge mode when all of the following conditions are met: - sps_bdof_enabled_flag equals 1; - cu_transquant_bypass_flag is set to 0; - predFlagL0 [xSbIdx] [ySbIdx] and predFlagL1 [xSbIdx] [ySbIdx] are both equal to 1; - DiffPicOrderCnt(currPic,RefPicList [0] [refIdxL0]) * DiffPicOrderCnt(currPic,RefPicList [1] [refIdxL1]) is less than 0; - MotionModelIdc[xCb][yCb] is equal to 0; - merge_subblock_flag[xCb][yCb] equals 0; - sym_mvd_flag[xCb][yCb] equals 0; - BcwIdx[xCb][yCb] equals 0; - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both 0; - cbHeight is greater than or equal to 8; - cIdx is equal to 0. Disable BDOF and DMVR

[0078] In current VVC, for a given merge candidate, if some bi-prediction and size constraint conditions are met, both BDOF and DMVR are always applied to decoder-side refinement to improve encoding / decoding efficiency, and are controlled by respective SPS flags. In one example of the present disclosure, it is proposed to disable both BDOF and DMVR by a 1-bit slice flag signaled by slice_disable_bdof_dmvr_flag. If the slice_disable_bdof_dmvr_flag flag is set to 1, both BDOF and DMVR are turned off. If the slice_disable_bdof_dmvr_flag flag is not signaled, it is inferred to be 1. In one example, slice_disable_bdof_dmvr_flag is signaled if the following condition is met: [Table 4]

[0079] The above methods may be implemented by an apparatus including one or more circuits, including an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processor (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components. These circuits may be used in combination with other hardware or software components to implement the above methods. Each module, sub-module, unit, or sub-unit disclosed above may be at least partially implemented using one or more circuits.

[0080] 7 is a block diagram illustrating an apparatus for video encoding and decoding according to an embodiment of the present disclosure. The apparatus 700 may be a terminal such as a mobile phone, a tablet computer, a digital broadcast terminal, a tablet device, or a personal digital assistant.

[0081] The device 700 may include one or more of a processing unit 702, a memory 704, a power supply unit 706, a multimedia unit 708, an audio unit 710, an input / output (I / O) interface 712, a sensor unit 714, and a communication unit 716, as shown in FIG.

[0082] The processing unit 702 typically controls the overall operation of the device 700, such as operations related to display, phone calls, data communications, camera operation, and recording operations. The processing unit 702 may include one or more processors 720 for executing instructions for implementing all or part of the steps of the methods described above. Furthermore, the processing unit 702 may include one or more modules that contribute to interaction between the processing unit 702 and other components. For example, the processing unit 702 may include a multimedia module for contributing to interaction between the multimedia unit 708 and the processing unit 702.

[0083] Memory 704 is configured to store different types of data to support the operation of device 700. Examples of such data include instructions for any applications or methods operating on device 700, contact data, phone book data, messages, images, videos, etc. Memory 704 may be implemented by any type of volatile or non-volatile storage device or combination thereof, and may be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or compact disk.

[0084] The power supply 706 provides power to the different components in the device 700. The power supply 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device 700.

[0085] The multimedia unit 708 includes a screen that provides an output interface between the device 700 and a user. In one example, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen that receives input signals from a user. The touch panel may include one or more touch sensors for sensing touches, slides, and gestures on the touch panel. The touch sensors can detect not only the boundaries of a touch or slide operation but also the duration and pressure associated with the touch or slide operation. In one example, the multimedia unit 708 may include a front camera and / or a rear camera. When the device 700 is in an operating mode, such as an imaging mode or a video mode, the front camera and / or the rear camera can receive external multimedia data.

[0086] The audio unit 710 is configured to output and / or input audio signals. For example, the audio unit 710 includes a microphone (MIC). The microphone is configured to receive external audio signals when the device 700 is in an operation mode such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 704 or may be transmitted via the communication unit 716. In an example, the audio unit 710 further includes a speaker for outputting audio signals.

[0087] The I / O interface 712 provides an interface between the processing unit 702 and a peripheral interface module, which may be a keyboard, a click wheel, buttons, etc. These buttons include, but are not limited to, a home button, volume buttons, a start button, and a lock button.

[0088] The sensor unit 714 includes one or more sensors for providing status assessments for the device 700 in different aspects. For example, the sensor unit 714 can detect the on / off state of the device 700 and the relative positions of components, such as the display and keypad of the device 700. The sensor unit 714 can also detect changes in the position of the device 700 or its components, the presence or absence of a user's touch on the device 700, the orientation or acceleration / deceleration of the device 700, and temperature changes of the device 700. The sensor unit 714 may include a proximity sensor configured to detect the presence of a nearby object without physical contact. The sensor unit 714 may further include an optical sensor, such as a CMOS or CCD image sensor used in imaging applications. In some examples, the sensor unit 714 may further include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0089] The communication unit 716 is configured to facilitate wired or wireless communication between the device 700 and other devices. The device 700 can access a wireless network based on a communication standard such as WiFi, 4G, or a combination thereof. In one example, the communication unit 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In one example, the communication unit 716 may further include a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0090] In one example, the apparatus 700 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processors (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements to perform the methods described above.

[0091] Non-transitory computer-readable storage media include, for example, hard disk drives (HDDs), solid-state drives (SSDs), flash memory, hybrid drives and solid-state hybrid drives (SSHDs), read-only memory (ROM), compact disk read-only memory (CD-ROM), magnetic tape, and floppy disks.

[0092] FIG. 8 is a flowchart illustrating an example process of a technique related to a lossless encoding / decoding mode in video encoding / decoding, according to an embodiment of the present disclosure.

[0093] In step 801, the processor 720 partitions the video image into a number of CUs, at least one of which is a lossless encoding / decoding unit (CU).

[0094] In step 802, the processor 720 determines the residual encoding / decoding block size of the lossless CU.

[0095] In step 803, in response to determining that the residual encoding / decoding block size of this lossless CU is greater than a predetermined maximum value, the processor 720 divides this residual encoding / decoding block into two or more residual blocks for residual encoding / decoding.

[0096] In one example, an apparatus for video encoding and decoding is provided, the apparatus including a processor 720 and a memory 704 configured to store instructions executable by the processor, where the processor, upon execution of the instructions, is configured to perform a method such as that shown in FIG.

[0097] In another example, a non-transitory computer-readable storage medium 704 is provided having instructions stored thereon that, when executed by a processor 720, cause the processor to perform a method such as that shown in FIG.

[0098] FIG. 9 is a flowchart illustrating an example process of a technique related to a lossless encoding / decoding mode in video encoding / decoding, according to an embodiment of the present disclosure.

[0099] In step 901, the processor 720 partitions the video image into a plurality of CUs, at least one of which is a lossless encoding / decoding unit (CU).

[0100] In step 902, processor 720 selects for this lossless CU the same residual encoding / decoding scheme used by the non-transform skip mode CU.

[0101] In one example, an apparatus for video encoding and decoding is provided, the apparatus including a processor 720 and a memory 704 configured to store instructions executable by the processor, where the processor, upon execution of the instructions, is configured to perform a method such as that shown in FIG.

[0102] In another example, a non-transitory computer-readable storage medium 704 is provided having instructions stored thereon that, when executed by a processor 720, cause the processor to perform a method such as that shown in FIG.

[0103] The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limiting of the present disclosure. Many modifications, variations, and alternative implementations will be apparent to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

[0104] The embodiments have been chosen and described to explain the principles of the disclosure and to enable those skilled in the art to understand the disclosure and make various implementations, and to best utilize the underlying principles and various implementations with various modifications to suit particular applications. Therefore, it should be understood that the scope of the disclosure is not limited to the specific examples of implementations disclosed, and that modifications and other implementations are also within the scope of the disclosure.

Claims

1. determining whether the current block is in a lossless mode based on a first indication derived from the bitstream; In response to determining that the current block is not in the lossless mode, determining that a first residual encoding / decoding scheme is applied to the current block, the first residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for non-transformed skip blocks; in response to determining that the current block is in the lossless mode, determining, based on a second indication derived from the bitstream, whether the first residual coding / decoding scheme or a second residual coding / decoding scheme, the second residual coding / decoding scheme being a predefined residual coding / decoding scheme for transform skip blocks, is to be applied to the current block in the lossless mode; 1. A method for video decoding, comprising:

2. receiving a one-bit flag for controlling turn-on and turn-off of decoder-side motion vector refinement (DMVR) at a slice level or a picture level for the current block; The method for video decoding of claim 1 further comprising:

3. receiving a one-bit flag for controlling turn-on and turn-off of decoder-side motion vector refinement (DMVR) at a CU level for the current block; The method for video decoding of claim 1 further comprising:

4. receiving a one-bit flag for controlling bidirectional optical flow (BDOF) turn-on and turn-off at a slice level or a picture level for the current block; The method for video decoding of claim 1 further comprising:

5. receiving a one-bit flag for controlling turning on and off bidirectional optical flow (BDOF) at a CU level for the current block; The method for video decoding of claim 1 further comprising:

6. receiving a one-bit flag for controlling turn-on and turn-off of both decoder-side motion vector refinement (DMVR) and bidirectional optical flow (BDOF) at a slice level or a picture level for the current block; The method for video decoding of claim 1 further comprising:

7. one or more processors; a memory configured to store instructions executable by the one or more processors; Equipped with The one or more processors, upon executing the instructions, determining whether the current block is in a lossless mode based on a first indication derived from the bitstream; In response to determining that the current block is not in the lossless mode, determining that a first residual encoding / decoding scheme is applied to the current block, the first residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for non-transformed skip blocks; in response to determining that the current block is in the lossless mode, determining, based on a second indication derived from the bitstream, whether the first residual encoding / decoding scheme or a second residual encoding / decoding scheme, the second residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for transform skip blocks, is to be applied to the current block in the lossless mode.

10. An apparatus for video decoding, configured to:

8. The one or more processors, upon executing the instructions, further receiving a one-bit flag for controlling the turn-on and turn-off of decoder-side motion vector refinement (DMVR) at a slice level or a picture level for the current block; 8. The apparatus for video decoding of claim 7, configured to:

9. The one or more processors further receiving a one-bit flag for controlling turn-on and turn-off of decoder-side motion vector refinement (DMVR) at a CU level for the current block; 8. The apparatus for video decoding of claim 7, configured to:

10. The one or more processors further receiving a one-bit flag for controlling bidirectional optical flow (BDOF) turn-on and turn-off at a slice level or a picture level for the current block; 8. The apparatus for video decoding of claim 7, configured to:

11. The one or more processors further receiving a one-bit flag for controlling bidirectional optical flow (BDOF) turn-on and turn-off at a CU level for the current block; 8. The apparatus for video decoding of claim 7, configured to:

12. The one or more processors, upon executing the instructions, further receiving a one-bit flag for controlling decoder-side motion vector refinement (DMVR) turn-on and turn-off and bidirectional optical flow (BDOF) at slice level or picture level for the current block; 8. The apparatus for video decoding of claim 7, configured to:

13. 1. A non-transitory computer-readable storage medium storing a plurality of programs for execution by a computing device having one or more processors, comprising: A non-transitory computer-readable storage medium, wherein the plurality of programs, when executed by the one or more processors, cause the computing device to perform the method for video decoding of any of claims 1 to 6.

14. A computer program storing instructions which, when executed by a processor, cause the processor to perform the method for video decoding according to any of claims 1 to 6.

Images