Semiconductor Devices

Abstract

This semiconductor device comprises: a semiconductor chip having a main surface; and a field insulation film having an insulation side wall that partially covers the main surface and has an inclination angle of 20°-40° formed between the main surface and the insulation side wall.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-160875 filed with the Japan Patent Office on September 25, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a thick oxide film, a thin oxide film, and a polysilicon layer. The thick oxide film is locally formed on the semiconductor substrate. The thin oxide film forms a high step with the thick oxide film on the semiconductor substrate. The sidewall angle of the thick oxide film is 70° to 80°. A polysilicon layer is formed on the thick oxide film and the thin oxide film. After the polysilicon layer formation process, residues called polysilicon sticks remain attached to the high step between the thick oxide film and the thin oxide film. The polysilicon sticks are completely removed by dry etching. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-112456 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device that can improve reliability. [Means for solving the problem]

[0005] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; and a field insulating film having insulating sidewalls that partially cover the main surface and form an inclination angle between the main surface and the field insulating film and the insulating sidewalls, the inclination angle being equal to or greater than 20° and equal to or less than 40°.

[0006] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; an isolation trench formed in the main surface; an isolation insulating film covering an inner wall of the isolation trench; and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure defining a device region on the main surface; a functional device formed on the main surface in the device region; and a field insulating film partially covering the main surface so as to expose the functional device in the device region, the field insulating film having insulating sidewalls that form an inclination angle between the main surface and the field insulating film and that is 20° or more and 40° or less. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is a plan view showing the structure of the semiconductor chip shown in FIG. [Figure 4] FIG. 4 is a block circuit diagram showing the electrical structure of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is an equivalent circuit diagram of the power transistor shown in FIG. [Figure 6] FIG. 6 is a further equivalent circuit diagram of the power transistor shown in FIG. [Figure 7] FIG. 7 is a block circuit diagram showing an example of the configuration of the semiconductor device shown in FIG. [Figure 8A] FIG. 8A is a circuit diagram for explaining an example of the operation of a power transistor. [Figure 8B] FIG. 8B is a circuit diagram for explaining an example of the operation of the power transistor. [Figure 8C] FIG. 8C is a circuit diagram for explaining an example of the operation of the power transistor. [Figure 9] FIG. 9 is an enlarged view of region IX shown in FIG. [Figure 10] FIG. 10 is an enlarged view of the region X shown in FIG. [Figure 11] FIG. 11 is an enlarged view showing a part of the region XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. [Figure 14A] FIG. 14A is an enlarged cross-sectional view of a main part of the structure shown in FIG. [Figure 14B] FIG. 14B is an enlarged cross-sectional view showing a main part of FIG. 14A. [Figure 15] FIG. 15 is a cross-sectional perspective view showing a main part of the first device region shown in FIG. [Figure 16A] FIG. 16A is a cross-sectional perspective view showing an example of control of a power transistor. [Figure 16B] FIG. 16B is a cross-sectional perspective view showing an example of control of a power transistor. [Figure 16C] FIG. 16C is a cross-sectional perspective view showing an example of control of a power transistor. [Figure 17] FIG. 17 is an enlarged view of area XVII shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19] FIG. 19 is an enlarged cross-sectional view of the main part of the structure shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is an enlarged cross-sectional view of a main part of the structure shown in FIG. [Figure 22A] FIG. 22A is a cross-sectional view corresponding to the region shown in FIG. 12 and illustrating an example of a method for manufacturing a semiconductor device. [Figure 22B] FIG. 22B is a cross-sectional view for explaining a step subsequent to FIG. 22A. [Figure 22C] FIG. 22C is a cross-sectional view for explaining a step subsequent to FIG. 22B. [Figure 22D] FIG. 22D is a cross-sectional view for explaining a step subsequent to FIG. 22C. [Figure 22E] FIG. 22E is a cross-sectional view for explaining a step subsequent to FIG. 22D. [Figure 22F] FIG. 22F is a cross-sectional view for explaining the step subsequent to FIG. 22E. [Figure 22G] FIG. 22G is a cross-sectional view for explaining the step subsequent to FIG. 22F. [Figure 22H] FIG. 22H is a cross-sectional view for explaining the step subsequent to FIG. 22G. [Figure 22I] FIG. 22I is a cross-sectional view for explaining the step subsequent to FIG. 22H. [Figure 22J] FIG. 22J is a cross-sectional view for explaining the step subsequent to FIG. 22I. [Figure 22K] FIG. 22K is a cross-sectional view for explaining the step subsequent to FIG. 22J. [Figure 22L] FIG. 22L is a cross-sectional view for explaining the step after FIG. 22K. [Figure 22M] FIG. 22M is a cross-sectional view for explaining the step subsequent to FIG. 22L. [Figure 22N] FIG. 22N is a cross-sectional view for explaining the step subsequent to FIG. 22M. [Figure 22O] FIG. 22O is a cross-sectional view for explaining the step subsequent to FIG. 22N. [Figure 22P] FIG. 22P is a cross-sectional view for explaining a step subsequent to FIG. 22O. [Figure 22Q] FIG. 22Q is a cross-sectional view for explaining the step subsequent to FIG. 22P. [Figure 22R] FIG. 22R is a cross-sectional view for explaining the step subsequent to FIG. 22Q. [Figure 22S] FIG. 22S is a cross-sectional view for explaining the step after FIG. 22R. [Figure 22T] FIG. 22T is a cross-sectional view for explaining the step subsequent to FIG. 22S. [Figure 22U] FIG. 22U is a cross-sectional view for explaining the step subsequent to FIG. 22T. [Figure 23A]FIG. 23A is a cross-sectional view corresponding to the region shown in FIG. 18 and illustrating an example of a method for manufacturing a semiconductor device. [Figure 23B] FIG. 23B is a cross-sectional view for explaining a step subsequent to FIG. 23A. [Figure 23C] FIG. 23C is a cross-sectional view for explaining a step subsequent to FIG. 23B. [Figure 23D] FIG. 23D is a cross-sectional view for explaining a step subsequent to FIG. 23C. [Figure 23E] FIG. 23E is a cross-sectional view for explaining the step subsequent to FIG. 23D. [Figure 23F] FIG. 23F is a cross-sectional view for explaining the step subsequent to FIG. 23E. [Figure 23G] FIG. 23G is a cross-sectional view for explaining the step subsequent to FIG. 23F. [Figure 23H] FIG. 23H is a cross-sectional view for explaining the step after FIG. 23G. [Figure 23I] FIG. 23I is a cross-sectional view for explaining the step after FIG. 23H. [Figure 23J] FIG. 23J is a cross-sectional view for explaining the step subsequent to FIG. 23I. [Figure 23K] FIG. 23K is a cross-sectional view for explaining the step subsequent to FIG. 23J. [Figure 23L] FIG. 23L is a cross-sectional view for explaining the step after FIG. 23K. [Figure 23M] FIG. 23M is a cross-sectional view for explaining the step after FIG. 23L. [Figure 23N] FIG. 23N is a cross-sectional view for explaining the step subsequent to FIG. 23M. [Figure 23O] FIG. 23O is a cross-sectional view for explaining the step subsequent to FIG. 23N. [Figure 23P] FIG. 23P is a cross-sectional view for explaining a step subsequent to FIG. 23O. [Figure 23Q] FIG. 23Q is a cross-sectional view for explaining the step subsequent to FIG. 23P. [Figure 23R] FIG. 23R is a cross-sectional view for explaining the step after FIG. 23Q. [Figure 23S] FIG. 23S is a cross-sectional view for explaining the step after FIG. 23R. [Figure 23T] FIG. 23T is a cross-sectional view for explaining the step after FIG. 23S. [Figure 23U] FIG. 23U is a cross-sectional view for explaining the step subsequent to FIG. 23T. [Figure 24] FIG. 24 corresponds to FIG. 12 and is a cross-sectional view showing a modified example of the first trench isolation structure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Fig. 1 is a plan view showing a semiconductor device 1 according to one embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing the structure of a semiconductor chip 2 shown in Fig. 1. Fig. 4 is a block circuit diagram showing the electrical structure of the semiconductor device 1 shown in Fig. 1. Fig. 5 is an equivalent circuit diagram of a power transistor 8 shown in Fig. 4. Fig. 6 is a further equivalent circuit diagram of the power transistor 8 shown in Fig. 5.

[0009] In the following, an example will be described in which the semiconductor device 1 is a high-side switching device, but the semiconductor device 1 can also be provided as a low-side switching device by adjusting the electrical connection forms and functions of various structures.

[0010] 1 and 2, in this embodiment, a semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape. Specifically, the semiconductor chip 2 is made of a Si (silicon) chip. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from a normal direction Z thereof (hereinafter simply referred to as a "plan view").

[0011] The first main surface 3 is a device surface on which functional devices are formed. The second main surface 4 is a mounting surface and may be a ground surface having grinding marks. The first to fourth side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0012] Referring to FIG. 3, the semiconductor device 1 includes a first device region 6 defined on the first main surface 3. The first device region 6 is an output region where an output signal output to the outside is generated. In this embodiment, the first device region 6 is defined in a region on the third side surface 5C side of the first main surface 3. The arrangement and planar shape of the first device region 6 are arbitrary and are not limited to a specific form. However, from the viewpoint of obtaining good output characteristics, it is preferable that the first device region 6 occupies an area of ​​at least half of the first main surface 3.

[0013] The semiconductor device 1 includes a second device region 7 defined on the first main surface 3 as a region different from the first device region 6. The second device region 7 is an input region to which an electrical signal is input from the outside. In this embodiment, the second device region 7 is defined as a region on the fourth side surface 5D side relative to the first device region 6. The arrangement and planar shape of the second device region 7 are arbitrary and are not limited to a specific form.

[0014] The second device region 7 preferably has a planar area equal to or smaller than the planar area of ​​the first device region 6. The second device region 7 is preferably formed with an area ratio of 0.1 to 1 relative to the first device region 6. The area ratio is the ratio of the planar area of ​​the second device region 7 to the planar area of ​​the first device region 6. The area ratio may be 0.1 to 0.25, 0.25 to 0.5, 0.5 to 0.75, or 0.75 to 1. The area ratio is preferably less than 1. Of course, the second device region 7 may have a planar area larger than the planar area of ​​the first device region 6.

[0015] 3 to 6, semiconductor device 1 includes n (n≧2) power transistors 8 as an example of insulated gate split transistors formed in first device region 6. Power transistor 8 may also be referred to as a power MISFET (Metal Insulator Semiconductor Field Effect Transistor). Power transistor 8 includes one main drain DM, one main source SM, and n (n≧2) main gates GM.

[0016] The n main gates GM are input with n gate signals G, which may be the same or different, at any timing. The gate signals G include an ON signal that controls the power transistor 8 to an ON state and an OFF signal that controls the power transistor 8 to an OFF state. In response to the n gate signals G input to the n main gates GM, the power transistor 8 outputs a single output current IOUT (output signal) from the main drain DM and main source SM. In other words, the power transistor 8 is a multi-input single-output switching device. The output current IOUT is specifically a drain-source current that flows between the main drain DM and the main source SM.

[0017] Referring to FIG. 5, the power transistor 8 specifically includes n (n≧2) system transistors 9 as individually controlled objects. More specifically, the power transistor 8 is configured by a parallel circuit of n system transistors 9 connected in parallel so that n gate signals G are individually input. In this embodiment, the n system transistors 9 are collectively formed in a single first device region 6. The n system transistors 9 are configured to be controlled to an on state and an off state electrically independent of each other. That is, the n power transistors 8 are configured so that the system transistors 9 in the on state and the system transistors 9 in the off state coexist at any timing.

[0018] Each of the n system transistors 9 includes a system drain DS, a system source SS, and a system gate GS. The system drain DS of each of the n system transistors 9 is connected to a main drain DM. The system source SS of each of the n system transistors 9 is connected to a main source SM. The system gate GS of each of the n system transistors 9 is connected to a main gate GM in a one-to-one correspondence.

[0019] That is, the main drain DM, main source SM and n main gates GM of the power transistor 8 are respectively formed by the system drain DS, system source SS and n system gates GS of the n system transistors 9. The n main gates GM are essentially made up of the n system gates GS.

[0020] The n system transistors 9 generate electrical signals for each system in response to a gate signal G and output them to the main drain DM and main source SM. Specifically, the electrical signals for each system are drain-source currents that flow between the system drain DS and system source SS of each system transistor 9. The electrical signals for each system are added between the main drain DM and main source SM. This generates a single output current IOUT.

[0021] It is preferable that the n system transistors 9 have gate threshold voltages that are approximately equal to each other. Hereinafter, the term "approximately equal" in this specification includes a case where a measurement value (here, the gate threshold voltage of one system transistor 9) is completely equal to a comparison value (here, the gate threshold voltage of another system transistor 9) as well as a case where the measurement value is within a range of 0.9 to 1.1 times the comparison value. The n system transistors 9 may have channel areas that are approximately equal to each other, or may have different channel areas. In other words, the n system transistors 9 may have on-resistance characteristics that are approximately equal to each other, or may have different on-resistance characteristics.

[0022] 6, each of the n system transistors 9 includes one or more unit transistors 10 that are grouped together as individual control targets. Specifically, each of the n system transistors 9 is configured as a parallel circuit of one or more unit transistors 10. A system transistor 9 that is made up of a single unit transistor 10 is also included in the "parallel circuit" referred to here.

[0023] Each system transistor 9 may include any number of unit transistors 10, but it is preferable that at least one of the n system transistors 9 includes a plurality of unit transistors 10. The n system transistors 9 may be composed of the same number of unit transistors 10, or may be composed of different numbers of unit transistors 10.

[0024] Each unit transistor 10 includes a unit drain DU, a unit source SU, and a unit gate GU. In each system transistor 9, the unit drain DU of one or more unit transistors 10 is electrically connected to the system drain DS. In each system transistor 9, the unit source SU of one or more unit transistors 10 is electrically connected to the system source SS. In each system transistor 9, the unit gate GU of one or more unit transistors 10 is electrically connected to the system gate GS.

[0025] That is, the system drain DS, system source SS and system gate GS of each system transistor 9 are respectively formed by the unit drain DU, unit source SU and unit gate GU of one or more unit transistors 10.

[0026] The unit transistors 10 may be trench gate or planar gate. The unit transistors 10 preferably have approximately the same gate threshold voltage. The unit transistors 10 may have approximately the same channel area, or different channel areas. That is, the unit transistors 10 may have approximately the same on-resistance characteristics, or different on-resistance characteristics.

[0027] By adjusting the number of unit transistors 10, the gate threshold voltage, the channel area, etc., it is possible to precisely adjust the gate threshold voltage and on-resistance characteristics (channel area) of each system transistor 9. The electrical characteristics of each system transistor 9 are adjusted according to the electrical specifications of the power transistor 8 to be achieved. Examples of the electrical specifications of the power transistor 8 include the channel utilization rate, on-resistance Ron, and switching waveform.

[0028] 3 and 4, the semiconductor device 1 includes a control integrated circuit (IC) 11 as an example of a control circuit formed in the second device region 7. The control IC 11 includes a plurality of types of functional circuits that realize various functions in response to electrical signals input from the outside. The plurality of types of functional circuits includes a gate control circuit 12 that drives and controls the power transistor 8 in response to the electrical signal from the outside. Specifically, the gate control circuit 12 is configured to generate n gate signals G that individually control n system transistors 9. The control IC 11, together with the power transistor 8, forms a so-called intelligent power device (IPD). The IPD is also called an intelligent power module (IPM).

[0029] Referring to FIG. 2, the semiconductor device 1 includes an interlayer insulating layer 13 covering the first main surface 3. The interlayer insulating layer 13 collectively covers the first device region 6 and the second device region 7. In this embodiment, the interlayer insulating layer 13 has a multilayer wiring structure in which multiple insulating layers and multiple wiring layers are alternately stacked. Each insulating layer includes at least one of an SiO2 film and an SiN film. Each wiring layer may include at least one of an Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0030] 3, the semiconductor device 1 includes n gate wirings 14 as an example of control wirings formed anywhere above the first main surface 3. The n gate wirings 14 are made up of n wiring layers formed in the interlayer insulating layer 13. The n gate wirings 14 are selectively routed within the interlayer insulating layer 13 and electrically connected to the n main gates GM of the power transistors 8 and the control IC 11 (gate control circuit 12), respectively.

[0031] Specifically, the n gate wirings 14 are electrically connected in one-to-one correspondence to the n main gates GM (n system gates GS) of the power transistors 8 while being electrically independent from one another. As a result, the n gate wirings 14 individually transmit the n gate signals G generated by the control IC 11 (gate control circuit 12) to the n main gates GM of the power transistors 8.

[0032] That is, the n gate wirings 14 are each electrically connected to the unit gate GU of one or more unit transistors 10 that are to be organized as individually controlled targets from a group of unit transistors 10. The n gate wirings 14 may include one or more gate wirings 14 electrically connected to one unit transistor 10 that is to be organized as an individually controlled target. The n gate wirings 14 may also include one or more gate wirings 14 that connect in parallel multiple unit transistors 10 that are to be organized as individually controlled targets.

[0033] The semiconductor device 1 includes a plurality of (six in this embodiment) terminal electrodes 15-20. In Fig. 1, the plurality of terminal electrodes 15-20 are indicated by hatching. The number, arrangement, and planar shape of the plurality of terminal electrodes 15-20 can be adjusted to any form depending on the specifications of the power transistor 8 and the specifications of the control IC 11, and are not limited to the form shown in Fig. 1. In this embodiment, the plurality of terminal electrodes 15-20 include a drain terminal 15 (power supply terminal VBB), a source terminal 16 (output terminal OUT), an input terminal 17, a reference terminal 18, an enable terminal 19, and a sense terminal 20.

[0034] The drain terminal 15 directly covers the second main surface 4 of the semiconductor chip 2 and is electrically connected to the second main surface 4. The drain terminal 15 is electrically connected to the main drain DM of the power transistor 8 and the control IC 11. The drain terminal 15 transmits the power supply voltage VB to the main drain DM of the power transistor 8 and various circuits of the control IC 11. The drain terminal 15 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain terminal 15 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner.

[0035] The source terminal 16, the input terminal 17, the reference terminal 18, the enable terminal 19, and the sense terminal 20 are formed on the interlayer insulating layer 13. The source terminal 16 is formed above the first device region 6 on the first main surface 3. The source terminal 16 is electrically connected to the main source SM of the power transistor 8 and the control IC 11. The source terminal 16 transmits the output current IOUT generated by the power transistor 8 to the outside.

[0036] The input terminal 17, the reference terminal 18, the enable terminal 19, and the sense terminal 20 are each formed on the first main surface 3 in an area outside the first device area 6 (specifically, above the second device area 7). The input terminal 17 transmits an input voltage that drives the control IC 11. The reference terminal 18 transmits a reference voltage (e.g., a ground voltage GND) to the power transistor 8 and the control IC 11. The enable terminal 19 transmits an electrical signal for enabling or disabling some or all of the functions of the control IC 11. The sense terminal 20 transmits an electrical signal for detecting an abnormality in the control IC 11.

[0037] The terminal electrodes 16 to 20, excluding the drain terminal 15, may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. A plating layer may be formed on the outer surface of each of the terminal electrodes 16 to 20. The plating layer may include at least one of a Ni layer, a Pd layer, and an Au layer.

[0038] Fig. 7 is a block circuit diagram showing an example of the configuration of the semiconductor device 1 shown in Fig. 1. The following describes an example in which the semiconductor device 1 is installed in a vehicle. The semiconductor device 1 includes a drain terminal 15, a source terminal 16, an input terminal 17, a reference terminal 18, an enable terminal 19, a sense terminal 20, a power transistor 8, and a control IC 11.

[0039] The drain terminal 15 is connected to a power supply. The power supply voltage VB may be 10 V or more and 20 V or less. The source terminal 16 is connected to an inductive load L. The inductive load L may be a coil, a solenoid, an inductance component of a harness, or the like. The input terminal 17 is externally connected to an MCU (Micro Controller Unit), a DC / DC converter, or an LDO (Low Drop Out). The input voltage may be 1 V or more and 10 V or less. The reference terminal 18 is grounded. The enable terminal 19 may be connected to the MCU. An electrical signal for enabling or disabling some or all of the functions of the control IC 11 is input to the enable terminal 19. The sense terminal 20 may be connected to a resistor.

[0040] The main drain DM of the power transistor 8 is electrically connected to a drain terminal 15. The main source SM of the power transistor 8 is electrically connected to a control IC 11 (a current detection circuit 26 described later) and a source terminal 16. The n main gates GM of the power transistor 8 are electrically connected to the control IC 11 (specifically, the gate control circuit 12) via n gate wirings 14. In FIG. 7, the n gate wirings 14 are simply shown by a single line.

[0041] The control IC 11 includes a gate control circuit 12, a sense transistor 21, an input circuit 22, a current / voltage control circuit 23, a protection circuit 24, an active clamp circuit 25, a current detection circuit 26, a power supply reverse connection protection circuit 27, and an abnormality detection circuit 28. The sense transistor 21 includes a drain, a source, and a gate. The gate of the sense transistor 21 is electrically connected to the gate control circuit 12. The drain of the sense transistor 21 is electrically connected to the drain terminal 15. The source of the sense transistor 21 is electrically connected to the current detection circuit 26.

[0042] The input circuit 22 is electrically connected to the input terminal 17 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input terminal 17. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0043] The current / voltage control circuit 23 is electrically connected to the protection circuit 24, the gate control circuit 12, the power supply reverse connection protection circuit 27, and the abnormality detection circuit 28. The current / voltage control circuit 23 may include a logic circuit. The current / voltage control circuit 23 generates various voltages and currents in response to electrical signals from the input circuit 22 and the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 29, a first constant voltage generation circuit 30, a second constant voltage generation circuit 31, and a reference voltage / current generation circuit 32.

[0044] The drive voltage generation circuit 29 generates a drive voltage for driving the gate control circuit 12. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 29 may generate a drive voltage between 5V and 15V, which is obtained by subtracting 5V from the power supply voltage VB. The drive voltage is input to the gate control circuit 12.

[0045] The first constant voltage generating circuit 30 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generating circuit 30 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The first constant voltage is input to the protection circuit 24 (specifically, the open load detection circuit 34, which will be described later, etc.).

[0046] The second constant voltage generating circuit 31 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generating circuit 31 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The second constant voltage is input to the protection circuit 24 (specifically, an overheat protection circuit 35 and an undervoltage lockout circuit 36, which will be described later).

[0047] The reference voltage / current generating circuit 32 generates a reference voltage and a reference current for the various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0048] The protection circuit 24 is electrically connected to the current / voltage control circuit 23, the gate control circuit 12, the abnormality detection circuit 28, the source of the power transistor 8, and the source of the sense transistor 21. The protection circuit 24 includes an overcurrent protection circuit 33, an open load detection circuit 34, an overheat protection circuit 35, and an undervoltage lockout circuit 36.

[0049] The overcurrent protection circuit 33 is electrically connected to the gate control circuit 12 and the source of the sense transistor 21. The overcurrent protection circuit 33 protects the power transistor 8 from overcurrent by detecting the output current flowing through the power transistor 8 and limiting it to a certain value or less. The overcurrent protection circuit 33 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 33 is input to the gate control circuit 12 (specifically, a drive signal output circuit described later).

[0050] The open load detection circuit 34 is electrically connected to the current / voltage control circuit 23 and the main source SM of the power transistor 8. The open load detection circuit 34 detects an open load state. A signal generated by the open load detection circuit 34 is input to the current / voltage control circuit 23.

[0051] The overheat protection circuit 35 is electrically connected to the current / voltage control circuit 23. The overheat protection circuit 35 monitors the temperature of the power transistor 8 and protects the power transistor 8 from excessive temperature rise. The overheat protection circuit 35 forcibly controls the power transistor 8 to an off state when the temperature of the power transistor 8 reaches a predetermined threshold or when the temperature difference between the power transistor 8 and other circuits reaches a predetermined threshold. The overheat protection circuit 35 may include a temperature-sensing device such as a temperature-sensing diode or a thermistor. A signal generated by the overheat protection circuit 35 is input to the current / voltage control circuit 23.

[0052] The low voltage malfunction suppression circuit 36 ​​is electrically connected to the current / voltage control circuit 23. The low voltage malfunction suppression circuit 36 ​​suppresses malfunction of the power transistor 8 when the power supply voltage VB is less than a predetermined value. A signal generated by the low voltage malfunction suppression circuit 36 ​​is input to the current / voltage control circuit 23.

[0053] The gate control circuit 12 is electrically connected to the current / voltage control circuit 23, the protection circuit 24, the n main gates GM of the power transistor 8, and the gate of the sense transistor 21. The gate control circuit 12 may include an oscillation circuit and a charge pump circuit. The gate control circuit 12 controls the on / off of the power transistor 8 in response to an electrical signal from the current / voltage control circuit 23 and an electrical signal from the protection circuit 24.

[0054] The gate control circuit 12 generates n gate signals G to be output to n gate wirings 14. The n gate signals G are input to the power transistor 8 via the n gate wirings 14. This controls the on / off of the power transistor 8. The gate control circuit 12 also controls the on / off of the sense transistor 21. The gate control circuit 12 generates gate signals to be output to the gate of the sense transistor 21 in response to an electrical signal from the current / voltage control circuit 23 and an electrical signal from the protection circuit 24. This controls the on / off of the sense transistor 21. It is preferable that the sense transistor 21 is controlled simultaneously with the power transistor 8.

[0055] The active clamp circuit 25 is electrically connected to the drain terminal 15, the main gate GM of the power transistor 8, and the gate of the sense transistor 21. The active clamp circuit 25 protects the power transistor 8 from back electromotive force. The active clamp circuit 25 may include a plurality of diodes. The active clamp circuit 25 may have a diode pair including a first diode string and a second diode string connected in reverse bias.

[0056] The first diode string includes one or more diodes connected in series in the forward direction. The second diode string includes one or more diodes connected in series in the forward direction and is connected in reverse bias to the first diode string. The one or more diodes constituting the first diode string may include at least one of a pn junction diode and a Zener diode. The one or more diodes constituting the second diode string may include at least one of a pn junction diode and a Zener diode.

[0057] The current detection circuit 26 is electrically connected to the protection circuit 24, the abnormality detection circuit 28, the source of the power transistor 8, and the source of the sense transistor 21. The current detection circuit 26 detects the current flowing through the power transistor 8 and the sense transistor 21, and generates a current detection signal. The current detection signal is input to the abnormality detection circuit 28.

[0058] The power supply reverse connection protection circuit 27 is electrically connected to the reference terminal 18 and the current / voltage control circuit 23. The power supply reverse connection protection circuit 27 protects the current / voltage control circuit 23, the power transistor 8, etc. from reverse voltage when the power supply is connected in reverse.

[0059] Abnormality detection circuit 28 is electrically connected to current / voltage control circuit 23, protection circuit 24, and current detection circuit 26. Abnormality detection circuit 28 monitors the voltage of protection circuit 24. If an abnormality (such as a voltage fluctuation) occurs in any of overcurrent protection circuit 33, open load detection circuit 34, overheat protection circuit 35, and low voltage malfunction suppression circuit 36, abnormality detection circuit 28 generates an abnormality detection signal corresponding to the voltage of protection circuit 24 and outputs it to the outside.

[0060] Specifically, the abnormality detection circuit 28 includes a first multiplexer circuit 37 and a second multiplexer circuit 38. The first multiplexer circuit 37 includes two input sections, one output section, and one selection input section. The protection circuit 24 and the current detection circuit 26 are connected to the input sections of the first multiplexer circuit 37. The second multiplexer circuit 38 is connected to the output section of the first multiplexer circuit 37. The current / voltage control circuit 23 is connected to the selection input section of the first multiplexer circuit 37.

[0061] The first multiplexer circuit 37 generates an abnormality detection signal in response to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 26. The abnormality detection signal generated by the first multiplexer circuit 37 is input to the second multiplexer circuit 38. The second multiplexer circuit 38 has two input sections and one output section. The input sections of the second multiplexer circuit 38 are connected to the output section of the first multiplexer circuit 37 and the enable terminal 19, respectively. The output section of the second multiplexer circuit 38 is connected to the sense terminal 20.

[0062] When an MCU is connected to the enable terminal 19 and a resistor is connected to the sense terminal 20, an ON signal is input from the MCU to the enable terminal 19 and an abnormality detection signal is extracted from the sense terminal 20. The abnormality detection signal is converted into a voltage signal by the resistor electrically connected to the sense terminal 20. An abnormal state of the semiconductor device 1 is detected based on this voltage signal.

[0063] 8A to 8C are circuit diagrams corresponding to FIG. 5, each illustrating an example of the operation of the power transistor 8. Referring to FIG. 8A, when a gate signal G (i.e., an ON signal) exceeding the gate threshold voltage is input to all of the n gate wirings 14, all of the system transistors 9 are turned on. In this case, the power transistor 8 is turned on with all current paths open. Therefore, the channel utilization rate of the power transistor 8 increases relatively, and the ON resistance Ron decreases relatively.

[0064] Referring to FIG. 8B, when a gate signal G (i.e., an on signal) exceeding the gate threshold voltage is input to x (1≦x<n) gate wirings 14 and a gate signal G (i.e., an off signal) less than the gate threshold voltage is input to (n−x) gate wirings 14, x system transistors 9 are turned on and (n−x) system transistors 9 are turned off. In this case, the power transistor 8 is turned on with some current paths closed. Therefore, the channel utilization rate of the power transistor 8 decreases relatively, and the on-resistance Ron increases relatively.

[0065] Referring to FIG. 8C, when a gate signal G (i.e., an off signal) less than the gate threshold voltage is input to all of the n gate wirings 14, all current paths are closed. As a result, all system transistors 9 are turned off and the power transistor 8 is turned off.

[0066] Next, referring to FIGS. 9 to 15, the specific structure of the first device region 6 (power transistor 8) will be described. FIG. 9 is an enlarged view of region IX shown in FIG. 3. FIG. 10 is an enlarged view of region X shown in FIG. 9. FIG. 11 is an enlarged view showing a partial omission of region XI shown in FIG. 9. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 10. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 10. FIG. 14A is an enlarged cross-sectional view of the main part of the structure shown in FIG. 12. FIG. 14B is an enlarged cross-sectional view showing the main part of FIG. 14A. FIG. 15 is a cross-sectional perspective view showing the main part of the first device region 6 shown in FIG. 9. In FIG. 14B, for convenience, the hatching is omitted. In FIG. 15, for convenience, the structure above the first main surface 3 is omitted and the gate wiring 14 and the like are simplified.

[0067] 9 to 15 (particularly FIGS. 12 and 13), the semiconductor device 1 includes an n-type (first conductivity type) first semiconductor region 41 formed in a surface layer portion of the second main surface 4 of the semiconductor chip 2. The first semiconductor region 41 forms a main drain DM of the power transistor 8. The first semiconductor region 41 may also be referred to as a drain region. The first semiconductor region 41 is formed over the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The n-type impurity concentration of the first semiconductor region 41 is 1×10 18 cm -3 More than 1×10 21 cm -3 The first semiconductor region 41 may be formed of a semiconductor substrate (Si substrate) in this embodiment.

[0068] The thickness of the first semiconductor region 41 may be 10 μm or more and 450 μm or less. The thickness of the first semiconductor region 41 may be 10 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 350 μm or less, or 350 μm or more and 450 μm or less. The thickness of the first semiconductor region 41 is preferably 50 μm or more and 150 μm or less.

[0069] The semiconductor device 1 includes an n-type second semiconductor region 42 formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. The second semiconductor region 42, together with the first semiconductor region 41, forms the main drain DM of the power transistor 8. The second semiconductor region 42 may also be referred to as a drift region or a drain-drift region. The second semiconductor region 42 is formed over the entire surface layer portion of the first main surface 3 so as to be electrically connected to the first semiconductor region 41, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0070] The second semiconductor region 42 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 41. The n-type impurity concentration of the second semiconductor region 42 is 1×10 15 cm -3 More than 1×10 18 cm -3The second semiconductor region 42 may be formed of an epitaxial layer (a Si epitaxial layer) in this embodiment.

[0071] The second semiconductor region 42 has a thickness less than the thickness of the first semiconductor region 41. The thickness of the second semiconductor region 42 may be 5 μm or more and 20 μm or less. The thickness of the second semiconductor region 42 may be 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less. The thickness of the second semiconductor region 42 is preferably 5 μm or more and 15 μm or less.

[0072] The semiconductor device 1 includes a first trench isolation structure 43 as an example of a region isolation structure that partitions the first device region 6 on the first main surface 3. The first trench isolation structure 43 may also be referred to as a deep trench isolation (DTI) structure or a shallow trench isolation (STI) structure.

[0073] The first trench isolation structure 43 is formed in a ring shape surrounding a partial region of the first main surface 3 in plan view, and defines a first device region 6 of a predetermined shape. In this embodiment, the first trench isolation structure 43 is formed in a quadrangular ring shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view, and defines the quadrangular first device region 6. The first trench isolation structure 43 may have any planar shape and may be formed in a polygonal ring shape. The first device region 6 may be defined in a polygonal shape according to the planar shape of the first trench isolation structure 43.

[0074] The first trench isolation structure 43 has an isolation width WI. The isolation width WI is the width in a direction perpendicular to the extension direction of the first trench isolation structure 43. The isolation width WI may be 0.5 μm or more and 2.5 μm or less. The isolation width WI may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, or 2 μm or more and 2.5 μm or less. The isolation width WI is preferably 1.2 μm or more and 2 μm or less.

[0075] The first trench isolation structure 43 has an isolation depth DI. The isolation depth DI may be 1 μm or more and 10 μm or less. The isolation depth DI may be 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. The isolation depth DI is preferably 2 μm or more and 6 μm or less.

[0076] The aspect ratio DI / WI of the first trench isolation structure 43 may be greater than 1 and not greater than 5. The aspect ratio DI / WI is the ratio of the isolation depth DI to the isolation width WI. The aspect ratio DI / WI is preferably 2 or greater. The bottom wall of the first trench isolation structure 43 is preferably formed with a gap of 1 μm or greater and 10 μm or less from the bottom of the second semiconductor region 42. It is particularly preferable that the bottom wall of the first trench isolation structure 43 is formed with a gap of 1 μm or greater and 5 μm or less from the bottom of the second semiconductor region 42.

[0077] The first trench isolation structure 43 has corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. In this embodiment, the four corners of the first trench isolation structure 43 are formed in an arc shape. In other words, the first device region 6 is defined in a quadrangle shape with four corners that each extend in an arc shape. The corners of the first trench isolation structure 43 preferably have a constant isolation width WI along the arc direction.

[0078] The first trench isolation structure 43 has a single electrode structure including an isolation trench 44, an isolation insulating film 45 (isolation insulator), and an isolation electrode 46. The isolation trench 44 is dug down from the first main surface 3 toward the second main surface 4. The isolation trench 44 is formed at an interval from the bottom of the second semiconductor region 42 toward the first main surface 3.

[0079] The isolation trench 44 includes a sidewall and a bottom wall. The angle that the sidewall of the isolation trench 44 forms with the first main surface 3 within the semiconductor chip 2 may be 90° or more and 92° or less. The isolation trench 44 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the isolation trench 44 are preferably formed in a curved shape. The entire bottom wall of the isolation trench 44 may be formed in a curved shape toward the second main surface 4.

[0080] The isolation insulating film 45 is formed on the wall surface of the isolation trench 44. Specifically, the isolation insulating film 45 is formed in the form of a film over the entire wall surface of the isolation trench 44, and defines a U-shaped recess space within the isolation trench 44. In this embodiment, the isolation insulating film 45 includes a silicon oxide film. Specifically, the isolation insulating film 45 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0081] The isolation insulating film 45 has an isolation thickness TI. The isolation thickness TI is the thickness of the isolation insulating film 45 along the normal direction to the wall surface of the isolation trench 44. The isolation thickness TI may be 0.1 μm or more and 1 μm or less. The isolation thickness TI may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, or 0.75 μm or more and 1 μm or less. The isolation thickness TI is preferably 0.15 μm or more and 0.65 μm or less.

[0082] Specifically, the isolation insulating film 45 includes a first portion 45a and a second portion 45b. The first portion 45a is a portion that covers the sidewall of the isolation trench 44. The second portion 45b is a portion that covers the bottom wall of the isolation trench 44. The first portion 45a has a first isolation thickness TI1. The first isolation thickness TI1 is the thickness of the first portion 45a along the normal direction to the sidewall of the isolation trench 44. The isolation thickness TI of the isolation insulating film 45 is defined by the first isolation thickness TI1.

[0083] The second part 45b has a second separation thickness TI2 (TI1 ≠ TI2) different from the first separation thickness TI1. The second separation thickness TI2 is the thickness of the second part 45b along the normal direction of the bottom wall of the separation trench 44. Preferably, the second separation thickness TI2 is less than the first separation thickness TI1 (TI2 < TI1). The second separation thickness TI2 may be 0.6 times or more and less than 1 time the first separation thickness TI1. Preferably, the second separation thickness TI2 is 0.7 times or more and 0.9 times or less the first separation thickness TI1.

[0084] The separation electrode 46 is embedded integrally with the separation trench 44 across the separation insulating film 45. In this form, the separation electrode 46 contains conductive polysilicon. A source voltage (for example, a ground voltage) as a reference voltage may be applied to the separation electrode 46.

[0085] The semiconductor device 1 includes a p-type (second conductivity type) body region 47 formed in the surface layer portion of the first main surface 3 in the first device region 6. The p-type impurity concentration of the body region 47 may be 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The body region 47 is formed over the entire surface layer portion of the first main surface 3 in the first device region 6 and is in contact with the first trench isolation structure 43. The body region 47 is formed in a region on the first main surface 3 side with respect to the bottom wall of the first trench isolation structure 43. Specifically, the body region 47 is formed in a region on the first main surface 3 side with respect to the middle portion of the first trench isolation structure 43.

[0086] The semiconductor device 1 includes a body space 48 formed along the inner peripheral wall of the first trench isolation structure 43 in the first device region 6. The body space 48 is part of the body region 47. The body space 48 is formed in an annular shape along the inner peripheral wall of the first trench isolation structure 43 in plan view and surrounds the inner side of the first device region 6.

[0087] The body space 48 has a space width WSP. The space width WSP may be greater than or equal to the separation width WI (WI ≦ WSP), or may be less than the separation width WI (WSP < WI). The body space 48 preferably has a constant space width WSP along the inner peripheral wall of the first trench isolation structure 43. The space width WSP may be 1 μm or more and 2.5 μm or less. The space width WSP may be 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, or 2 μm or more and 2.5 μm or less. The space width WSP is preferably 1.2 μm or more and 2 μm or less.

[0088] The semiconductor device 1 includes a power transistor 8 formed on the first main surface 3 in the first device region 6. The power transistor 8 is formed on the first main surface 3 at a distance of the space width WSP from the first trench isolation structure 43. Thereby, the power transistor 8 faces the first trench isolation structure 43 with the body space 48 interposed therebetween.

[0089] Specifically, the power transistor 8 includes a plurality of unit transistors 10 formed in a concentrated manner on the first main surface 3 of the first device region 6. In FIG. 9, an example in which 16 unit transistors 10 are formed is shown, but the number of unit transistors 10 is arbitrary. The plurality of unit transistors 10 are each formed in a strip shape (rectangular shape) extending in the first direction X in a plan view and are arranged in a line in the second direction Y. Thereby, the plurality of unit transistors 10 are formed in a stripe shape extending in the first direction X in a plan view.

[0090] Referring to FIGS. 10 and 11, specifically, the plurality of unit transistors 10 are each constituted by a unit cell 50. Each unit cell 50 includes one trench gate structure 51 and a channel cell 52 controlled by the trench gate structure 51. The channel cell 52 is a region where the opening and closing of the current path are controlled by the trench gate structure 51. In this form, the unit cell 50 includes a pair of channel cells 52 formed on both sides of one trench gate structure 51.

[0091] The cell width of the unit cell 50 may be 1 μm or more and 5 μm or less. The cell width is the width in the direction orthogonal to the direction in which the unit cell 50 extends (i.e., the second direction Y). The length of the unit cell 50 in the first direction X is arbitrary and is adjusted according to the length of the trench gate structure 51. Hereinafter, after explaining the structure of one unit transistor 10 (unit cell 50), the arrangement of a plurality of unit transistors 10 (unit cells 50) will be described.

[0092] The trench gate structure 51 is formed in a strip shape (rectangular shape) extending in the first direction X in a plan view. The trench gate structure 51 has a first end portion 51A on one side and a second end portion 51B on the other side with respect to the first direction X (longitudinal direction).

[0093] The trench gate structure 51 has a first width W1. The first width W1 is the width of the trench gate structure 51 in the short side direction (second direction Y). The first width W1 may be substantially equal to the separation width WI of the first trench isolation structure 43 (W1≒WI). The first width W1 is preferably less than the separation width WI (W1 < WI). The first width W1 is preferably less than the space width WSP (W1 < WSP). The first width W1 may be 0.5 μm or more and 2 μm or less. The first width W1 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0094] The trench gate structure 51 has a first depth D1. In this form, the first depth D1 is substantially equal to the separation depth DI of the first trench isolation structure 43 (D1≒DI). The first depth D1 is preferably less than the separation depth DI (D1 < DI). The first depth D1 may be 1 μm or more and 10 μm or less. The first depth D1 may be 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. The first depth D1 is preferably 2 μm or more and 6 μm or less.

[0095] The aspect ratio D1 / W1 of the trench gate structure 51 may be greater than 1 and less than or equal to 5. The aspect ratio D1 / W1 is the ratio of the first depth D1 to the first width W1. It is particularly preferable that the aspect ratio D1 / W1 be 2 or greater. It is preferable that the bottom wall of the trench gate structure 51 be spaced apart from the bottom of the second semiconductor region 42 by 1 μm or more and 10 μm or less. It is particularly preferable that the bottom wall of the trench gate structure 51 be spaced apart from the bottom of the second semiconductor region 42 by 1 μm or more and 5 μm or less.

[0096] The trench gate structure 51 has a multi-electrode structure including a gate trench 53, an upper insulating film 54, a lower insulating film 55, an upper electrode 56, a lower electrode 57, and an intermediate insulating film 58. The upper insulating film 54, the lower insulating film 55, and the intermediate insulating film 58 form a first insulator. As a result, the upper electrode 56 and the lower electrode 57 are buried in the gate trench 53 so as to be insulated and separated in the vertical direction by the first insulator.

[0097] The gate trench 53 is dug down from the first main surface 3 toward the second main surface 4. The gate trench 53 penetrates the body region 47 and is formed at an interval from the bottom of the second semiconductor region 42 toward the first main surface 3. The gate trench 53 includes a sidewall and a bottom wall. The angle formed by the sidewall of the gate trench 53 and the first main surface 3 within the semiconductor chip 2 may be equal to or greater than 90° and equal to or less than 92°.

[0098] The gate trench 53 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the gate trench 53 are preferably formed in a curved shape. The entire bottom wall of the gate trench 53 may be formed in a curved shape toward the second main surface 4.

[0099] The upper insulating film 54 covers the upper wall surface of the gate trench 53. Specifically, the upper insulating film 54 covers the upper wall surface located in a region on the opening side of the gate trench 53 relative to the bottom of the body region 47. A lower portion of the upper insulating film 54 crosses the boundary between the second semiconductor region 42 and the body region 47.

[0100] The upper insulating film 54 has a portion covering the body region 47 and a portion covering the second semiconductor region 42. The covering area of the upper insulating film 54 with respect to the body region 47 is larger than the covering area of the upper insulating film 54 with respect to the second semiconductor region 42. In this form, the upper insulating film 54 contains silicon oxide. Specifically, the upper insulating film 54 includes a silicon oxide film made of the oxide of the semiconductor chip 2. The upper insulating film 54 is formed as a gate insulating film.

[0101] The upper insulating film 54 has a first thickness T1 (T1 < TI) less than the separation thickness TI of the isolation insulating film 45. The first thickness T1 is the thickness of the upper insulating film 54 along the normal direction of the wall surface of the gate trench 53. The first thickness T1 may be 0.01 μm or more and 0.05 μm or less. The first thickness T1 may be 0.01 μm or more and 0.02 μm or less, 0.02 μm or more and 0.03 μm or less, 0.03 μm or more and 0.04 μm or less, or 0.04 μm or more and 0.05 μm or less. It is preferable that the first thickness T1 is 0.02 μm or more and 0.04 μm or less.

[0102] The lower insulating film 55 covers the lower wall surface of the gate trench 53. Specifically, the lower insulating film 55 covers the lower wall surface located in the region on the bottom wall side of the gate trench 53 with respect to the bottom of the body region 47. The lower insulating film 55 demarcates a U-shaped recess space in the region on the bottom wall side of the gate trench 53. The lower insulating film 55 is in contact with the second semiconductor region 42. In this form, the lower insulating film 55 contains silicon oxide. Specifically, the lower insulating film 55 includes a silicon oxide film made of the oxide of the semiconductor chip 2. The lower insulating film 55 is formed as a field insulating film.

[0103] The lower insulating film 55 has a second thickness T2 (T1 < T2) that exceeds the first thickness T1 of the upper insulating film 54. The second thickness T2 may be approximately equal to the separation thickness TI of the separation insulating film 45 (T2 ≒ TI). The second thickness T2 is the thickness of the lower insulating film 55 along the normal direction of the wall surface of the gate trench 53. The second thickness T2 may be 0.1 μm or more and 1 μm or less. The second thickness T2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, or 0.75 μm or more and 1 μm or less. The second thickness T2 is preferably 0.15 μm or more and 0.65 μm or less.

[0104] Specifically, the lower insulating film 55 includes a first portion 55a and a second portion 55b. The first portion 55a is a portion that covers the side wall of the gate trench 53. The second portion 55b is a portion that covers the bottom wall of the gate trench 53. The first portion 55a has a first lower thickness T21. The first lower thickness T21 is the thickness of the first portion 55a along the normal direction of the side wall of the gate trench 53. The second thickness T2 of the lower insulating film 55 is defined by the first lower thickness T21.

[0105] The second portion 45b has a second lower thickness T22 (T21 ≠ T22) that is different from the first lower thickness T21. The second lower thickness T22 is the thickness of the second portion 45b along the normal direction of the bottom wall of the gate trench 53. The second lower thickness T22 is preferably less than the first lower thickness T21 (T22 < T21). The second lower thickness T22 may be 0.6 times or more and less than 1 times the first lower thickness T21. The second lower thickness T22 is preferably 0.7 times or more and 0.9 times or less the first lower thickness T21. The second lower thickness T22 may be approximately equal to the second separation thickness TI2 of the separation insulating film 45 (T22 ≒ TI2).

[0106] The upper electrode 56 is embedded in the upper side (opening side) of the gate trench 53 with the upper insulating film 54 sandwiched therebetween. The upper electrode 56 is formed in a strip shape (rectangular shape) extending in the first direction X in a plan view. The upper electrode 56 faces the body region 47 and the second semiconductor region 42 with the upper insulating film 54 sandwiched therebetween. The facing area of ​​the upper electrode 56 with respect to the body region 47 is larger than the facing area of ​​the upper electrode 56 with respect to the second semiconductor region 42. In this embodiment, the upper electrode 56 includes conductive polysilicon. The upper electrode 56 is formed as a gate electrode. A gate signal G is applied to the upper electrode 56.

[0107] The lower electrode 57 is embedded in the lower side (bottom wall side) of the gate trench 53 with the lower insulating film 55 sandwiched therebetween. The lower electrode 57 faces the second semiconductor region 42 with the lower insulating film 55 sandwiched therebetween. The lower electrode 57 has an upper end portion that protrudes from the lower insulating film 55 toward the first main surface 3. The upper end portion of the lower electrode 57 extends toward the upper electrode 56 so as to engage with the bottom portion of the upper electrode 56. As a result, the upper end portion of the lower electrode 57 faces the upper insulating film 54 with the bottom portion of the upper electrode 56 sandwiched therebetween in the second direction Y.

[0108] In this embodiment, the lower electrode 57 includes conductive polysilicon. In this embodiment, the lower electrode 57 is formed as a gate electrode. Therefore, a gate signal G is applied to the lower electrode 57 simultaneously with the upper electrode 56. The upper electrode 56 and the lower electrode 57, which are arranged in a common gate trench 53, are controlled simultaneously. This makes it possible to suppress a voltage drop between the upper electrode 56 and the lower electrode 57, thereby suppressing electric field concentration between the upper electrode 56 and the lower electrode 57. Furthermore, the on-resistance Ron of the semiconductor chip 2 (particularly the second semiconductor region 42) can be reduced. This structure is particularly effective when the semiconductor device 1 is provided as an in-vehicle device.

[0109] The intermediate insulating film 58 is interposed between the upper electrode 56 and the lower electrode 57, electrically insulating the upper electrode 56 and the lower electrode 57. Specifically, the intermediate insulating film 58 covers the lower electrode 57 (upper end portion) exposed from the lower insulating film 55 in the region between the upper electrode 56 and the lower electrode 57. The intermediate insulating film 58 is continuous with the upper insulating film 54 and the lower insulating film 55. In this form, the intermediate insulating film 58 contains silicon oxide. Specifically, the intermediate insulating film 58 contains a silicon oxide film made of an oxide of the lower electrode 57.

[0110] The intermediate insulating film 58 has an intermediate thickness TM (TM < T2) less than the second thickness T2 of the lower insulating film 55 with respect to the normal direction Z. The intermediate thickness TM may be 0.01 μm or more and 0.05 μm or less. The intermediate thickness TM may be 0.01 μm or more and 0.02 μm or less, 0.02 μm or more and 0.03 μm or less, 0.03 μm or more and 0.04 μm or less, or 0.04 μm or more and 0.05 μm or less. Preferably, the intermediate thickness TM is 0.02 μm or more and 0.04 μm or less.

[0111] The pair of channel cells 52 are each formed in a strip shape extending in the first direction X on both sides of the trench gate structure 51. The pair of channel cells 52 each have a channel width WC. The channel width WC may be 0.1 μm or more and 1 μm or less.

[0112] The pair of channel cells 52 each include an n-type source region 60 formed in the surface layer portion of the body region 47. The number of source regions 60 included in the pair of channel cells 52 is arbitrary. In this form, the pair of channel cells 52 each include a plurality of source regions 60. One or more source regions 60 included in the unit cell 50 form the unit source SU (a part of the main source SM of the power transistor 8) of the unit transistor 10.

[0113] The n-type impurity concentration of the source region 60 exceeds the n-type impurity concentration of the second semiconductor region 42. The n-type impurity concentration of the source region 60 is 1×10 18 cm -3 or more 1×1021 cm -3 The plurality of source regions 60 are formed in each channel cell 52 at intervals in the first direction X. The bottoms of the plurality of source regions 60 are located in a region on the first main surface 3 side with respect to the bottom of the body region 47.

[0114] The pair of channel cells 52 each include a p-type contact region 61 formed in a region different from the source region 60 in the surface layer portion of the body region 47. The number of contact regions 61 included in the pair of channel cells 52 is arbitrary. In this embodiment, the pair of channel cells 52 each include a plurality of contact regions 61. The p-type impurity concentration of the contact region 61 exceeds the p-type impurity concentration of the body region 47. The p-type impurity concentration of the contact region 61 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0115] The plurality of contact regions 61 are formed at intervals in the first direction X in each channel cell 52. Specifically, the plurality of contact regions 61 are formed alternately with the plurality of source regions 60 in the first direction X so as to sandwich one source region 60 therebetween. The bottoms of the plurality of contact regions 61 are located in a region on the first main surface 3 side relative to the bottom of the body region 47.

[0116] The pair of channel cells 52 includes a plurality of channel regions 62 defined between a plurality of source regions 60 and the second semiconductor region 42 in the body region 47. The on / off of the plurality of channel regions 62 is simultaneously controlled by the trench gate structure 51. Therefore, the plurality of channel regions 62 form one channel of the unit transistor 10.

[0117] The multiple unit cells 50 are formed such that the multiple trench gate structures 51 are arranged in a row at a first interval I1 in the second direction Y. That is, the multiple trench gate structures 51 are each formed in a strip shape extending in the first direction X in the first device region 6 in a plan view, and are formed at the first interval I1 in the second direction Y. That is, the multiple unit cells 50 (multiple trench gate structures 51) are formed in a stripe shape extending in the first direction X in a plan view.

[0118] In the region between a pair of adjacent trench gate structures 51, plateau-shaped mesa portions 63 extending in the first direction X are defined. In other words, the trench gate structures 51 are alternately formed with the mesa portions 63 in the second direction Y, with one mesa portion 63 sandwiched between them.

[0119] In this embodiment, the plurality of unit cells 50 are each formed such that the channel cells 52 are integrated in a mesa portion 63 located between a pair of adjacent unit cells 50. In each mesa portion 63, a plurality of source regions 60 and a plurality of contact regions 61 are alternately formed in a surface layer portion of the body region 47 along the first direction X. In this embodiment, the plurality of unit cells 50 are each formed by a region between the centers of a pair of adjacent mesa portions 63.

[0120] Even in this structure, the on / off of the channel region 62 of each unit cell 50 is controlled for each unit cell 50. Looking at a pair of adjacent unit cells 50, when one unit cell 50 (trench gate structure 51) is controlled to be in the on state, the channel region 62 of that unit cell 50 is turned on, but the channel region 62 of the other unit cell 50 is not turned on. Therefore, unless there is an external electrical connection, the multiple unit cells 50 (trench gate structures 51) are electrically independent. This allows each unit cell 50 to function as a single unit transistor 10.

[0121] In the second direction Y, the trench gate structures 51 of the two unit cells 50 arranged on both sides are formed with a space width WSP in the first direction X from the first trench isolation structure 43. In this configuration, the two unit cells 50 arranged on both sides do not include a source region 60 in the channel cell 52 on the first trench isolation structure 43 side. With this structure, the main current path can be limited to the mesa portion 63, and at the same time, leakage current between the trench gate structure 51 and the first trench isolation structure 43 can be suppressed.

[0122] In this embodiment, the two unit cells 50 arranged on both sides include only a contact region 61 (hereinafter referred to as the "outermost contact region 61") in the channel cell 52 on the first trench isolation structure 43 side. The outermost contact region 61 is preferably formed at an interval from the first trench isolation structure 43 toward the trench gate structure 51. The outermost contact region 61 is connected to the sidewall of the corresponding trench gate structure 51. The outermost contact region 61 may be formed in a strip shape extending along the sidewall of the corresponding trench gate structure 51.

[0123] 10 and 11, in this embodiment, the first interval I1 corresponds to twice the channel width WC. The first interval I1 is preferably set to a value that allows the depletion layers extending from the trench gate structures 51 to unite below the bottom walls of the trench gate structures 51. The first interval I1 may be 0.25 times or more and 1.5 times or less the first width W1. The first interval I1 is preferably equal to or less than the first width W1 (I1≦W1). The first interval I1 is preferably less than the space width WSP (I1≦WSP).

[0124] The first interval I1 may be 0.5 μm or more and 2 μm or less. The first interval I1 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or more, or 1.5 μm or more and 2 μm or less. The first interval I1 is preferably 0.4 μm or more and 1.6 μm or less.

[0125] 9 to 11, the semiconductor device 1 includes a plurality of (32 in this embodiment) trench contact structures 71 formed on the first main surface 3 in the first device region 6. The plurality of trench contact structures 71 are also components of the power transistor 8. Specifically, the plurality of trench contact structures 71 include a plurality of (16 in this embodiment) first trench contact structures 71A and a plurality of (16 in this embodiment) second trench contact structures 71B.

[0126] The multiple first trench contact structures 71A are formed in regions between the first ends 51A of the multiple trench gate structures 51 and the first trench isolation structure 43. The multiple first trench contact structures 71A are connected to the first ends 51A of the multiple trench gate structures 51, respectively, and are formed in strip shapes (rectangular shapes) extending in the first direction X. The multiple first trench contact structures 71A are formed at intervals of the space width WSP from the first trench isolation structure 43 in the first direction X. The length of the multiple first trench contact structures 71A in the first direction X is arbitrary.

[0127] The second trench contact structures 71B are each formed in a region between the second ends 51B of the trench gate structures 51 and the first trench isolation structure 43. The second trench contact structures 71B are each connected to the second ends 51B of the trench gate structures 51, and are each formed in a strip shape (rectangular shape) extending in the first direction X. The second trench contact structures 71B are formed at intervals of the space width WSP from the first trench isolation structure 43 in the first direction X. The length of the second trench contact structures 71B in the first direction X is arbitrary.

[0128] Each of the trench contact structures 71 has a second width W2 and a second depth D2. The second width W2 is the width in a direction (second direction Y) perpendicular to the direction in which the trench contact structures 71 extend (first direction X). In this embodiment, the second width W2 is approximately equal to the first width W1 of the trench gate structure 51 (W2≒W1). In addition, the second depth D2 is approximately equal to the first depth D1 of the trench gate structure 51 (D2≒D1). Therefore, the aspect ratio D2 / W2 of the trench contact structures 71 is approximately equal to the aspect ratio D1 / W1 of the trench gate structure 51 (D2 / W2≒D1 / W1).

[0129] Specifically, each of the multiple trench contact structures 71 has a single electrode structure including a contact trench 72, a contact insulating film 73 (second insulator), and a contact electrode 74. The contact trench 72 is dug down from the first main surface 3 toward the second main surface 4 so as to communicate with the gate trench 53. The contact trench 72 is formed at an interval from the bottom of the second semiconductor region 42 toward the first main surface 3.

[0130] The contact trench 72 includes a sidewall and a bottom wall. The angle that the sidewall of the contact trench 72 forms with the first main surface 3 within the semiconductor chip 2 may be 90° or more and 92° or less. The contact trench 72 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the contact trench 72 are preferably formed in a curved shape. The entire bottom wall of the contact trench 72 may be formed in a curved shape toward the second main surface 4. The bottom wall of the contact trench 72 is smoothly connected to the bottom wall of the gate trench 53.

[0131] The contact insulating film 73 is formed on the wall surface of the contact trench 72. Specifically, the contact insulating film 73 is formed in a film shape over the entire wall surface of the contact trench 72, partitioning a U-shaped recess space within the contact trench 72. In this form, the contact insulating film 73 includes a silicon oxide film. Specifically, the contact insulating film 73 includes a silicon oxide film made of the oxide of the semiconductor chip 2.

[0132] The contact insulating film 73 has a third thickness T3 (T1 < T3) that exceeds the first thickness T1 of the upper insulating film 54. The third thickness T3 is the thickness of the contact insulating film 73 along the normal direction of the wall surface of the contact trench 72. The third thickness T3 may be approximately equal to the separation thickness TI of the separation insulating film 45 (T3 ≒ TI). The third thickness T3 may be approximately equal to the second thickness T2 of the lower insulating film 55 (T3 ≒ T2).

[0133] The third thickness T3 may be 0.1 μm or more and 1 μm or less. The third thickness T3 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, or 0.75 μm or more and 1 μm or less. The third thickness T3 is preferably 0.15 μm or more and 0.65 μm or less.

[0134] Specifically, the contact insulating film 73 includes a first portion 73a and a second portion 73b. The first portion 73a is the portion that covers the side wall of the contact trench 72. The second portion 73b is the portion that covers the bottom wall of the contact trench 72. The first portion 73a has a first contact thickness T31. The first contact thickness T31 is the thickness of the first portion 73a along the normal direction of the side wall of the contact trench 72. The third thickness T3 of the contact insulating film 73 is defined by the first contact thickness T31.

[0135] The second part 73b has a second contact thickness T32 different from the first contact thickness T31 (T31≠T32). The second contact thickness T32 is the thickness of the second part 73b along the normal direction of the bottom wall of the contact trench 72. Preferably, the second contact thickness T32 is less than the first contact thickness T31 (T32<T31). The second contact thickness T32 may be 0.6 times or more and less than 1 times the first contact thickness T31. Preferably, the second contact thickness T32 is 0.7 times or more and 0.9 times or less the first contact thickness T31. The second contact thickness T32 may be approximately equal to the second separation thickness TI2 of the separation insulating film 45 (T32≒TI2).

[0136] The contact electrode 74 is integrally embedded in the contact trench 72 with the contact insulating film 73 interposed therebetween. In this form, the contact electrode 74 contains conductive polysilicon. The contact electrode 74 is fixed at the same potential as the lower electrode 57 of the trench gate structure 51. That is, the contact electrode 74 is formed as a gate electrode, and a gate signal G is applied to the contact electrode 74.

[0137] Specifically, the contact electrode 74 is connected to the lower electrode 57 of the trench gate structure 51 at the communication portion of the contact trench 72 and the gate trench 53. Also, the contact electrode 74 is electrically insulated from the upper electrode 56 of the trench gate structure 51 with the intermediate insulating film 58 interposed therebetween. That is, the contact electrode 74 consists of a lead-out portion drawn from the gate trench 53 to the contact trench 72 at the lower electrode 57 with the contact insulating film 73 and the intermediate insulating film 58 interposed therebetween.

[0138] The trench contact structure 71 is controlled simultaneously with the connected trench gate structure 51 in terms of structure including the contact electrode 74 fixed at the same potential as the lower electrode 57. Therefore, the total number of trench gate structures 51 (unit cells 50) that can be systematized as the system transistor 9 (that is, the maximum number of systems of the power transistor 8) is determined by the trench contact structure 71.

[0139] In this embodiment, one trench contact structure 71 is connected to each end (first end 51A and second end 51B) of each trench gate structure 51. Therefore, each trench gate structure 51 is controlled simultaneously with the two trench contact structures 71 at both ends. In other words, in this embodiment, 16 trench gate structures 51 are configured to be electrically and independently controlled.

[0140] Therefore, in this embodiment, the total number of unit transistors 10 that can be organized as system transistors 9 is "16," and the maximum number of systems for power transistors 8 is "16." By adjusting the number of gate wirings 14 connected to the multiple trench gate structures 51, up to 16 gate signals G can be individually input to the 16 trench gate structures 51 in a one-to-one correspondence. By increasing the number of systems, the number of combination patterns of gate signals G input to the n system transistors 9 can be increased.

[0141] 12 to 14B, semiconductor device 1 includes a first field insulating film 80 that partially covers first main surface 3 in first device region 6. In this embodiment, first field insulating film 80 includes a silicon oxide film. Specifically, first field insulating film 80 includes a silicon oxide film made of an oxide of semiconductor chip 2.

[0142] The first field insulating film 80 is formed at a distance from the power transistor 8 (the plurality of trench gate structures 51 and the plurality of trench contact structures 71) toward the first trench isolation structure 43 in a plan view, and covers the periphery of the first trench isolation structure 43. The first field insulating film 80 covers the body region 47 (body space 48). In other words, the first field insulating film 80 faces the second semiconductor region 42 (first semiconductor region 41) at the periphery of the first device region 6, with the body region 47 (body space 48) in between.

[0143] In plan view, the first field insulating film 80 extends in a band shape along the inner wall surface of the first trench isolation structure 43. In this embodiment, the first field insulating film 80 is formed in a ring shape extending along the inner peripheral wall of the first trench isolation structure 43 in plan view, and surrounds the entire inner portion of the first device region 6. In other words, the first field insulating film 80 has a side extending in one direction (first direction X) in plan view and a side extending in an intersecting direction (second direction Y) that intersects the one direction.

[0144] The first field insulating film 80 is continuous with the isolation insulating film 45 exposed from the inner circumferential wall of the first trench isolation structure 43. In other words, the first device region 6 is defined by the first trench isolation structure 43 within the semiconductor chip 2, and is defined by the first field insulating film 80 on the semiconductor chip 2.

[0145] The first field insulating film 80 has a first insulating sidewall 80a that defines the inner portion of the first device region 6. The first insulating sidewall 80a is formed around the entire inner periphery of the first field insulating film 80. In other words, the first insulating sidewall 80a is formed on a side of the first field insulating film 80 that extends in one direction (first direction X) and on a side that extends in an intersecting direction (second direction Y) that intersects with the one direction.

[0146] The first insulating sidewall 80a is located on the body region 47 (body space 48). The first insulating sidewall 80a slopes obliquely downward at an acute angle with respect to the first main surface 3. Specifically, the first insulating sidewall 80a has an upper end located on the main surface side of the first field insulating film 80 and a lower end located on the first main surface 3 side, and slopes obliquely downward from the upper end to the lower end.

[0147] The first insulating side wall 80a forms a first inclination angle θ1 (20° ≤ θ1 ≤ 40°) of 20° or more and 40° or less with the first main surface 3. The first inclination angle θ1 is the angle (absolute value) formed by the straight line connecting the upper end portion and the lower end portion of the first insulating side wall 80a with respect to the first main surface 3 inside the first field insulating film 80 when the straight line is set. The first inclination angle θ1 is preferably less than 40° (θ1 < 40°).

[0148] The first inclination angle θ1 particularly preferably falls within the range of 30° ± 6° (24° ≤ θ1 ≤ 36°). Typically, the first inclination angle θ1 falls within the range of 28° or more and 36° or less (28° ≤ θ1 ≤ 36°). The first insulating side wall 80a may be inclined in a curved shape that is recessed toward the first main surface 3 in the region between the upper end portion and the lower end portion. Also in this case, the first inclination angle θ1 is the angle (absolute value) formed by the straight line connecting the upper end portion and the lower end portion of the first insulating side wall 80a with respect to the first main surface 3 when the straight line is set in a cross-sectional view.

[0149] The first field insulating film 80 has a first field thickness TF1. The first field thickness TF1 is the thickness along the normal direction Z of the portion of the first field insulating film 80 other than the portion forming the first insulating side wall 80a. The first field thickness TF1 may be substantially equal to the first separation thickness TI1 (= separation thickness TI) of the separation insulating film 45 (TF1 ≈ TI1). Preferably, the first field thickness TF1 exceeds the second separation thickness TI2 of the separation insulating film 45 (TI2 < TF1).

[0150] The first field thickness TF1 is preferably equal to or greater than the first thickness T1 of the upper insulating film 54 (T1 ≤ TF1). Particularly preferably, the first field thickness TF1 exceeds the first thickness T1 (T1 < TF1). The first field thickness TF1 may be substantially equal to the first lower thickness T21 (= second thickness T2) of the lower insulating film 55 (TF1 ≈ T21). Preferably, the first field thickness TF1 exceeds the second lower thickness T22 of the lower insulating film 55 (T22 < TF1).

[0151] The first field thickness TF1 preferably exceeds the intermediate thickness TM (TM < TF1). The first field thickness TF1 may be approximately equal to the first contact thickness T31 (= the third thickness T3) of the contact insulating film 73 (TF1 ≒ T31). The first field thickness TF1 preferably exceeds the second contact thickness T32 of the contact insulating film 73 (T32 < TF1).

[0152] The first field thickness TF1 may be 0.1 μm or more and 1 μm or less. The first field thickness TF1 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, or 0.75 μm or more and 1 μm or less. The first field thickness TF1 is preferably 0.15 μm or more and 0.65 μm or less.

[0153] Referring to FIGS. 12 to 14B (particularly FIGS. 14A and 14B), the semiconductor device 1 includes a first hidden surface 81 and a first exposed surface 82 formed on the first main surface 3 in the first device region 6. The first hidden surface 81 is formed in a portion covered by the first field insulating film 80 on the first main surface 3.

[0154] The first exposed surface 82 is formed in a portion exposed from the first field insulating film 80 on the first main surface 3. In other words, the first main surface 3 includes the first hidden surface 81 and the first exposed surface 82 partitioned by the first field insulating film 80 in the first device region 6, and the power transistor 8 (a plurality of unit cells 50) is formed on the first exposed surface 82.

[0155] In this embodiment, the first exposed surface 82 is recessed in the thickness direction of the semiconductor chip 2 (toward the second main surface 4) with respect to the first hidden surface 81. Specifically, the first exposed surface 82 is recessed by one step with respect to the first insulating sidewall 80a of the first field insulating film 80 in the thickness direction of the semiconductor chip 2 with respect to the first hidden surface 81. The first exposed surface 82 is formed at a depth position between the bottom of the body region 47 and the first hidden surface 81 with respect to the normal direction Z. The first exposed surface 82 is preferably recessed in the normal direction Z with respect to the first hidden surface 81 by more than 0 μm and not more than 0.5 μm (preferably not more than 0.2 μm).

[0156] 12 to 14B (particularly FIGS. 14A and 14B), the semiconductor device 1 includes a first main surface insulating film 83 that selectively covers the first main surface 3 in the first device region 6. In this embodiment, the first main surface insulating film 83 includes a silicon oxide film. Specifically, the first main surface insulating film 83 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The first main surface insulating film 83 covers the region of the first main surface 3 other than the gate trench 53, the contact trench 72, and the first field insulating film 80.

[0157] The first main surface insulating film 83 covers the first exposed surface 82 and is continuous with the upper insulating film 54, the contact insulating film 73, and the first insulating sidewall 80a of the first field insulating film 80. The first main surface insulating film 83 is formed at a distance from the middle portion of the first field insulating film 80 in the thickness direction toward the semiconductor chip 2 (the side toward the first exposed surface 82). Specifically, when a line is set that passes through the middle portion of the first field insulating film 80 in the thickness direction along the first exposed surface 82 (first main surface 3) in a cross-sectional view, the first main surface insulating film 83 is formed at a distance from the line toward the semiconductor chip 2.

[0158] The first main surface insulating film 83 includes a first region 83a and a second region 83b. The first region 83a is located on the side of the semiconductor chip 2 with respect to the first hidden surface 81. The second region 83b is located on the side opposite to the semiconductor chip 2 (the main surface side of the first field insulating film 80) with respect to the first hidden surface 81. Specifically, the first region 83a is located on the side of the semiconductor chip 2 with respect to an extension line that extends parallel to the first hidden surface 81 from above the first hidden surface 81 in a cross-sectional view. The second region 83b is located on the side opposite to the first region 83a (that is, the side opposite to the semiconductor chip 2) across the extension line.

[0159] The first main surface insulating film 83 has a first insulation thickness TMI1 (TMI1 < TF1) that is less than the first field thickness TF1 of the first field insulating film 80. It is preferable that the first insulation thickness TMI1 is not more than one-fifth of the first field thickness TF1 (TMI1 ≤ 1 / 5 × TF1). The first insulation thickness TMI1 may be approximately equal to the first thickness T1 of the upper insulating film 54 (TMI1 ≈ T1).

[0160] The first insulation thickness TMI1 may be 0.01 μm or more and 0.05 μm or less. The first insulation thickness TMI1 may be 0.01 μm or more and 0.02 μm or less, 0.02 μm or more and 0.03 μm or less, 0.03 μm or more and 0.04 μm or less, or 0.04 μm or more and 0.05 μm or less. It is preferable that the first insulation thickness TMI1 is 0.02 μm or more and 0.04 μm or less.

[0161] The semiconductor device 1 includes an outer field insulating film 84 that covers the region outside the first device region 6. The outer field insulating film 84 covers the periphery of the first trench isolation structure 43 in the region outside the first device region 6. In the region outside the first device region 6, the outer field insulating film 84 surrounds the first trench isolation structure 43 in a plan view and is continuous with the isolation insulating film 45 exposed from the outer peripheral wall of the first trench isolation structure 43. The outer field insulating film 84 has the same first field thickness TF1 as the first field insulating film 80.

[0162] The semiconductor device 1 includes the aforementioned interlayer insulating layer 13 covering the first main surface 3. The interlayer insulating layer 13 covers the first trench isolation structure 43, the plurality of trench gate structures 51, the first field insulating film 80, and the first main surface insulating film 83 in the first device region 6. The interlayer insulating layer 13 extends from above the first main surface insulating film 83, passing through the first insulating sidewall 80a, and covering the first field insulating film 80. In the first device region 6, the interlayer insulating layer 13 covers the first insulating sidewall 80a over the entire periphery of the first insulating sidewall 80a.

[0163] The semiconductor device 1 includes a plurality of plug electrodes 91-95 embedded in an interlayer insulating layer 13. The plurality of plug electrodes 91-95 includes a plurality of first plug electrodes 91, a plurality of second plug electrodes 92, a plurality of third plug electrodes 93, a plurality of fourth plug electrodes 94, and a plurality of fifth plug electrodes 95. Each of the plurality of plug electrodes 91-95 may be a tungsten plug electrode having a laminated structure including a titanium-based metal film and a tungsten film. In FIGS. 9-11, the plurality of plug electrodes 91-95 are indicated by X marks. In FIG. 15, the first plug electrode 91 and the fifth plug electrode 95 are simply indicated by lines.

[0164] The plurality of first plug electrodes 91 are each formed as a source plug electrode for the isolation electrode 46. The plurality of first plug electrodes 91 are each embedded in a portion of the interlayer insulating layer 13 that covers the first trench isolation structure 43. The plurality of first plug electrodes 91 are embedded at intervals along the isolation electrode 46 and are each electrically connected to the isolation electrode 46. The arrangement and shape of the plurality of first plug electrodes 91 are arbitrary. One or more first plug electrodes 91 extending in a strip shape or annular shape in a plan view may be formed on the isolation electrode 46.

[0165] The multiple second plug electrodes 92 are each formed as a gate plug electrode for the upper electrode 56. The multiple second plug electrodes 92 are embedded in portions of the interlayer insulating layer 13 that cover the multiple trench gate structures 51. The multiple second plug electrodes 92 are embedded at intervals along each upper electrode 56 and are electrically connected to each upper electrode 56. In this embodiment, the multiple second plug electrodes 92 are electrically connected to both end portions of each upper electrode 56. The multiple second plug electrodes 92 may be arranged and shaped arbitrarily. One or more second plug electrodes 92 extending in a strip shape along the upper electrode 56 in a plan view may be formed on each upper electrode 56.

[0166] The plurality of third plug electrodes 93 are each formed as a source plug electrode for the source region 60 (contact region 61). The plurality of third plug electrodes 93 are respectively embedded in portions of the interlayer insulating layer 13 that cover the plurality of mesa portions 63. The plurality of third plug electrodes 93 are respectively embedded in strip shapes that extend along the plurality of mesa portions 63 in a plan view. Each third plug electrode 93 is electrically connected to the plurality of source regions 60 and the plurality of contact regions 61 in each mesa portion 63. The arrangement and shape of the plurality of third plug electrodes 93 are arbitrary. The plurality of third plug electrodes 93 may be formed on each mesa portion 63.

[0167] The plurality of fourth plug electrodes 94 are each formed as a source plug electrode for the outermost contact region 61. The plurality of fourth plug electrodes 94 are embedded in portions of the interlayer insulating layer 13 that cover the plurality of outermost contact regions 61. The plurality of fourth plug electrodes 94 are embedded at intervals along each of the outermost contact regions 61 and are electrically connected to each of the outermost contact regions 61. The arrangement and shape of the plurality of fourth plug electrodes 94 are arbitrary. One or more fourth plug electrodes 94 extending in a strip shape along the outermost contact region 61 in a plan view may be formed on each of the outermost contact regions 61.

[0168] The plurality of fifth plug electrodes 95 each comprise a gate plug electrode for the contact electrode 74. The plurality of fifth plug electrodes 95 are embedded in portions of the interlayer insulating layer 13 that cover the plurality of contact electrodes 74. Each fifth plug electrode 95 is electrically connected to a corresponding contact electrode 74. The arrangement and shape of the plurality of fifth plug electrodes 95 are arbitrary. One or more fifth plug electrodes 95 extending in a strip shape along the contact electrode 74 in a plan view may be formed on each contact electrode 74.

[0169] The semiconductor device 1 includes one or more source wirings 96 formed in the interlayer insulating layer 13. The one or more source wirings 96 are made of a wiring layer formed in the interlayer insulating layer 13. The one or more source wirings 96 are selectively routed within the interlayer insulating layer 13 and electrically connected to the isolation electrode 46, the source region 60, and the contact region 61 via a plurality of first plug electrodes 91, a plurality of third plug electrodes 93, and a plurality of fourth plug electrodes 94. The one or more source wirings 96 are electrically connected to the source terminal 16 described above.

[0170] The semiconductor device 1 includes the aforementioned n gate wirings 14 formed in the interlayer insulating layer 13. In this embodiment, the n gate wirings 14 are routed from the second device region 7 to the first device region 6 across the first trench isolation structure 43 and the first field insulating film 80 in a plan view.

[0171] The n gate wirings 14 are electrically connected to the control IC 11 (gate control circuit 12) in the second device region 7. The n gate wirings 14 are electrically connected to a plurality of second plug electrodes 92 and a plurality of fifth plug electrodes 95 in the first device region 6. That is, the n gate wirings 14 are electrically connected to the upper electrode 56, the lower electrode 57, and the contact electrode 74 in the first device region 6, respectively.

[0172] Specifically, the n gate wirings 14 are each electrically connected to one or more trench gate structures 51 (unit transistors 10) to be organized as individually controlled targets. The n gate wirings 14 may include one or more gate wirings 14 electrically connected to one trench gate structure 51 to be organized as individually controlled targets. The n gate wirings 14 may also include one or more gate wirings 14 that connect in parallel multiple trench gate structures 51 to be organized as individually controlled targets.

[0173] The n gate wirings 14 are electrically connected to the upper electrodes 56 and lower electrodes 57 of the trench gate structures 51, respectively. That is, the n gate wirings 14 are electrically connected to one or more trench gate structures 51 and one or more trench contact structures 71 connected to the one or more trench gate structures 51, respectively. One system transistor 9 is configured by a parallel circuit of one or more trench gate structures 51 (unit transistors 10) electrically connected to one gate wiring 14.

[0174] Each of the multiple unit transistors 10 (unit cells 50) has a predetermined channel ratio RC. When the planar area of ​​the pair of channel cells 52 in each unit transistor 10 is taken as 100%, the channel ratio RC is defined as the ratio of the channel area of ​​the channel region 62 to the planar area. The channel area is defined as the sum of the planar areas of one or more source regions 60 in each unit transistor 10.

[0175] In this embodiment, each of the unit transistors 10 has a channel ratio RC of 50%. Therefore, the total channel ratio RT of the unit transistors 10 is 50%. The total channel ratio RT is defined as the ratio of the total channel area of ​​all the channel regions 62 to the total planar area of ​​the channel cells 52, where the total planar area of ​​the channel cells 52 is 100%.

[0176] In the n-system power transistors 8, the total channel ratio RT is divided into n system channel ratios RS, each of which may have the same or different values, by the n system transistors 9. In other words, the sum of the n system channel ratios RS is the total channel ratio RT.

[0177] The channel ratio RC of each unit transistor 10 can be adjusted within a range of 0% to 100%. When the channel ratio RC is 0%, no source region 60 is formed in the pair of channel cells 52. In this case, either or both of the body region 47 and the contact region 61 are formed in the pair of channel cells 52. When the channel ratio RC is 100%, only the source region 60 is formed in the pair of channel cells 52, and neither the contact region 61 nor the body region 47 is formed. In consideration of the electrical characteristics of the unit transistor 10, it is preferable that the channel ratio RC be adjusted within a range of more than 0% and less than 100%.

[0178] The channel ratio RC may be adjusted for each unit transistor 10. That is, the multiple unit transistors 10 may have different channel ratios RC, or may have approximately equal channel ratios RC. In this case, the n system transistors 9 may include one or more unit transistors 10 that are systemized as individually controlled targets from a collection of multiple unit transistors 10, each having the same or different channel ratios RC. The n system transistors 9 may also have the same or different system channel ratios RS.

[0179] The channel ratio RC is related to the temperature rise in the first device region 6 (semiconductor chip 2). For example, increasing the channel ratio RC makes it easier for the temperature to rise in the first device region 6. On the other hand, decreasing the channel ratio RC makes it harder for the temperature to rise in the first device region 6. Therefore, the channel ratio RC may be adjusted for each unit transistor 10 based on the temperature distribution in the first device region 6.

[0180] One or more unit transistors 10 having a relatively small channel ratio R may be arranged in a region where the temperature is likely to rise, and one or more unit transistors 10 having a relatively large channel ratio R may be arranged in a region where the temperature is unlikely to rise. The central portion of the first device region 6 is an example of the region where the temperature is likely to rise. The peripheral portion of the first device region 6 is an example of the region where the temperature is unlikely to rise.

[0181] One or more unit transistors 10 having a relatively low first channel ratio RC may be arranged in an area where the temperature is likely to rise (e.g., the central portion). For example, the first channel ratio RC may be 20% or more and 40% or less (e.g., 25%). One or more unit transistors 10 having a second channel ratio RC that exceeds the first channel ratio RC may be arranged in an area where the temperature is unlikely to rise (e.g., the periphery). For example, the second channel ratio RC may be 60% or more and 80% or less (e.g., 75%).

[0182] One or more unit transistors 10 having a third channel ratio RC greater than the first channel ratio RC and less than the second channel ratio RC may be arranged between the region where the temperature is likely to rise and the region where the temperature is unlikely to rise. The third channel ratio RC may be greater than 40% and less than 60% (e.g., 50%). The total channel ratio RT of the first to third channel ratios RC may be adjusted to 50%. In other words, the total channel ratio RT may be adjusted while adjusting the channel ratio RC for each unit transistor 10 based on the temperature distribution in the first device region 6.

[0183] Also, unit transistors 10 having a first channel ratio RC, unit transistors 10 having a second channel ratio RC, and unit transistors 10 having a third channel ratio RC may be repeatedly arranged in a regular order. The plurality of types of unit transistors 10 may be repeatedly arranged in this order in the second direction Y. In this case, the total channel ratio RT may be adjusted to 50%. According to such a structure, with a relatively simple design, it is possible to suppress the formation of a bias in the temperature distribution of the first device region 6.

[0184] FIGS. 16A to 16C are cross-sectional perspective views showing control examples of the power transistor 8. In FIGS. 16A to 16C, an off-state channel (source region 60) is shown by shaded hatching.

[0185] Referring to FIG. 16A, when gate signals G (that is, on signals) exceeding the gate threshold voltage are input to all of the n gate wirings 14, all of the unit transistors 10 (n system transistors 9) are simultaneously controlled to be in the on state. Thereby, the power transistor 8 is driven at the total channel ratio RT (that is, the n system channel ratios RS). Therefore, the channel utilization rate of the power transistor 8 relatively increases, and the on-resistance Ron relatively decreases. The total channel ratio RT determines the minimum value of the on-resistance Ron.

[0186] Referring to FIG. 16B, when gate signals G (that is, on signals) exceeding the gate threshold voltage are input to x (1≦x<n) gate wirings 14 and gate signals G (that is, off signals) less than the gate threshold voltage are input to (n-x) gate wirings 14, the x system transistors 9 are turned on, while the (n-x) system transistors 9 are turned off. In this case, the power transistor 8 is driven at the x system channel ratio RS (that is, less than the total channel ratio RT). Therefore, the channel utilization rate of the power transistor 8 relatively decreases, and the on-resistance Ron relatively increases.

[0187] 16C, when a gate signal G (i.e., an OFF signal) lower than the gate threshold voltage is input to all of the n gate wirings 14, all of the unit transistors 10 (n system transistors 9) are simultaneously turned OFF, and the power transistor 8 is therefore stopped.

[0188] The power transistor 8 is electrically connected to, for example, an inductive load L. In this case, when a gate signal G exceeding the gate threshold voltage is input to the power transistor 8, the power transistor 8 goes from a stopped state to an ON transition operation and then to a normal operation.

[0189] On the other hand, when a gate signal G lower than the gate threshold voltage is input to the power transistor 8 during normal operation, the power transistor 8 goes from normal operation to an off transition operation and then to an active clamp operation. The active clamp operation is an operation in which the power transistor 8 consumes (absorbs) the back electromotive force caused by the inductive energy of the inductive load L. The power transistor 8 goes into a stopped state after the active clamp operation.

[0190] The power transistor 8 may be configured with at least two systems (i.e., n≧2) and include at least two system transistors 9. Each of the at least two system transistors 9 includes one or more unit transistors 10. The at least two system transistors 9 are electrically connected to at least two gate wirings 14, respectively, and are individually controlled by at least two gate signals G. Therefore, the two or more systems of power transistors 8 can realize at least two operating modes, each having a different on-resistance Ron.

[0191] The two-system power transistors 8 including the first and second system transistors 9 are controlled in a first operation mode, a second operation mode, and a third operation mode. In the first operation mode, the first and second system transistors 9 are simultaneously controlled to be in an on state. In the second operation mode, one of the first and second system transistors 9 is controlled to be in an on state, and the other is controlled to be in an off state. In the third operation mode, the first and second system transistors 9 are simultaneously controlled to be in an off state.

[0192] That is, the power transistor 8 is driven at the total channel ratio RT (for example, 50%) in the first operation mode. Also, the power transistor 8 is driven at the system channel ratio RS of either one of the first and second system transistors 9 (for example, 25% less than the total channel ratio RT) in the second operation mode. Also, the power transistor 8 is in a stopped state in the third operation mode.

[0193] The power transistor 8 may be driven in the first operation mode during the on-transition operation, normal operation, and off-transition operation. In this case, a current can be passed by using the first and second system transistors 9. That is, the power transistor 8 is driven at the total channel ratio RT (=50%) during the on-transition operation, normal operation, and off-transition operation.

[0194] On the other hand, the power transistor 8 may be driven in the second operation mode during active clamp operation. In this case, a current can be passed through only one of the first and second system transistors 9. That is, the power transistor 8 is driven at a channel ratio (=25%) less than the total channel ratio RT (=50%) during active clamp operation.

[0195] In other words, the power transistor 8 is driven by an on-resistance Ron during active clamp operation that exceeds the on-resistance Ron during normal operation. This allows the counter electromotive force to be consumed (absorbed) while suppressing a sudden temperature rise. As a result, the active clamp tolerance can be improved. When all of the counter electromotive force caused by the inductive load L is consumed, the power transistor 8 enters the third operation mode (=stopped state).

[0196] Preferably, the power transistors 8 are made up of at least three systems (i.e., n≧3) and include at least three system transistors 9. Each of the at least three system transistors 9 includes one or more unit transistors 10. The at least three system transistors 9 are electrically connected to at least three gate wirings 14, respectively, and are individually controlled by at least three gate signals G. Therefore, the three or more systems of power transistors 8 can realize at least three operating modes, each having a different on-resistance Ron.

[0197] The three systems of power transistors 8 including the first to third system transistors 9 are controlled in a first operation mode, a second operation mode, a third operation mode, and a fourth operation mode. In the first operation mode, the first to third system transistors 9 are simultaneously controlled to be in an on state. In the second operation mode, only two of the first to third system transistors 9 are simultaneously controlled to be in an on state. In the third operation mode, only one of the first to third system transistors 9 is controlled to be in an on state. In the fourth operation mode, the first to third system transistors 9 are simultaneously controlled to be in an off state.

[0198] That is, the power transistor 8 is driven at the total channel ratio RT (for example, 75%) in the first operation mode. Also, the power transistor 8 is driven at the sum (for example, 50%) of any two of the system channel ratios RS of the first to third system transistors 9 in the second operation mode. Also, the power transistor 8 is driven at any one of the system channel ratios RS of the first to third system transistors 9 (for example, 25%) in the third operation mode. Also, the power transistor 8 is in a stopped state in the fourth operation mode.

[0199] The power transistor 8 may be driven in the first operation mode during the ON transition operation. In this case, current can be passed by using the transistors 9 of the first to third systems. That is, the power transistor 8 is driven at the total channel ratio RT (=75%) during the ON transition operation. This reduces the ON resistance Ron. Therefore, power consumption can be suppressed even in a situation where an excessive rush current may flow during the ON transition operation.

[0200] The power transistor 8 may be driven in the second operation mode during normal operation. In this case, a current can be passed through only two of the first to third system transistors 9. As a result, the power transistor 8 is driven with a channel ratio (=50%) during normal operation that is lower than the channel ratio (=75%) during on-transition operation.

[0201] The power transistor 8 may be driven in the first operation mode during the OFF transition operation. In this case, a current can be passed by using the transistors 9 of the first to third systems. That is, during the OFF transition operation, the power transistor 8 is driven at a total channel ratio RT (=75%) that exceeds the channel ratio (=50%) during normal operation.

[0202] The power transistor 8 may be driven in a third operation mode during active clamp operation. In this case, a current can be passed through only one of the first to third system transistors 9. That is, during active clamp operation, the power transistor 8 is driven with a channel ratio (=25%) that is lower than the channel ratio (=50%) during normal operation.

[0203] In other words, the power transistor 8 is driven by an on-resistance Ron during active clamp operation that exceeds the on-resistance Ron during normal operation. This allows the counter electromotive force to be consumed (absorbed) while suppressing a sudden temperature rise. As a result, the active clamp tolerance can be improved. When all of the counter electromotive force caused by the inductive load L is consumed, the power transistor 8 enters the fourth operation mode (=stopped state).

[0204] Fig. 17 is an enlarged view of region XVII shown in Fig. 3. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. Fig. 19 is an enlarged cross-sectional view of a main part of the structure shown in Fig. 18. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 17. Fig. 21 is an enlarged cross-sectional view of a main part of the structure shown in Fig. 20.

[0205] 17 to 21, semiconductor device 1 includes a CMIS region 100 (Complementary Metal Insulator Semiconductor region) defined on first main surface 3 in second device region 7. CMIS region 100 is a region to which a voltage (potential) different from that of first device region 6 is applied, and is a region in which CMIS 100a constituting one circuit of control IC 11 is formed. In other words, control IC 11 includes CMIS 100a formed in an arbitrary region on first main surface 3 of second device region 7.

[0206] Specifically, the CMIS 100a includes a first n-type MISFET 101 and a second p-type MISFET 102 that are complementarily connected. The first MISFET 101 is driven and controlled under voltage application conditions that differ from those of the power transistor 8. The second MISFET 102 is driven and controlled under voltage application conditions that differ from those of the power transistor 8 and the first MISFET 101. A specific structure within the CMIS region 100 will be described below.

[0207] 17 to 19, the semiconductor device 1 includes a second trench isolation structure 104 as an example of a region isolation structure that partitions the first MIS region 103 in the first main surface 3 of the CMIS region 100. The first MIS region 103 is a device region that is controlled under voltage application conditions different from those of the first device region 6. The second trench isolation structure 104 may also be referred to as a deep trench isolation (DTI) structure or a shallow trench isolation (STI) structure.

[0208] The second trench isolation structure 104 is formed in a ring shape surrounding a partial region of the first main surface 3 in plan view, and defines a first MIS region 103 of a predetermined shape. In this embodiment, the second trench isolation structure 104 is formed in a quadrangular ring shape having four sides parallel to the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) in plan view, and defines the quadrangular first MIS region 103. The second trench isolation structure 104 may have any planar shape and may be formed in a polygonal ring shape. The first MIS region 103 may be defined in a polygonal shape according to the planar shape of the second trench isolation structure 104.

[0209] The second trench isolation structure 104 has an isolation width WI and an isolation depth DI (i.e., an aspect ratio DI / WI) similar to the first trench isolation structure 43. It is particularly preferable that the bottom wall of the second trench isolation structure 104 be formed with a gap of 1 μm or more and 5 μm or less from the bottom of the second semiconductor region 42.

[0210] The second trench isolation structure 104 has corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. In this embodiment, the four corners of the second trench isolation structure 104 are formed in an arc shape. In other words, the first MIS region 103 is partitioned into a quadrangle having four corners that each extend in an arc shape. The corners of the second trench isolation structure 104 preferably have a constant isolation width WI along the arc direction.

[0211] Similar to the first trench isolation structure 43, the second trench isolation structure 104 has a single electrode structure including an isolation trench 44, an isolation insulating film 45 (isolation insulator), and an isolation electrode 46. The "isolation trench 44," "isolation insulating film 45," and "isolation electrode 46" of the second trench isolation structure 104 may be referred to as a "second isolation trench," a "second isolation insulating film," and a "second isolation electrode," respectively. The explanation of the isolation trench 44, isolation insulating film 45, and isolation electrode 46 of the second trench isolation structure 104 is omitted here because the explanation of the isolation trench 44, isolation insulating film 45, and isolation electrode 46 of the first trench isolation structure 43 also applies.

[0212] The semiconductor device 1 includes a p-type first well region 105 formed in a surface layer portion of the first main surface 3 in the first MIS region 103. The first well region 105 is formed throughout the surface layer portion of the first main surface 3 in the first MIS region 103 and is in contact with the second trench isolation structure 104. The first well region 105 is formed in a region on the first main surface 3 side with respect to the bottom wall of the second trench isolation structure 104. The bottom of the first well region 105 is formed in a region on the bottom wall side of the second trench isolation structure 104 with respect to the intermediate portion of the second trench isolation structure 104. In other words, the bottom of the first well region 105 is formed in a region on the bottom wall side of the second trench isolation structure 104 with respect to the depth position of the bottom of the body region 47.

[0213] The semiconductor device 1 includes an n-type first drift region 107 formed in a surface layer portion of the first well region 105. The first drift region 107 is formed in the surface layer portion of the first well region 105 at a distance from the second trench isolation structure 104. The first drift region 107 may be formed in a strip shape extending in one direction (first direction X) in a plan view. The first drift region 107 is formed at a distance from the bottom of the first well region 105 toward the first main surface 3. The first drift region 107 faces the second semiconductor region 42 across a part of the first well region 105.

[0214] The semiconductor device 1 includes an n-type first drain region 108 formed in a surface layer portion of the first drift region 107. The first drain region 108 has an n-type impurity concentration that exceeds the n-type impurity concentration of the first drift region 107. The first drain region 108 is formed in a surface layer portion of the first drift region 107 at a distance from the periphery of the first drift region 107. The first drain region 108 may be formed in a strip shape extending in one direction (first direction X) in plan view. The first drain region 108 is formed at a distance from the bottom of the first drift region 107 toward the first main surface 3. The first drain region 108 faces the first well region 105 across a part of the first drift region 107.

[0215] The semiconductor device 1 includes an n-type first source region 109 formed in a surface layer portion of the first well region 105 and spaced apart from the first drift region 107. The first source region 109 has an n-type impurity concentration substantially equal to the n-type impurity concentration of the first drain region 108. The first source region 109 is formed and spaced apart from the second trench isolation structure 104. The first source region 109 may be formed in a strip shape extending in one direction (first direction X) in plan view. The first source region 109 is formed and spaced apart from the depth position of the bottom of the first drift region 107 toward the first main surface 3.

[0216] The semiconductor device 1 includes a first channel region 110 formed in a region between the first drift region 107 and the first source region 109 in a surface layer portion of the first well region 105. The first channel region 110 forms the channel of the first MISFET 101.

[0217] The semiconductor device 1 includes a p-type first contact region 111 formed in a surface layer portion of the first well region 105. The first contact region 111 has a p-type impurity concentration higher than the p-type impurity concentration of the first well region 105. The first contact region 111 is formed at a distance from the second trench isolation structure 104. The first contact region 111 is formed in a strip shape extending along the second trench isolation structure 104 in a plan view. The first contact region 111 is preferably formed in a ring shape surrounding the first drift region 107 and the first source region 109. The first contact region 111 may be in contact with the second trench isolation structure 104.

[0218] The semiconductor device 1 includes a second field insulating film 120 that partially covers the first main surface 3 in the first MIS region 103. In this embodiment, the second field insulating film 120 includes a silicon oxide film. Specifically, the second field insulating film 120 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0219] The second field insulating film 120 covers the first drift region 107. The second field insulating film 120 covers the region between the first drain region 108 and the first contact region 111. The second field insulating film 120 covers the region between the first source region 109 and the first contact region 111. The second field insulating film 120 covers the region between the second trench isolation structure 104 and the first contact region 111. The second field insulating film 120 is continuous with the isolation insulating film 45 exposed from the inner wall of the second trench isolation structure 104 at the periphery of the first MIS region 103.

[0220] The second field insulating film 120 includes a plurality of first openings 121 that respectively expose the first main surface 3. The plurality of first openings 121 include at least one first drain opening 121A, at least one first channel opening 121B, and at least one first contact opening 121C.

[0221] The first drain opening 121A exposes the first drain region 108. The number of first drain openings 121A is arbitrary. One first drain opening 121A may be formed, or a plurality of first drain openings 121A may be formed. The first channel opening 121B exposes the first source region 109 and the first channel region 110. The first channel opening 121B may expose the first drift region 107. The number of first channel openings 121B is arbitrary. One first channel opening 121B may be formed, or a plurality of first channel openings 121B may be formed.

[0222] The first contact opening 121C exposes the first contact region 111. The number of first contact openings 121C is arbitrary. One first contact opening 121C may be formed, or multiple first contact openings 121C may be formed. In this case, it is preferable that the multiple first contact openings 121C are formed at intervals along the first contact region 111.

[0223] The plurality of first openings 121 may each be formed in a quadrangular shape in plan view. That is, the plurality of first openings 121 may each have a side extending in one direction (first direction X) in plan view and a side extending in an intersecting direction (second direction Y) that intersects the one direction.

[0224] The second field insulating film 120 has a plurality of second insulating sidewalls 120a that respectively define a plurality of first openings 121. The plurality of second insulating sidewalls 120a are formed around the entire periphery of the inner wall of each of the plurality of first openings 121. That is, the plurality of second insulating sidewalls 120a are formed on the sides of each of the plurality of first openings 121 that extend in one direction (first direction X) and on the sides that extend in an intersecting direction (second direction Y) that intersects with the one direction. Each second insulating sidewall 120a slopes obliquely downward at an acute angle with respect to the first main surface 3. Specifically, each second insulating sidewall 120a has an upper end located on the main surface side of the second field insulating film 120 and a lower end located on the first main surface 3 side, and slopes obliquely downward from the upper end to the lower end.

[0225] Each second insulating side wall 120a forms a second inclination angle θ2 of 20° to 40° (20°≦θ2≦40°) with the first main surface 3. The second inclination angle θ2 is the angle (absolute value) that a line connecting the upper end and lower end of each second insulating side wall 120a forms with the first main surface 3 inside the second field insulating film 120 when the line is set in a cross-sectional view.

[0226] The second tilt angle θ2 is preferably less than 40° (θ2<40°). It is particularly preferable that the second tilt angle θ2 be within the range of 30°±6° (24°≦θ2≦36°). The second tilt angle θ2 is typically within the range of 28° to 36° (28°≦θ2≦36°). It is preferable that the second tilt angle θ2 be approximately equal to the first tilt angle θ1 of the first field insulating film 80 (θ1≈θ2).

[0227] The region between the upper and lower ends of each second insulating side wall 120a may be inclined in a curved manner recessed toward the first main surface 3. In this case as well, the second inclination angle θ2 is the angle (absolute value) that a line connecting the upper and lower ends of each second insulating side wall 120a in a cross-sectional view forms with the first main surface 3.

[0228] The second field insulating film 120 has a second field thickness TF2. The second field thickness TF2 is the thickness along the normal direction Z of the portion of the second field insulating film 120 other than the portion forming the second insulating side wall 120a. The second field thickness TF2 may be approximately equal to the first separation thickness TI1 of the separation insulating film 45 (TF2≈TI1). Preferably, the second field thickness TF2 exceeds the second separation thickness TI2 of the separation insulating film 45 (TI2<TF2).

[0229] Preferably, the second field thickness TF2 is greater than or equal to the first thickness T1 of the upper insulating film 54 (T1≤TF2). Particularly preferably, the second field thickness TF2 exceeds the first thickness T1 (T1<TF2). The second field thickness TF2 may be approximately equal to the first lower thickness T21 (= second thickness T2) of the lower insulating film 55 (TF2≈T21). Preferably, the second field thickness TF2 exceeds the second lower thickness T22 of the lower insulating film 55 (T22<TF2).

[0230] Preferably, the second field thickness TF2 exceeds the intermediate thickness TM (TM<TF2). The second field thickness TF2 may be approximately equal to the first contact thickness T31 (= third thickness T3) of the contact insulating film 73 (TF2≈T31). Preferably, the second field thickness TF2 exceeds the second contact thickness T32 of the contact insulating film 73 (T32<TF2). Preferably, the second field thickness TF2 is approximately equal to the first field thickness TF1 of the first field insulating film 80 (TF1≈TF2).

[0231] The second field thickness TF2 may be 0.1 μm or more and 1 μm or less. The second field thickness TF2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, or 0.75 μm or more and 1 μm or less. Preferably, the second field thickness TF2 is 0.15 μm or more and 0.65 μm or less.

[0232] The semiconductor device 1 includes a second hidden surface 131 and a second exposed surface 132 formed on the first main surface 3 in the first MIS region 103. The second hidden surface 131 is formed in a portion of the first main surface 3 that is covered by the second field insulating film 120. The second exposed surface 132 is formed in a portion of the first main surface 3 that is exposed from the second field insulating film 120. In other words, the first main surface 3 includes the second hidden surface 131 and the second exposed surface 132 that are partitioned by the second field insulating film 120 in the first MIS region 103.

[0233] In this embodiment, the second exposed surface 132 is recessed in the thickness direction (toward the second main surface 4) of the semiconductor chip 2 with respect to the second hidden surface 131. Specifically, the second exposed surface 132 is recessed by one step with respect to the second hidden surface 131 in the thickness direction of the semiconductor chip 2, starting from each second insulating sidewall 120a of the second field insulating film 120.

[0234] Second exposed surface 132 is formed at a depth position between the bottom of first source region 109 (the bottom of first drain region 108 and the bottom of first contact region 111) and second hidden surface 131 in normal direction Z. Second exposed surface 132 is preferably recessed from second hidden surface 131 in normal direction Z by a depth in the range of more than 0 μm to 0.5 μm or less (preferably 0.2 μm or less).

[0235] The semiconductor device 1 includes a second main surface insulating film 133 that selectively covers the first main surface 3 in the first MIS region 103. In this embodiment, the second main surface insulating film 133 includes a silicon oxide film. Specifically, the second main surface insulating film 133 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The second main surface insulating film 133 covers the portions of the first main surface 3 that are exposed from the multiple first openings 121. In other words, the second main surface insulating film 133 covers at least the first drain region 108, the first source region 109, the first channel region 110, and the first contact region 111.

[0236] The second main surface insulating film 133 covers the second exposed surface 132 and is continuous with each second insulating side wall 120a of the second field insulating film 120. The second main surface insulating film 133 is formed at a distance from the middle portion in the thickness direction of the second field insulating film 120 toward the semiconductor chip 2 side (the second exposed surface 132 side). Specifically, when a line passing through the middle portion in the thickness direction of the second field insulating film 120 along the second exposed surface 132 (the first main surface 3) is set in a cross-sectional view, the second main surface insulating film 133 is formed at a distance from the line toward the semiconductor chip 2 side.

[0237] The second main surface insulating film 133 includes a first region 133a and a second region 133b. The first region 133a is located on the semiconductor chip 2 side with respect to the second hidden surface 131. The second region 133b is located on the side opposite to the semiconductor chip 2 with respect to the second hidden surface 131 (the main surface side of the second field insulating film 120). Specifically, when an extension line extending parallel to the second hidden surface 131 from above the second hidden surface 131 is set in a cross-sectional view, the first region 133a is located on the semiconductor chip 2 side with respect to the extension line. The second region 133b is located on the side opposite to the first region 133a across the extension line (that is, on the side opposite to the semiconductor chip 2).

[0238] The second main surface insulating film 133 has a second insulating thickness TMI2 (TMI2 < TF2) less than the second field thickness TF2 of the second field insulating film 120. It is preferable that the second insulating thickness TMI2 is 1 / 5 or less of the second field thickness TF2 (TMI2 ≤ 1 / 5 × TF2). The second insulating thickness TMI2 may be substantially equal to the first insulating thickness TMI1 of the first main surface insulating film 83 (TMI2 ≈ TMI1).

[0239] The semiconductor device 1 includes the aforementioned outer field insulating film 84 that covers the region outside the first MIS region 103. The outer field insulating film 84 covers the periphery of the second trench isolation structure 104 in the region outside the first MIS region 103. In the region outside the first MIS region 103, the outer field insulating film 84 surrounds the second trench isolation structure 104 in a plan view and is continuous with the isolation insulating film 45 exposed from the outer peripheral wall of the second trench isolation structure 104.

[0240] The semiconductor device 1 includes a first gate electrode 134 (main surface electrode) facing the first channel region 110 in the first channel opening 121B with the second main surface insulating film 133 sandwiched therebetween. In this embodiment, the first gate electrode 134 includes conductive polysilicon. A gate potential is applied to the first gate electrode 134. The first gate electrode 134 controls the on / off of the first channel region 110. Specifically, the first gate electrode 134 faces the first drift region 107, the first source region 109, and the first channel region 110 in a plan view.

[0241] The first gate electrode 134 is formed in a strip shape extending along the first channel region 110 in a plan view. The first gate electrode 134 has a first drawn portion 135 drawn from above the second main surface insulating film 133, through the second insulating sidewall 120a, and onto the second field insulating film 120 located on the first drain region 108 side. The first drawn portion 135 is formed at an interval from the first drain region 108 toward the first source region 109, and faces the first drift region 107 with the second field insulating film 120 sandwiched between them.

[0242] The first gate electrode 134 has sidewalls with a steeper inclination angle than the second insulating sidewalls 120a of the second field insulating film 120. The inclination angle of the sidewalls of the first gate electrode 134 is the angle (absolute value) that a line connecting the upper and lower ends of the sidewalls of the first gate electrode 134 forms with the first main surface 3 inside the first gate electrode 134. The inclination angle of the sidewalls of the first gate electrode 134 may be 45° or more and 90° or less. The inclination angle of the sidewalls of the first gate electrode 134 is preferably 60° or more and 90° or less.

[0243] The semiconductor device 1 includes a first sidewall structure 136 covering the sidewall of the first gate electrode 134. The first sidewall structure 136 is located on the second field insulating film 120 and the second main surface insulating film 133. The first sidewall structure 136 includes at least one of silicon oxide and silicon nitride. In this embodiment, the first sidewall structure 136 includes silicon oxide. The first sidewall structure 136 may also include silicon nitride. In other words, the first sidewall structure 136 may include an insulator different from the second field insulating film 120 and the second main surface insulating film 133.

[0244] The semiconductor device 1 includes the aforementioned interlayer insulating layer 13 covering the first main surface 3 in the first MIS region 103. The semiconductor device 1 also includes a plurality of plug electrodes 141-145 embedded in the interlayer insulating layer 13. Each of the plurality of plug electrodes 141-145 may be a tungsten plug electrode having a stacked structure including a titanium-based metal film and a tungsten film. The plurality of plug electrodes 141-145 includes at least one sixth plug electrode 141, at least one seventh plug electrode 142, at least one eighth plug electrode 143, at least one ninth plug electrode 144, and at least one tenth plug electrode 145.

[0245] The sixth plug electrode 141 is a source plug electrode for the isolation electrode 46. The sixth plug electrode 141 is embedded in a portion of the interlayer insulating layer 13 that covers the second trench isolation structure 104, and is electrically connected to the isolation electrode 46. The seventh plug electrode 142 is a drain plug electrode for the first drain region 108.

[0246] The seventh plug electrode 142 is embedded in a portion of the interlayer insulating layer 13 that covers the first drain region 108, and is electrically connected to the first drain region 108. The eighth plug electrode 143 is a source plug electrode for the first source region 109. The eighth plug electrode 143 is embedded in a portion of the interlayer insulating layer 13 that covers the first source region 109, and is electrically connected to the first source region 109.

[0247] The ninth plug electrode 144 is a source plug electrode for the first contact region 111. The ninth plug electrode 144 is embedded in a portion of the interlayer insulating layer 13 that covers the first contact region 111, and is electrically connected to the first contact region 111. The tenth plug electrode 145 is a gate plug electrode for the first gate electrode 134. The tenth plug electrode 145 is embedded in a portion of the interlayer insulating layer 13 that covers the first gate electrode 134, and is electrically connected to the first gate electrode 134. The tenth plug electrode 145 may be connected to the first lead portion 135 of the first gate electrode 134.

[0248] The semiconductor device 1 includes one or more first drain wirings 146 formed in the interlayer insulating layer 13. The one or more first drain wirings 146 are made of a wiring layer formed in the interlayer insulating layer 13. The one or more first drain wirings 146 are selectively routed in the interlayer insulating layer 13 and electrically connected to the first drain region 108 via the seventh plug electrode 142.

[0249] The semiconductor device 1 includes one or more first source interconnects 147 formed in the interlayer insulating layer 13. The one or more first source interconnects 147 are made of a wiring layer formed in the interlayer insulating layer 13. The one or more first source interconnects 147 are selectively routed within the interlayer insulating layer 13 and electrically connected to the isolation electrode 46, the first source region 109, and the first contact region 111 via the sixth plug electrode 141, the eighth plug electrode 143, and the ninth plug electrode 144.

[0250] The semiconductor device 1 includes one or more first gate wirings 148 formed in the interlayer insulating layer 13. The one or more first gate wirings 148 are made of a wiring layer formed in the interlayer insulating layer 13. The one or more first gate wirings 148 are selectively routed in the interlayer insulating layer 13 and electrically connected to the first gate electrode 134 via a tenth plug electrode 145.

[0251] 17, 20, and 21, the semiconductor device 1 includes a third trench isolation structure 154 as an example of a region isolation structure that partitions the second MIS region 153 in the first main surface 3 of the CMIS region 100. The second MIS region 153 is a device region controlled under voltage application conditions different from those of the first device region 6 and the first MIS region 103. The third trench isolation structure 154 may also be referred to as a deep trench isolation (DTI) structure or a shallow trench isolation (STI) structure.

[0252] The third trench isolation structure 154 is formed in a ring shape surrounding a partial region of the first main surface 3 at a distance from the second trench isolation structure 104 in a plan view, and defines a second MIS region 153 of a predetermined shape. The third trench isolation structure 154 may be formed integrally with the second trench isolation structure 104 in the region between the first MIS region 103 and the second MIS region 153.

[0253] In this embodiment, the third trench isolation structure 154 is formed in a quadrangular ring shape having four sides parallel to the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) in plan view, and defines a quadrangular second MIS region 153. The third trench isolation structure 154 may have any planar shape and may be formed in a polygonal ring shape. The second MIS region 153 may be defined in a polygonal shape according to the planar shape of the third trench isolation structure 154.

[0254] The third trench isolation structure 154 has an isolation width WI and an isolation depth DI (i.e., an aspect ratio DI / WI) similar to the first trench isolation structure 43. It is particularly preferable that the bottom wall of the third trench isolation structure 154 be formed with a gap of 1 μm or more and 5 μm or less from the bottom of the second semiconductor region 42.

[0255] The third trench isolation structure 154 has corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. In this embodiment, the four corners of the third trench isolation structure 154 are formed in an arc shape. In other words, the second MIS region 153 is partitioned into a quadrangle having four corners that each extend in an arc shape. It is preferable that the corners of the third trench isolation structure 154 have a constant isolation width WI along the arc direction.

[0256] Similar to the first trench isolation structure 43, the third trench isolation structure 154 has a single electrode structure including an isolation trench 44, an isolation insulating film 45 (isolation insulator), and an isolation electrode 46. The "isolation trench 44," "isolation insulating film 45," and "isolation electrode 46" of the third trench isolation structure 154 may be referred to as a "third isolation trench," a "third isolation insulating film," and a "third isolation electrode," respectively. The explanation of the isolation trench 44, isolation insulating film 45, and isolation electrode 46 of the third trench isolation structure 154 is omitted here because the explanation of the isolation trench 44, isolation insulating film 45, and isolation electrode 46 of the first trench isolation structure 43 also applies.

[0257] The semiconductor device 1 includes a p-type second well region 155 formed in the second MIS region 153 in a surface layer portion of the first main surface 3. The second well region 155 is formed in the second MIS region 153 over the entire surface layer portion of the first main surface 3 and is in contact with a third trench isolation structure 154. The second well region 155 is formed in a region on the first main surface 3 side with respect to the bottom wall of the third trench isolation structure 154. The bottom of the second well region 155 is formed in a region on the bottom wall side of the third trench isolation structure 154 with respect to the central portion of the third trench isolation structure 154. In other words, the bottom of the second well region 155 is formed in a region on the bottom wall side of the third trench isolation structure 154 with respect to the depth position of the bottom of the body region 47.

[0258] The semiconductor device 1 includes an n-type third well region 156 formed in a surface layer portion of the second well region 155 at a distance from the third trench isolation structure 154. The third well region 156 may be formed in a quadrangle shape having four sides parallel to the third trench isolation structure 154 in a plan view. The third well region 156 is formed in a region on the first main surface 3 side of the bottom of the second well region 155. The third well region 156 faces the second semiconductor region 42 with a part of the second well region 155 in between.

[0259] The semiconductor device 1 includes a p-type second drift region 157 formed in a surface layer portion of the third well region 156. The second drift region 157 is formed in a surface layer portion of the third well region 156 at a distance from the periphery of the third well region 156. The second drift region 157 may be formed in a strip shape extending in one direction (first direction X) in a plan view. The second drift region 157 is formed at a distance from the bottom of the third well region 156 toward the first main surface 3. The second drift region 157 faces the second well region 155 across a part of the third well region 156.

[0260] The semiconductor device 1 includes a p-type second drain region 158 formed in a surface layer portion of the second drift region 157. The second drain region 158 has a p-type impurity concentration that exceeds the p-type impurity concentration of the second drift region 157. The second drain region 158 is formed in a surface layer portion of the second drift region 157 at a distance from the periphery of the second drift region 157. The second drain region 158 may be formed in a strip shape extending in one direction (first direction X) in plan view. The second drain region 158 is formed at a distance from the bottom of the second drift region 157 toward the first main surface 3. The second drain region 158 faces the second well region 155 across a part of the second drift region 157.

[0261] The semiconductor device 1 includes a p-type second source region 159 formed in a surface layer portion of the third well region 156 and spaced apart from the second drift region 157. The second source region 159 has a p-type impurity concentration obtained by subtracting the p-type impurity concentration of the second drift region 157 from the p-type impurity concentration of the second drain region 158. The second source region 159 is formed and spaced apart from the third trench isolation structure 154. The second source region 159 may be formed in a strip shape extending in one direction (first direction X) in plan view. The second source region 159 is formed and spaced apart from the depth position of the bottom of the second drift region 157 toward the first main surface 3.

[0262] The semiconductor device 1 includes a second channel region 160 formed in a region between the second drift region 157 and the second source region 159 in a surface layer portion of the second well region 155. The second channel region 160 forms the channel of the second MISFET 102.

[0263] The semiconductor device 1 includes a p-type second contact region 161 formed in a surface layer portion of the second well region 155. The second contact region 161 has a p-type impurity concentration higher than the p-type impurity concentration of the second well region 155. The second contact region 161 is formed in a region between the third trench isolation structure 154 and the third well region 156 and spaced apart from the third trench isolation structure 154 and the third well region 156. The second contact region 161 is formed in a strip shape extending along the third trench isolation structure 154 in a plan view. The second contact region 161 is preferably formed in a ring shape surrounding the third well region 156. The second contact region 161 may be in contact with the third trench isolation structure 154.

[0264] The semiconductor device 1 includes a third field insulating film 170 that partially covers the first main surface 3 in the second MIS region 153. In this embodiment, the third field insulating film 170 includes a silicon oxide film. Specifically, the third field insulating film 170 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0265] The third field insulating film 170 covers the second drift region 157. The third field insulating film 170 covers the region between the second drain region 158 and the second contact region 161. The third field insulating film 170 covers the region between the second source region 159 and the second contact region 161. The third field insulating film 170 covers the region between the third trench isolation structure 154 and the second contact region 161. The third field insulating film 170 is continuous with the isolation insulating film 45 exposed from the inner wall of the third trench isolation structure 154 at the periphery of the second MIS region 153.

[0266] The third field insulating film 170 includes a plurality of second openings 171 that respectively expose the first main surface 3. The plurality of second openings 171 include at least one second drain opening 171A, at least one second channel opening 171B, and at least one second contact opening 171C.

[0267] The second drain opening 171A exposes the second drain region 158. The number of second drain openings 171A is arbitrary. One second drain opening 171A may be formed, or multiple second drain openings 171A may be formed. The second channel opening 171B exposes the second source region 159 and the second channel region 160. The number of second channel openings 171B is arbitrary. One second channel opening 171B may be formed, or multiple second channel openings 171B may be formed.

[0268] The second contact opening 171C exposes the second contact region 161. The number of second contact openings 171C is arbitrary. One second contact opening 171C may be formed, or multiple second contact openings 171C may be formed. In this case, it is preferable that the multiple second contact openings 171C are formed at intervals along the second contact region 161.

[0269] The second openings 171 may each be formed in a quadrangular shape in plan view. That is, the second openings 171 may each have a side extending in one direction (first direction X) in plan view and a side extending in an intersecting direction (second direction Y) that intersects the first direction.

[0270] The third field insulating film 170 has a plurality of third insulating sidewalls 170a that respectively define a plurality of second openings 171. The plurality of third insulating sidewalls 170a are formed around the entire periphery of the inner wall of each of the second openings 171. That is, the plurality of third insulating sidewalls 170a are formed on the sides of each of the second openings 171 that extend in one direction (first direction X) and on the sides that extend in an intersecting direction (second direction Y) that intersects with the one direction. Each of the third insulating sidewalls 170a slopes obliquely downward at an acute angle with respect to the first main surface 3. Specifically, each of the third insulating sidewalls 170a has an upper end located on the main surface side of the third field insulating film 170 and a lower end located on the first main surface 3 side, and slopes obliquely downward from the upper end to the lower end.

[0271] Each third insulating side wall 170a forms a third inclination angle θ3 (20° ≤ θ3 ≤ 40°) of 20° or more and 40° or less with the first main surface 3. The third inclination angle θ3 is the angle (absolute value) formed by a straight line connecting the upper end portion and the lower end portion of each third insulating side wall 170a with respect to the first main surface 3 inside the third field insulating film 170 when viewed in cross section. It is preferable that the third inclination angle θ3 is less than 40° (θ3 < 40°).

[0272] It is particularly preferable that the third inclination angle θ3 falls within the range of 30° ± 6° (24° ≤ θ3 ≤ 36°). Typically, the third inclination angle θ3 falls within the range of 28° or more and 36° or less (28° ≤ θ3 ≤ 36°). It is preferable that the third inclination angle θ3 is substantially equal to the first inclination angle θ1 of the first field insulating film 80 (θ1 ≒ θ3). It is preferable that the third inclination angle θ3 is substantially equal to the second inclination angle θ2 of the second field insulating film 120 (θ2 ≒ θ3).

[0273] Each third insulating side wall 170a may be inclined in a curved shape recessed toward the first main surface 3 in the region between the upper end portion and the lower end portion. Also in this case, the third inclination angle θ3 is the angle (absolute value) formed by a straight line connecting the upper end portion and the lower end portion of each third insulating side wall 170a with respect to the first main surface 3 when viewed in cross section.

[0274] The third field insulating film 170 has a third field thickness TF3. The third field thickness TF3 is the thickness along the normal direction Z of the portion of the third field insulating film 170 other than the portion forming the third insulating side wall 170a. The third field thickness TF3 may be substantially equal to the first separation thickness TI1 of the separation insulating film 45 (TF3 ≒ TI1). It is preferable that the third field thickness TF3 exceeds the second separation thickness TI2 of the separation insulating film 45 (TI2 < TF3).

[0275] The third field thickness TF3 is preferably not less than the first thickness T1 of the upper insulating film 54 (T1 ≦ TF3). Particularly preferably, the third field thickness TF3 exceeds the first thickness T1 (T1 < TF3). The third field thickness TF3 may be substantially equal to the first lower thickness T21 (= the second thickness T2) of the lower insulating film 55 (TF3 ≒ T21). Preferably, the third field thickness TF3 exceeds the second lower thickness T22 of the lower insulating film 55 (T22 < TF3).

[0276] Preferably, the third field thickness TF3 exceeds the intermediate thickness TM (TM < TF3). The third field thickness TF3 may be substantially equal to the first contact thickness T31 (= the third thickness T3) of the contact insulating film 73 (TF3 ≒ T31). Preferably, the third field thickness TF3 exceeds the second contact thickness T32 of the contact insulating film 73 (T32 < TF3). Preferably, the third field thickness TF3 is substantially equal to the first field thickness TF1 of the first field insulating film 80 (TF1 ≒ TF3). Preferably, the third field thickness TF3 is substantially equal to the second field thickness TF2 of the second field insulating film 120 (TF2 ≒ TF3).

[0277] The third field thickness TF3 may be not less than 0.1 μm and not more than 1 μm. The third field thickness TF3 may be not less than 0.1 μm and not more than 0.25 μm, not less than 0.25 μm and not more than 0.5 μm, not less than 0.5 μm and not more than 0.75 μm, or not less than 0.75 μm and not more than 1 μm. Preferably, the third field thickness TF3 is not less than 0.15 μm and not more than 0.65 μm.

[0278] The semiconductor device 1 includes the above-described outer field insulating film 84 that covers the region outside the second MIS region 153. The outer field insulating film 84 covers the periphery of the third trench isolation structure 154 in the region outside the second MIS region 153. In the region outside the second MIS region 153, the outer field insulating film 84 surrounds the third trench isolation structure 154 in plan view and is continuous with the isolation insulating film 45 exposed from the outer peripheral wall of the third trench isolation structure 154.

[0279] The semiconductor device 1 includes a third hidden surface 181 and a third exposed surface 182 formed on the first main surface 3 in the second MIS region 153. The third hidden surface 181 is formed in a portion of the first main surface 3 that is covered by the third field insulating film 170. The third exposed surface 182 is formed in a portion of the first main surface 3 that is exposed from the third field insulating film 170. In other words, the first main surface 3 includes the third hidden surface 181 and the third exposed surface 182 that are partitioned by the third field insulating film 170 in the second MIS region 153.

[0280] In this embodiment, the third exposed surface 182 is recessed in the thickness direction (toward the second main surface 4) of the semiconductor chip 2 with respect to the third hidden surface 181. Specifically, the third exposed surface 182 is recessed by one step in the thickness direction of the semiconductor chip 2 with respect to the third hidden surface 181, starting from each third insulating sidewall 170a of the third field insulating film 170.

[0281] Third exposed surface 182 is formed at a depth position between the bottom of second source region 159 (the bottom of second drain region 158 and the bottom of second contact region 161) and third hidden surface 181 in normal direction Z. Third exposed surface 182 is preferably recessed from third hidden surface 181 in normal direction Z by a depth in the range of more than 0 μm to 0.5 μm or less (preferably 0.2 μm or less).

[0282] The semiconductor device 1 includes a third main surface insulating film 183 that selectively covers the first main surface 3 in the second MIS region 153. In this embodiment, the third main surface insulating film 183 includes a silicon oxide film. Specifically, the third main surface insulating film 183 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The third main surface insulating film 183 covers the region of the first main surface 3 outside the third field insulating film 170.

[0283] The third main surface insulating film 183 covers the third exposed surface 182 and is continuous with each third insulating sidewall 170a of the third field insulating film 170. The third main surface insulating film 183 is formed at an interval from the middle portion in the thickness direction of the third field insulating film 170 toward the semiconductor chip 2 side (the third exposed surface 182 side). Specifically, when a line passing through the middle portion in the thickness direction of the third field insulating film 170 along the third exposed surface 182 (the first main surface 3) is set in a cross-sectional view, the third main surface insulating film 183 is formed at an interval from the line toward the semiconductor chip 2 side.

[0284] The third main surface insulating film 183 includes a first region 183a and a second region 183b. The first region 183a is located on the semiconductor chip 2 side with respect to the third hidden surface 181. The second region 183b is located on the side opposite to the semiconductor chip 2 (the main surface side of the third field insulating film 170) with respect to the third hidden surface 181. Specifically, when an extension line that extends parallel to the third hidden surface 181 from above the third hidden surface 181 is set in a cross-sectional view, the first region 183a is located on the semiconductor chip 2 side with respect to the extension line. The second region 183b is located on the side opposite to the first region 183a (that is, the side opposite to the semiconductor chip 2) across the extension line.

[0285] The third main surface insulating film 183 has a third insulating thickness TMI3 (TMI3 < TF3) less than the third field thickness TF3 of the third field insulating film 170. It is preferable that the third insulating thickness TMI3 is equal to or less than one-fifth of the third field thickness TF3 (TMI3 ≤ 1 / 5 × TF3). The third insulating thickness TMI3 may be substantially equal to the first insulating thickness TMI1 of the first main surface insulating film 83 (TMI3 ≈ TMI1).

[0286] The semiconductor device 1 includes a second gate electrode 184 (main surface electrode) facing the second channel region 160 in the first channel opening 121B with a third main surface insulating film 183 sandwiched therebetween. In this embodiment, the second gate electrode 184 includes conductive polysilicon. A gate potential is applied to the second gate electrode 184. The second gate electrode 184 controls the on / off of the second channel region 160. Specifically, the second gate electrode 184 faces the second drift region 157, the second source region 159, and the second channel region 160 in a plan view.

[0287] The second gate electrode 184 is formed in a strip shape extending along the second channel region 160 in a plan view. The second gate electrode 184 has a second lead portion 185 that is led from above the third main surface insulating film 183, through the second insulating sidewall 120a, and onto the third field insulating film 170 located on the second drain region 158 side. The second lead portion 185 is formed at an interval from the second drain region 158 to the second source region 159 side, and faces the second drift region 157 with the third field insulating film 170 sandwiched between them.

[0288] The second gate electrode 184 has sidewalls with a steeper inclination angle than the third insulating sidewalls 170a of the third field insulating film 170. The inclination angle of the sidewalls of the second gate electrode 184 is the angle (absolute value) that a line connecting the upper and lower ends of the sidewalls of the second gate electrode 184 forms with the first main surface 3 inside the second gate electrode 184. The inclination angle of the sidewalls of the second gate electrode 184 may be 45° or more and 90° or less. The inclination angle of the sidewalls of the second gate electrode 184 is preferably 60° or more and 90° or less.

[0289] The semiconductor device 1 includes a second sidewall structure 186 covering the sidewall of the second gate electrode 184. The second sidewall structure 186 is located on the third field insulating film 170 and the third main surface insulating film 183. The second sidewall structure 186 includes at least one of silicon oxide and silicon nitride. In this embodiment, the second sidewall structure 186 includes silicon oxide. The second sidewall structure 186 may also include silicon nitride. In other words, the second sidewall structure 186 may include an insulator different from the third field insulating film 170 and the third main surface insulating film 183.

[0290] The semiconductor device 1 includes the aforementioned interlayer insulating layer 13 covering the first main surface 3 in the second MIS region 153. The semiconductor device 1 also includes a plurality of plug electrodes 191-195 embedded in the interlayer insulating layer 13. Each of the plurality of plug electrodes 191-195 may be a tungsten plug electrode having a stacked structure including a titanium-based metal film and a tungsten film. The plurality of plug electrodes 191-195 includes at least one eleventh plug electrode 191, at least one twelfth plug electrode 192, at least one thirteenth plug electrode 193, at least one fourteenth plug electrode 194, and at least one fifteenth plug electrode 195.

[0291] The eleventh plug electrode 191 is a source plug electrode for the isolation electrode 46. The eleventh plug electrode 191 is embedded in a portion of the interlayer insulating layer 13 that covers the third trench isolation structure 154, and is electrically connected to the isolation electrode 46. The twelfth plug electrode 192 is a drain plug electrode for the second drain region 158. The twelfth plug electrode 192 is embedded in a portion of the interlayer insulating layer 13 that covers the second drain region 158, and is electrically connected to the second drain region 158. The thirteenth plug electrode 193 is a source plug electrode for the second source region 159. The thirteenth plug electrode 193 is embedded in a portion of the interlayer insulating layer 13 that covers the second source region 159, and is electrically connected to the second source region 159.

[0292] The fourteenth plug electrode 194 is a source plug electrode for the second contact region 161. The fourteenth plug electrode 194 is embedded in a portion of the interlayer insulating layer 13 that covers the second contact region 161, and is electrically connected to the second contact region 161. The fifteenth plug electrode 195 is a gate plug electrode for the second gate electrode 184. The fifteenth plug electrode 195 is embedded in a portion of the interlayer insulating layer 13 that covers the second gate electrode 184, and is electrically connected to the second gate electrode 184. The tenth plug electrode 145 may be connected to the second lead portion 185 of the second gate electrode 184.

[0293] The semiconductor device 1 includes one or more second drain wirings 196 formed in the interlayer insulating layer 13. The one or more second drain wirings 196 are made of a wiring layer formed in the interlayer insulating layer 13. The one or more second drain wirings 196 are selectively routed in the interlayer insulating layer 13 and electrically connected to the second drain region 158 via the twelfth plug electrode 192.

[0294] The semiconductor device 1 includes one or more second source interconnects 197 formed in the interlayer insulating layer 13. The one or more second source interconnects 197 are made of an interconnect layer formed in the interlayer insulating layer 13. The one or more second source interconnects 197 are selectively routed in the interlayer insulating layer 13 and electrically connected to the isolation electrode 46, the second source region 159, and the second contact region 161 via the eleventh plug electrode 191, the thirteenth plug electrode 193, and the fourteenth plug electrode 194.

[0295] The semiconductor device 1 includes one or more second gate wirings 198 formed in the interlayer insulating layer 13. The one or more second gate wirings 198 are made of a wiring layer formed in the interlayer insulating layer 13. The one or more second gate wirings 198 are selectively routed in the interlayer insulating layer 13 and electrically connected to the second gate electrode 184 via a fifteenth plug electrode 195.

[0296] 22A to 22U are cross-sectional views corresponding to the region shown in Fig. 12 (region where the power transistor 8 is formed) and illustrating an example of a method for manufacturing the semiconductor device 1. Figs. 23A to 23U are cross-sectional views corresponding to the region shown in Fig. 18 (region where the n-type MISFET 102 is formed) and illustrating an example of a method for manufacturing the semiconductor device 1.

[0297] 22A and 23A, a disk-shaped semiconductor wafer 201 is prepared as the base of the semiconductor chip 2. The semiconductor wafer 201 has a first wafer main surface 203 on one side and a second wafer main surface 204 on the other side. The first wafer main surface 203 and the second wafer main surface 204 correspond to the first main surface 3 and the second main surface 4 of the semiconductor chip 2, respectively.

[0298] The semiconductor wafer 201 has an n-type first semiconductor region 41 in a surface layer portion of the second wafer main surface 204. In this form, the first semiconductor region 41 is made of a disk-shaped semiconductor substrate. The semiconductor wafer 201 has an n-type second semiconductor region 42 in a surface layer portion of the first wafer main surface 203. In this form, the second semiconductor region 42 is made of an epitaxial layer formed on the main surface of the semiconductor substrate.

[0299] Next, a plurality of device formation regions 205 each corresponding to a semiconductor device 1 are set on the first wafer main surface 203. Figures 22A to 22U show a region in one device formation region 205 that corresponds to Figure 12, and Figures 23A to 23U show a region in one device formation region 205 that corresponds to Figure 18. The plurality of device formation regions 205 are set, for example, in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0300] Next, in the first MIS region 103, a p-type first well region 105 and an n-type first drift region 107 are formed in a surface layer portion of the first wafer main surface 203. The first well region 105 is formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The first drift region 107 is formed by introducing n-type impurities into the first wafer main surface 203 (specifically, the first well region 105) by ion implantation using an ion implantation mask (not shown).

[0301] In the second MIS region 153, a p-type second well region 155, an n-type third well region 156, and a p-type second drift region 157 are formed in a surface layer portion of the first wafer main surface 203. The second well region 155 is formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The third well region 156 is formed by introducing n-type impurities into the first wafer main surface 203 (specifically, the second well region 155) by ion implantation using an ion implantation mask (not shown).

[0302] Second drift region 157 is formed by introducing p-type impurities into first wafer main surface 203 (specifically, third well region 156) by ion implantation using an ion implantation mask (not shown). The steps of forming first well region 105, first drift region 107, second well region 155, third well region 156, and second drift region 157 do not necessarily have to be performed at this timing, and can be performed at any timing.

[0303] Next, referring to FIGS. 22B and 23B, a hard mask 206 having a predetermined pattern is formed on the first wafer main surface 203. In this embodiment, the hard mask 206 is made of a silicon oxide film. The hard mask 206 may be formed by an oxidation process (e.g., a thermal oxidation process) and / or a CVD (Chemical Vapor Deposition) process. In this embodiment, the hard mask 206 is formed by a thermal oxidation process and shaped into the predetermined pattern by etching using a mask (not shown).

[0304] Specifically, the hard mask 206 exposes regions where a plurality of trenches 207 are to be formed on the first wafer main surface 203, and covers other regions. The plurality of trenches 207 include the isolation trenches 44 of the first to third trench isolation structures 43, 104, and 154, the gate trench 53 of the trench gate structure 51, and the contact trench 72 of the trench contact structure 71.

[0305] Next, unnecessary portions of the semiconductor wafer 201 are removed by etching through the hard mask 206. The etching may be wet etching and / or dry etching. The etching is preferably anisotropic dry etching (e.g., RIE (Reactive Ion Etching)). This forms a plurality of trenches 207. The hard mask 206 is then removed.

[0306] 22C and 23C, first base insulating film 208 (first insulating film) is formed on first wafer main surface 203 and on inner walls of multiple trenches 207. First base insulating film 208 serves as a base for isolation insulating film 45, lower insulating film 55, contact insulating film 73, first to third field insulating films 80, 120, 170, and outer field insulating film 84. In this embodiment, first base insulating film 208 is made of an insulating film having a relatively low first etching rate.

[0307] Specifically, the first base insulating film 208 is made of a silicon oxide film. The first base insulating film 208 may be formed by an oxidation process (for example, a thermal oxidation process) and / or a CVD process. In this embodiment, the first base insulating film 208 is formed by a thermal oxidation process. That is, the first base insulating film 208 is made of an oxide of the semiconductor wafer 201 and is made of a silicon oxide film having a relatively high density.

[0308] The thickness of the first base insulating film 208 may be 0.1 μm or more and 1 μm or less. The thickness of the first base insulating film 208 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, or 0.75 μm or more and 1 μm or less. The thickness of the first base insulating film 208 is preferably 0.15 μm or more and 0.65 μm or less.

[0309] 22D and 23D, a first base electrode film 209 is formed on the first base insulating film 208. The first base electrode film 209 fills the trenches 207 with the first base insulating film 208 in between, and covers the first wafer main surface 203 with the first base insulating film 208 in between. The first base electrode film 209 serves as a base for the isolation electrode 46, the lower electrode 57, and the contact electrode 74. In this embodiment, the first base insulating film 208 is made of conductive polysilicon. The first base electrode film 209 may be formed by a CVD method.

[0310] 22E and 23E, unnecessary portions of the first base electrode film 209 are removed until the first base insulating film 208 is exposed. The unnecessary portions of the first base electrode film 209 may be removed by etching. The etching may be wet etching and / or dry etching. As a result, portions of the first base electrode film 209 are embedded in the plurality of trenches 207 with the first base insulating film 208 sandwiched therebetween.

[0311] Next, referring to FIGS. 22F and 23F, a first resist mask 210 having a predetermined pattern is formed on the first wafer main surface 203. The first resist mask 210 exposes the region where the lower electrode 57 is to be formed and covers the other regions. Next, unnecessary portions of the first base electrode film 209 are removed by etching via the first resist mask 210. The etching may be wet etching and / or dry etching. As a result, the separation electrode 46, the lower electrode 57, and the contact electrode 74 are formed. The first resist mask 210 is then removed.

[0312] 22G and 23G, second base insulating film 211 (second insulating film) is formed on first base insulating film 208, separation electrode 46, lower electrode 57, and contact electrode 74. Second base insulating film 211, together with first base insulating film 208, forms stacked insulating film 212 that serves as a base for first to third field insulating films 80, 120, 170 and outer field insulating film 84. In this embodiment, second base insulating film 211 is made of an insulating film having a second etching rate higher than the first etching rate.

[0313] The second base insulating film 211 is specifically made of a silicon oxide film having properties different from those of the first base insulating film 208. More specifically, the second base insulating film 211 is made of a TEOS (Tetraethyl orthosilicate) film. That is, the second base insulating film 211 is made of an oxide (an oxide different from the oxide of the semiconductor wafer 201) attached from the outside to the first base insulating film 208, etc., and is made of a silicon oxide film having a lower density than the first base insulating film 208. The second base insulating film 211 is formed by a CVD method.

[0314] The second base insulating film 211 has a thickness less than that of the first base insulating film 208. The second base insulating film 211 preferably has a thickness equal to or less than half the thickness of the first base insulating film 208. It is particularly preferable that the second base insulating film 211 has a thickness equal to or less than one-third the thickness of the first base insulating film 208.

[0315] The thickness of the second base insulating film 211 may be 0.01 μm or more and 0.5 μm or less. The thickness of the second base insulating film 211 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, or 0.4 μm or more and 0.5 μm or less. The thickness of the second base insulating film 211 is preferably 0.01 μm or more and 0.2 μm or less.

[0316] Next, the second base insulating film 211 is baked by a heat treatment method. This increases the density of the second base insulating film 211. The density of the second base insulating film 211 after baking is lower than that of the first base insulating film 208. Therefore, the second etching rate of the second base insulating film 211 after baking is higher than the first etching rate of the first base insulating film 208. The heating step for the second base insulating film 211 may be omitted as necessary. When the second base insulating film 211 is removed by wet etching, the heating step for the second base insulating film 211 is effective in adjusting the second etching rate.

[0317] 22H and 23H, a second resist mask 213 having a predetermined pattern is formed on second base insulating film 211. Specifically, second resist mask 213 covers regions in stacked insulating film 212 (second base insulating film 211) where first to third field insulating films 80, 120, and 170 are to be formed, a region where outer field insulating film 84 is to be formed, a region where isolation electrode 46 is to be formed, and a region where contact electrode 74 is to be formed, and exposes a region where lower insulating film 55 is to be formed (i.e., a part of gate trench 53).

[0318] Next, unnecessary portions of the stacked insulating film 212 are removed by etching through the second resist mask 213. In this step, first, the second base insulating film 211 is removed by etching through the second resist mask 213. The second base insulating film 211 is preferably removed by isotropic wet etching using an acidic etchant (e.g., hydrofluoric acid). Next, the first base insulating film 208 is removed by etching through the second resist mask 213. The first base insulating film 208 is preferably removed by isotropic wet etching using an acidic etchant (e.g., hydrofluoric acid). It is particularly preferable that the step of removing the first base insulating film 208 and the step of removing the second base insulating film 211 are performed simultaneously under the same conditions.

[0319] The removal rate of first base insulating film 208 is lower than the removal rate of second base insulating film 211. Therefore, during the step of removing first base insulating film 208, second base insulating film 211 is removed earlier than first base insulating film 208 so as to spread in the planar direction of first wafer main surface 203. This increases the area of ​​first base insulating film 208 exposed from second base insulating film 211 (second resist mask 213).

[0320] As a result, the amount of first base insulating film 208 removed starting from the main surface of first base insulating film 208 is increased compared to when second base insulating film 211 is not present. As a result, first to third field insulating films 80, 120, 170 having relatively gentle first to third insulating sidewalls 80a, 120a, 170a, respectively, are formed on first wafer main surface 203. Also, as a result, lower insulating film 55 is formed on the inner wall of gate trench 53. Second resist mask 213 is then removed.

[0321] 22I and 23I, second base insulating film 211 is removed. In practice, second base insulating film 211 is removed at any timing after the steps of forming first to third field insulating films 80, 120, and 170. Second base insulating film 211 may be naturally removed by a chemical solution used in the step of stripping second resist mask 213, in partially removing other structures (for example, structures on the control IC 11 side), or in the step of cleaning semiconductor wafer 201. In this case, the thickness of second base insulating film 211 is preferably set in advance to a value that allows it to be completely removed naturally.

[0322] The second base insulating film 211 prevents the first to third field insulating films 80, 120, 170, etc. from being thinned due to the chemical solution. Of course, part of the second base insulating film 211 may remain as part of the first to third field insulating films 80, 120, 170. In other words, the first to third field insulating films 80, 120, 170 may each have a layered structure including a first insulating film (silicon oxide film) and a second insulating film (TEOS film) having physical properties different from those of the first insulating film.

[0323] Next, referring to FIGS. 22J and 23J, a third base insulating film 214 is formed on the first wafer main surface 203, the isolation electrode 46, the lower electrode 57, and the inner wall of the gate trench 53. The third base insulating film 214 serves as a base for the upper insulating film 54, the intermediate insulating film 58, and the first to third main surface insulating films 83, 133, and 183. In this embodiment, the second base insulating film 211 is made of a silicon oxide film. The third base insulating film 214 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method) and / or a CVD method. In this embodiment, the third base insulating film 214 is formed by a thermal oxidation treatment method. As a result, the upper insulating film 54, the intermediate insulating film 58, and the first to third main surface insulating films 83, 133, and 183 are formed.

[0324] In the oxidation treatment, oxidation of the first wafer main surface 203 progresses in the thickness direction of the semiconductor wafer 201. As a result, first to third concealed surfaces 81, 131, 181 that are concealed by the first to third field insulating films 80, 120, 170, and first to third exposed surfaces 82, 132, 182 that are recessed in the thickness direction of the semiconductor wafer 201 relative to the first to third concealed surfaces 81, 131, 181 are formed on the first wafer main surface 203 (see also FIGS. 14A, 14B, 19, and 21). The first to third exposed surfaces 82, 132, 182 are also portions of the first wafer main surface 203 that are concealed by the first to third main surface insulating films 83, 133, 183.

[0325] Next, referring to FIGS. 22K and 23K, a second base electrode film 215 is formed on the first wafer main surface 203. The second base electrode film 215 fills the multiple gate trenches 53 with the upper insulating film 54 and intermediate insulating film 58 sandwiched therebetween, and covers the first wafer main surface 203 with the first to third field insulating films 80, 120, and 170 and the first to third main surface insulating films 83, 133, and 183 sandwiched therebetween. The second base electrode film 215 serves as the base for the upper electrode 56, the first gate electrode 134, and the second gate electrode 184. In this embodiment, the second base insulating film 211 is made of conductive polysilicon. The second base electrode film 215 may be formed by a CVD method.

[0326] 22L and 23L, a third resist mask 216 having a predetermined pattern is formed on the second base electrode film 215. The third resist mask 216 covers the regions where the first gate electrode 134 and the second gate electrode 184 are to be formed, and leaves the other regions exposed. Next, unnecessary portions of the second base electrode film 215 are removed by etching through the third resist mask 216 until the first to third field insulating films 80, 120, and 170 and the first to third main surface insulating films 83, 133, and 183 are exposed. The etching method may be wet etching and / or dry etching. As a result, the upper electrode 56, the first gate electrode 134, and the second gate electrode 184 are formed.

[0327] The first to third field insulating films 80, 120, and 170 have relatively gentle first to third insulating sidewalls 80a, 120a, and 170a, respectively. Therefore, in this process, residues (remaining materials) of the second base electrode film 215 are prevented from remaining attached to the first to third insulating sidewalls 80a, 120a, and 170a. This reduces variations in electrical characteristics due to the residues. Furthermore, after the process of removing the second base electrode film 215, the process of removing the residues of the second base electrode film 215 can be omitted. This means that the over-etching process of the second base electrode film 215 can be omitted. This reduces thinning of the first to third field insulating films 80, 120, and 170 and the first to third main surface insulating films 83, 133, and 183.

[0328] 22M and 23M, a fourth base insulating film 217 is formed on the first wafer main surface 203. The fourth base insulating film 217 serves as a base for the first and second sidewall structures 136, 186. In this embodiment, the fourth base insulating film 217 is made of a silicon nitride film. The fourth base insulating film 217 may be formed by a CVD method.

[0329] 22N and 23N, unnecessary portions of the fourth base insulating film 217 are removed by etching. The fourth base insulating film 217 is removed so that portions of the fourth base insulating film 217 remain on the side walls of the first and second gate electrodes 134, 184. The etching method may be wet etching and / or dry etching. The etching method is preferably anisotropic dry etching. As a result, the first and second sidewall structures 136, 186 are formed in a self-aligned manner with the first and second gate electrodes 134, 184.

[0330] The first and second gate electrodes 134 and 184 have sidewalls with steeper inclination angles than the first to third insulating sidewalls 80a, 120a, and 170a of the first to third field insulating films 80, 120, and 170. Therefore, in this step, while part of the fourth base insulating film 217 remains attached to the sidewalls of the first and second gate electrodes 134 and 184, part of the fourth base insulating film 217 is prevented from remaining attached to the first to third insulating sidewalls 80a, 120a, and 170a.

[0331] Therefore, after the step of removing the fourth base insulating film 217, it is possible to omit the step of removing residues of the fourth base insulating film 217. In other words, it is possible to omit the step of overetching the fourth base insulating film 217. This makes it possible to form the first and second sidewall structures 136 and 186 while suppressing thinning of the first to third field insulating films 80, 120, and 170 and the first to third main surface insulating films 83, 133, and 183, etc.

[0332] 22O and 23O, in the first device region 6, the body region 47, the source region 60, and the contact region 61 are formed in the surface layer portion of the first wafer main surface 203. The body region 47, the source region 60, and the contact region 61 are each formed in the surface layer portion of the first wafer main surface 203 via the sidewall of the gate trench 53. The steps of forming the body region 47, the source region 60, and the contact region 61 may be performed in any order. The body region 47 is formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown).

[0333] The source region 60 is formed by introducing n-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The source region 60 is formed so as to be located in a surface layer portion of the body region 47. The contact region 61 is formed in a surface layer portion of the first wafer main surface 203. The contact region 61 is formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The contact region 61 is formed so as to be located in a surface layer portion of the body region 47.

[0334] In the first MIS region 103 of the second device region 7, the first drain region 108, the first source region 109, and the first contact region 111 are formed in a surface layer portion of the first wafer main surface 203. The first drain region 108, the first source region 109, and the first contact region 111 are each formed in a surface layer portion of the first wafer main surface 203 with a second main surface insulating film 133 interposed therebetween. The steps of forming the first drain region 108, the first source region 109, and the first contact region 111 may be performed in any order. In this embodiment, the first drain region 108 and the first source region 109 are formed simultaneously.

[0335] The first drain region 108 and the first source region 109 are formed by introducing n-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The first drain region 108 is formed to be located in a surface layer portion of the first drift region 107. The first source region 109 is formed to be located in a surface layer portion of the first well region 105. The first contact region 111 is formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The first contact region 111 is formed in a surface layer portion of the first well region 105.

[0336] Furthermore, in the second MIS region 153 of the second device region 7, a second drain region 158, a second source region 159, and a second contact region 161 are formed in a surface layer portion of the first wafer main surface 203. The second drain region 158, the second source region 159, and the second contact region 161 are each formed in a surface layer portion of the first wafer main surface 203 with a third main surface insulating film 183 interposed therebetween. The steps of forming the second drain region 158, the second source region 159, and the second contact region 161 may be performed in any order. In this embodiment, the second drain region 158 and the second source region 159 are formed simultaneously.

[0337] The second drain region 158 and the second source region 159 are formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The second drain region 158 is formed to be located in a surface layer portion of the second drift region 157. The second source region 159 is formed to be located in a surface layer portion of the third well region 156. The second contact region 161 is formed by introducing p-type impurities into the first wafer main surface 203 by ion implantation using an ion implantation mask (not shown). The second contact region 161 is formed in a surface layer portion of the second well region 155.

[0338] In these steps, n-type impurities and p-type impurities can be introduced into the first wafer main surface 203 in a structure in which adhesion of residues to the first to third insulating sidewalls 80a, 120a, 170a of the first to third field insulating films 80, 120, 170 is suppressed. Therefore, it is possible to suppress the introduction of n-type impurities and p-type impurities from being hindered by residues. This allows the n-type impurities and p-type impurities to be appropriately introduced into the first wafer main surface 203.

[0339] 22P and 23P, a bottom insulating film 218 is formed on the first wafer main surface 203. The bottom insulating film 218 forms the bottom layer of the interlayer insulating layer 13. The bottom insulating film 218 may include at least one of a silicon oxide film and a silicon nitride film. The bottom insulating film 218 may be formed by a CVD method.

[0340] 22Q and 23Q, fourth resist mask 219 having a predetermined pattern is formed on lowermost insulating film 218. Fourth resist mask 219 exposes regions in lowermost insulating film 218 where a plurality of plug openings 220 for a plurality of plug electrodes 91-95, 141-145, 191-195 are to be formed, and covers the other regions.

[0341] Next, unnecessary portions of the bottom insulating film 218 are removed by etching. The etching may be wet etching and / or dry etching. Preferably, the etching is anisotropic dry etching. This forms a plurality of plug openings 220 in the bottom insulating film 218. The fourth resist mask 219 is then removed.

[0342] 22R and 23R, a fourth base electrode film 221 is formed on the bottom insulating film 218. The fourth base electrode film 221 fills the plug openings 220 and covers the bottom insulating film 218. The fourth base electrode film 221 may have a layered structure including a titanium-based metal film and a tungsten film. The fourth base electrode film 221 may be formed by sputtering and / or CVD.

[0343] 22S and 23S, unnecessary portions of the fourth base electrode film 221 are removed by etching. The fourth base electrode film 221 is removed until the bottom insulating film 218 is exposed. The etching may be wet etching and / or dry etching. As a result, the plurality of plug electrodes 91-95, 141-145, and 191-195 are embedded in the bottom insulating film 218.

[0344] Next, referring to FIGS. 22T and 23T, a fifth base electrode film 222 is formed on the bottom insulating film 218. The fifth base electrode film 222 serves as a base for a wiring layer that forms part of the multilayer wiring. In this embodiment, the fifth base electrode film 222 serves as a base for the gate wiring 14, the source wiring 96, the first drain wiring 146, the first source wiring 147, the first gate wiring 148, the second drain wiring 196, the second source wiring 197, and the second gate wiring 198. The fifth base electrode film 222 may include at least one of an Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. The fifth base electrode film 222 may be formed by sputtering and / or CVD.

[0345] 22U and 23U, unnecessary portions of the fifth base electrode film 222 are removed by etching using a resist mask (not shown). The unnecessary portions of the fifth base electrode film 222 are removed until the bottom insulating film 218 is exposed. The etching may be wet etching and / or dry etching. As a result, the gate wiring 14, the source wiring 96, the first drain wiring 146, the first source wiring 147, the first gate wiring 148, the second drain wiring 196, the second source wiring 197, and the second gate wiring 198 are formed.

[0346] Next, the remaining portion of the interlayer insulating layer 13 is formed on the lowermost insulating film 218. The remaining portion of the interlayer insulating layer 13 may include at least one of a silicon oxide film and a silicon nitride film. Like the lowermost insulating film 218, the remaining portion of the interlayer insulating layer 13 may be formed by a CVD method. During the process of forming the remaining portion of the interlayer insulating layer 13, a wiring layer that forms part of the multilayer wiring may be formed through a process similar to that for the fifth base electrode film 222.

[0347] Next, a sixth base electrode film (not shown) is formed on the interlayer insulating layer 13. The sixth base electrode film serves as a base for the plurality of terminal electrodes 16-20. The sixth base electrode film may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. The sixth base electrode film may be formed by a sputtering method and / or a CVD method. Next, unnecessary portions of the sixth base electrode film are removed by an etching method using a resist mask (not shown). This forms the plurality of terminal electrodes 16-20.

[0348] Next, the drain terminal 15 is formed on the second wafer main surface 204. The drain terminal 15 covers the entire area of ​​the second wafer main surface 204. The drain terminal 15 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain terminal 15 may be formed by a sputtering method, a vapor deposition method, and / or a plating method. Prior to the step of forming the drain terminal 15, a thinning step of the semiconductor wafer 201 may be performed. In this case, the semiconductor wafer 201 may be thinned by grinding the second wafer main surface 204. The second wafer main surface 204 may be ground by a CMP (Chemical Mechanical Polishing) method.

[0349] Thereafter, the semiconductor wafer 201 is cut along the plurality of device formation regions 205. As a result, a plurality of semiconductor devices 1 are cut out from one semiconductor wafer 201. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0350] As described above, the semiconductor device 1 includes the semiconductor chip 2 and n (n≧2) systems of power transistors 8. The n systems of power transistors 8 include n (n≧2) systems of transistors 9 formed on the semiconductor chip 2 so as to be individually controllable, and a single output current IOUT (output signal) is generated by selectively controlling the n systems of transistors 9.

[0351] Specifically, the n-system power transistors 8 are configured by a parallel circuit of n-system transistors 9 connected in parallel so that n gate signals G are individually input. The n-system transistors 9 generate electrical signals for each system in response to the gate signals G. The n-system power transistors 8 generate a single output current IOUT consisting of the sum of the n electrical signals generated by the n-system transistors 9.

[0352] The channel utilization rate and on-resistance Ron of the n-system power transistors 8 are changed by selectively controlling the n-system transistors 9. This allows the power transistors 8 to be controlled in a plurality of operation modes each having a different on-resistance Ron. This makes it possible to provide a variable on-resistance semiconductor device 1. With this semiconductor device 1, the power transistors 8 can be driven and controlled with an appropriate on-resistance Ron according to the operating conditions.

[0353] The power transistor 8 may be controlled in at least two operation modes by selectively controlling at least two system transistors 9. It is preferable that the power transistor 8 is controlled in at least three operation modes by selectively controlling at least three system transistors 9.

[0354] The semiconductor device 1 includes a first device region 6 defined in a semiconductor chip 2. The power transistor 8 has n system transistors 9 formed in a concentrated manner in the first device region 6. This structure eliminates the need to dispose the n system transistors 9 discretely on the semiconductor chip 2, thereby reducing the wiring distance and reducing wiring resistance. This makes it possible to suppress variations in the switching speeds of the n system transistors 9, thereby enabling the power transistor 8 to be appropriately driven and controlled.

[0355] Each of the n system transistors 9 preferably includes one or more unit transistors 10 that are systemized as targets for individual control. With this structure, the channel utilization rate and on-resistance characteristics can be adjusted for each system transistor 9 by adjusting the number of unit transistors 10 and the channel ratio RC. This allows the on-resistance characteristics of the power transistor 8 to be appropriately adjusted.

[0356] Each unit transistor 10 may have a trench gate structure 51. The trench gate structure 51 may have a multi-electrode structure including an upper electrode 56 and a lower electrode 57 buried in a gate trench 53 so as to be vertically isolated by insulators (an upper insulating film 54, a lower insulating film 55, and an intermediate insulating film 58). In this structure, the lower electrode 57 is preferably fixed at the same potential as the upper electrode 56.

[0357] This structure can suppress the voltage drop between the upper electrode 56 and the lower electrode 57, thereby suppressing electric field concentration between the upper electrode 56 and the lower electrode 57. It also reduces the on-resistance Ron of the semiconductor chip 2 (particularly the second semiconductor region 42). This structure is effective when the semiconductor device 1 is provided as an in-vehicle device.

[0358] The semiconductor device 1 includes a second device region 7 that is partitioned in a region different from the first device region 6 in the semiconductor chip 2, and a control IC 11 formed in the second device region 7. The semiconductor device 1 also includes n gate wirings 14 formed on the semiconductor chip 2 so as to be electrically connected to the power transistor 8 and the control IC 11.

[0359] The control IC 11 generates n gate signals G that individually control the n system transistors 9, and outputs them to n gate wirings 14. The n gate wirings 14 individually transmit the n gate signals G generated by the control IC 11 to the n system transistors 9. This structure makes it possible to provide a semiconductor device 1 having an IPD that integrally includes the power transistors 8 and the control IC 11.

[0360] The semiconductor device 1 includes a semiconductor chip 2 and a first field insulating film 80. The first field insulating film 80 partially covers the first main surface 3 of the semiconductor chip 2 and has a first insulating sidewall 80a having a first inclination angle θ1 formed between the first main surface 3 and the first insulating sidewall 80a that is equal to or greater than 20° and equal to or less than 40°. This structure can prevent residue from adhering to and remaining on the first insulating sidewall 80a.

[0361] Furthermore, with the first insulating sidewall 80a having the relatively gentle first inclination angle θ1, for example, the step of removing residues can be omitted or the time required for the step of removing residues can be shortened. Therefore, thinning of structures other than the residues (e.g., the first field insulating film 80) caused by the step of removing residues can be suppressed. Therefore, a decrease in the reliability of the semiconductor device 1 caused by the residues can be suppressed.

[0362] The first tilt angle θ1 is preferably less than 40° (θ1<40°). It is particularly preferable that the first tilt angle θ1 be within the range of 30°±6° (24°≦θ1≦36°). The first tilt angle θ1 is typically within the range of 28° to 36° (28°≦θ1≦36°). The first field insulating film 80 is preferably made of an oxide of the semiconductor chip 2.

[0363] The semiconductor device 1 includes a first hidden surface 81 formed in a portion of the first main surface 3 that is covered with the first field insulating film 80. In this case, the semiconductor device 1 may include a first exposed surface 82 formed in a portion of the first main surface 3 that is exposed from the first field insulating film 80 and that is recessed from the first hidden surface 81 in the thickness direction of the semiconductor chip 2.

[0364] The semiconductor device 1 may include a first main surface insulating film 83 that covers the first exposed surface 82. In this case, the first main surface insulating film 83 may have a first insulating thickness TMI1 (TMI1 < TF1) that is less than the first field thickness TF1 of the first field insulating film 80. According to this structure, thinning of the first main surface insulating film 83 having the relatively thin first insulating thickness TMI1 due to the residue removal process can be suppressed. In this case, it is preferable that the first main surface insulating film 83 is continuous with the first insulating sidewall 80a of the first field insulating film 80.

[0365] The first main surface insulating film 83 may include a first region 83a located on the semiconductor chip 2 side with respect to the first hidden surface 81, and a second region 83b located on the side opposite to the semiconductor chip 2 (the main surface side of the first field insulating film 80) with respect to the first hidden surface 81. The first main surface insulating film 83 may be formed at an interval from the middle portion in the thickness direction of the first field insulating film 80 toward the semiconductor chip 2 side. The first main surface insulating film 83 may have a thickness that is 1 / 5 or less of the thickness of the first field insulating film 80.

[0366] The first main surface insulating film 83 may further include a first trench isolation structure 43 that partitions the first device region 6 on the first main surface 3. The first trench isolation structure 43 may include a separation trench 44 formed on the first main surface 3, a separation insulating film 45 that covers the inner wall of the separation trench 44, and a separation electrode 46 embedded in the separation trench 44 with the separation insulating film 45 interposed therebetween.

[0367] In this case, it is preferable that the first field insulating film 80 covers the first main surface 3 in the first device region 6. According to this structure, the reliability of the first field insulating film 80 can be improved, so that the reliability of the functional device (the power transistor 8 in this form) formed in the first device region 6 can be improved.

[0368] In this case, the first field insulating film 80 is preferably continuous with the isolation insulating film 45. The isolation insulating film 45 may include a first portion 45a covering the sidewall of the isolation trench 44 and a second portion 45b covering the bottom wall of the isolation trench 44. The first portion 45a has a first isolation thickness TI1, and the second portion 45b has a second isolation thickness TI2. The first field insulating film 80 preferably has a first field thickness TF1 that exceeds the second isolation thickness TI2. The second isolation thickness TI2 is preferably less than the first isolation thickness TI1.

[0369] The semiconductor device 1 may include a functional device formed on the first main surface 3 in the first device region 6. In this case, the first field insulating film 80 preferably partially covers the first main surface 3 at a distance from the functional device in the first device region 6. In this case, the reliability of the first field insulating film 80 can be improved, and therefore the reliability of the functional device (in this embodiment, the power transistor 8) formed in the first device region 6 can be improved.

[0370] In this case, it is preferable that the first trench isolation structure 43 defines the first device region 6 within the semiconductor chip 2, and the first field insulating film 80 defines the first device region 6 on the semiconductor chip 2. The first field insulating film 80 may be continuous with the isolation insulating film 45.

[0371] The functional device may include a trench gate structure 51 having a multi-electrode structure including a gate trench 53 formed in the first main surface 3, and an upper electrode 56 and a lower electrode 57 buried in the gate trench 53 so as to be insulated and separated in the vertical direction by insulators (an upper insulating film 54, a lower insulating film 55, and an intermediate insulating film 58). In this case, the first field insulating film 80 is preferably formed at a distance from the trench gate structure 51.

[0372] The functional device may include a plurality of unit transistors 10, each having a trench gate structure 51. In this case, the functional device may include n (n≧2) system transistors 9, each made up of one or more unit transistors 10 systemized as individually controlled objects, and may include n power transistors 8 (gate-split transistors) that generate a single output current IOUT by selectively controlling the n system transistors 9. This structure can improve the reliability of the first field insulating film 80, and therefore the reliability of the n power transistors 8.

[0373] The semiconductor device 1 may include a gate control circuit 12 that individually controls the n system transistors 9. The gate control circuit 12 is preferably formed in a region of the first main surface 3 that is different from the first device region 6.

[0374] The semiconductor device 1 includes a semiconductor chip 2 and second, third, and fourth field insulating films 120, 170. The second, third, and fourth field insulating films 120, 170 partially cover the first main surface 3 of the semiconductor chip 2 and have second, third, and fourth insulating sidewalls 120a, 170a whose second, third, and fourth inclination angles θ2, θ3 formed with the first main surface 3 are between 20° and 40°. This structure makes it possible to prevent residue from adhering to the second, third, and fourth insulating sidewalls 120a, 170a.

[0375] Furthermore, the second to third insulating sidewalls 120a, 170a having the relatively gentle second to third inclination angles θ2, θ3 can, for example, omit the step of removing residues or shorten the time required for the step of removing residues. Therefore, it is possible to prevent thinning of structures other than the residues (e.g., the second to third field insulating films 120, 170) caused by the step of removing residues. Therefore, it is possible to prevent a decrease in the reliability of the semiconductor device 1 caused by the residues.

[0376] The second to third inclination angles θ2, θ3 are preferably less than 40° (θ1 < 40°). The second to third inclination angles θ2, θ3 particularly preferably fall within the range of 30° ± 6° (24° ≤ θ1 ≤ 36°). The second to third inclination angles θ2, θ3 typically fall within the range of 28° or more and 36° or less (28° ≤ θ1 ≤ 36°). The second to third field insulating films 120, 170 are preferably made of an oxide of the semiconductor chip 2.

[0377] The semiconductor device 1 includes second to third hidden surfaces 131, 181 formed on portions covered with the second to third field insulating films 120, 170 on the first main surface 3. In this case, the semiconductor device 1 may further include second to third exposed surfaces 132, 182 that are recessed in the thickness direction of the semiconductor chip 2 from the second to third hidden surfaces 131, 181 on portions exposed from the second to third field insulating films 120, 170 on the first main surface 3.

[0378] The semiconductor device 1 may include second to third main surface insulating films 133, 183 that cover the second to third exposed surfaces 132, 182. In this case, the second to third main surface insulating films 133, 183 may have second to third insulating thicknesses TMI2, TMI3 (TMI2, TMI3 < TF2, TF3) that are less than the second to third field thicknesses TF2, TF3 of the second to third field insulating films 120, 170. According to this structure, thinning of the second to third main surface insulating films 133, 183 having the relatively thin second to third insulating thicknesses TMI2, TMI3 due to the residue removal process can be suppressed. In this case, the second to third main surface insulating films 133, 183 are preferably continuous with the second to third insulating side walls 120a, 170a of the second to third field insulating films 120, 170.

[0379] The second to third main surface insulating films 133, 183 may include first regions 133a, 183a located on the semiconductor chip 2 side with respect to the second to third hidden surfaces 131, 181, and second regions 133b, 183b located on the opposite side to the semiconductor chip 2 (on the main surface side of the second to third field insulating films 120, 170) with respect to the second to third hidden surfaces 131, 181. The second to third main surface insulating films 133, 183 may be formed at intervals from the middle of the second to third field insulating films 120, 170 in the thickness direction toward the semiconductor chip 2. The second to third main surface insulating films 133, 183 may have a thickness that is one-fifth or less of the second to third field insulating films 120, 170.

[0380] The second and third main surface insulating films 133 and 183 may further include second and third trench isolation structures 104 and 154 that define a CMIS region 100 (first and second MIS regions 103 and 153) as an example of a device region on the first main surface 3. The second and third trench isolation structures 104 and 154 may include an isolation trench 44 (second and third isolation trench) formed on the first main surface 3, an isolation insulating film 45 (second and third isolation insulating films) that covers the inner wall of the isolation trench 44, and an isolation electrode 46 (second and third isolation electrodes) that is embedded in the isolation trench 44 with the isolation insulating film 45 sandwiched therebetween.

[0381] In this case, the second and third field insulating films 120 and 170 preferably cover the first main surface 3 in the first and second MIS regions 103 and 153. This structure can improve the reliability of the second and third field insulating films 120 and 170, thereby improving the reliability of the functional device (in this embodiment, the CMIS 100a including the n-type first MISFET 101 and the p-type second MISFET 102) formed in the first and second MIS regions 103 and 153.

[0382] In this case, it is preferable that the second to third field insulating films 120 and 170 are continuous with the isolation insulating film 45. The isolation insulating film 45 may include a first portion 45a that covers the side wall of the isolation trench 44 and a second portion 45b that covers the bottom wall of the isolation trench 44. The first portion 45a has a first isolation thickness TI1, and the second portion 45b has a second isolation thickness TI2. It is preferable that the second to third field insulating films 120 and 170 have second to third field thicknesses TF2 and TF3 (TI2 < TF2, TF3) that exceed the second isolation thickness TI2. It is preferable that the second isolation thickness TI2 is less than the first isolation thickness TI1.

[0383] The semiconductor device 1 may further include first to second gate electrodes 134 and 184 that cover the second to third main surface insulating films 133 and 183. According to this structure, adhesion of residues to the second to third insulating side walls 120a and 170a can be suppressed, so that a decrease in the reliability of the first to second gate electrodes 134 and 184 due to residues can be suppressed. For example, the film forming property of the first to second gate electrodes 134 and 184 and fluctuations in the gate threshold voltage due to residues can be suppressed.

[0384] The first to second gate electrodes 134 and 184 may have first to second lead-out portions 135 and 185 that are drawn out from above the second to third main surface insulating films 133 and 183, pass through the second to third insulating side walls 120a and 170a, and are on the second to third field insulating films 120 and 170. According to this structure, in a structure having the first to second lead-out portions 135 and 185, a decrease in the reliability of the first to second gate electrodes 134 and 184 due to residues can be suppressed.

[0385] The present invention can be implemented in other forms.

[0386] As in the above-described embodiment, the first to third field insulating films 80, 120, 170 having the relatively gentle first to third insulating sidewalls 80 a, 120 a, 170 a are applied to various functional devices. For example, in a semiconductor device including a LOCOS film, the LOCOS film can be replaced with the first to third field insulating films 80, 120, 170 having the relatively gentle first to third insulating sidewalls 80 a, 120 a, 170 a.

[0387] In the above-described embodiment, a configuration may be adopted in which the power transistor 8 is not provided. In other words, the above-described semiconductor device 1 may include only the control IC 11. In the above-described embodiment, a configuration may be adopted in which the control IC 11 is not provided. In other words, the above-described semiconductor device 1 may include only the power transistor 8. Of course, a semiconductor device 1 including only the CMIS region 100 may be used.

[0388] In the above-described embodiment, the lower electrode 57 of the trench gate structure 51 and the contact electrode 74 of the trench contact structure 71 are formed as gate electrodes. However, the lower electrode 57 and the contact electrode 74 may be formed as source electrodes. That is, the lower electrode 57 and the contact electrode 74 may be formed as field electrodes. In this case, the source wiring 96 is electrically connected to the contact electrode 74 instead of the gate wiring 14. This structure can reduce the parasitic capacitance between the trench gate structure 51 and the semiconductor chip 2 (specifically, the second semiconductor region 42), thereby improving the switching speed.

[0389] In the above embodiment, an example has been described in which the control IC 11 includes a sense transistor 21. The sense transistor 21 preferably has a structure similar to that of the power transistor 8, in view of its function of monitoring the current flowing through the power transistor 8. In other words, the sense transistor 21 preferably includes one or more unit transistors 10 (unit cells 50).

[0390] The sense transistor 21 may be formed in the second device region 7 or may be formed in the first device region 6. When the sense transistor 21 is formed in the first device region 6, one or a plurality of unit transistors 10 (unit cells 50) among the plurality of unit transistors 10 may be used as the sense transistor 21. In this case, the power transistor 8 is constituted by the unit transistors 10 (unit cells 50) excluding the unit transistor 10 (unit cell 50) that functions as the sense transistor 21.

[0391] In the foregoing embodiment, an example in which the semiconductor device 1 includes a p-type second well region 155, an n-type third well region 156, and a p-type second contact region 161 in the second MIS region 153 has been described. However, the semiconductor device 1 does not necessarily have to include the p-type second well region 155 and the n-type third well region 156 in the second MIS region 153. In this case, an n-type contact region 161 may be employed instead of the p-type contact region 161. The n-type contact region 161 preferably has an n-type impurity concentration exceeding the n-type impurity concentration of the second semiconductor region 42.

[0392] In the foregoing embodiment, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been described, but the first conductivity type may be p-type and the second conductivity type may be n-type. The specific configuration in this case can be obtained by replacing the n-type regions with p-type regions and replacing the p-type regions with n-type regions in the foregoing description and the accompanying drawings.

[0393] In the foregoing embodiment, it has been described that it is preferable that the first depth D1 of the trench gate structure 51 is less than the separation depth DI of the first trench isolation structure 43 (D1 < DI). This specific structure is shown in FIG. 24. FIG. 24 corresponds to FIG. 12 and is a cross-sectional view showing a modified example of the first trench isolation structure 51. Specific descriptions of the structures corresponding to the structures described in the foregoing embodiment in FIG. 24 are omitted.

[0394] Referring to FIG. 24, the first trench isolation structure 43 has a separation depth DI (D1 < DI) that exceeds the first depth D1 of the trench gate structure 51. The first trench isolation structure 43 has a separation width WI (W1 < WI) that exceeds the first width W1 of the trench gate structure 51. Therefore, the total amount of etchant that enters the isolation trench 44 in the processes of FIGS. 22B and 23B described above is greater than the total amount of etchant that enters the gate trench 53 (contact trench 72). As a result, the first trench isolation structure 43 (isolation trench 44) is formed deeper than the trench gate structure 51 (gate trench 53). According to such a structure, the first trench isolation structure 43 can appropriately partition the first device region 6 from other regions.

[0395] Such a structure is not limited to the first trench isolation structure 43 and can also be applied to the second trench isolation structure 104 and the third trench isolation structure 154. That is, the second trench isolation structure 104 and the third trench isolation structure 154 may each have a separation depth DI (D1 < DI) that exceeds the first depth D1 of the trench gate structure 51. In this case, the second trench isolation structure 104 and the third trench isolation structure 154 may have a separation depth DI that is approximately equal to that of the first trench isolation structure 51.

[0396] Also, the second trench isolation structure 104 and the third trench isolation structure 154 may each have a separation width WI (W1 < WI) that exceeds the first width W1 of the trench gate structure 51. In this case, the second trench isolation structure 104 and the third trench isolation structure 154 may have a separation width WI that is approximately equal to that of the first trench isolation structure 51. According to such a structure, the second trench isolation structure 104 can appropriately partition the first MIS region 101 from other regions, and the third trench isolation structure 154 can appropriately partition the second MIS region 153 from other regions.

[0397] Examples of features extracted from this specification and the drawings are shown below.

[0398] When the inclination angle of the insulating sidewall is relatively steep (for example, when the inclination angle exceeds 45°), residues remain attached to the insulating sidewall during the manufacturing process of the semiconductor device. When residues adhere to the insulating sidewall, the residues can cause fluctuations in electrical characteristics or deterioration in film formability.

[0399] Such residues are removed by performing an over-etching process on the film-formed material that may leave the residues or an etching process on the residues. The over-etching process refers to a process in which the film-formed material is etched for an amount of time exceeding the amount of etching (etching time) required to remove the film-formed material.

[0400] In the residue removal process, structures other than the residue are also exposed to the chemical solution, so that small amounts of structures other than the residue are also removed. For example, if the field insulating film is thinned due to the residue removal process, the reliability of the field insulating film decreases. As a result, the reliability of the semiconductor device decreases. [A1] to [A20] below provide a semiconductor device that can improve reliability. [B1] to [B15] below provide a method for manufacturing a semiconductor device that can improve reliability.

[0401] [A1] A semiconductor device (1) comprising: a semiconductor chip (2) having a main surface (3); and a field insulating film (80, 120, 170) partially covering the main surface (3) and having insulating sidewalls (80a, 120a, 170a) whose inclination angles (θ1, θ2, θ3) between the main surface (3) are 20° or more and 40° or less.

[0402] This semiconductor device has a structure that suppresses residues from remaining attached to the insulating sidewalls. Furthermore, the relatively gentle insulating sidewalls allow, for example, the step of removing the residues to be omitted or the time required for the step of removing the residues to be shortened. Therefore, thinning of structures other than the residues (e.g., field insulating films) caused by the step of removing the residues can be suppressed. Therefore, a decrease in the reliability of the semiconductor device can be suppressed.

[0403] [A2] The semiconductor device (1) according to A1, further comprising: a hidden surface (81, 131, 181) formed in a portion of the main surface (3) covered with the field insulating film (80, 120, 170); and an exposed surface (82, 132, 182) formed in a portion of the main surface (3) exposed from the field insulating film (80, 120, 170) and recessed from the hidden surface (81, 131, 181) in the thickness direction of the semiconductor chip (2).

[0404] [A3] The semiconductor device (1) according to A2, further comprising a main surface insulating film (83, 133, 183) having a thickness (TMI1, TMI2, TMI3) less than the thickness (TF1, TF2, TF3) of the field insulating film (80, 120, 170) and covering the exposed surface (82, 132, 182).

[0405] [A4] The semiconductor device (1) according to A3, wherein the main surface insulating film (83, 133, 183) is continuous with the insulating sidewall (80a, 120a, 170a) of the field insulating film (80, 120, 170).

[0406] [A5] The semiconductor device (1) according to A3 or A4, wherein the main surface insulating film (83, 133, 183) includes a first region (83a, 133a, 183a) located on the semiconductor chip (2) side relative to the hidden surface (81, 131, 181), and a second region (83b, 133b, 183b) located on the upper end side of the field insulating film (80, 120, 170) relative to the hidden surface (81, 131, 181).

[0407] [A6] The semiconductor device (1) according to any one of A3 to A5, wherein the main surface insulating film (83, 133, 183) is formed at an interval from the middle of the thickness direction of the field insulating film (80, 120, 170) toward the semiconductor chip (2).

[0408] [A7] The semiconductor device (1) according to any one of A3 to A6, wherein the main surface insulating film (83, 133, 183) has a thickness equal to or less than one-fifth of the thickness of the field insulating film (80, 120, 170).

[0409] [A8] The semiconductor device (1) according to any one of A3 to A7, further comprising a main surface electrode (134, 184) covering the main surface insulating film (133, 183).

[0410] [A9] The semiconductor device (1) according to A8, wherein the main surface electrode (134, 184) is extended from above the main surface insulating film (133, 183) through the insulating sidewall (120a, 170a) onto the field insulating film (120, 170).

[0411] [A10] The semiconductor device (1) according to any one of A1 to A9, further comprising a trench isolation structure (43) that defines a device region (6, 7, 100, 103, 153) on the main surface (3), including an isolation trench (44) formed in the main surface (3), an isolation insulating film (45) covering the inner wall of the isolation trench (44), and an isolation electrode (46) embedded in the isolation trench (44) across the isolation insulating film (45), and the field insulating film (80, 120, 170) covers the main surface (3) in the device region (6, 7, 100, 103, 153).

[0412] [A11] The semiconductor device (1) according to A10, wherein the field insulating film (80, 120, 170) is continuous with the isolation insulating film (45).

[0413] [A12] The semiconductor device (1) according to A10 or A11, wherein the isolation insulating film (45) includes a first portion (45a) covering the sidewall of the isolation trench (44) and a second portion (45b) covering the bottom wall of the isolation trench (44), and the field insulating film (80, 120, 170) has a thickness (TF1, TF2, TF3) that exceeds a thickness (TI2) of the second portion (45b).

[0414] [A13] The semiconductor device (1) according to any one of A1 to A12, wherein the field insulating film (80, 120, 170) has a first side extending in one direction (X) in a planar view and a second side extending in an intersecting direction (Y) intersecting the one direction (X), and the insulating sidewalls (80a, 120a, 170a) are formed on the first side and the second side of the field insulating film (80, 120, 170).

[0415] [A14] The semiconductor device (1) according to any one of A1 to A13, wherein the field insulating film (80, 120, 170) is made of an oxide of the semiconductor chip (2).

[0416] [A15] A semiconductor device (1) comprising: a semiconductor chip (2) having a main surface (3); a trench isolation structure (43) including an isolation trench (44) formed in the main surface (3), an isolation insulating film (45) covering the inner wall of the isolation trench (44), and an isolation electrode (46) embedded in the isolation trench (44) with the isolation insulating film (45) sandwiched therebetween, the trench isolation structure (43) defining a device region (6) on the main surface (3); a functional device (8) formed on the main surface (3) in the device region (6); and a field insulating film (80) partially covering the main surface (3) at a distance from the functional device (8) in the device region (6), the field insulating film (80) having insulating sidewalls (80a) with an inclination angle (θ1) formed with respect to the main surface (3) of 20° or more and 40° or less.

[0417] This semiconductor device has a structure that suppresses residues from remaining attached to the insulating sidewalls. Furthermore, the relatively gentle insulating sidewalls allow, for example, the step of removing the residues to be omitted or the time required for the step of removing the residues to be shortened. Therefore, thinning of structures other than the residues (e.g., the field insulating film) caused by the step of removing the residues can be suppressed. Furthermore, the reliability of the field insulating film can be improved, thereby improving the reliability of the functional devices formed in the device region. Therefore, a decrease in the reliability of the semiconductor device can be suppressed.

[0418] [A16] The semiconductor device (1) according to A15, wherein the field insulating film (80, 120, 170) is continuous with the isolation insulating film (45).

[0419] [A17] The semiconductor device (1) described in A15 or A16, wherein the functional device (8) includes a trench gate structure (51) having a gate trench (53) formed in the main surface (3), an upper electrode (56) and a lower electrode (57) buried in the gate trench (53) so as to be vertically insulated and separated by insulators (54, 55, 58), and the field insulating film (80) is formed at a distance from the trench gate structure (51).

[0420] [A18] The semiconductor device according to A17, wherein the functional device (8) includes a plurality of unit transistors (10) each having a plurality of the trench gate structures (51).

[0421] [A19] The semiconductor device (1) described in A18, wherein the functional device (8) includes n (n≧2) system transistors (9) each composed of one or more unit transistors (10) systemized as individual control objects, and includes n systems of gate-divided transistors (8) that generate a single output signal by selectively controlling the n system transistors (9).

[0422] [A20] The semiconductor device (1) according to A19, further comprising a control circuit (11) formed in a region of the main surface (3) different from the device region (6) and configured to individually control the n system transistors (9).

[0423] [B1] A method for manufacturing a semiconductor wafer (201) having a main surface (203), a step of forming a first insulating film (208) having a first etching rate and covering the main surface (203), a step of forming a second insulating film (211) having a second etching rate higher than the first etching rate and covering the first insulating film (208), a step of forming a laminated insulating film (212) having a laminated structure including the first insulating film (208) and the second insulating film (211), and a step of forming a mask (21) partially covering the laminated insulating film (212). and partially removing the stacked insulating film (212) by etching using the mask (213) to form a field insulating film (80, 120, 170) that partially covers the main surface (203), has insulating side walls (80a, 120a, 170a) on the main surface (203), and has an inclination angle (θ1, θ2, θ3) between the main surface (203) and the insulating side walls (80a, 120a, 170a) that is 20° or more and 40° or less.

[0424] [B2] A method for manufacturing a semiconductor device (1) according to B1, wherein the first insulating film (208) has a first thickness, and the second insulating film (211) has a second thickness that is less than the first thickness.

[0425] [B3] The method for manufacturing a semiconductor device (1) according to B1 or B2, wherein the first insulating film (208) is made of an oxide film formed by an oxidation treatment method, and the second insulating film (211) is made of an oxide film formed by a CVD method.

[0426] [B4] The method for manufacturing the semiconductor device (1) according to B3, further comprising the step of baking the second insulating film (211) before the step of forming the mask (213).

[0427] [B5] A method for producing a semiconductor device (1) according to any one of B1 to B4, wherein the second insulating film (211) is partially removed by wet etching.

[0428] [B6] A method for producing a semiconductor device (1) according to any one of B1 to B5, wherein the first insulating film (208) is partially removed by wet etching.

[0429] [B7] The method for manufacturing a semiconductor device (1) according to any one of B1 to B6, wherein the step of removing the first insulating film (208) is carried out under the same conditions as the step of removing the second insulating film (211).

[0430] [B8] The method for manufacturing a semiconductor device (1) according to any one of B1 to B7, further comprising the step of forming trenches (207, 44, 53, 72) in the main surface (203) before the step of forming the first insulating film (208), and the first insulating film (208) is formed to cover the main surface (203) and the inner walls of the trenches (207, 44, 53, 72).

[0431] [B9] The method for manufacturing a semiconductor device (1) according to B8, further comprising the step of embedding electrodes (209, 46, 57, 74) in the trenches (207, 44, 53, 72) with the first insulating film (208) interposed therebetween before the step of forming the second insulating film (211), wherein the second insulating film (211) covers the first insulating film (208) and the electrodes (209, 46, 57, 74).

[0432] [B10] A method for manufacturing a semiconductor device (1) according to any one of B1 to B9, further comprising, after the step of removing the field insulating film (80, 120, 170), a step of forming a main surface insulating film (83, 133, 183) having a thickness less than that of the field insulating film (80, 120, 170) and covering the portion of the main surface (203) exposed from the field insulating film (80, 120, 170).

[0433] [B11] The method for producing a semiconductor device (1) according to B10, wherein the main surface insulating film (83, 133, 183) is made of an oxide film formed by an oxidation treatment method.

[0434] [B12] A method for manufacturing a semiconductor device (1) according to B10 or B11, wherein the main surface insulating film (83, 133, 183) is formed at an interval from a middle portion in the thickness direction of the field insulating film (80, 120, 170) toward the semiconductor wafer (201).

[0435] [B13] The method for manufacturing a semiconductor device (1) according to any one of B10 to B12, wherein the main surface insulating film (83, 133, 183) has a thickness equal to or less than one-fifth of the thickness of the field insulating film (80, 120, 170).

[0436] [B14] A method for manufacturing a semiconductor device (1) according to any one of B10 to B13, further comprising the steps of: forming an electrode film (215) that covers the main surface insulating film (83, 133, 183), the first insulating film (208), and the second insulating film (211); and forming a main surface electrode (134, 184) that covers at least a portion of the main surface insulating film (83, 133, 183) by partially removing the electrode film (215).

[0437] [B15] A method for manufacturing a semiconductor device (1) according to any one of B10 to B14, comprising, after the step of forming the field insulating film (80, 120, 170), removing the second insulating film (211) by an etching method and forming the field insulating film (80, 120, 170) made of the first insulating film (208).

[0438] The following [C1] to [C22] provide semiconductor devices including transistors with variable on-resistance.

[0439] [C1] A semiconductor device (1) including a semiconductor chip (2) and a plurality of gate-divided transistors (8) including first and second system transistors (9) formed on the semiconductor chip (2), the gate-divided transistors (8) generating a single output signal (IOUT) by selectively controlling the first and second system transistors (9). This structure makes it possible to provide a semiconductor device equipped with variable on-resistance transistors.

[0440] [C2] The semiconductor device (1) according to C1, wherein the gate split transistor (8) is controlled in a plurality of operating modes with different switching patterns of the first system transistor (9) and the second system transistor (9) during normal operation and active clamp operation.

[0441] [C3] The semiconductor device (1) according to C2, wherein the gate split transistor (8) is controlled to an on state by both the first system transistor (9) and the second system transistor (9) during the normal operation.

[0442] [C4] The semiconductor device (1) according to C2 or C3, wherein the gate split transistor (8) is controlled to an on state by either the first system transistor (9) or the second system transistor (9) during the active clamp operation.

[0443] [C5] The semiconductor device (1) according to any one of C2 to C4, wherein the gate split transistor (8) operates at a first on-resistance during the normal operation and at a second on-resistance exceeding the first on-resistance during the active clamp operation.

[0444] [C6] The semiconductor device (1) according to any one of C1 to C5, wherein a first gate signal (G) is individually input to the first system transistors (9), and a second gate signal (G) is individually input to the second system transistors (9).

[0445] [C7] The semiconductor device (1) according to any one of C1 to C6, further including a first gate wiring (14) connected to the first system transistor (9) on the semiconductor chip (2), and a second gate wiring (14) connected to the second system transistor (9) on the semiconductor chip (2).

[0446] [C8] The semiconductor device (1) according to any one of C1 to C7, further comprising a device region (6) defined in the semiconductor chip (2), wherein the first system transistors (9) and the second system transistors (9) are collectively formed in the device region (6).

[0447] [C9] A semiconductor device (1) according to any one of C1 to C8, further comprising a plurality of unit transistors (10) formed on the semiconductor chip (2), wherein the first system transistors (9) comprise one or more first unit transistors (10) organized as individual control targets from the plurality of unit transistors (10), and the second system transistors (9) comprise one or more second unit transistors (10) organized as individual control targets from the plurality of unit transistors (10) excluding the first unit transistor (10).

[0448] [C10] The semiconductor device (1) according to any one of C1 to C9, further comprising a control circuit (11) formed in a region of the semiconductor chip (2) different from the gate split transistor (8) and controlling the gate split transistor (8).

[0449] [C11] A semiconductor device (1) including a semiconductor chip (2) and a plurality of gate-divided transistors (8) including first system transistors (9), second system transistors (9), and third system transistors (9) formed on the semiconductor chip (2), and generating a single output signal (IOUT) by selectively controlling the first system transistors (9), the second system transistors (9), and the third system transistors (9). This structure makes it possible to provide a semiconductor device equipped with a transistor having a variable on-resistance.

[0450] [C12] The semiconductor device (1) according to C11, wherein the gate split transistor (8) is controlled in a plurality of operation modes in which the switching patterns of the first system transistor (9), the second system transistor (9), and the third system transistor (9) are different during at least two of an on-transition operation, a normal operation, an off-transition operation, and an active clamp operation.

[0451] [C13] The semiconductor device (1) according to C12, wherein the gate split transistor (8) is controlled to an on state by all of the first system transistor (9), the second system transistor (9), and the third system transistor (9) during the on transition operation.

[0452] [C14] The semiconductor device (1) according to C12 or C13, wherein the gate split transistor (8) is controlled to an on state by any two of the first system transistor (9), the second system transistor (9), and the third system transistor (9) during the normal operation.

[0453] [C15] The semiconductor device (1) according to any one of C12 to C14, wherein the gate split transistor (8) is controlled to an on state by all of the first system transistor (9), the second system transistor (9), and the third system transistor (9) during the off transition operation.

[0454] [C16] The semiconductor device (1) according to any one of C12 to C15, wherein the gate split transistor (8) is controlled to an on state by any one of the first system transistor (9), the second system transistor (9), and the third system transistor (9) during the active clamp operation.

[0455] [C17] The semiconductor device (1) according to any one of C12 to C16, wherein the gate split transistor (8) operates at a first on-resistance during the on-transition operation, operates at a second on-resistance exceeding the first on-resistance during the normal operation, operates at a third on-resistance less than the second on-resistance during the off-transition operation, and operates at a fourth on-resistance exceeding the second on-resistance during the active clamp operation.

[0456] [C18] The semiconductor device (1) according to any one of C11 to C17, wherein a first gate signal (G) is individually input to the first system transistors (9), a second gate signal (G) is individually input to the second system transistors (9), and a third gate signal (G) is individually input to the third system transistors (9).

[0457] [C19] The semiconductor device (1) according to any one of C11 to C18, further including a first gate wiring (14) connected to the first system transistor (9) on the semiconductor chip (2), a second gate wiring (14) connected to the second system transistor (9) on the semiconductor chip (2), and a third gate wiring (14) connected to the third system transistor (9) on the semiconductor chip (2).

[0458] [C20] The semiconductor device (1) according to any one of C11 to C19, further comprising a device region (6) defined in the semiconductor chip (2), wherein the first system transistors (9), the second system transistors (9) and the third system transistors (9) are collectively formed in the device region (6).

[0459] [C21] A semiconductor device (1) according to any one of C11 to C20, further comprising a plurality of unit transistors (10) formed on the semiconductor chip (2), wherein the first system transistors (9) comprise one or more first unit transistors (10) organized as individual control targets from the plurality of unit transistors (10), the second system transistors (9) comprise one or more second unit transistors (10) organized as individual control targets from the plurality of unit transistors (10) excluding the first unit transistor (10), and the third system transistors (9) comprise one or more third unit transistors (10) organized as individual control targets from the plurality of unit transistors (10) excluding the first unit transistor (10) and the second unit transistor (10).

[0460] [C22] The semiconductor device (1) according to any one of C11 to C21, further comprising a control circuit (11) formed in a region of the semiconductor chip (2) different from the gate split transistor (8) and controlling the gate split transistor (8).

[0461] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0462] 1. Semiconductor device 2. Semiconductor chips 3 First main surface 6 First Device Area 8 Power transistor (split-gate transistor) 9 transistors 10 unit transistors 12 Gate control circuit (control circuit) 43 First trench isolation structure 44 Separation trench 45 Isolation insulating film 45a first portion of isolation insulating film 45b second portion of isolation insulating film 46 Separation electrode 51 Trench gate structure 53 Gate Trench 54 Upper insulating film 55 Lower insulating film 56 Upper electrode 57 Lower electrode 58 Intermediate insulating film 80 First field insulating film 80a First insulating side wall 81 First concealed surface 82 1st exposed surface 83 First main surface insulating film 83a: First region of first main surface insulating film 83b: second region of the first main surface insulating film 100 CMIS areas 101 1st MIS area 104 Second trench isolation structure 120 Second field insulating film 120a Second insulating side wall 131 Second Concealed Surface 132 2nd exposed surface 133 Second main surface insulating film 133a: First region of second main surface insulating film 133b: second region of second main surface insulating film 134 Second gate electrode (electrode) 153 2nd MIS area 154 Third trench isolation structure 170 Third field insulating film 170a Third insulating side wall 181 Third Hidden Surface 182 3rd exposed surface 183 Third main surface insulating film 183a 1st area 183b Second area 184 Second gate electrode (electrode) IOUT Output current (output signal) TF1 First field thickness TF2 Second Field Thickness TF3 Third field thickness TI1 First separation thickness TI2 Second separation thickness TMI1 First Insulation Thickness TMI2 Second Insulation Thickness TMI3 Third Insulation Thickness θ1 1st inclination angle θ2 2nd inclination angle θ3 3rd inclination angle

Claims

1. a semiconductor chip having a main surface; a field insulating film partially covering the main surface and having an insulating sidewall with an inclination angle between the main surface and the field insulating film being 20° or more and 40° or less; a hidden surface formed on the main surface in a portion covered with the field insulating film; an exposed surface formed in a portion of the main surface exposed from the field insulating film and recessed from the hidden surface in a thickness direction of the semiconductor chip.

2. 2. The semiconductor device according to claim 1, further comprising a main surface insulating film having a thickness less than a thickness of said field insulating film and covering said exposed surface.

3. 3. The semiconductor device according to claim 2, wherein said main surface insulating film is continuous with said insulating sidewall of said field insulating film.

4. 4. The semiconductor device according to claim 2, wherein the main surface insulating film includes a first region located on the semiconductor chip side with respect to the hidden surface, and a second region located on the opposite side of the hidden surface from the semiconductor chip.

5. 5. The semiconductor device according to claim 2, wherein said main surface insulating film is formed on said semiconductor chip side with a gap from a middle portion of said field insulating film in the thickness direction.

6. 6. The semiconductor device according to claim 2, wherein said main surface insulating film has a thickness equal to or less than one-fifth of said field insulating film.

7. 7. The semiconductor device according to claim 2, further comprising a main surface electrode covering said main surface insulating film.

8. 8. The semiconductor device according to claim 7, wherein said main surface electrode is led out from above said main surface insulating film through said insulating sidewall onto said field insulating film.

9. the semiconductor device further includes a trench isolation structure that includes an isolation trench formed in the main surface, an isolation insulating film covering an inner wall of the isolation trench, and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, and that defines a device region on the main surface; 9. The semiconductor device according to claim 1, wherein said field insulating film covers said main surface in said device region.

10. 10. The semiconductor device according to claim 9, wherein said field insulating film is continuous with said isolation insulating film.

11. the isolation insulating film includes a first portion covering a sidewall of the isolation trench and a second portion covering a bottom wall of the isolation trench; 11. The semiconductor device according to claim 9, wherein the field insulating film has a thickness greater than a thickness of the second portion.

12. the field insulating film has a first side extending in one direction in a plan view and a second side extending in an intersecting direction intersecting the one direction, 12. The semiconductor device according to claim 1, wherein the insulating sidewalls are formed on the first and second sides of the field insulating film.

13. 13. The semiconductor device according to claim 1, wherein said field insulating film includes an oxide of said semiconductor chip.

14. a semiconductor chip having a main surface; a trench isolation structure including an isolation trench formed in the main surface, an isolation insulating film covering an inner wall of the isolation trench, and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure defining a device region in the main surface; a functional device formed on the main surface in the device region; a field insulating film partially covering the main surface in the device region at a distance from the functional device, the field insulating film having insulating sidewalls that form an inclination angle between the main surface and the insulating sidewalls and that is equal to or greater than 20° and equal to or less than 40°.

15. 15. The semiconductor device according to claim 14, wherein said field insulating film is continuous with said isolation insulating film.

16. the functional device includes a trench gate structure having a gate trench formed in the main surface, and an upper electrode and a lower electrode buried in the gate trench so as to be insulated and separated in a vertical direction by an insulator; 16. The semiconductor device according to claim 14, wherein said field insulating film is formed at a distance from said trench gate structure.

17. 17. The semiconductor device according to claim 16, wherein said functional device includes a plurality of unit transistors each including a plurality of said trench gate structures.

18. 18. The semiconductor device according to claim 17, wherein the functional device includes n (n≧2) system transistors each configured with one or more of the unit transistors organized as individual control targets, and includes n systems of gate-divided transistors that generate a single output signal by selectively controlling the n system transistors.

19. 19. The semiconductor device according to claim 18, further comprising a control circuit formed in a region of said main surface different from said device region, said control circuit individually controlling said n system transistors.

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