Semiconductor device manufacturing method

Abstract

To provide a semiconductor device capable of suppressing a decrease in carrier mobility.SOLUTION: A manufacturing method of a semiconductor device includes performing first ion implantation to implant aluminum into a silicon carbide layer at a first dose, performing first heat treatment at 1600°C or higher, performing first etching processing to etch a surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen, performing second etching processing to etch the surface in an atmosphere containing hydrogen plasma or atomic hydrogen, forming a silicon oxide film on the surface, and forming a gate electrode on the silicon oxide film.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] For example, when a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is formed using silicon carbide, there is a problem that the mobility of carriers decreases. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] K. Tachiki et al., “Formation of high-quality SiC(0001) / SiO2 structures by excluding oxidation process with H2 etching before SiO2 deposition and high-temperature N2 annealing”, Appl.Phys.Express 13,121002(2020). [Non-patent document 2] K. Tachiki et al., “Mobility improvement of 4H-SiC(0001)MOSFETs by three-step process of H2 etching, SiO2 deposition, and interface nitridation”, Appl.Phys.Express 14,031001(2021). Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing a decrease in carrier mobility. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to an embodiment includes: performing a first ion implantation step of implanting aluminum into a silicon carbide layer at a first dose; performing a first heat treatment at 1600°C or higher; performing a first etching step of etching a surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen; performing a second etching step of etching the surface in an atmosphere containing hydrogen plasma or atomic hydrogen; forming a silicon oxide film on the surface; and forming a gate electrode on the silicon oxide film. In the second etching process, the surface is etched by 5 nm to 25 nm. . [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a first embodiment. [Figure 2] A diagram showing the crystal structure of a SiC semiconductor. [Figure 3] FIG. 2 is a process flow diagram of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 5A to 5C are explanatory diagrams illustrating the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] FIG. 10 is a process flow diagram of a method for manufacturing a semiconductor device according to a comparative example. [Figure 21] 5A to 5C are explanatory diagrams illustrating the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 5A to 5C are explanatory diagrams illustrating the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 23] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device manufacturing method according to the modified example of the first embodiment. [Figure 24] FIG. 6 is a process flow diagram of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 26] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 27] 8A to 8C are explanatory diagrams illustrating the operation and effect of the semiconductor device manufacturing method according to the second embodiment. [Figure 28] FIG. 10 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a third embodiment. [Figure 29]FIG. 10 is a process flow diagram of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 30] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 31] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 32] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 33] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 34] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 35] FIG. 10 is a process flow diagram of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 36] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 37] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - and p + , p, p - When the notation is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p -The type may be simply referred to as p-type. Unless otherwise specified, the impurity concentration of each region is represented by the value of the impurity concentration at the center of each region.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] The depth of the trench, the thickness of the insulating layer, etc. can be measured, for example, on a SIMS profile, a transmission electron microscope (TEM) image, or a scanning electron microscope (SEM) image.

[0012] (First embodiment) The method for manufacturing a semiconductor device of the first embodiment includes performing a first ion implantation to implant aluminum into a silicon carbide layer at a first dose, performing a first heat treatment at 1600°C or higher, performing a first etching treatment to etch the surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen, performing a second etching treatment to etch the surface in an atmosphere containing hydrogen plasma or atomic hydrogen, forming a silicon oxide film on the surface, and forming a gate electrode on the silicon oxide film.

[0013] 1 is a schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment. The semiconductor device is a MOSFET 100. The MOSFET 100 is a double implantation MOSFET (DIMOSFET) in which a p-well and a source region are formed by ion implantation. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0014] The MOSFET 100 includes a silicon carbide layer 10, a gate insulating layer 28, a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40.

[0015] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0016] The silicon carbide layer 10 is, for example, a single crystal of 4H—SiC. The silicon carbide layer 10 is located between a source electrode 34 and a drain electrode 36.

[0017] Figure 2 is a diagram showing the crystal structure of SiC semiconductor. A typical crystal structure of SiC semiconductor is a hexagonal system like 4H-SiC. One of the faces (top faces of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face (Si face) and is written as the {0001} face. Silicon atoms (Si) are arranged on the top surface of the silicon face.

[0018] The other surface (top surface of the hexagonal prism) normal to the c-axis along the axial direction of the hexagonal prism is the (000-1) surface. The surface equivalent to the (000-1) surface is called the carbon surface (C-surface) and is written as the {000-1} surface. Carbon atoms (C) are arranged on the outermost surface of the carbon surface.

[0019] On the other hand, the side surfaces of the hexagonal prism (cylindrical surfaces) are m-planes, i.e., {1-100} planes, which are equivalent to the (1-100) plane. Furthermore, the planes passing through pairs of non-adjacent ridges are a-planes, i.e., {11-20} planes, which are equivalent to the (11-20) plane. Both silicon atoms (Si) and carbon atoms (C) are arranged on the outermost surfaces of the m-plane and a-plane.

[0020] Hereinafter, an example will be described in which the front surface of silicon carbide layer 10 is inclined at an angle of 0 to 8 degrees relative to the silicon surface, and the back surface is inclined at an angle of 0 to 8 degrees relative to the carbon surface. The front surface of silicon carbide layer 10 has an off angle of 0 to 8 degrees relative to the silicon surface.

[0021] The drain region 12 is n + The drain region 12 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0022] The drift region 14 is provided on the drain region 12. The drift region 14 has an n - The drift region 14 is made of SiC of n-type. The drift region 14 contains, for example, nitrogen as an n-type impurity.

[0023] The n-type impurity concentration of the drift region 14 is lower than the n-type impurity concentration of the drain region 12. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The drift region 14 is, for example, an epitaxially grown layer of SiC formed on the drain region 12 by epitaxial growth.

[0024] The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0025] The p-well region 16 is provided on a portion of the surface of the drift region 14. The p-well region 16 is located between the drift region 14 and the gate insulating layer 28. The p-well region 16 is made of p-type SiC.

[0026] The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0027] The depth of the p-well region 16 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 16 functions as a channel region of the MOSFET 100. A portion of the p-well region 16 facing the gate electrode 30 functions as the channel region.

[0028] The carbon vacancy density in the p-well region 16 is, for example, 1×10 12 cm -3 The electron hole mobility in the p-well region 16 is, for example, 200 cm 2 / V·s or more.

[0029] The source region 18 is provided on a part of the surface of the p-well region 16. The source region 18 is an n + The source region 18 is made of n-type SiC. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 18 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 It is less than cm.

[0030] The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0031] The p-well contact region 20 is provided on a part of the surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is provided on the p+ It is a type of SiC.

[0032] The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the p-well contact region 20 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0033] The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. The depth of the p-well contact region 20 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0034] The gate insulating layer 28 is provided between the silicon carbide layer 10 and the gate electrode 30. The gate insulating layer 28 is provided between the drift region 14 and the gate electrode 30, and between the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided on the drift region 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift region 14 and the p-well region 16.

[0035] The gate insulating layer 28 includes silicon oxide and is an example of a silicon oxide layer.

[0036] The gate insulating layer 28 has a thickness of, for example, 30 nm to 100 nm. The gate insulating layer 28 functions as a gate insulating layer for the MOSFET 100.

[0037] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the gate insulating layer 28, and between the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a terminating element that terminates dangling bonds in the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0038] The nitrogen concentration in the interface termination region 40 is, for example, 1×10 21 cm -3That's all.

[0039] Nitrogen atoms present in interface termination region 40 terminate dangling bonds on the surface of silicon carbide layer 10 .

[0040] The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the silicon carbide layer 10. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the drift region 14. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the p-well region 16.

[0041] The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0042] The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is located between the gate electrode 30 and the source electrode 34. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0043] The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16. The source electrode 34 is in contact with, for example, the source region 18 and the p-well contact region 20.

[0044] The source electrode 34 has a laminated structure of, for example, a Ni (nickel) barrier metal layer and an aluminum metal layer on the barrier metal layer. The nickel barrier metal layer and the silicon carbide layer may react to form nickel silicide (NiSi, NiSi, etc.). The nickel barrier metal layer and the aluminum metal layer may react to form an alloy.

[0045] The drain electrode 36 is provided on the opposite side of the silicon carbide layer 10 to the source electrode 34, i.e., on the back surface side. The drain electrode 36 is electrically connected to the drain region 12. The drain electrode 36 is in contact with the drain region 12, for example.

[0046] The drain electrode 36 is made of, for example, nickel. Nickel may react with the drain region 12 to form nickel silicide (NiSi, Ni2Si, etc.).

[0047] In the first embodiment, the n-type impurity is, for example, nitrogen or phosphorus. Arsenic (As) or antimony (Sb) can also be used as the n-type impurity.

[0048] In the first embodiment, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be used as the p-type impurity.

[0049] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0050] Fig. 3 is a process flow diagram of the method for manufacturing the semiconductor device of the first embodiment. Figs. 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are explanatory diagrams of the method for manufacturing the semiconductor device of the first embodiment. Figs. 4 to 6 and 8 to 18 are cross-sectional views during manufacturing. Fig. 7 is a diagram showing the element distribution immediately after ion implantation.

[0051] As shown in FIG. 3 , the method for manufacturing the semiconductor device according to the first embodiment includes silicon carbide layer preparation (step S100), aluminum ion implantation (step S101), carbon ion implantation (step S102), phosphorus ion implantation (step S103), aluminum ion implantation (step S104), carbon film formation (step S105), first heat treatment (step S106), carbon film removal (step S107), field oxide film formation (step S108), chemical dry etching (step S109), hydrogen plasma etching (step S110), silicon oxide film formation (step S111), second heat treatment (step S112), third heat treatment (step S113), gate electrode formation (step S114), interlayer insulating film formation (step S115), and source and drain electrode formation (step S116).

[0052] In step S100, an n-type silicon carbide layer 10 is prepared (FIG. 4). + type drain region 12 and n - The semiconductor device includes a drift region 14. The drift region 14 is formed on the drain region 12 by, for example, epitaxial growth.

[0053] The drain region 12 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0054] The drift region 14 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0055] In step S101, for example, an insulating film is formed and then patterned by photolithography and etching to form a first mask material 51. Then, using the first mask material 51 as an ion implantation mask, aluminum ions are implanted into the drift region 14. The ion implantation forms a p-well region 16 (FIG. 5).

[0056] The ion implantation to form the p-well region 16 is an example of a first ion implantation. The aluminum ion implantation is performed with a first projected range and a first dose. The projected range is the average projected distance.

[0057] The first projected range is, for example, 0.1 μm or more and 0.6 μm or less. The first dose is, for example, 1×10 12 cm -2 More than 1×10 14 cm-2 The following is the result.

[0058] In step S102, carbon ions are implanted into the p-well region 16 using the first mask material 51 as an ion implantation mask (FIG. 6). The carbon ion implantation into the p-well region 16 is an example of a second ion implantation. The carbon ion implantation is performed in a second projected range and at a second dose. Thereafter, the first mask material 51 is removed.

[0059] The second projected range is, for example, 0.1 μm or more and 0.6 μm or less. The second projected range is, for example, 80% or more and 120% or less of the first projected range. The second dose is, for example, 10 times or more the first dose. The second dose is, for example, 10,000 times or less the first dose. The second dose is, for example, 1×10 15 cm -2 More than 1×10 18 cm -2 The following is the result.

[0060] 7 shows the concentration distribution of aluminum implanted into silicon carbide layer 10 by the first ion implantation and the concentration distribution of carbon implanted into silicon carbide layer 10 by the second ion implantation. Fig. 7 shows the element distribution immediately after ion implantation.

[0061] As shown in Figure 7, the second projected range Rp2 for carbon ion implantation is located near the first projected range Rp1 for aluminum ion implantation. Since the second dose of carbon ion implantation is 10 times or more the first dose of aluminum ion implantation, the carbon concentration distribution after ion implantation completely covers, for example, the aluminum concentration distribution after ion implantation. At each depth after ion implantation, the concentration of interstitial carbon is higher than the concentration of interstitial aluminum.

[0062] The peak concentration of the aluminum distribution is, for example, 1 x 10 16 cm -3 More than 1×10 20 cm-3 The peak concentration of the carbon distribution is, for example, 1 × 10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0063] In step S103, for example, an insulating film is formed and then patterned by photolithography and etching to form a second mask material 52. Then, using the second mask material 52 as an ion implantation mask, phosphorus (P) is ion-implanted into the drift region 14 to form the source region 18 (FIG. 8). Thereafter, the second mask material 52 is removed.

[0064] In step S104, for example, an insulating film is formed and then patterned by photolithography and etching to form a third mask material 53. Using the third mask material 53 as an ion implantation mask, aluminum is ion-implanted into the drift region 14 to form the p-well contact region 20 (FIG. 9).

[0065] Next, the third mask material 53 is removed (FIG. 10).

[0066] In step S105, a carbon film 54 is formed on the silicon carbide layer 10 (FIG. 11).

[0067] In step S106, a first heat treatment is performed. The first heat treatment is performed at 1600°C or higher. The first heat treatment is performed, for example, at 2000°C or lower. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The first heat treatment is performed, for example, in an argon gas atmosphere.

[0068] The first heat treatment activates the aluminum and phosphorus ions implanted into the silicon carbide layer 10. The first heat treatment is an activation annealing of the aluminum and phosphorus. Furthermore, the first heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0069] Carbon film 54 suppresses desorption of silicon and carbon from silicon carbide layer 10 into the atmosphere during the first heat treatment. Carbon film 54 also absorbs excess interstitial carbon in silicon carbide layer 10 during the first heat treatment.

[0070] The first heat treatment is composed of a first step at a temperature of, for example, 1600° C. or higher and a second step at a temperature lower than the first step, for example, 1000° C. or lower.

[0071] For example, in a first step, aluminum and phosphorus ions implanted into the silicon carbide layer 10 are activated, and the interstitial carbon fills the carbon vacancies. In a second step, for example, at a low temperature, the excess interstitial carbon is expelled from the silicon carbide layer 10 and absorbed into the carbon film 54.

[0072] In step S107, the carbon film 54 is removed (FIG. 12). The carbon film 54 is removed by an ashing process using oxygen plasma. The carbon film 54 is removed in the oxygen plasma.

[0073] In step S108, a field oxide film 55 is formed on the silicon carbide layer 10 (FIG. 13). The field oxide film 55 contains oxygen. The field oxide film 55 is, for example, a silicon oxide film. The field oxide film 55 is deposited by, for example, a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method).

[0074] The field oxide film 55 functions as, for example, an element isolation region in a peripheral region (not shown).

[0075] Next, the field oxide film 55 is removed by, for example, wet etching.

[0076] In step S109, a chemical dry etching process is performed to etch the surface of the silicon carbide layer 10 by a chemical dry etching (CDE) process (FIG. 14). The chemical dry etching process is an example of a first etching process.

[0077] The CDE method is a dry etching method performed using an etching apparatus in which the plasma generation section and the etching section are separated. The CDE method has the advantage of causing less damage to the substrate being etched because the plasma generation section and the etching section are separated. Another advantage of the CDE method is that it can achieve isotropic etching.

[0078] In the first etching process, the surface of the silicon carbide layer 10 is etched in an atmosphere containing plasma generated from a gas containing halogen and oxygen. The first etching process is a cleaning process. By etching the surface of the silicon carbide layer 10, for example, impurities on the surface of the silicon carbide layer 10 and damaged layers on the surface are removed.

[0079] In the first etching process, the gas for generating the plasma includes, for example, a perfluorocarbon (PFC) and oxygen (O2), and the perfluorocarbon (PFC) is, for example, CF4, C2F6, C3F8, or C5F8.

[0080] The atomic ratio of oxygen atoms to halogen atoms in the gas that generates plasma is, for example, 1.5 or more. For example, when a gas containing CF4 and oxygen (O2) is used as the gas that generates plasma, the flow rate of oxygen (O2) introduced into the etching apparatus is, for example, three times or more the flow rate of CF4. By making the flow rate of oxygen (O2) three times or more the flow rate of CF4, the atomic ratio of oxygen atoms to halogen atoms in the gas becomes 1.5 or more.

[0081] The gas for generating the plasma may contain, for example, nitrogen (N).

[0082] The first etching process is performed at a temperature of, for example, 20° C. or higher and 1300° C. or lower.

[0083] In the first etching treatment, the surface of the silicon carbide layer 10 is etched to a depth of, for example, 5 nm or more and 50 nm or less.

[0084] In step S110, a hydrogen etching process is performed to etch the surface of the silicon carbide layer 10 in an atmosphere containing hydrogen plasma or atomic hydrogen (FIG. 15). The hydrogen etching process is an example of a second etching process.

[0085] In the second etching process, the surface of the silicon carbide layer 10 is etched in an atmosphere containing hydrogen plasma, which is activated hydrogen, or atomic hydrogen, which is activated hydrogen. In the second etching process, for example, a plasma etching apparatus using hydrogen plasma generated from hydrogen gas (H2) is used. In the second etching process, for example, an etching apparatus using a thermal catalytic method to generate atomic hydrogen from hydrogen gas (H2) is used.

[0086] The second etching process is performed at a temperature of, for example, 20° C. or higher and 300° C. or lower.

[0087] In the second etching treatment, the surface of the silicon carbide layer 10 is etched to a depth of, for example, 5 nm or more and 25 nm or less.

[0088] In step S111, a silicon oxide film 57 is formed on the silicon carbide layer 10 (FIG. 16). The silicon oxide film 57 will eventually become the gate insulating layer .

[0089] The silicon oxide film 57 is formed by, for example, a vapor phase growth method at a low temperature and a low oxygen partial pressure. The silicon oxide film 57 is formed by, for example, a CVD method or a PVD method at a low temperature and a low oxygen partial pressure. The silicon oxide film 57 is a deposited film. The thickness of the silicon oxide film 57 is, for example, 30 nm or more and 100 nm or less.

[0090] The silicon oxide film 57 is formed by a CVD method using, for example, tetraethyl orthosilicate (TEOS) as a source gas, or by a CVD method using, for example, dichlorosilane gas (SiH2Cl2) and dinitrogen monoxide gas (N2O) as source gases.

[0091] In step S112, a second heat treatment is performed in an atmosphere containing ammonia gas (NH3).

[0092] For example, ammonia gas (NH 3 ) is supplied to a reactor in which the silicon carbide layer 10 is placed, and heat treatment is performed.

[0093] The temperature of the second heat treatment is, for example, 1200°C or higher and 1600°C or lower.

[0094] The partial pressure of ammonia gas in the atmosphere for the second heat treatment is, for example, 90% or more.

[0095] The second heat treatment forms interface termination region 40 at the interface between silicon carbide layer 10 and the silicon oxide film (FIG. 17).

[0096] The second heat treatment also functions as a densifying anneal for the silicon oxide film, making the silicon oxide film into a high-density film.

[0097] In step S113, a third heat treatment is performed. The third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx). The nitrogen oxide gas is, for example, nitric oxide gas (NO). The nitrogen oxide gas is, for example, dinitrogen monoxide gas (NO).

[0098] For example, nitrogen oxide gas (NOx) is supplied to a reactor in which the silicon carbide layer 10 is placed, and heat treatment is performed.

[0099] The temperature of the third heat treatment is, for example, not less than 750° C. and not more than 1050° C. The temperature of the third heat treatment is, for example, lower than the temperature of the second heat treatment.

[0100] The partial pressure of the nitrogen oxide gas in the atmosphere for the third heat treatment is, for example, 10% or more.

[0101] The third heat treatment removes nitrogen from the silicon oxide film, forming a silicon oxide film with reduced nitrogen defects.

[0102] In step S114, the gate electrode 30 is formed on the gate insulating layer 28. The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0103] In step S115, an interlayer insulating film 32 (FIG. 18) is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0104] In step S116, a source electrode 34 and a drain electrode 36 are formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed by, for example, sputtering nickel (Ni) and aluminum (Al).

[0105] The drain electrode 36 is formed on the back surface side of the silicon carbide layer 10. The drain electrode 36 is formed by, for example, sputtering nickel.

[0106] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0107] Next, the operation and effects of the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0108] In the method for manufacturing a semiconductor device according to the first embodiment, the carbon vacancy density in the silicon carbide layer 10 is reduced by ion implanting carbon in addition to ion implanting aluminum, performing a cleaning process using the CDE method, and then performing a hydrogen etching process. This reduces the carbon vacancy density in the silicon carbide layer 10 of the MOSFET 100 to be manufactured. In particular, it reduces the carbon vacancy density in the channel region of the MOSFET 100 to be manufactured. This prevents a decrease in carrier mobility in the MOSFET 100 to be manufactured. This will be described in detail below.

[0109] When forming a MOSFET using silicon carbide, there is a problem of reduced carrier mobility. One factor that reduces carrier mobility is thought to be the intersurface state between the silicon carbide layer and the gate insulating layer. The interface state is thought to be caused by dangling bonds present on the surface of the silicon carbide layer.

[0110] The MOSFET 100 of the first embodiment includes an interface termination region 40 in which nitrogen is segregated between the silicon carbide layer 10 and the gate insulating layer 28. In the interface termination region 40, nitrogen atoms are bonded to silicon atoms in a three-coordinate configuration, thereby reducing dangling bonds. This results in a MOSFET in which a decrease in carrier mobility is suppressed.

[0111] Another factor that causes the problem of reduced carrier mobility when forming a MOSFET using silicon carbide is thought to be the presence of carbon vacancies in silicon carbide layer 10.

[0112] For example, the presence of carbon vacancies in the channel region of a MOSFET is thought to scatter carriers and reduce the hole mobility of carriers.

[0113] In the MOSFET 100 of the first embodiment, the carbon vacancy density in the silicon carbide layer 10 is reduced by using the semiconductor device manufacturing method of the first embodiment. In particular, the carbon vacancy density is reduced in the channel region of the MOSFET 100. For example, the carbon vacancy density is reduced in the channel region between the gate insulating layer 28 and a position about 100 nm away from the gate insulating layer 28 on the silicon carbide layer 10 side.

[0114] In the MOSFET 100 of the first embodiment, the carbon vacancy density in the channel region is sufficiently low, so that the hole mobility of electrons in the channel region is, for example, 200 cm 2 / V·s or more.

[0115] The field-effect mobility, which is an index of the on-current of a MOSFET, is determined by the proportion of mobile charges in the hole mobility. In other words, the field-effect mobility is smaller than the hole mobility. At the MOS interface of silicon carbide, the proportion of mobile charges is low due to poor interface termination efficiency and the large number of defects in the substrate and gate insulating layer. Charges other than the mobile charges are trapped charges.

[0116] For example, it is possible to increase the proportion of mobile charges by optimizing the interface termination method and termination elements. However, if the hole mobility is low, it is difficult to significantly improve the field-effect mobility. To significantly improve the field-effect mobility, the hole mobility must be increased to 150 cm 2 It is desirable to improve this to more than / V·s.

[0117] In the method for manufacturing a semiconductor device according to the first embodiment, the hole mobility of the MOSFET 100 can be significantly improved by reducing the carbon vacancy density. The hole mobility can be increased to, for example, 200 cm 2 / V·s or more. By further reducing the density of carbon vacancies, for example, 2 / V·s or more, and even 450cm 2 A hole mobility of 1 / V·s or higher is achieved.

[0118] When manufacturing a MOSFET, the following three processes are considered to be manufacturing processes that generate carbon vacancies in the silicon carbide layer, which reduce carrier mobility.

[0119] The first process is ion implantation of impurities into the silicon carbide layer. The energy of the implanted impurities forms carbon vacancies and interstitial carbon in the silicon carbide layer 10. For example, in the p-well region, carbon vacancies and interstitial carbon are formed at a volume density similar to the volume density of the implanted ions.

[0120] The second process is activation annealing to activate the impurities introduced into the silicon carbide layer by ion implantation. During activation annealing, the free energy of the silicon carbide layer is reduced, and carbon vacancies and interstitial carbon are generated in the silicon carbide layer, increasing entropy. The higher the temperature of activation annealing, the greater the amount of carbon vacancies and interstitial carbon generated. Since the formation of a silicon carbide layer by epitaxial growth is also a high-temperature process, the silicon carbide layer contains 10 13 cm -3 Carbon vacancies on the order of 1×10 remain. 14 cm -3 Carbon vacancies of the order are created.

[0121] The third process is a process of oxidizing the surface of the silicon carbide layer. For example, it is a thermal oxidation process to form a thermal oxide film. During oxidation, strain occurs on the surface of the silicon carbide layer, which causes carbon vacancies and interstitial carbon to form in the silicon carbide layer. The surface is significantly strained by oxidation, and the strain increases to 1×10 18 cm -3 Carbon vacancies of the order are created.

[0122] In the method for manufacturing the MOSFET 100 of the first embodiment, after aluminum ion implantation to form the p-well region 16 is performed in the silicon carbide layer 10, carbon ion implantation is performed in the same region of the silicon carbide layer 10. The second dose of carbon is at least 10 times the first dose of aluminum.

[0123] According to the manufacturing method of the MOSFET 100 of the first embodiment, the carbon ion implantation causes a large amount of excess interstitial carbon to be present in the p-well region 16. The heat treatment performed after the carbon ion implantation fills the carbon vacancies generated by the aluminum ion implantation with the excess interstitial carbon, thereby reducing the carbon vacancy density in the p-well region 16.

[0124] From the viewpoint of maintaining an appropriate p-type impurity concentration in the p-well region 16, the first dose of aluminum is set to 1×10 14 cm -2 From the viewpoint of reducing the carbon vacancy density in the p-well region 16, the second dose of carbon is preferably 1×10 15 cm -2 It is preferable that the concentration is 1×10 or more. 16 cm -2 More preferably, it is equal to or greater than this.

[0125] From the viewpoint of reducing the carbon vacancy density in the p-well region 16, the second dose of carbon is preferably 100 times or more the first dose of aluminum.

[0126] From the viewpoint of reducing the carbon vacancy density in the p-well region 16, the second projected range Rp2 of the carbon ion implantation is preferably 80% or more and 120% or less of the first projected range Rp1 of the aluminum ion implantation, and more preferably 90% or more and 110% or less.

[0127] By bringing the first projected range Rp1 and the second projected range Rp2 closer to each other, the carbon concentration distribution after ion implantation can easily completely cover the aluminum concentration distribution after ion implantation. The carbon concentration distribution after ion implantation completely covers the aluminum concentration distribution after ion implantation, which reduces the carbon vacancy density in the p-well region 16.

[0128] In order to maintain the depth of the p-well region 16 appropriately, the first projected range Rp1 and the second projected range Rp2 are preferably 0.6 μm or less.

[0129] In the method for manufacturing the MOSFET 100 of the first embodiment, a large amount of excess interstitial carbon is present in the silicon carbide layer 10 during the first heat treatment for activating aluminum introduced into the silicon carbide layer 10 by ion implantation. The presence of a large amount of interstitial carbon increases the entropy required to reduce the free energy of the silicon carbide layer 10. Therefore, an increase in carbon vacancies in the silicon carbide layer 10 due to the first heat treatment is suppressed.

[0130] In the manufacturing method of the MOSFET 100 of the first embodiment, the presence of a large amount of excess interstitial carbon in the silicon carbide layer 10 during the first heat treatment inhibits aluminum atoms from entering the carbon sites of the silicon carbide. This promotes the entry of aluminum atoms into the silicon sites of the silicon carbide. This improves the activation rate of aluminum.

[0131] Furthermore, in the method for manufacturing the MOSFET 100 of the first embodiment, the presence of a large amount of excess interstitial carbon in the silicon carbide layer 10 during the first heat treatment suppresses an increase in the carbon vacancy density in the silicon carbide layer 10 even if the first heat treatment is performed at a high temperature. This allows the first heat treatment to be performed at a high temperature, thereby improving the activation rate of aluminum.

[0132] From the viewpoint of improving the activity rate of aluminum, the temperature of the first heat treatment is preferably 1850°C or higher, more preferably 1900°C or higher, and even more preferably 1950°C or higher. From the viewpoint of carrying out an efficient process, the temperature of the first heat treatment is preferably 2000°C or lower. From the viewpoint of the activity rate, a significant increase in the activity rate cannot be expected even if the temperature exceeds 2000°C.

[0133] The first heat treatment preferably comprises a first step at 1600°C or higher and a second step at a lower temperature than the first step. The second step is preferably at 1000°C or lower. The heat treatment time of the second step is preferably longer than that of the first step.

[0134] In the first step, aluminum and phosphorus ions implanted into the silicon carbide layer 10 are activated, and the interstitial carbon fills the carbon vacancies. Even after the carbon vacancies are filled, there is still excess interstitial carbon. Then, in the second low-temperature step, the excess interstitial carbon is expelled from the silicon carbide layer 10 and absorbed into the carbon film 54.

[0135] Fig. 19 is an explanatory diagram of the operation and effect of the method for manufacturing a semiconductor device according to the first embodiment. Fig. 19 is a diagram showing the relationship between the depth from the surface of a silicon carbide layer and the density of carbon vacancies. Fig. 19 assumes that a heat treatment equivalent to activation annealing is performed, regardless of whether ion implantation is performed or not.

[0136] As shown in FIG. 19, the carbon vacancy density of the silicon carbide layer is increased to 1E14 cm by applying a heat treatment equivalent to activation annealing. -3 Furthermore, when aluminum ions are implanted, carbon vacancies are formed in the silicon carbide layer 10 due to the energy of the implanted aluminum ions, and the carbon vacancy density becomes 1E15 cm 3 on the surface. -3 That's all.

[0137] On the other hand, as shown in FIG. 19, when carbon ion implantation is performed in addition to aluminum ion implantation, the carbon vacancy density is increased to 1E11 cm -3 It can be kept as low as below.

[0138] FIG. 20 is a process flow diagram of a method for manufacturing a semiconductor device according to a comparative example.

[0139] As shown in FIG. 20, the method for manufacturing the semiconductor device of the comparative example includes silicon carbide layer preparation (step S100), aluminum ion implantation (step S101), carbon ion implantation (step S102), phosphorus ion implantation (step S103), aluminum ion implantation (step S104), carbon film formation (step S105), first heat treatment (step S106), carbon film removal (step S107), field oxide film formation (step S108), sacrificial oxidation (step S999), silicon oxide film formation (step S111), second heat treatment (step S112), third heat treatment (step S113), gate electrode formation (step S114), interlayer insulating film formation (step S115), and source electrode / drain electrode formation (step S116). The method for manufacturing a semiconductor device of the comparative example differs from the method for manufacturing a semiconductor device of the first embodiment in that it includes sacrificial oxidation (step S999) instead of chemical dry etching treatment (step S109) and hydrogen plasma etching treatment (step S110).

[0140] In the method for manufacturing a semiconductor device of the comparative example, a field oxide film is formed on a silicon carbide layer in step S108, as in the method for manufacturing a semiconductor device of the first embodiment. After that, the field oxide film is removed, and then a sacrificial oxide film is formed on the silicon carbide layer in step S109.

[0141] The sacrificial oxide film is a silicon oxide film formed by thermal oxidation of the surface of the silicon carbide layer. The sacrificial oxide film is then removed by, for example, wet etching.

[0142] When the sacrificial oxide film is formed, the surface of the silicon carbide layer is oxidized. By forming the sacrificial oxide film, for example, impurities and damage on the surface of the silicon carbide layer are removed. Formation of the sacrificial oxide film is a cleaning process.

[0143] Thereafter, in step S111, a silicon oxide film is formed on the silicon carbide layer, as in the method for manufacturing the semiconductor device of the first embodiment. The silicon oxide film will ultimately become a gate insulating layer.

[0144] Fig. 21 is an explanatory diagram of the operation and effect of the method for manufacturing a semiconductor device according to Embodiment 1. Fig. 21 is a diagram showing the relationship between the depth from the surface of a silicon carbide layer and the density of carbon vacancies.

[0145] Fig. 21 is an explanatory diagram of the change in carbon vacancy density due to the formation of a sacrificial oxide film in the semiconductor device manufacturing method of the comparative example, assuming that a heat treatment equivalent to activation annealing is applied regardless of whether ion implantation is performed or not.

[0146] FIG. 21 shows the effect of the formation of a sacrificial oxide film on the carbon vacancy density, with the presence or absence of aluminum ion implantation and the presence or absence of carbon ion implantation as parameters.

[0147] As shown in Figure 21, regardless of whether aluminum ion implantation or carbon ion implantation is performed, the formation of a sacrificial oxide film reduces the ion implantation rate by 1 × 10 18 cm -3 Carbon vacancies of order are formed on the surface of the silicon carbide layer.

[0148] In addition to aluminum ion implantation, carbon ion implantation was performed to increase the carbon vacancy density to 1E11cm -3 Even when the carbon vacancy density on the surface of the silicon carbide layer is suppressed to a low level of 1×10 or less, the formation of a sacrificial oxide film reduces the carbon vacancy density to 1×10 18 cm -3 By forming a sacrificial oxide film, the density of carbon vacancies increases from the surface of the silicon carbide layer to a region about 50 μm deep.

[0149] The reason why many carbon vacancies are formed on the surface of the silicon carbide layer is believed to be that strain occurs on the surface of the silicon carbide layer when a sacrificial oxide film is formed by thermal oxidation.

[0150] In the method for manufacturing a semiconductor device according to the first embodiment, instead of forming a sacrificial oxide film by thermal oxidation, a cleaning process using the CDE method and a subsequent hydrogen etching process are performed.

[0151] Fig. 22 is an explanatory diagram of the operation and effect of the method for manufacturing a semiconductor device according to Embodiment 1. Fig. 22 is a diagram showing the relationship between the depth from the surface of a silicon carbide layer and the density of carbon vacancies.

[0152] 22 is a diagram illustrating the change in carbon vacancy density due to the cleaning process using the CDE method in the semiconductor device manufacturing method according to the first embodiment. In FIG. 22, it is assumed that a heat treatment equivalent to activation annealing is performed, regardless of whether ion implantation is performed or not.

[0153] As shown in Figure 22, the cleaning process using the CDE method reduced the 16 cm -3 Carbon vacancies of order are formed on the surface of the silicon carbide layer.

[0154] In addition to aluminum ion implantation, carbon ion implantation was performed to increase the carbon vacancy density to 1E11cm -3 When the thickness is kept low at or below this, the density of carbon vacancies increases from the surface of the silicon carbide layer to a region of about 10 μm.

[0155] The reason why carbon vacancies are formed during cleaning using the CDE method is thought to be because the surface of the silicon carbide layer is oxidized by using plasma generated from an oxygen-containing gas for etching. However, the amount of oxidation on the surface of the silicon carbide layer is small compared to when a sacrificial oxide film is formed by thermal oxidation. Therefore, it is thought that the increase in carbon vacancy density is significantly suppressed compared to when a sacrificial oxide film is formed by thermal oxidation.

[0156] Furthermore, in the method for manufacturing a semiconductor device according to the first embodiment, after the cleaning process using the CDE method, a hydrogen etching process is performed to etch the surface of the silicon carbide layer.

[0157] By etching the surface of the silicon carbide layer, the carbon vacancy density in the silicon carbide layer can be reduced. For example, referring to the distribution of carbon vacancy density after cleaning treatment using the CDE method shown in FIG. 22, etching the surface of the silicon carbide layer by 10 nm reduces the carbon vacancy density in the surface of the silicon carbide layer to 1E11 cm3 before cleaning treatment. -3 You can return to the following:

[0158] Carbon vacancy density is 1E17cm -3 So, the Hall mobility is 130 cm 2 / V·s, and the carbon vacancy density is expected to be 1E16cm -3 So, the hole mobility is 160 cm 2 / V·s, and the carbon vacancy density is expected to be 1E15cm -3 So, the hole mobility is 180cm 2 / V·s, and the carbon vacancy density is expected to be 1E14 cm -3 So, the hole mobility is 200 cm 2 / V·s, and the carbon vacancy density is expected to be 1E13cm -3 So, the Hall mobility is 250 cm 2 / V·s, and the carbon vacancy density is expected to be 1E12 cm -3 So, the Hall mobility is 300 cm 2 / V·s, and the carbon vacancy density is expected to be 1E11cm -3 So, the Hall mobility is 350 cm 2 / V·s, and the carbon vacancy density is expected to be 5E10cm -3 So, the Hall mobility is 400 cm 2 / V·s, and the carbon vacancy density is expected to be 1E10cm -3 So, the Hall mobility is 450 cm 2 / V·s is expected.

[0159] According to the semiconductor device manufacturing method of the first embodiment, an increase in the carbon vacancy density in the silicon carbide layer can be suppressed by performing a cleaning process using the CDE method and a subsequent hydrogen etching process. Suppressing the increase in the carbon vacancy density can suppress a decrease in the hole mobility in the channel region of the MOSFET. Therefore, according to the semiconductor device manufacturing method of the first embodiment, a MOSFET in which a decrease in carrier mobility is suppressed can be manufactured.

[0160] The cleaning process using the CDE method causes less damage to the surface of the silicon carbide layer being etched. Therefore, for example, roughening of the surface of the silicon carbide layer due to etching damage is also suppressed. Therefore, deterioration of the characteristics of the MOSFET due to roughening of the surface of the silicon carbide layer is suppressed.

[0161] Furthermore, the hydrogen etching process smoothes the surface of the silicon carbide layer, which, for example, suppresses carrier scattering and improves mobility, thereby improving the characteristics of the MOSFET.

[0162] In a cleaning process using the CDE method, the atomic ratio of oxygen atoms to halogen atoms in the gas that generates plasma is preferably 1.5 or more. Having an atomic ratio of oxygen to halogen in the gas that is 1.5 or more improves the flatness of the surface of the silicon carbide layer after etching. For example, when a gas containing CF4 and oxygen (O2) is used as the gas that generates plasma, the flow rate of oxygen (O2) introduced into the etching apparatus is preferably three times or more the flow rate of CF4.

[0163] The temperature of the cleaning treatment using the CDE method is preferably 20° C. or higher, more preferably 50° C. or higher, and even more preferably 100° C. or higher. When the temperature of the cleaning treatment is equal to or higher than the above lower limit, the etching rate of the silicon carbide layer becomes stable.

[0164] The temperature for the cleaning treatment using the CDE method is preferably 1300° C. or less, more preferably 950° C. or less, even more preferably 850° C. or less, and most preferably 750° C. or less. By setting the temperature for the cleaning treatment to the above upper limit or less, the flatness of the surface of the silicon carbide layer after etching is improved.

[0165] The etching amount of the silicon carbide layer by the cleaning treatment using the CDE method is preferably 5 nm to 50 nm, more preferably 10 nm to 25 nm. When the etching amount of the silicon carbide layer is equal to or greater than the above lower limit, impurities and damage on the surface of the silicon carbide layer are effectively removed. Furthermore, when the etching amount of the silicon carbide layer is equal to or less than the above upper limit, the flatness of the surface of the silicon carbide layer after etching is improved.

[0166] The hydrogen etching process is performed in an atmosphere containing hydrogen plasma or atomic hydrogen. By performing the hydrogen etching process in an atmosphere containing active hydrogen, the hydrogen etching process can be performed at a relatively low temperature.

[0167] The temperature of the hydrogen etching treatment is preferably 300°C or less, more preferably 200°C or less, and even more preferably 100°C or less. When the temperature of the hydrogen etching treatment is equal to or less than the above upper limit, the flatness of the surface of the silicon carbide layer after etching is improved. In addition, it becomes possible to selectively etch regions of the silicon carbide layer with a high density of carbon vacancies. In hydrogen etching, etching progresses as hydrogen enters the carbon vacancies in the silicon carbide layer, so the treatment is preferably performed at room temperature (20°C) or higher to sufficiently diffuse the hydrogen.

[0168] The etching amount of the silicon carbide layer by the hydrogen etching treatment is preferably 5 nm or more and 25 nm or less, and more preferably 10 nm or more and 20 nm or less. When the etching amount of the silicon carbide layer is equal to or greater than the above lower limit, the carbon vacancy density in the silicon carbide layer can be effectively reduced. When the etching amount of the silicon carbide layer is equal to or less than the above upper limit, the flatness of the surface of the silicon carbide layer after etching is improved. An etching amount of the silicon carbide layer equal to or less than the above upper limit is sufficient. Even if etching is performed further, the amount of carbon vacancies does not decrease significantly. Since etching hardly proceeds further, additional measures such as raising the temperature to above 300°C are required to proceed with etching. For example, increasing the temperature may deteriorate the flatness of the surface of the silicon carbide layer after etching.

[0169] In the method for manufacturing the MOSFET 100 of the first embodiment, the gate insulating layer 28 is formed by vapor phase epitaxy at a low temperature and a low oxygen partial pressure. Therefore, oxidation of the surface of the silicon carbide layer 10 is suppressed compared to thermal oxidation. Therefore, an increase in carbon vacancies in the silicon carbide layer 10 during the formation of the gate insulating layer 28 is suppressed.

[0170] Furthermore, in the method for manufacturing MOSFET 100 according to the first embodiment, interface termination region 40 is formed by a second heat treatment in an atmosphere containing ammonia gas (NH). Forming interface termination region 40 in an atmosphere containing ammonia gas without interfacial oxidation suppresses an increase in carbon vacancies in silicon carbide layer 10.

[0171] In the method for manufacturing the MOSFET 100 of the first embodiment, after the second heat treatment for forming the interface termination region 40, a third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx).

[0172] The third heat treatment removes nitrogen from the gate insulating layer 28. The third heat treatment forms a gate insulating layer 28 with reduced nitrogen defects.

[0173] (Variation) The method for manufacturing a semiconductor device according to the modified example of the first embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that the second ion implantation of carbon ions is not performed.

[0174] In the method for manufacturing a semiconductor device according to the modification of the first embodiment, carbon ion implantation (step S102) is not performed in the process flow of the method for manufacturing a semiconductor device according to the first embodiment shown in, for example, FIG.

[0175] Fig. 23 is an explanatory diagram of the operation and effect of the method for manufacturing a semiconductor device according to the modified example of Embodiment 1. Fig. 23 is a diagram showing the relationship between the depth from the surface of a silicon carbide layer and the density of carbon vacancies.

[0176] 23 is an explanatory diagram of a change in carbon vacancy density due to a cleaning process using the CDE method in the semiconductor device manufacturing method according to the modified example of Embodiment 1. In FIG. 23, it is assumed that a heat treatment equivalent to activation annealing is performed, regardless of whether ion implantation is performed or not.

[0177] When only aluminum ions are implanted, but not carbon ions, the carbon vacancy density on the surface of the silicon carbide layer is 1E15 cm before the cleaning process using the CDE method. -3 Furthermore, by carrying out cleaning processing using the CDE method, the 16 cm -3 The carbon vacancies are formed on the surface of the silicon carbide layer.

[0178] For example, by etching the silicon carbide layer by about 25 nm from the surface by hydrogen etching, it is possible to return the carbon vacancy density on the surface of the silicon carbide layer to the state before the cleaning process using the CDE method.

[0179] Although the cleaning process using the CDE method has been described as an alternative to sacrificial oxidation, it is also possible to combine the sacrificial oxidation and the cleaning process using the CDE method. In this case, for example, by reducing the amount of oxidation in the sacrificial oxidation, it is possible to suppress an increase in the carbon vacancy density on the surface of the silicon carbide layer.

[0180] As described above, according to the first embodiment and its modified examples, a method for manufacturing a semiconductor device is realized that can reduce the carbon vacancy density in the channel region and suppress a decrease in carrier mobility by performing a cleaning process and a hydrogen etching process using the CDE method.

[0181] (Second embodiment) The method for manufacturing a semiconductor device according to the second embodiment includes forming a p-type silicon carbide film on an n-type silicon carbide layer by epitaxial growth, performing a first etching process to etch the surface of the silicon carbide film in an atmosphere containing plasma generated from a gas containing a halogen element and oxygen, performing a second etching process to etch the surface in an atmosphere containing hydrogen plasma or atomic hydrogen, forming a silicon oxide film on the surface, and forming a gate electrode on the silicon oxide film. The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that the p-type silicon carbide film is formed by epitaxial growth. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0182] The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment has the same structure as the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment shown in Fig. 1. However, the p-well is formed using epitaxial growth rather than ion implantation.

[0183] Fig. 24 is a process flow diagram of the method for manufacturing the semiconductor device of the second embodiment. Fig. 25 and Fig. 26 are explanatory views of the method for manufacturing the semiconductor device of the second embodiment. Fig. 25 and Fig. 26 are cross-sectional views during manufacturing.

[0184] As shown in FIG. 24, the method for manufacturing the semiconductor device of the second embodiment includes silicon carbide layer preparation (step S100), p-well trench formation (step S201), epitaxial film formation (step S202), phosphorus ion implantation (step S103), aluminum ion implantation (step S104), carbon film formation (step S105), first heat treatment (step S106), carbon film removal (step S107), field oxide film formation (step S108), chemical dry etching treatment (step S109), hydrogen plasma etching treatment (step S110), silicon oxide film formation (step S111), second heat treatment (step S112), third heat treatment (step S113), gate electrode formation (step S114), interlayer insulating film formation (step S115), and source electrode / drain electrode formation (step S116).

[0185] The method for manufacturing a semiconductor device of the second embodiment differs from the method for manufacturing a semiconductor device of the first embodiment shown in FIG. 3 in that it includes formation of a trench for a p-well (step S201) and formation of an epitaxial film (step S202) instead of aluminum ion implantation (step S101) and carbon ion implantation (step S102).

[0186] In step S100, an n-type silicon carbide layer 10 is prepared.

[0187] In step S201, a mask material 61 is formed on the surface of the n-type silicon carbide layer 10 by, for example, forming an insulating film and patterning the insulating film by photolithography and etching.

[0188] Next, the n-type silicon carbide layer 10 is etched using the mask material 61 as a mask to form p-well trenches 62 (FIG. 25). The p-well trenches 62 are an example of trenches. The p-well trenches 62 are formed by, for example, reactive ion etching (RIE).

[0189] Next, in step S202, a p-type silicon carbide film is formed on the n-type silicon carbide layer 10 by epitaxial growth (FIG. 26).

[0190] Next, the mask material 61 is removed by, for example, wet etching.

[0191] Thereafter, steps S103 to S116 are performed in the same manner as in the method for manufacturing the semiconductor device of the first embodiment.

[0192] Fig. 27 is an explanatory diagram of the action and effect of the semiconductor device manufacturing method of the second embodiment. Fig. 27 is an explanatory diagram of the change in carbon vacancy density due to the cleaning process using the CDE method in the semiconductor device manufacturing method of the second embodiment. Fig. 27 assumes that a heat treatment equivalent to activation annealing for ion implantation is applied.

[0193] As shown in FIG. 27, before the cleaning process using the CDE method, the carbon vacancy density in the silicon carbide layer was 1E14 cm -3 That's about it.

[0194] As shown in Figure 27, the cleaning process using the CDE method resulted in a 1 × 10 16 cm -3 Carbon vacancies of order are formed on the surface of the silicon carbide layer.

[0195] In the method for manufacturing a semiconductor device according to the second embodiment, a hydrogen etching process is performed after the cleaning process using the CDE method, and the surface of the silicon carbide layer is etched by the hydrogen etching process.

[0196] By etching the surface of the silicon carbide layer, the carbon vacancy density in the silicon carbide layer can be reduced. For example, referring to the distribution of carbon vacancy density after cleaning treatment using the CDE method shown in FIG. 27, etching the surface of the silicon carbide layer by 10 nm reduces the carbon vacancy density to 1E14 cm3 before cleaning treatment. -3 You can return to the following:

[0197] As described above, according to the second embodiment, a method for manufacturing a semiconductor device is realized in which the carbon vacancy density in the channel region is reduced by performing a cleaning process and a hydrogen etching process using the CDE method, thereby suppressing a decrease in carrier mobility.

[0198] (Third embodiment) The method for manufacturing a semiconductor device according to the third embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that, after the first heat treatment and before the first etching treatment, a trench is formed in the silicon carbide layer, and the surface of the silicon carbide layer on which the first etching treatment and the second etching treatment are performed is the sidewall surface of the trench. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0199] 28 is a schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of the third embodiment. The semiconductor device of the third embodiment is a MOSFET 200. The MOSFET 200 is a trench gate type MOSFET having a gate electrode in a trench. The MOSFET 200 is an n-channel type MOSFET that uses electrons as carriers.

[0200] The MOSFET 200 includes a silicon carbide layer 10 , a gate insulating layer 28 , a gate electrode 30 , an interlayer insulating film 32 , a source electrode 34 , a drain electrode 36 , an interface termination region 40 , and a trench 50 .

[0201] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0202] The trench 50 penetrates the source region 18 and the p-well region 16 and reaches the drift region 14. The bottom surface of the trench 50 is located in the drift region 14.

[0203] A gate insulating layer 28 and a gate electrode 30 are provided in the trench 50. The side surface of the trench 50 is, for example, a surface having an off angle of 0 to 8 degrees with respect to the m-plane. The side surface of the trench 50 is, for example, a surface having an off angle of 0 to 8 degrees with respect to the a-plane.

[0204] The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0205] The depth of the p-well region 16 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 16 functions as a channel region of the MOSFET 200. The channel region of the MOSFET 200 contacts the sidewall surface of the trench 50.

[0206] The electron hole mobility in the channel region is, for example, 200 cm 2 / V·s or more.

[0207] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a terminating element that terminates dangling bonds in the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0208] The nitrogen concentration in the interface termination region 40 is, for example, 1×10 21 cm -3 That's all.

[0209] Next, an example of a method for manufacturing the semiconductor device according to the third embodiment will be described.

[0210] Fig. 29 is a process flow diagram of the method for manufacturing the semiconductor device of the third embodiment. Fig. 30, Fig. 31, Fig. 32, Fig. 33, and Fig. 34 are explanatory views of the method for manufacturing the semiconductor device of the third embodiment. Fig. 30 to Fig. 34 are cross-sectional views during manufacturing.

[0211] As shown in FIG. 29, the method for manufacturing the semiconductor device of the third embodiment includes silicon carbide layer preparation (step S100), aluminum ion implantation (step S101), carbon ion implantation (step S102), phosphorus ion implantation (step S103), aluminum ion implantation (step S104), carbon film formation (step S105), first heat treatment (step S106), carbon film removal (step S107), field oxide film formation (step S108), gate trench formation (step S301), chemical dry etching treatment (step S109), hydrogen plasma etching treatment (step S110), silicon oxide film formation (step S111), second heat treatment (step S112), third heat treatment (step S113), gate electrode formation (step S114), interlayer insulating film formation (step S115), and source electrode / drain electrode formation (step S116).

[0212] The method for manufacturing a semiconductor device of the third embodiment differs from the method for manufacturing a semiconductor device of the first embodiment in that it includes gate trench formation (step S301) between field oxide film formation (step S108) and chemical dry etching processing (step S109).

[0213] In step S100, an n-type silicon carbide layer 10 is prepared. The upper surface of the n-type silicon carbide layer 10 is a surface inclined at an angle of 0 to 8 degrees with respect to the silicon surface. + type drain region 12 and n - The semiconductor device includes a drift region 14. The drift region 14 is formed on the drain region 12 by, for example, epitaxial growth.

[0214] The drain region 12 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×1018 cm -3 More than 1×10 21 cm -3 The following is the result.

[0215] The drift region 14 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0216] In step S101, the p-well region 16 is formed by aluminum ion implantation.

[0217] In step S102, carbon ions are implanted into the p-well region 16.

[0218] In step S103, phosphorus (P) is ion-implanted into the p-well region 16 to form the source region 18.

[0219] In step S104, aluminum is ion-implanted into the p-well region 16 to form the p-well contact region 20 (FIG. 30).

[0220] In step S105, a carbon film is formed on silicon carbide layer 10.

[0221] In step S106, a first heat treatment is performed, which is an activation annealing of aluminum and phosphorus.

[0222] In step S107, the carbon film 54 is removed.

[0223] In step S108, a field oxide film is formed on silicon carbide layer 10. Next, the field oxide film is removed.

[0224] In step S301, a mask material 71 is formed on the upper surface of the silicon carbide layer 10 by, for example, forming an insulating film and patterning the insulating film by photolithography and etching.

[0225] Next, the n-type silicon carbide layer 10 is etched using the mask material 71 as a mask to form a gate trench 72 (FIG. 31). The gate trench 72 is formed by using, for example, an RIE method. The gate trench 72 is an example of a trench. The gate trench 72 will eventually become the trench 50.

[0226] The sidewall surface of the gate trench 72 has an inclination of, for example, 0 to 8 degrees with respect to the m-plane, or an inclination of 0 to 8 degrees with respect to the a-plane.

[0227] Next, the mask material 71 is removed by, for example, wet etching.

[0228] In step S109, a chemical dry etching process is performed to etch the sidewall surface of the gate trench 72 by a chemical dry etching method (CDE method) (FIG. 32). The chemical dry etching process is an example of a first etching process.

[0229] In step S110, a hydrogen etching process is performed to etch the sidewall surface of the gate trench 72 in an atmosphere containing hydrogen plasma or atomic hydrogen (FIG. 33). The hydrogen etching process is an example of a second etching process.

[0230] In step S111, a silicon oxide film is formed on the silicon carbide layer 10. The silicon oxide film will eventually become the gate insulating layer .

[0231] In step S112, a second heat treatment is performed in an atmosphere containing ammonia gas (NH3). By the second heat treatment, an interface termination region 40 is formed at the interface between the silicon carbide layer 10 and the silicon oxide film.

[0232] In step S113, a third heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx).

[0233] In step S114, the gate electrode 30 is formed on the gate insulating layer .

[0234] In step S115, an interlayer insulating film 32 is formed on the gate electrode 30 (FIG. 34).

[0235] In step S116, the source electrode 34 and the drain electrode 36 are formed.

[0236] By the above manufacturing method, the MOSFET 200 shown in FIG. 28 is formed.

[0237] The method for manufacturing a semiconductor device according to the third embodiment performs cleaning and hydrogen etching by the CDE method, similarly to the method for manufacturing a semiconductor device according to the first embodiment. Therefore, with the same effects and advantages as the method for manufacturing a semiconductor device according to the first embodiment, it is possible to reduce the carbon vacancy density in the channel region and suppress a decrease in the carrier mobility of the MOSFET 200.

[0238] The MOSFET 200 manufactured by the method for manufacturing a semiconductor device according to the third embodiment is a trench-gate MOSFET. The channel region of the MOSFET 200 is in contact with the sidewall surface of the trench 50.

[0239] The sidewall surface of trench 50 has an inclination with respect to the m-plane of 0 to 8 degrees, or an inclination with respect to the a-plane of 0 to 8 degrees. It is known that the thermal oxidation rate of the m-plane and the a-plane is higher than that of the silicon plane.

[0240] When the sidewall surface of the trench 50 formed on the m-plane or a-plane is cleaned by sacrificial oxidation, the amount of oxidation increases compared to the case of the silicon surface, and it is expected that the carbon vacancy density in the channel region will increase. The increase in the carbon vacancy density in the channel region will further reduce the carrier mobility of the MOSFET.

[0241] In the semiconductor device manufacturing method of the third embodiment, a cleaning process using the CDE method and a hydrogen etching process are performed instead of a cleaning process using sacrificial oxidation. The semiconductor device manufacturing method of the third embodiment does not involve thermal oxidation. Therefore, even on the m-plane or a-plane, a decrease in carrier mobility in the MOSFET 200 can be suppressed, as in the case of the silicon plane. The semiconductor device manufacturing method of the third embodiment is particularly effective for MOSFETs with a trench gate structure in which the channel region is in contact with the m-plane or a-plane.

[0242] As described above, according to the third embodiment, a method for manufacturing a semiconductor device is realized that can reduce the carbon vacancy density in the channel region and suppress a decrease in carrier mobility by performing a cleaning process and a hydrogen etching process using the CDE method.

[0243] (Fourth embodiment) A semiconductor device manufacturing method according to the fourth embodiment includes forming a p-type silicon carbide film on an n-type silicon carbide layer using epitaxial growth. After forming the silicon carbide film, a trench is formed in the silicon carbide film before a first etching process. A first etching process is performed to etch the surface of the silicon carbide film in an atmosphere containing plasma generated from a gas containing halogen elements and oxygen. A second etching process is performed to etch the surface in an atmosphere containing hydrogen plasma or atomic hydrogen. A silicon oxide film is formed on the surface, and a gate electrode is formed on the silicon oxide film. The semiconductor device manufacturing method according to the fourth embodiment differs from the semiconductor device manufacturing method according to the third embodiment in that a p-type silicon carbide film is formed using epitaxial growth. Hereinafter, some of the details overlapping with those of the third embodiment may be omitted.

[0244] The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment has the same structure as the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment shown in Fig. 28. However, the p-well is formed by epitaxial growth rather than by ion implantation.

[0245] Fig. 35 is a process flow diagram of the method for manufacturing the semiconductor device of the fourth embodiment. Fig. 36 and Fig. 37 are explanatory views of the method for manufacturing the semiconductor device of the fourth embodiment. Fig. 36 and Fig. 37 are cross-sectional views during manufacturing.

[0246] As shown in FIG. 35, the method for manufacturing the semiconductor device of the fourth embodiment includes silicon carbide layer preparation (step S100), epitaxial film formation (step S401), phosphorus ion implantation (step S103), aluminum ion implantation (step S104), carbon film formation (step S105), first heat treatment (step S106), carbon film removal (step S107), field oxide film formation (step S108), gate trench formation (step S301), chemical dry etching treatment (step S109), hydrogen plasma etching treatment (step S110), silicon oxide film formation (step S111), second heat treatment (step S112), third heat treatment (step S113), gate electrode formation (step S114), interlayer insulating film formation (step S115), and source electrode / drain electrode formation (step S116).

[0247] The manufacturing method of the semiconductor device of the fourth embodiment differs from the manufacturing method of the semiconductor device of the third embodiment shown in FIG. 29 in that it includes epitaxial film formation (step S401) instead of aluminum ion implantation (step S101) and carbon ion implantation (step S102).

[0248] In step S100, an n-type silicon carbide layer 10 is prepared (FIG. 36).

[0249] In step S401, a p-type silicon carbide film 74 is formed by epitaxial growth on the n-type silicon carbide layer 10 (FIG. 37). A part of the p-type silicon carbide film 74 will eventually become the p-well region 16.

[0250] Thereafter, steps S103 to S116 are performed in the same manner as in the semiconductor device manufacturing method of the third embodiment.

[0251] The method for manufacturing a semiconductor device according to the fourth embodiment performs cleaning and hydrogen etching by the CDE method, similarly to the method for manufacturing a semiconductor device according to the third embodiment. Therefore, with the same effects and advantages as those of the method for manufacturing a semiconductor device according to the third embodiment, it is possible to reduce the carbon vacancy density in the channel region and suppress a decrease in the carrier mobility of the MOSFET 200.

[0252] As described above, according to the fourth embodiment, a method for manufacturing a semiconductor device is realized in which the carbon vacancy density in the channel region is reduced by performing a cleaning process and a hydrogen etching process using the CDE method, thereby suppressing a decrease in carrier mobility.

[0253] In the above, the first to fourth embodiments have been described using 4H—SiC as an example of the crystal structure of silicon carbide, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0254] Furthermore, in the first to fourth embodiments, the gate insulating layer 28 is provided on the silicon face, m face, or a face of the silicon carbide layer. However, the present invention can also be applied to cases where the gate insulating layer 28 is provided on other faces of silicon carbide, such as the carbon face or (0-33-8) face.

[0255] The present invention can also be applied to an n-channel IGBT (Insulated Gate Bipolar Transistor).

[0256] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0257] 10 Silicon carbide layer 57 Silicon oxide film 62 P-well trench (trench) 72 Gate trench (trench)

Claims

1. performing a first ion implantation of aluminum into the silicon carbide layer at a first dose; A first heat treatment is performed at 1600°C or more, performing a first etching process of etching a surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen; performing a second etching process in which the surface is etched in an atmosphere containing hydrogen plasma or atomic hydrogen; forming a silicon oxide film on the surface; forming a gate electrode on the silicon oxide film; In the second etching treatment, the surface is etched by 5 nm to 25 nm.

2. A method for manufacturing a silicon carbide layer, comprising: performing a first ion implantation step of implanting aluminum into the silicon carbide layer at a first dose; A first heat treatment is performed at 1600°C or more, performing a first etching process of etching a surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen; performing a second etching process in which the surface is etched in an atmosphere containing hydrogen plasma or atomic hydrogen; forming a silicon oxide film on the surface; forming a gate electrode on the silicon oxide film; forming a trench in the silicon carbide layer after the first heat treatment and before the first etching treatment; The method for manufacturing a semiconductor device, wherein the surface is a sidewall surface of the trench.

3. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising, before the first heat treatment, performing a second ion implantation of carbon into the silicon carbide layer at a second dose that is at least 10 times the first dose.

4. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching process is performed using an etching apparatus in which a plasma generating section and an etching section are separated from each other.

5. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching process is an isotropic etching process.

6. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the gas used in the first etching process includes a perfluorocarbon.

7. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching process is performed at a temperature of 20.degree. C. or more and 1300.degree. C. or less.

8. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second etching process is performed at a temperature of 20.degree. C. or more and 300.degree. C. or less.

9. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching process etches the surface by 5 nm to 50 nm.

10. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the surface has an inclination of 0 to 8 degrees with respect to the a-plane, or an inclination of 0 to 8 degrees with respect to the m-plane.

11. forming a trench in the silicon carbide layer after the first heat treatment and before the first etching treatment; 2. The method for manufacturing a semiconductor device according to claim 1, wherein said surface is a sidewall surface of said trench.

12. forming a p-type silicon carbide film on the n-type silicon carbide layer by epitaxial growth; a first etching process is performed in which the surface of the silicon carbide film is etched in an atmosphere containing plasma generated from a gas containing a halogen element and oxygen; performing a second etching process in which the surface is etched in an atmosphere containing hydrogen plasma or atomic hydrogen; forming a silicon oxide film on the surface; forming a gate electrode on the silicon oxide film; In the second etching treatment, the surface is etched by 5 nm to 25 nm.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first etching process is performed using an etching apparatus in which a plasma generating section and an etching section are separated from each other.

14. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first etching process is an isotropic etching process.

15. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the gas used in the first etching process includes a perfluorocarbon.

16. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first etching process is performed at a temperature of 20[deg.] C. or more and 1300[deg.] C. or less.

17. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the second etching process is performed at a temperature of 20[deg.] C. or more and 300[deg.] C. or less.

18. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first etching process etches the surface by 5 nm to 50 nm.

19. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the surface has an inclination of 0 to 8 degrees with respect to the a-plane, or an inclination of 0 to 8 degrees with respect to the m-plane.

20. After forming the silicon carbide film, and before the first etching treatment, a trench is formed in the silicon carbide film; The method for manufacturing a semiconductor device according to claim 12 , wherein the surface is a sidewall surface of the trench.

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