Light-emitting device and display device including the same

Abstract

To provide a light emitting element capable of reducing electrode disconnection failure.SOLUTION: A light emitting element according to one embodiment of the present specification includes a first semiconductor layer, a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer, a light emitting layer positioned between a plurality of first electrodes on the first semiconductor layer, a second semiconductor layer positioned on the light emitting layer, a second electrode positioned on the second semiconductor layer, and a passivation layer covering at least a portion of the first semiconductor layer, the light emitting layer, and the second semiconductor layer, and a plurality of first openings are formed in the passivation layer, exposing portions of the upper surface and side surfaces of the plurality of first electrodes.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present specification relates to a light emitting device and a display device including the same, and more particularly to a light emitting device capable of minimizing disconnection defects and a display device including the same. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and are therefore highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a light emitting diode capable of reducing the occurrence of electrode disconnection defects.

[0006] Another problem to be solved by the present invention is to provide a display device in which pixel defects are minimized by preventing disconnection of a light emitting element.

[0007] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A light-emitting device according to an embodiment of the present specification includes a first semiconductor layer, a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer between the plurality of first electrodes, a second semiconductor layer disposed on the light-emitting layer, a second electrode disposed on the second semiconductor layer, and a passivation layer covering at least a portion of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, wherein a plurality of first openings exposing a portion of an upper surface and a portion of a side surface of the plurality of first electrodes are disposed in the passivation layer, thereby reducing disconnection defects of the first electrodes in a display device.

[0009] A display device according to an embodiment of the present disclosure includes a substrate defining pixels each including a plurality of sub-pixels, and a plurality of light-emitting elements disposed in the plurality of sub-pixels, each including a plurality of first electrodes and a plurality of second electrodes, wherein the light-emitting elements include a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer between the plurality of first electrodes, a second semiconductor layer disposed on the light-emitting layer, and a passivation layer covering the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, wherein the plurality of first electrodes are disposed on one side and the other side of the first semiconductor layer, the second electrode is disposed on the second semiconductor layer, and a plurality of first openings are disposed in the passivation layer exposing portions of upper surfaces and portions of side surfaces of the plurality of first electrodes. This minimizes disconnection of the light-emitting elements, thereby improving the luminous efficiency of the display device.

[0010] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0011] In the present specification, the height of the upper surface of the passivation layer disposed around the first electrodes can be lowered by not disposing a passivation layer on a portion of the upper surface or a portion of the side surface of a plurality of first electrodes disposed on one side and the other side of the light-emitting element.

[0012] This specification can prevent the problem of a connection electrode disposed on the passivation layer and connected to the first electrode being damaged during the manufacturing process by lowering the height of the upper surface of the passivation layer above part of the upper surface or part of the side surface of the first electrode.

[0013] The present invention can prevent the occurrence of disconnection defects between the first electrode and the connection electrode that occur when the first electrode is etched.

[0014] The present disclosure provides a light emitting device in which a plurality of first electrodes are partially exposed, and a display device including the light emitting device, which can reduce pixel defects caused by disconnection of the first electrodes.

[0015] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic plan view of a light emitting device according to an embodiment of the present specification; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 3] 1 is a schematic configuration diagram of a display device according to an embodiment of the present specification. [Figure 4a] 1 is a partial cross-sectional view of a display device according to an embodiment of the present specification. [Figure 4b] 1 is a perspective view of a tiling display device according to an embodiment of the present specification; [Figure 5] FIG. 2 is a cross-sectional view of one sub-pixel of a display device according to an embodiment of the present specification. [Figure 6a]10 is an SEM image of a light-emitting element in a step of applying and etching a photoresist after arranging a first connection wiring during a manufacturing process of a display device of a comparative example. [Figure 6b] 10 is a SEM image of a light emitting device in a step of applying and etching a photoresist after arranging a first connecting wire during a manufacturing process of a display device of a comparative example. [Figure 7] FIG. 10 is a schematic plan view of a light emitting device according to another embodiment of the present specification. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII′ in FIG. 7. DETAILED DESCRIPTION OF THE INVENTION

[0017] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the present invention to those skilled in the art.

[0018] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0019] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0020] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0021] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0022] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0023] Like reference numbers refer to like elements throughout the specification.

[0024] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0025] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0026] In the following, the present specification will be described with reference to the drawings.

[0027] 1 is a schematic plan view of a light emitting device according to an embodiment of the present specification, and FIG 2 is a cross-sectional view taken along line II-II' of FIG 1.

[0028] Referring to Figures 1 and 2, a light-emitting element LED according to one embodiment of the present specification includes a first semiconductor layer NL, a plurality of first electrodes NE, an emission layer EL, a second semiconductor layer PL, a second electrode PE, and a passivation layer PAS.

[0029] The first semiconductor layer NL may be a layer formed by doping a specific material with n-type or p-type impurities. For example, the first semiconductor layer NL may be a layer formed by doping n-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The n-type impurities may be, but are not limited to, silicon (Si), germanium (Sn), tin (Sn), etc.

[0030] A plurality of first electrodes NE are arranged on one side and the other side of the first semiconductor layer NL. The plurality of first electrodes may be, for example, a plurality of n-type electrodes. The plurality of first electrodes may be electrodes for electrically connecting the driving transistor DT and the first semiconductor layer NL. Each of the plurality of first electrodes NE is arranged on the upper surface of both sides of the first semiconductor layer NL exposed by the light-emitting layer EL and the second semiconductor layer PL described below.

[0031] The first electrodes NE may have a fan-shaped planar shape. In this case, the pointed vertices of the first electrodes NE may be disposed adjacent to the light-emitting layer EL. The arc-shaped sides of the first electrodes NE may be disposed outward away from the light-emitting layer EL. The first electrodes NE may have a circular, elliptical, or polygonal shape, without being limited thereto.

[0032] At least some of the side surfaces and at least some of the top surfaces of the plurality of first electrodes NE may be covered by a passivation layer PAS, which will be described later. Furthermore, other parts of the side surfaces and other parts of the top surfaces of the plurality of first electrodes NE may be exposed and not covered by the passivation layer PAS. Specifically, at least some of the side surfaces and at least some of the top surfaces of the plurality of first electrodes NE adjacent to the light-emitting layer EL may be covered by the passivation layer PAS. As a result, other parts of the side surfaces and other parts of the top surfaces of the plurality of first electrodes NE may be exposed and not covered by the passivation layer PAS.

[0033] The cross-sectional distance between each of the plurality of first electrodes NE and the side surface closest to the light-emitting layer EL may be shorter than the cross-sectional distance between each of the plurality of first electrodes NE and the side surface farthest from the light-emitting layer EL and the end of the first semiconductor layer NL. Each of the plurality of first electrodes NE may be disposed so as to be closer to the light-emitting layer EL than the end of the first semiconductor layer NL.

[0034] The plurality of first electrodes NE may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0035] The light-emitting layer EL is disposed between a plurality of first electrodes NE on the first semiconductor layer NL. The light-emitting layer EL can emit light by receiving holes and electrons from the first semiconductor layer NL and a second semiconductor layer PL (described later). The light-emitting layer EL may have a single-layer or multi-quantum well (MQW) structure and may be made of, for example, indium gallium nitride (InGaN), gallium arsenide (GaAs), gallium nitride (GaN), or the like, but is not limited thereto.

[0036] A second semiconductor layer PL is disposed on the light-emitting layer EL. The second semiconductor layer PL may be formed by doping a specific material with p-type impurities. For example, the second semiconductor layer PL may be a layer in which a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. is doped with p-type impurities. In this case, the p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., but are not limited thereto.

[0037] A second electrode PE is disposed on the second semiconductor layer PL. The second electrode PE may be an electrode for electrically connecting a power supply wiring to the second semiconductor layer PL. The side surfaces of the second electrode PE may be covered with a passivation layer PAS, which will be described later. Furthermore, at least a portion of the upper surface of the second electrode PE may be covered with the passivation layer PAS. As a result, another portion of the upper surface of the second electrode PE may be exposed and not covered by the passivation layer PAS.

[0038] The second electrode PE may have a circular, elliptical or polygonal shape in plan view. The second electrode PE may be disposed in the center of the upper surface of the second semiconductor layer PL.

[0039] The second electrode PE may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0040] Meanwhile, one of the first electrode NE and the second electrode PE of the light-emitting element LED may include a ferromagnetic material such as iron (Fe), cobalt (Co), or nickel (Ni). This allows the light-emitting element LED to be moved by a magnetic field, but is not limited thereto. The passivation layer PAS covers at least a portion of the first semiconductor layer NL, the light-emitting layer EL, and the second semiconductor layer PL. The passivation layer PAS may cover the side surfaces of the first semiconductor layer NL. The passivation layer PAS may also cover at least a portion of the top surface of the first semiconductor layer NL. The passivation layer PAS may include a first opening OA1 exposing at least a portion of the top surface of the first semiconductor layer NL. Thus, a portion of the end of the passivation layer PAS may contact the top surface of the first semiconductor layer NL. The exposed portion of the top surface of the first semiconductor layer NL may be located farther from the light-emitting layer EL than the first electrode NE. At least a portion of the end of the passivation layer PAS in contact with the upper surface of the first semiconductor layer NL may be spaced apart from the first electrode NE.

[0041] The first opening OA1 may have at least a portion of its planar shape that is arc-shaped or polygonal. In this case, the arc-shaped portion may be convex toward the side away from the light-emitting layer EL. The arc-shaped side surface of the first opening OA1 may be positioned outward from the arc-shaped side surface of the first electrode NE. At least one end of the first opening OA1 may be positioned outward from at least one end of the first electrode NE. The exposed first semiconductor layer NL may be positioned between the arc-shaped side surface of the first opening OA1 and the arc-shaped side surface of the first electrode NE. This allows the planar shape of the top surface of the portion of the first semiconductor layer NL exposed by the first opening OA1 to include arc-shaped portions on both sides.

[0042] The passivation layer PAS may expose portions of the upper surfaces and portions of the side surfaces of the plurality of first electrodes NE through the first openings OA1. Specifically, the passivation layer PAS may expose portions of the arc-shaped side surfaces of the first electrodes NE. The passivation layer PAS may cover portions of the upper surfaces of the first electrodes NE connected to the linear side surfaces of the first electrodes NE. The passivation layer PAS may expose portions of the upper surfaces of the first electrodes NE connected to the arc-shaped side surfaces of the first electrodes NE. The area of ​​the exposed upper surfaces of the first electrodes NE may be larger than the area of ​​the exposed upper surfaces of the first semiconductor layers NL.

[0043] The passivation layer PAS covers the side surfaces of the light-emitting layer EL. The passivation layer PAS also covers the side surfaces and top surface of the second semiconductor layer PL. The passivation layer PAS, which covers the top surface and side surfaces of the second semiconductor layer PL and the side surfaces of the light-emitting layer EL, may extend to a portion of the side surfaces and a portion of the top surface of the first electrode NE. Therefore, a portion of the side surfaces and a portion of the top surface of the first electrode NE adjacent to the light-emitting layer EL may be covered by the passivation layer PAS. The passivation layer PAS may cover a linear side surface among the side surfaces of the first electrode NE and a portion of the top surface adjacent thereto. The side surface of the first electrode NE closest to the light-emitting layer EL may be positioned closer to the light-emitting layer EL than the side surface of the first opening OA1 closest to the light-emitting layer EL.

[0044] The passivation layer PAS may cover the side surfaces of the second electrode PE. The passivation layer PAS may also cover a portion of the upper surface of the second electrode PE. Therefore, the passivation layer PAS may include a second opening OA2 that exposes a portion of the upper surface of the second electrode PE. The second opening OA2 may be disposed in the center of the upper surface of the second electrode PE. The second opening OA2 may have a circular or elliptical planar shape. The planar shape of the second opening OA2 may correspond to the planar shape of the upper surface of the second electrode PE. The planar area of ​​the second opening OA2 may be smaller than the planar area of ​​the second electrode PE. The passivation layer PAS may be disposed on the second electrode PE so as to surround the second opening OA2. The second opening OA2 may be disposed between the multiple first openings OA1. The distances from the second opening OA2 to the multiple first openings OA1 may be the same.

[0045] A display device 100 including a light emitting device according to an embodiment of the present specification will be described below with reference to FIGS.

[0046] FIG. 3 is a schematic diagram of a display device according to an embodiment of the present specification.

[0047] For ease of explanation, Fig. 3 shows only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among the various components of the display device 100. Furthermore, the light emitting element LED of the display device 100 of Figs. 3 to 6 is the same as the light emitting element LED of Figs. 1 and 2, so a duplicated description will be omitted.

[0048] Referring to FIG. 3, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0049] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided by the timing controller TC. Although one gate driver GD is shown as being spaced apart from one side of the display panel PN in FIG. 1, the number and arrangement of the gate drivers GD are not limited thereto.

[0050] The data driver DD converts image data input from the timing controller TC into data voltages using a reference gamma voltage in response to a plurality of data control signals provided from the timing controller TC, and supplies the converted data voltages to a plurality of data lines DL.

[0051] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC then supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0052] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL intersect with each other in the display panel PN, and each of the sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, although not shown in the drawings, each of the sub-pixels SP may be connected to a high-potential power supply line VDD, a low-potential power supply line VDD, a reference line, etc.

[0053] A display area AA and a non-display area NA surrounding the display area AA can be defined on the display panel PN.

[0054] The display area AA is an area where an image is displayed on the display device 100. A plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. The plurality of sub-pixels SP are the smallest unit constituting the display area AA, and n sub-pixels SP may form one pixel PX. A light-emitting element LED and a thin-film transistor for driving the light-emitting element LED may be arranged in each of the plurality of sub-pixels SP. The light-emitting elements LED may be defined differently depending on the type of the display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel PN, the light-emitting element LED may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0055] A plurality of signal lines are arranged in the display area AA to transmit various signals to the subpixels SP. For example, the signal lines may include a plurality of data lines DL that supply data voltages to the subpixels SP, and a plurality of scan lines SL that supply gate voltages to the subpixels SP. The scan lines SL may extend in one direction from the display area AA to be connected to the subpixels SP, and the data lines DL may extend in a direction different from the one direction from the display area AA to be connected to the subpixels SP. In addition, a low-potential power supply line VDD, a high-potential power supply line VDD, etc. may also be arranged in the display area AA, but are not limited thereto.

[0056] The non-display area NA is an area where no image is displayed and may be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, as well as driving ICs such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0057] Meanwhile, the non-display area NA may be located on the rear surface of the display panel PN, that is, on a surface without sub-pixels SP, or may be omitted, and is not limited to what is shown in the drawings.

[0058] Meanwhile, drivers such as the gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD may be implemented in the non-display area NA using a GIP (Gate In Panel) method, or may be implemented between multiple sub-pixels SP in the display area AA using a GIA (Gate In Active Area) method. For example, the data driver DD and timing controller TC may be formed on a separate flexible film and printed circuit board and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. If the gate driver GD is implemented using the GIP method and the data driver DD and timing controller TC transmit signals to the display panel PN through pad electrodes in the non-display area NA, it is necessary to secure an area in the non-display area NA for arranging the gate driver GD and the pad electrodes, which may increase the bezel.

[0059] Alternatively, if the gate driver GD is mounted within the display area AA using the GIA method, and side wiring SRL is formed to connect signal wiring on the front side of the display panel PN to pad electrodes on the rear side of the display panel PN, and a flexible film and a printed circuit board are bonded to the rear side of the display panel PN, the non-display area NA on the front side of the display panel PN can be minimized. That is, if the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN in the above manner, a zero-bezel configuration in which there is essentially no bezel may be possible. For a more detailed description, refer to Figures 4a and 4b.

[0060] 4a and 4b are partial cross-sectional and perspective views of a display device according to an embodiment of the present disclosure, respectively;

[0061] 4A, a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels SP are arranged in a non-display area NA of a display panel PN. For example, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is arranged in the non-display area NA on the front side of the display panel PN, and a second pad electrode PAD2 electrically connected to driving components such as a flexible film and a printed circuit board is arranged in the non-display area NA on the rear side of the display panel PN.

[0062] In this case, although not shown in the drawing, various signal wirings connected to multiple subpixels SP, such as scan wirings SL and data wirings DL, may extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0063] Side wiring SRL is disposed along the side of the display panel PN. The side wiring SRL electrically connects a first pad electrode PAD1 on the front surface of the display panel PN to a second pad electrode PAD2 on the rear surface of the display panel PN. Thus, signals from driving components on the rear surface of the display panel PN can be transmitted to the sub-pixels SP through the second pad electrode PAD2, the side wiring SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front surface to the side and rear surface of the display panel PN, thereby minimizing the area of ​​the non-display region NA of the display panel PN.

[0064] 4b, a tiling display device TD having a large screen can be configured by connecting a plurality of display devices 100. In this case, when the tiling display device TD is configured using the display device 100 with a minimized bezel as shown in FIG. 4a, a seam area where no image is displayed between the display devices 100 can be minimized, thereby improving display quality.

[0065] For example, a plurality of sub-pixels SP may form one pixel PX, and the interval between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 may be configured to be the same as the interval between pixels PX within one display device 100. Therefore, the interval between pixels PX may be configured to be constant between display devices 100, thereby minimizing seam areas.

[0066] However, FIGS. 4a and 4b are merely examples, and the display device 100 according to an embodiment of the present specification may be a general display device 100 having a bezel, and is not limited thereto.

[0067] FIG. 5 is a cross-sectional view of one subpixel of a display device according to an embodiment of the present specification.

[0068] Referring to FIG. 5, each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to one embodiment of the present specification may include a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, an adhesive layer 116, a second planarization layer 117, a third planarization layer 118, a driving transistor DT, a light-emitting element LED, a plurality of reflective electrodes RE, a plurality of first connection electrodes CE1, a second connection electrode CE2, a light-shielding layer LS, and an auxiliary electrode LE.

[0069] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also be made of a flexible material including a polymer or plastic.

[0070] A light-shielding layer LS may be disposed in each of the sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident on an active layer ACT of a driving transistor DT (described later) below the substrate 110. The light-shielding layer LS blocks light incident on the active layer ACT of the driving transistor DT, thereby minimizing leakage current.

[0071] A buffer layer 111 may be disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of, for example, but not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, and is not limited thereto.

[0072] The drive transistor DT is disposed on the buffer layer 111. The drive transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0073] An active layer ACT may be disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. The buffer layer 111 may include a contact hole for connecting the auxiliary electrode LE and the light-shielding layer LS.

[0074] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE. The gate insulating layer 112 may include a contact hole for connecting the auxiliary electrode LE and the light-shielding layer LS. The gate insulating layer 112 may further include a contact hole for connecting the source electrode SE and the active layer ACT. The gate insulating layer 112 may be formed of, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0075] A gate electrode GE may be disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0076] An auxiliary electrode LE may be disposed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS under the buffer layer 111 to one of the source electrode SE and the drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to one of the source electrode SE or the drain electrode DE through the auxiliary electrode LE and does not function as a floating gate, thereby minimizing fluctuations in the threshold voltage of the driving transistor DT caused by the floating light-shielding layer LS. Although the light-shielding layer LS is illustrated as being connected to the source electrode SE in the drawings, the light-shielding layer LS may be connected to the drain electrode DE and is not limited thereto.

[0077] A first interlayer insulating layer 113 may be disposed on the gate electrode GE and the auxiliary electrode LE. The first interlayer insulating layer 113 may include a contact hole for connecting the source electrode SE and the auxiliary electrode LE. The first interlayer insulating layer 113 may also include a contact hole for connecting the source electrode SE and the active layer ACT. The first interlayer insulating layer 113 is an insulating layer for protecting components below the first interlayer insulating layer 113, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0078] A conductive layer TM may be disposed on the first interlayer insulating layer 113. The conductive layer TM may be disposed on the gate electrode GE. The conductive layer TM may also form a storage capacitor (not shown) together with the gate electrode GE. However, the conductive layer TM may be omitted depending on the embodiment.

[0079] A second interlayer insulating layer 114 may be disposed on the conductive layer TM. Contact holes for connecting the source electrode SE and the drain electrode DE to the active layer ACT may be formed in the second interlayer insulating layer 114. The second interlayer insulating layer 114 is an insulating layer for protecting the underlying components and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0080] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT may be disposed on the second interlayer insulating layer 114. The source electrode SE may be connected to the active layer ACT and the auxiliary electrode LE through contact holes included in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The drain electrode DE may be connected to the active layer ACT through contact holes included in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0081] A first planarization layer 115 may be disposed on the driving transistor DT. The first planarization layer 115 may planarize the upper surface of the substrate 110 on which the driving transistor DT is disposed. The planarization layer 115 may include a contact hole for connecting the reflective electrode RE and the drain electrode DE. The first planarization layer 115 may be configured as a single layer or multiple layers and may be made of, for example, photoresist or an acrylic organic material, but is not limited thereto.

[0082] At least one reflective electrode RE may be disposed on the first planarization layer 115. The reflective electrode RE may be connected to the drain electrode DE of the driving transistor DT through a contact hole included in the first planarization layer 115. In addition, a plurality of reflective electrodes RE may be formed to electrically connect the light emitting element LED to a power wiring (not shown). The reflective electrode RE may be disposed below the light emitting element LED and function as a reflector that reflects light emitted from the light emitting element LED toward the upper portion of the light emitting element LED. The plurality of reflective electrodes RE may be formed of a conductive material with excellent reflective properties and may reflect light emitted from the light emitting element LED toward the upper portion of the light emitting element LED.

[0083] An adhesive layer 116 may be disposed on the reflective electrode RE. The adhesive layer 116 is coated on the front surface of the substrate 110 and can fix the light emitting element LED disposed on the adhesive layer 116. The adhesive layer 116 may include a contact hole for connecting the first connection electrode CE1 and the reflective electrode RE. The adhesive layer 116 may be made of an organic material. In this case, the organic material may be selected from, but is not limited to, any one of adhesive polymer, epoxy resist, UV resin, polyimide-based, acrylate-based, urethane-based, and polydimethylsiloxane (PDMS).

[0084] A plurality of light-emitting elements LED may be disposed in each of the plurality of sub-pixels SP on the adhesive layer 116. The plurality of light-emitting elements LED are elements that emit light when an electric current is applied, and may include light-emitting elements LED that emit red light, green light, blue light, etc., and a combination of these may form light of various hues including white. For example, the plurality of light-emitting elements LED may be, but are not limited to, LEDs (Light Emitting Diodes) or micro LEDs.

[0085] A second planarization layer 117 may be disposed on the adhesive layer 116. In this case, the second planarization layer 117 may be disposed to surround the first semiconductor layer NL disposed under the plurality of first electrodes NE of the plurality of light-emitting elements LED. This allows the plurality of light-emitting elements LED to be fixed and protected. The second planarization layer 117 may expose an upper surface of the first semiconductor layer NL. The second planarization layer 117 may include at least one contact hole for connecting the first connection electrode CE1 and the reflective electrode RE. The second planarization layer 117 may be made of, for example, but not limited to, a photoresist or an acrylic organic material.

[0086] A plurality of first connection electrodes CE1 may be disposed on the second planarization layer 117. The plurality of first connection electrodes CE1 are disposed in each of the plurality of sub-pixels SP and serve to electrically connect the light-emitting element LED and the driving transistor DT. The plurality of first connection electrodes CE1 may be connected to the reflective electrode RE through contact holes formed in the second planarization layer 117 and the adhesive layer 116. Therefore, the plurality of first connection electrodes CE1 may be electrically connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through the reflective electrode RE. However, without being limited thereto, one first connection electrode CE1 may be directly electrically connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT.

[0087] The plurality of first connection electrodes CE1 may be connected to the plurality of first electrodes NE of the plurality of light-emitting elements LED. The plurality of first connection electrodes CE1 may be formed to cover an upper surface and some side surfaces of the first semiconductor layer NL. In this case, the plurality of first connection electrodes CE1 may contact portions of the upper surface of the first semiconductor layer NL through the plurality of first openings OA1 of the plurality of light-emitting elements LED. The plurality of first connection electrodes CE1 may also cover ends of a passivation layer PAS disposed on the upper surface of a portion of the first semiconductor layer NL. Therefore, the first connection electrode CE1 may be disposed on the upper surface of the passivation layer PAS disposed on the upper surface of the first semiconductor layer NL outside the plurality of light-emitting elements LED. That is, the first semiconductor layer NL, the passivation layer PAS, and the first connection electrode CE1 may be sequentially stacked outside the plurality of light-emitting elements LED. In an adjacent region, the first semiconductor layer NL and the first connection electrode CE1 may be sequentially stacked. Meanwhile, there may be only one first connection electrode CE1, and the single first connection electrode CE1 may be electrically connected to the plurality of first electrodes NE.

[0088] Within the light-emitting elements LED, the first connection electrodes CE1 may be disposed to cover the first electrodes NE. Specifically, the first connection electrodes CE1 may contact a portion of the upper surfaces and a portion of the side surfaces of the first electrodes NE exposed through the first openings OA1, and may directly contact the upper surface of the first semiconductor layer NL exposed through the first opening OA1 in FIG. 2. The first connection electrodes CE1 may also be disposed on a passivation layer PAS disposed on a portion of the upper surfaces of the first electrodes NE. That is, within the light-emitting elements LED, the first electrodes NE, the passivation layer PAS, and the first connection electrodes CE1 may be sequentially stacked. In addition, in an area adjacent thereto, the first electrodes NE and the first connection electrodes CE1 may be sequentially stacked.

[0089] The plurality of first connection electrodes CE1 may be arranged on the upper surface and side surfaces of a portion of the second semiconductor layer PL. The plurality of first connection electrodes CE1 may be arranged at a position lower than the upper surface of the second semiconductor layer PL. That is, the position of the highest upper surface among the plurality of first connection electrodes CE1 may be lower than the upper surface of the second semiconductor layer PL.

[0090] Meanwhile, the first connection electrode CE1 connecting the driving transistor DT and the light emitting element LED arranged in each of the plurality of sub-pixels SP may be individually arranged in each of the plurality of sub-pixels SP.

[0091] A third planarization layer 118 may be disposed on the plurality of first connection electrodes CE1 and the second planarization layer 117. The third planarization layer 118 may include contact holes for connecting the second connection electrodes CE2 to power wiring (not shown). The third planarization layer 118 may expose at least a portion of the upper surfaces of the second semiconductor layers PE of the plurality of light-emitting elements LED. The third planarization layer 118 may also expose the second electrodes PE by exposing the second openings OA2. The third planarization layer 118 may be disposed to surround the side surfaces of the second semiconductor layers PL. The third planarization layer 118 may entirely cover the plurality of first connection electrodes CE1. Therefore, the height of the upper surface of the third planarization layer 118 may be higher than the height of the highest upper surface of the plurality of first connection electrodes CE1.

[0092] A second connection electrode CE2 may be disposed on the third planarization layer 118. The second connection electrode CE2 may be connected to the second electrode PE of the plurality of light-emitting elements LED. Although not shown in the drawings, the second connection electrode CE2 may be electrically connected to a power supply wiring (not shown) through a reflective electrode RE. The second connection electrode CE2 may be disposed on the plurality of light-emitting elements LED so as to cover the second opening OA2. Thus, the second connection electrode CE2 may be in contact with the upper surface of the second electrode PE exposed by the second opening OA2. The second connection electrode CE2 may cover the upper surface of the passivation layer PAS disposed at the uppermost end of the plurality of light-emitting elements LED. Furthermore, the second connection electrode CE2 may be formed to fill the second opening OA2. Thus, the second connection electrode CE2 may be in contact with the side surface of the passivation layer PAS in contact with the upper surface of the second opening OA2.

[0093] The second connection electrode CE2 and the first connection electrode CE1 may be disposed on different layers. The second connection electrode CE2 may be disposed at a higher position than the first connection electrode CE1. Thus, the highest upper surface of the first connection electrode CE1 may be lower than the lower surface of the second connection electrode CE2. The first connection electrode CE1 and the second connection electrode CE2 may be vertically spaced apart from each other.

[0094] Banks BB may be disposed on the third planarization layer 118. The banks BB are components for dividing adjacent sub-pixels SP. The banks BB may be disposed so as not to overlap with the light-emitting layers EL of the respective light-emitting elements LED. The banks BB may be disposed on the first connection electrodes CE1 so as to partially overlap them. In contrast, the banks BB may be disposed spaced apart from the second connection electrodes CE2. The banks BB may be made of an acrylic resin, a benzocyclobutene (BCB) resin, or polyimide, and may further include a black component, but are not limited thereto.

[0095] A light-emitting device is a semiconductor light-emitting device that utilizes the property of emitting light when a current is passed through a semiconductor. In this case, holes and electrons injected from different electrodes meet in the light-emitting layer to emit light. The different electrodes of the light-emitting device are connected to a driving transistor or a power supply wiring, respectively. For example, if one electrode of the light-emitting device is connected to a driving transistor, the other electrode is connected to a power supply wiring. Thus, the light-emitting device includes at least two different electrodes. The two different electrodes may be arranged on the same plane or on different planes. For example, one electrode may be arranged on a plane higher than the other electrode.

[0096] In this manner, different electrodes of the light emitting device may be connected to the driving transistor or the power supply wiring using separate connection electrodes. In this case, if different electrodes of the light emitting device are arranged on different planes, the connection electrodes connected to the different electrodes may also be arranged at different positions. In this case, a problem may occur in which the connection electrodes are damaged during the process of arranging the different connection electrodes on the different electrodes.

[0097] The above-mentioned problem will be specifically explained below with reference to FIGS. 6a and 6b.

[0098] 6a and 6b are SEM (scanning electron microscope) images of a light emitting device in a step of applying and etching a photoresist after a first connection arrangement in a manufacturing process of a display device of a comparative example.

[0099] 6a and 6b, if one electrode PE of a light emitting device is disposed on a higher plane than another electrode NE, the first connection electrode CE1 is disposed on the electrode NE disposed on the lower plane as a process priority. In this case, the first connection electrode CE1 is disposed in a single layer so as to cover the entire lower structure. Therefore, in a light emitting device in which the different electrodes NE and PE are both exposed, the first connection electrode CE1 is disposed not only on the electrode NE disposed on the lower plane but also on the other electrode PE disposed on the higher plane.

[0100] However, as explained above, because different voltages must be applied to the two electrodes NE and PE of the light-emitting element, a common connection electrode cannot be connected to the electrode NE arranged on the lower plane and the electrode PE arranged on the higher plane. Therefore, a different connection electrode must be arranged on the electrode PE arranged on the higher plane to apply a different voltage to the electrode NE arranged on the lower plane. Therefore, a process of removing the connection electrode CE arranged on the other electrode PE on the higher plane, which was formed during the process of forming the first connection electrode CE1 on the electrode NE on the lower plane of the light-emitting element, is required. Since the first connection electrode CE1 connected to the electrode NE on the lower plane of the light-emitting element must be maintained intact, a photoresist PR is applied to the electrode NE on the lower plane and the first connection electrode CE1 connected to it to protect them. The photoresist PR is initially arranged to cover the entire light-emitting element. The photoresist PR is then etched until the first connection electrode CE1 connected to the electrode PE on the higher plane of the light-emitting element is exposed and removed.

[0101] However, due to the material properties, the photoresist PR is not coated flat on its top surface. That is, the height of the top surface of the photoresist PR coated on the higher plane of the light emitting device differs from the height of the top surface of the photoresist PR coated on the lower plane, resulting in a certain level difference. At this time, the height of the top surface of the photoresist PR decreases from the higher plane to the lower plane of the light emitting device, and decreases the further away from the light emitting device. That is, as shown in FIG. 6a, the height H1 from the top surface of the first connection electrode CE1 disposed on the lower plane of the light emitting device, which is adjacent to the higher plane, to the photoresist PR is higher than the height H2 from the top surface of the first connection electrode CE1 to the photoresist PR, which is farther away from the higher plane of the light emitting device.

[0102] 6b, when the photoresist PR is etched, the height of the upper surface of the photoresist PR gradually decreases depending on the position. As a result, the height H2' of the upper surface of the photoresist PR on the side far from the high plane of the light emitting device is lower than the height H1' of the upper surface of the photoresist PR on the adjacent side. Therefore, of the first connection electrodes CE1 disposed on the electrodes NE on the low plane of the light emitting device, the first connection electrodes CE1 on the side far from the high plane of the light emitting device may be exposed A by the etching of the photoresist PR. As a result, a portion of the first connection electrode CE1 is exposed A by the photoresist PR, which may cause damage and breakage during the subsequent etching of the photoresist PR and the subsequent process of removing unnecessary connection electrodes CE1.

[0103] Therefore, in the light-emitting element LED and the display device 100 including the same according to an embodiment of the present specification, the passivation layer PAS is not disposed on a portion of the upper surfaces and a portion of the side surfaces of the plurality of first electrodes NE arranged on a lower plane of the light-emitting element LED. By not disposing the passivation layer PAS on a portion of the upper surfaces of the plurality of first electrodes NE in this manner, the height of a portion of the upper surface of the passivation layer PAS can be lowered. Lowering the height of the upper surface of the passivation layer PAS in this manner can further increase the distance between the upper surface of the photoresist PR applied during the process and the upper surface of the passivation layer PAS. This prevents the underlying components from being exposed due to etching of the photoresist PR during the process. Furthermore, damage to the underlying components caused by the exposure of the underlying components can be prevented.

[0104] In addition, in the light emitting device LED and the display device 100 including the light emitting device LED according to an embodiment of the present disclosure, the plurality of first electrodes NE can be disposed adjacent to the light emitting layer EL from the end of the first semiconductor layer NL. That is, each of the plurality of first electrodes NE can be disposed inside the light emitting device LED, where the height of the photoresist PR is relatively high. Therefore, the plurality of first electrodes NE can be prevented from being exposed by etching the photoresist PR. This prevents damage to the first electrodes NE. Furthermore, by disposing the plurality of first electrodes NE inside the light emitting device LED, a space can be secured in which the passivation layer PAS can be directly disposed on the upper surface of the first semiconductor layer NL adjacent to the end of the first semiconductor layer NL. Therefore, the passivation layer PAS can be partially spaced from the plurality of first electrodes NE. This makes it easier to lower the height of a portion of the upper surface of the passivation layer PAS.

[0105] Figure 7 is a schematic plan view of a light-emitting device according to another embodiment of the present specification. Figure 8 is a cross-sectional view taken along line VIII-VIII' in Figure 7. The light-emitting device LED' in Figures 7 and 8 is substantially the same as the light-emitting device LED in Figures 1 and 2 except for the configuration of the passivation layer PAS, and therefore a redundant description thereof will be omitted.

[0106] 7 and 8, a light emitting device LED' according to another embodiment of the present specification includes a first semiconductor layer NL, a plurality of first electrodes NE disposed on one side and the other side of the first semiconductor layer NL, an emitting layer EL disposed between the plurality of first electrodes NE on the first semiconductor layer NL, a second semiconductor layer PL disposed on the emitting layer EL, a second electrode PE disposed on the second semiconductor layer PL, and a passivation layer PAS covering the first semiconductor layer NL, the plurality of first electrodes NE, the second semiconductor layer PL, and the second electrode PE. That is, the passivation layer PAS may be disposed to cover the entire structure disposed below.

[0107] The passivation layer PAS also includes at least one portion with a different thickness. The passivation layer PAS may include at least three portions with different thicknesses. For example, the passivation layer PAS may include first portions T1-1, T1-2, and T1-3 with the thinnest thickness, second portions T2-1 and T2-2 with intermediate thicknesses, and third portions T3-1, T3-2, T3-3, and T3-4 with the thickest thicknesses. However, the passivation layer PAS is not limited thereto, and may further include at least one portion with a different thickness in addition to the above-mentioned portions. More specifically, referring to FIG. 8, a passivation layer PAS is disposed on the upper surface of the first semiconductor layer NL, on the outer side of the first electrodes NE. In this case, the passivation layer PAS may include at least one portion with a different thickness. For example, the passivation layer PAS on the first semiconductor layer NL disposed outside the plurality of first electrodes NE may include a thin first portion T1-1 and a thick second portion T3-1. The thin first portion T1-1 may be disposed adjacent to the first electrode NE, and the thick second portion T3-1 may be disposed far from the first electrode NE. Thus, the thin first portion T1-1 may be disposed far from the light-emitting layer EL and surround at least a portion of the first electrode NE, such that the first electrode NE is between the first portion T1-1 and the light-emitting layer EL.

[0108] The passivation layer PAS disposed on the plurality of first electrodes NE may include at least one portion having a different thickness. For example, the passivation layer PAS disposed on the plurality of first electrodes NE may include a first portion T1-2 having a thin thickness and a second portion T3-2 having a thick thickness. In this case, the second portion T3-2 having a thick thickness may be disposed adjacent to the light-emitting layer EL. The first portion T1-2 having a thin thickness may be disposed far from the light-emitting layer EL. The first portion T1-2 having a thin thickness of the passivation layer PAS disposed on the plurality of first electrodes NE may extend to a side surface of a portion of the plurality of first electrodes NE and connect to the thin portion T1-1 of the passivation layer PAS disposed on the first semiconductor layer NL. Therefore, the thin portions T1-1 and T1-2 of the passivation layer PAS disposed on the first semiconductor layer NL and the plurality of first electrodes NE may have substantially the same or similar thicknesses, but are not limited thereto. Furthermore, the second portion T3-2 having a larger thickness among the passivation layer PAS on the plurality of first electrodes NE and the second portion T3-1 having a larger thickness among the passivation layer PAS on the first semiconductor layer NL may have substantially the same or similar thicknesses, but is not limited to this.

[0109] The passivation layer PAS disposed on the second electrode PE may include a first thin portion T1-3 and a second thick portion T3-4. The first thin portion T1-3 may be disposed in the center of the second electrode PE, and the second thick portion T3-4 may be disposed along the edge of the second electrode PE. The second thick portion T3-4 of the passivation layer PAS on the second electrode PE may be disposed to surround the first thin portion T1-3. The second thick portion T3-4 of the passivation layer PAS on the second electrode PE may extend outside the second electrode PE and connect with the passivation layer PAS on the second semiconductor layer PL. The passivation layer PAS on the second semiconductor layer PL may extend along the side of the second semiconductor layer PL and connect with the second thick portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE. Therefore, the thicknesses of the thick second portion T3-4 of the passivation layer PAS on the second electrode PE, the passivation layer T3-3 on the second semiconductor layer PL, and the thick second portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE may be substantially the same or similar, but are not limited to this.

[0110] The thicknesses of the thinner portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE disposed outside the plurality of first electrodes NE may be substantially the same or similar to each other, but are not limited thereto. Furthermore, the thicknesses of the thinner portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE disposed outside the plurality of first electrodes NE may be thinner than the thicknesses T2-1 and T2-2 of the passivation layer PAS disposed on the side surfaces of the first semiconductor layer NL and the second semiconductor layer PL, respectively. Furthermore, the thicknesses of the thinner portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE disposed outside the plurality of first electrodes NE may be the thinnest of the thickness of the entire passivation layer PAS. These can protect the first electrodes NE and the second electrodes PE, respectively, and can be removed as needed. For example, the first semiconductor layer NL disposed outside the first electrodes NE and the thin portions T1-1 and T1-2 of the passivation layer PAS on the first electrodes NE can be removed as needed during the process of manufacturing the display device. The removed portions T1-1 and T1-2 can form a plurality of first openings OA1. The first connection electrodes CE1 can be connected to the first electrodes NE through the first openings OA1 formed in this way. Furthermore, the thin portion T1-3 of the passivation layer PAS disposed on the second electrode PE can be removed as needed, thereby forming a second opening OA2. The second connection electrode CE2 can be connected to the second electrode PE through the second opening OA2 formed in this way.

[0111] On the other hand, the thicknesses of the thicker portions T3-1, T3-2, and T3-3 of the passivation layer PAS arranged on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE, which are arranged outside the plurality of first electrodes NE, may be thicker than the thicknesses T2-1 and T2-2 of the passivation layer PAS arranged on the respective side surfaces of the first semiconductor layer NL and the second semiconductor layer PL.

[0112] The light emitting device includes at least two different electrodes for connection to a driving transistor or a power wiring. The two different electrodes may be disposed on the same plane or on different planes. Since the two different electrodes must be electrically connected to the driving transistor or the power wiring, respectively, at least a portion of the two different electrodes of the light emitting device must be exposed.

[0113] In this case, in the light emitting device LED' according to another embodiment of the present specification, the passivation layer PAS on the plurality of first electrodes NE and second electrodes PE may include portions having different thicknesses. Therefore, if the passivation layer PAS on the plurality of first electrodes NE and second electrodes PE includes portions T1-2 and T1-3 having thinner thicknesses, it may be easier to remove the corresponding portions. This may make it easier to expose at least a portion of the plurality of first electrodes NE and second electrodes PE.

[0114] In addition, in a light emitting device LED' according to another embodiment of the present specification, the passivation layer PAS on the first semiconductor layer NL disposed outside the plurality of first electrodes NE may include portions having different thicknesses. Thus, a thinner portion T1-1 of the passivation layer PAS may be disposed on at least a portion of the first semiconductor layer NL disposed outside the plurality of first electrodes NE. This may make it easy to expose at least a portion of the first semiconductor layer NL disposed outside the plurality of first electrodes NE.

[0115] The thin portions T1-1 of the passivation layer PAS on the first semiconductor layer NL disposed outside the plurality of first electrodes NE may be disposed adjacent to the plurality of first electrodes NE. Therefore, by removing the thin portions T1-1 of the passivation layer PAS on the first semiconductor layer NL disposed outside the plurality of first electrodes NE, at least one side of the plurality of first electrodes NE and one end of the passivation layer PAS may be spaced apart from each other. Therefore, the plurality of first electrodes NE may be disposed inside the light emitting element LED′ adjacent to the light emitting layer EL. This prevents damage to the plurality of first electrodes NE.

[0116] An embodiment of the present invention can also be described as follows.

[0117] According to an aspect of the present invention, a light-emitting element includes a first semiconductor layer, a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer, a light-emitting layer arranged between the plurality of first electrodes on the first semiconductor layer, a second semiconductor layer arranged on the light-emitting layer, a second electrode arranged on the second semiconductor layer, and a passivation layer covering at least a portion of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and a plurality of first openings exposing a portion of the top surface and a portion of the side surface of the plurality of first electrodes are arranged in the passivation layer.

[0118] According to another embodiment of the present specification, the side surfaces of the plurality of first electrodes facing the light emitting layer may be covered with a passivation layer, and the remaining side surfaces of the plurality of first electrodes may be exposed by the passivation layer.

[0119] According to still other embodiments herein, a portion of the end of the passivation layer may contact the top surface of the first semiconductor layer.

[0120] According to still another embodiment of the present disclosure, a portion of the top surface of the first semiconductor layer may be exposed by the first opening.

[0121] According to still another embodiment of the present disclosure, a portion of the top surface of the first semiconductor layer exposed by the first opening may be disposed farther from the light emitting layer than the first electrode.

[0122] According to still other embodiments herein, the passivation layer may include a second opening exposing a portion of the top surface of the second electrode.

[0123] According to another embodiment of the present disclosure, each of the plurality of first electrodes may be disposed closer to the light emitting layer than the end of the first semiconductor layer.

[0124] According to another aspect of the present invention, a display device includes a substrate defining pixels each including a plurality of sub-pixels, and a plurality of light-emitting elements arranged in the plurality of sub-pixels, each including a plurality of first electrodes and a second electrode, wherein the plurality of light-emitting elements include a first semiconductor layer, a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer, a light-emitting layer arranged on the first semiconductor layer between the plurality of first electrodes, a second semiconductor layer arranged on the light-emitting layer, a second electrode arranged on the second semiconductor layer, and a passivation layer covering at least a portion of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and a plurality of first openings are arranged in the passivation layer exposing a portion of the top surface and a portion of the side surface of the plurality of first electrodes.

[0125] According to another embodiment of the present specification, the display device may further include a plurality of first connection electrodes connected to the plurality of first electrodes respectively, and a second connection electrode connected to the P-type electrode.

[0126] According to still another embodiment of the present specification, the plurality of first connection electrodes and the plurality of second connection electrodes may be disposed on different layers.

[0127] According to still another embodiment of the present specification, each of the plurality of first connection electrodes may be disposed so as to contact the top and side surfaces of the plurality of first electrodes exposed by the plurality of first openings.

[0128] According to still another embodiment of the present specification, each of the plurality of first connection electrodes may be disposed so as to contact the upper surface of the first semiconductor layer exposed by the plurality of first openings.

[0129] According to still another embodiment of the present specification, the second connection electrode may be disposed so as to be in contact with the upper surface of the second electrode exposed by the second opening.

[0130] According to yet another aspect of the present invention, a light-emitting element includes a first semiconductor layer, a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer, a light-emitting layer arranged between the plurality of first electrodes on the first semiconductor layer, a second semiconductor layer arranged on the light-emitting layer, a second electrode arranged on the second semiconductor layer, and a passivation layer covering the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer, and the second electrode, wherein the passivation layer includes portions with different thicknesses.

[0131] According to yet another embodiment of the present disclosure, the number of portions with different thicknesses may be three or more.

[0132] According to another embodiment of the present specification, the first semiconductor layer disposed outside the first electrode, and the passivation layer disposed on the first electrode and the second electrode may each include at least one portion having a different thickness.

[0133] According to another embodiment of the present disclosure, a thicker portion of the passivation layer having different thicknesses may be disposed on the first electrode so as to be adjacent to the light emitting layer.

[0134] According to another embodiment of the present specification, on the first semiconductor layer arranged outside the first electrode, the thinner part of the passivation layer having different thicknesses may be arranged adjacent to the first electrode.

[0135] According to still another embodiment of the present disclosure, a thinner portion of the portion of the passivation layer having different thicknesses on the second electrode may be disposed at the center of the second electrode.

[0136] According to another embodiment of the present specification, the thickness of the thinner portion of the passivation layer disposed on the first semiconductor layer, the first electrode, and the second electrode disposed outside the first electrode may be thinner than the thickness of the passivation layer disposed on the side surfaces of the first semiconductor layer and the second semiconductor layer.

[0137] According to another embodiment of the present specification, the thickness of the thicker portion of the passivation layer disposed on the first semiconductor layer, the first electrode, and the second electrode disposed outside the first electrode may be thicker than the thickness of the passivation layer disposed on the side surfaces of the first semiconductor layer and the second semiconductor layer.

[0138] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present specification should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present specification.

Claims

1. a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light emitting layer; a second electrode disposed on the second semiconductor layer; a passivation layer that covers at least a portion of the first semiconductor layer, the light emitting layer, and the second semiconductor layer; Including, a plurality of first openings are disposed in the passivation layer, exposing portions of upper surfaces and portions of side surfaces of the plurality of first electrodes; a portion of each of the first electrodes facing the light-emitting layer is covered with the passivation layer; remaining portions of the side surfaces of the plurality of first electrodes are exposed by the passivation layer; Light-emitting element.

2. The light-emitting element according to claim 1 , wherein a portion of an end of the passivation layer is in contact with the top surface of the first semiconductor layer.

3. The light emitting device according to claim 1 , wherein a portion of an upper surface of the first semiconductor layer is exposed by the first opening.

4. The light emitting device according to claim 3 , wherein a portion of the upper surface of the first semiconductor layer exposed by the first opening is disposed farther from the light emitting layer than the first electrode.

5. The light-emitting device of claim 1 , wherein the passivation layer includes a second opening that exposes a portion of an upper surface of the second electrode.

6. The light emitting device according to claim 1 , wherein each of the plurality of first electrodes is disposed closer to the light emitting layer than an end of the first semiconductor layer.

7. a substrate defining a pixel including a plurality of sub-pixels; a plurality of light-emitting elements disposed in the plurality of sub-pixels, each including a plurality of first electrodes and a plurality of second electrodes; Including, The plurality of light-emitting elements are a first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light emitting layer; a passivation layer covering at least a portion of the first semiconductor layer, the light emitting layer, and the second semiconductor layer; a plurality of first connection electrodes connected to the plurality of first electrodes, respectively; a second connection electrode connected to the second electrode; Including, the plurality of first electrodes are disposed on one side and the other side of the first semiconductor layer; the second electrode is disposed on the second semiconductor layer; a plurality of first openings are disposed in the passivation layer, exposing portions of upper surfaces and portions of side surfaces of the plurality of first electrodes; The display device, wherein the plurality of first connection electrodes and the second connection electrodes are arranged on different layers.

8. A substrate on which pixels each including a plurality of sub-pixels are defined; a plurality of light-emitting elements disposed in the plurality of sub-pixels, each including a plurality of first electrodes and a plurality of second electrodes; Including, The plurality of light-emitting elements are a first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light emitting layer; a passivation layer covering at least a portion of the first semiconductor layer, the light emitting layer, and the second semiconductor layer; a plurality of first connection electrodes connected to the plurality of first electrodes, respectively; a second connection electrode connected to the second electrode; Including, the plurality of first electrodes are disposed on one side and the other side of the first semiconductor layer; the second electrode is disposed on the second semiconductor layer; a plurality of first openings are disposed in the passivation layer, exposing portions of upper surfaces and portions of side surfaces of the plurality of first electrodes; the plurality of first connection electrodes are arranged so as to be in contact with upper surfaces and side surfaces of the plurality of first electrodes exposed by the plurality of first openings, Display device.

9. The display device according to claim 7 , wherein each of the plurality of first connection electrodes is disposed so as to be in contact with an upper surface of the first semiconductor layer exposed by the plurality of first openings.

10. The display device according to claim 7 , wherein the second connection electrode is disposed so as to be in contact with an upper surface of the second electrode exposed by the second opening in the passivation layer.

11. a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light emitting layer; a second electrode disposed on the second semiconductor layer; a passivation layer covering the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer, and the second electrodes; Including, the passivation layer includes portions with different thicknesses; a portion of the passivation layer having a different thickness, the portion having a thinner thickness, being disposed adjacent to the plurality of first electrodes on the first semiconductor layer disposed outside the plurality of first electrodes; Light-emitting element.

12. The light-emitting element according to claim 11 , wherein the number of the portions with different thicknesses is three or more.

13. The light emitting device of claim 11 , wherein the first semiconductor layer disposed outside the plurality of first electrodes and the passivation layer disposed on the plurality of first electrodes and the second electrode each include at least one portion having a different thickness.

14. The light-emitting element according to claim 13 , wherein the thicker portions of the passivation layer that are different in thickness are disposed on the plurality of first electrodes so as to be adjacent to the light-emitting layer.

15. The light-emitting device according to claim 13 , wherein the thinner portion of the passivation layer having different thicknesses is disposed on the second electrode at a center of the second electrode.

16. 14. The light-emitting element of claim 13, wherein the thickness of the thin portions of the first semiconductor layer arranged outside the plurality of first electrodes, the passivation layer arranged on the plurality of first electrodes and the second electrode is thinner than the thickness of the passivation layer arranged on the side surfaces of the first semiconductor layer and the second semiconductor layer.

17. 14. The light-emitting element of claim 13, wherein the thickness of the thicker portions of the first semiconductor layer arranged outside the plurality of first electrodes, the passivation layer arranged on the plurality of first electrodes and the second electrode is thicker than the thickness of the passivation layer arranged on the side surfaces of the first semiconductor layer and the second semiconductor layer.

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