Optical module switch device

Abstract

To reduce power consumption of an optical module switch device.SOLUTION: An optical module switch device includes a first serial-to-parallel conversion unit that is connected to first signal lines connected to an optical module and second signal lines greater in number than the first signal lines, and transmits and receives a first signal at a first transmission rate to and from the optical module using the first signal line, a second serial-to-parallel conversion unit that is connected to the second signal lines connected to the first serial-parallel conversion unit and third signal lines that are greater in number than the second signal lines, and transmits and receives a second signal to and from the first serial-to-parallel conversion unit at a second transmission rate lower than the first transmission rate using each of the second signal lines, and a logic unit that is connected to the third signal lines, transmits and receives a third signal to and from the second serial-parallel conversion unit at a third transmission rate lower than the second transmission rate using each of the third signal lines, and performs routing processing on the basis of the received third signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an optical module switch device. [Background technology]

[0002] There is known a repeater that improves transmission efficiency by converting an optical signal received from an optical terminal device at a first transmission rate into an optical signal at a second transmission rate that is faster than the first transmission rate, and outputting the converted optical signal to an optical terminal device (see, for example, Patent Document 1). For example, the optical terminal device converts the received optical signal into an electrical signal using an optical receiver, and then converts it into parallel electrical signals using a serializer / deserializer, thereby reducing the transmission rate of the electrical signal, and then performs signal reception processing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-30987 Summary of the Invention [Problem to be solved by the invention]

[0004] Optical module switch devices are known that receive optical signals using an optical module, route the data contained in the received optical signal using a switch circuit, and transmit the data as an optical signal from another optical module to a destination. As the speed of optical module switch devices increases (bandwidth expansion), the speed of the optical modules installed in the optical module switch devices and the number of installed optical modules are also increasing, and the power consumption of optical module switch devices is on the rise.

[0005] The switch circuit that performs routing processing and the optical module are connected by electrical signal lines. As the speed of optical modules increases, the transmission speed of the electrical signals transmitted through these electrical signal lines also increases. Furthermore, as the number of optical modules installed increases, the wiring length of the electrical signal lines also increases due to restrictions on the placement of the optical modules. As a result, there is a risk that signal distortion of the electrical signals transmitted between the switch circuit and the optical module will become significant.

[0006] To receive high-speed electrical signals and correctly determine the logical value (1 or 0) of the data contained in the electrical signals, a circuit is required to correct signal distortion, and the power consumption of this circuit increases as the speed of optical modules increases and the number of modules installed increases. At the same time, when the re-timer function, which suppresses waveform degradation in the time domain, is turned on, power consumption increases even further.

[0007] In one aspect, the present invention aims to reduce the power consumption of an optical module switch device. [Means for solving the problem]

[0008] According to one aspect, an optical module switch device includes: a first serial-to-parallel conversion unit connected to first signal lines connected to an optical module and second signal lines, the number of which is greater than the first signal lines, and configured to transmit and receive first signals to and from the optical module at a first transmission rate using the first signal lines; a second serial-to-parallel conversion unit connected to the second signal lines connected to the first serial-to-parallel conversion unit and third signal lines, the number of which is greater than the second signal lines, and configured to transmit and receive second signals to and from the first serial-to-parallel conversion unit at a second transmission rate lower than the first transmission rate using each of the second signal lines; and a logic unit connected to the third signal lines, configured to transmit and receive third signals to and from the second serial-to-parallel conversion unit at a third transmission rate lower than the second transmission rate using each of the third signal lines, and configured to perform routing processing based on the received third signals. the first serial-to-parallel conversion unit has a first phase-locked loop that synchronizes the second signal of multiple bits received from the second serial-to-parallel conversion unit with a first clock signal used in the first serial-to-parallel conversion unit, and the second serial-to-parallel conversion unit has a second phase-locked loop that synchronizes the second signal of multiple bits received from the first serial-to-parallel conversion unit with a second clock signal used in the second serial-to-parallel conversion unit. do. [Effects of the Invention]

[0009] The power consumption of the optical module switch device can be reduced. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view illustrating an example of an optical module switch device according to an embodiment; [Figure 2] 2 is a circuit block diagram showing an example of a SERDES_H shown in FIG. 1; [Figure 3] 2 is a circuit block diagram showing an example of SERDES_L in FIG. 1. [Figure 4] FIG. 4 is a timing diagram showing an outline of the operation of SERDES_H and SERDES_L in FIGS. 2 and 3. [Figure 5] 4 is a circuit block diagram showing an example of the delay locked loop DLL_H of FIG. 2 and the delay locked loop DLL_L of FIG. 3. FIG. [Figure 6] 6 is a circuit diagram showing an example of a selection control unit in FIG. 5. [Figure 7] 7 is a timing chart showing an example of the operation of the selection control section in FIG. 6. FIG. [Figure 8] 6 is a circuit diagram showing an example of a phase comparator and a charge pump shown in FIG. 5. [Figure 9] 9 is a timing diagram showing an example of the operation of the phase comparator of FIG. 8 when the phase of a data signal is ahead of the phase of a clock signal. [Figure 10] 9 is a timing diagram showing an example of the operation of the phase comparator of FIG. 8 when the phase of a data signal lags behind the phase of a clock signal. [Figure 11] FIG. 10 is a plan view illustrating an example of an optical module switch device according to another embodiment. [Figure 12] 10 is a circuit block diagram showing an example of a delay locked loop mounted in SERDES_H and SERDES_L of an optical module switch device according to another embodiment. FIG. [Figure 13] 13 is a circuit diagram showing an example of a selection control section in FIG. 12. FIG. [Figure 14] 14 is a timing chart showing an example of the operation of the selection control section in FIG. 13. FIG. [Figure 15] FIG. 10 is a plan view showing an example of another optical module switch device. [Figure 16] FIG. 10 is a plan view showing another example of another optical module switch device. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings.

[0012] FIG. 1 shows an example of an optical module switch device according to an embodiment. The optical module switch device 100 shown in FIG. 1 includes a substrate BRD, such as a printed circuit board, on which a plurality of optical modules OM and packages PKG are mounted. While not particularly limited, for example, 16 optical modules OM (8 on the front side and 8 on the back side) are mounted along each side of the rectangular substrate BRD. The optical modules OM are disposed on the substrate BRD outside the periphery of the package PKG (at a position adjacent to the periphery). Each optical module OM is connected to an optical cable OC, which transmits optical signals to be transmitted and received. Note that in FIG. 1, signal lines other than the optical cable OC are electrical signal lines.

[0013] The package PKG has an organic substrate, and a plurality of serializers / deserializers SERDES_H and a semiconductor chip SWIC mounted on the organic substrate. The serializers / deserializers SERDES_H are arranged on the package PKG inside the outer periphery of the package PKG (at a position adjacent to the outer periphery). The semiconductor chip SWIC is mounted in the center of the package PKG.

[0014] For example, the optical module switch device 100 has an NPO (Near Package Optics) configuration in which the optical module OM is disposed in a position close to the package PKG. Each optical module OM and each serializer / deserializer SERDES_H are disposed in positions adjacent to the outer periphery of the package PKG, and the semiconductor chip SWIC is mounted in the center of the package PKG. Therefore, the length of the signal line connecting the optical module OM and the serializer / deserializer SERDES_H can be made shorter than the length of the signal line connecting the serializer / deserializer SERDES_H and the semiconductor chip SWIC.

[0015] Although not particularly limited, for example, 128 serializers / deserializers SERDES_H are mounted along each side of a rectangular package PKG. In other words, one group of serializers / deserializers SERDES_H shown by a rectangle in FIG. 1 includes 64 serializers / deserializers SERDES_H. Of these 64, 32 serializers / deserializers SERDES_H are connected to four optical modules OM on the front surface of the substrate BRD. The remaining 32 serializers / deserializers SERDES_H are connected to four optical modules OM on the back surface of the substrate BRD. In other words, each optical module OM is connected to eight serializers / deserializers SERDES_H.

[0016] The optical module OM and the serializer / deserializer SERDES_H on the back surface of the substrate BRD are connected via wiring formed on the substrate BRD, bumps connecting the substrate BRD and the package PKG, and wiring formed on the package PKG. The optical module OM and the substrate BRD may be connected via bumps. The serializer / deserializer SERDES_H and the package PKG may be connected via bumps.

[0017] The semiconductor chip SWIC includes a plurality of serializers / deserializers SERDES_L and a logic unit LOGIC that performs routing processing. Hereinafter, the serializers / deserializers SERDES_H will also be simply referred to as SERDES_H, and the serializers / deserializers SERDES_L will also be simply referred to as SERDES_L. SERDES_H is an example of a first serial-to-parallel conversion unit, and SERDES_L is an example of a second serial-to-parallel conversion unit.

[0018] The logic unit LOGIC is placed in the center of the semiconductor chip SWIC. By mounting the semiconductor chip SWIC in the center of the package PKG, it is possible to suppress variations in the length of the signal lines inside the package PKG that interconnect the SERDES_H and SERDES_L. This makes it possible to suppress variations in the delay amount of signals transmitted between each optical module OM and the semiconductor chip SWIC.

[0019] In Figure 1, one SERDES_L arranged along each side of the rectangular semiconductor chip SWIC corresponds to 128 SERDES_L. Therefore, one SERDES_L is connected to one SERDES_H. Between each SERDES_L and each SERDES_H, a 4-bit signal is transmitted in parallel, and a 4-bit signal is received in parallel.

[0020] Here, each bit signal transmitted within the package PKG is a differential signal, and is transmitted or received using a pair of signal lines and one shielded line. Therefore, 24 wires are used to transmit and receive 4-bit signals between each SERDES_L and each SERDES_H. Therefore, the 128 SERDES_H arranged on each side of the package PKG and the 128 SERDES_L arranged on each side of the semiconductor chip SWIC are connected by 3072 wires (128 × 24 wires).

[0021] Although not particularly limited, assume that the length of each side of the package PKG is 85 mm, and the wiring area (line / space) used for one wire within the package PKG is 0.002 mm. Here, "line" indicates the wiring width, and "space" indicates the minimum distance between adjacent wires. In this case, the width of the wiring area required for 3,072 wires is 6.144 mm, allowing for wiring with ample margin within the package PKG. It is also possible to form 3,072 terminals per side of the semiconductor chip SWIC.

[0022] Between each SERDES_L and the logic section LOGIC, 32-bit signals are transmitted in parallel, and 32-bit signals are received in parallel. The speed of these signals is lower than the speed of signals transmitted between SERDES_H and SERDES_L, and because each SERDES_L and the logic section LOGIC are mounted on the same chip, the wiring length of the 32-bit signal lines is short and the impact of external noise is small. For this reason, signals transmitted between each SERDES_L and the logic section LOGIC are transmitted as single-ended signals without using shielded wires. Therefore, there are 64 signal wires connected between one SERDES_L and the logic section LOGIC. The 64 wires are broken down into 32 signal lines for transmission and 32 signal lines for reception.

[0023] The transmission speed of an optical signal that each optical module OM transmits to or receives from the optical cable OC is, for example, 800 Gb / s. The transmission speed of a 1-bit signal that one SERDES_H transmits to or receives from the optical module OM is, for example, 100 Gb / s. Therefore, the transmission speed of a signal transmitted between eight SERDES_Hs and one optical module OM is 800 Gb / s.

[0024] The transmission speed of each 4-bit signal that one SERDES_L transmits to or receives from one SERDES_H is, for example, 25 Gb / s, and therefore the transmission speed of a signal transmitted between one SERDES_L and one SERDES_H is 100 Gb / s.

[0025] The transmission speed of each 32-bit signal that one SERDES_L transmits to or receives from the semiconductor chip SWIC is, for example, 3.125 Gb / s, which corresponds to the operating frequency of the logic chip. Therefore, the transmission speed of signals transmitted between one SERDES_L and the semiconductor chip SWIC is 100 Gb / s. 100 Gb / s is an example of a first transmission speed. 25 Gb / s is an example of a second transmission speed. 3.125 Gb / s is an example of a third transmission speed.

[0026] The optical module switch device 100 transmits signals (information contained in packets, etc.) received from the outside via the optical cable OC to the logic unit LOGIC via SERDES_H and SERDES_L. The optical module switch device 100 transmits signals containing information such as packets to one of the optical modules OM via SERDES_L and SERDES_H in accordance with routing processing performed by the logic unit LOGIC. The optical module OM converts the transmitted signals into optical signals and outputs them to the optical cable OC.

[0027] In this embodiment, by arranging each SERDES_H on the outer periphery of the package PKG, the distance between each SERDES_H and the optical module OM connected to it can be shortened. This makes it possible to minimize the length of the wiring connecting each SERDES_H to the optical module OM. Since the length of the wiring through which the highest speed signal (100 Gb / s) in FIG. 1 is transmitted can be minimized, distortion of the transmitted signal can be reduced. As a result, the circuitry used to correct distortion to correctly determine the logical value (1 or 0) on the signal receiving side can be significantly simplified, thereby reducing power consumption.

[0028] Furthermore, by minimizing the length of the wiring connecting each SERDES_H and the optical module OM, it is possible to suppress waveform disturbances caused by the influence of noise and the like in signals transmitted through the wiring. This makes it possible, for example, to turn off the re-timer function installed in the optical module OM in order to correct waveform disturbances in the time domain of signals transmitted from the SERDES_H. As a result, it is possible to reduce the power consumption of the optical module OM to, for example, half of the power consumption when the re-timer function is turned on.

[0029] Figure 2 shows an example of the serializer / deserializer SERDES_H shown in Figure 1. One SERDES_H group, shown as a rectangle in Figure 1, contains 64 SERDES_Hs shown in Figure 2. The SERDES_H includes a delay-locked loop DLL_H, a multiplexer MUX1, an output driver ODRV, a phase-locked loop PLL, a divider FDIV1, and a buffer B1. The SERDES_H also includes an equalizer EQ, a clock recovery circuit CRU, a demultiplexer DMX1, a divider FDIV2, a buffer B2, and a flip-flop FF_H.

[0030] The delay locked loop DLL_H operates while receiving an enable signal DLL_EN at an active level from the logic unit LOGIC of the semiconductor chip SWIC. The delay locked loop DLL_H then matches the phase of each of the 4-bit data signals DT25T_DLI received from SERDES_L to the phase of the clock signal CK25T, and outputs them as 4-bit data signals DT25T_DLO.

[0031] The delay locked loop DLL_H is an example of a first phase locked loop. For example, the transmission speed of each of the data signals DT25T_DLI is 25 Gb / s, and the frequency of the clock signal CK25T is 25 GHz. The data signal DT25T_DLI is an example of a second signal, and the signal line through which the data signal DT25T_DLI is transmitted is an example of a second signal line. The clock signal CK25T is an example of a first clock signal.

[0032] The multiplexer MUX1 multiplexes the 4-bit data signal DT25T_DLO two bits at a time in synchronization with the clock signal CK50T, and outputs the multiplexed data signal as a 2-bit data signal DT50T. For example, the transmission speed of each data signal DT50T is 50 Gb / s, and the frequency of the clock signal CK50T is 50 GHz.

[0033] The output driver ODRV converts a 2-bit data signal DT50T (each binary) into a 4-value data signal TXDT and outputs it to the optical module OM. For example, the data signal TXDT output by the output driver ODRV is a PAM4 (Pulse Amplitude Modulation 4) signal with a transmission speed of 100 Gb / s. Then, the 8-bit data signal TXDT is output from the eight SERDES_H to one optical module OM. The data signal TXDT is an example of a first signal, and the signal line through which the data signal TXDT is transmitted is an example of a first signal line.

[0034] The phase-locked loop (PLL) receives an external reference clock signal (REFCK) and generates a clock signal (CK50T) synchronized with the reference clock signal (REFCK). The frequency divider (FDIV1) divides the frequency of the 50 GHz clock signal (CK50T) to generate a 25 GHz clock signal (CK25T). The buffer (B1) outputs the clock signal (CK25T) to the SERDES_L as a clock signal (CK25T_HL).

[0035] The equalizer EQ compensates for high-frequency components of a 100 Gb / s data signal RXDT received from the optical module OM and outputs the signal as a 100 Gb / s data signal DT100R. For example, the data signal RXDT is a PAM4 signal. The optical module OM outputs an 8-bit data signal RXDT to each of eight SERDES_H. The data signal RXDT is an example of a first signal, and the signal line through which the data signal RXDT is transmitted is an example of a first signal line.

[0036] The clock recovery circuit CRU recovers the clock signal superimposed on the data signal DT100R and generates a clock signal CK50R having a rising edge in the center of the cycle of the data signal RXDT. The demultiplexer DMX1 outputs the quaternary data signal DT100R as a 4-bit data signal DT25R in synchronization with the clock signal CK50R. For example, the transmission speed of each bit of the data signal DT25R is 25 Gb / s.

[0037] The frequency divider FDIV2 divides the frequency of the 50 GHz clock signal CK50R to generate a 25 GHz clock signal CK25R. The buffer B2 outputs the clock signal CK25R to the SERDES_L as the clock signal CK25R_HL. The flip-flop FF_H outputs the 4-bit data signal DT25R to the SERDES_L as the 4-bit data signal DT25R_DLI in synchronization with the clock signal CK25R. For example, the transmission rate of each bit of the data signal DT25R_DLI is 25 Gb / s. The data signal DT25R_DLI is an example of a second signal, and the signal line through which the data signal DT25R_DLI is transmitted is an example of a second signal line. The clock signal CK25R_HL is an example of a second clock signal.

[0038] Figure 3 shows an example of the serializer / deserializer SERDES_L shown in Figure 1. One SERDES_L group shown in Figure 1 includes 128 SERDES_Ls shown in Figure 3. The SERDES_L includes a multiplexer MUX2, a flip-flop FF_L, a delay-locked loop DLL_L, a demultiplexer DMX2, and an elastic buffer ELBUF.

[0039] The multiplexer MUX2 converts the 32-bit data signal TXDT_LOGIC from parallel to serial in synchronization with the clock signal CK25T_HL from the SERDES_H and outputs the resulting 4-bit data signal DT25T_L. For example, the transmission rate of each bit of the data signal TXDT_LOGIC is 3.125 Gb / s, and the transmission rate of each bit of the data signal DT25T_L is 25 Gb / s. The data signal TXDT_LOGIC is an example of a third signal, and the signal line through which the data signal TXDT_LOGIC is transmitted is an example of a third signal line. The multiplexer MUX2 also divides the frequency of the clock signal CK25T_HL to generate a 3.125 GHz clock signal CK_LOGIC and outputs it to the logic unit LOGIC.

[0040] The flip-flop FF_L outputs the 4-bit data signal DT25T_L as a 4-bit data signal DT25T_DLI to the SERDES_H in synchronization with the clock signal CK25T_HL. For example, the transmission rate of each bit of the data signal DT25T_DLI is 25 Gb / s.

[0041] The delay locked loop DLL_L synchronizes the phase of each bit of the 4-bit data signal DT25R_DLI received from the SERDES_H with the phase of the clock signal CK25R_HL and outputs the resulting 4-bit data signal DT25R_DLO. The delay locked loop DLL_L is an example of a second phase-locked loop. For example, the transmission speed of each bit of the data signal DT25R_DLO is 25 Gb / s.

[0042] The demultiplexer DMX2 converts each bit of the 4-bit data signal DT25R_DLO from serial to parallel in synchronization with the clock signal CK25R_HL to generate a 32-bit DTR_L. The demultiplexer DMX2 also divides the clock signal CK25R_HL to generate a 3.125 GHz clock signal CKR_L. For example, the transmission speed of each bit of the data signal DTR_L is 3.125 Gb / s.

[0043] The elastic buffer ELBUF synchronizes the 32-bit data signal DTR_L received from the demultiplexer DMX2 with the clock signal CK_LOGIC using the clock signals CKR_L and CK_LOGIC. The elastic buffer ELBUF then outputs the 32-bit data signal RXDT_LOGIC synchronized with the clock signal CK_LOGIC to the logic unit LOGIC. The transmission rate of each bit of the data signal RXDT_LOGIC is 3.125 Gb / s. The data signal RXDT_LOGIC is an example of a third signal, and the signal line through which the data signal RXDT_LOGIC is transmitted is an example of a third signal line.

[0044] Figure 4 shows an overview of the operation of SERDES_H and SERDES_L in Figures 2 and 3. The four-digit numbers shown in the data signals DT25T_DLI, DT25T_DLO, DT25R_DLI, and DT25R_DLO indicate four-bit binary data. The two-digit numbers shown in the data signals DT50T and DT50R indicate two-bit binary data.

[0045] First, when transmitting a data signal TXDT to the optical module OM, the SERDES_L outputs a data signal DT25T_DLI to the SERDES_H in synchronization with a clock signal CK25T_HL received from the SERDES_H. The phase of the clock signal CK25T_HL lags behind the phase of the clock signal CK25T used in the SERDES_H due to propagation delay, etc. Therefore, the data signal DT25T_DLI lags behind the clock signal CK25T.

[0046] The delay-locked loop DLL_H of the SERDES_H uses the clock signal CK25T to adjust the phase of the delayed data signal DT25T_DLI. This allows the generation of a data signal DT25T_DLO synchronized with the clock signal CK25T, even if the signal line between SERDES_H and SERDES_L is long. The multiplexer MUX1 multiplexes the 4-bit data signal DT25T_DLO and generates two 2-bit data signals DT50T synchronized with the clock signal CK50T. The output driver ODRV then converts the 2-bit data signal DT50T into a quaternary data signal TXDT (PAM4) and outputs it to the optical module OM.

[0047] On the other hand, when receiving a data signal RXDT (PAM4) from the optical module OM, the equalizer EQ of the SERDES_H generates a data signal DT100R from the data signal RXDT. The clock recovery circuit CRU generates a clock signal CK50R having a rising edge in the center of the cycle of the data signal RXDT based on the data signal DT100R. The flip-flop FF_H of the SERDES_H outputs the data signal DT25R output by the demultiplexer DMX1 to the SERDES_L as a data signal DT25R_DLI in synchronization with the clock signal CK25R.

[0048] The delay locked loop DLL_L of SERDES_L adjusts the phase of the data signal DT25R_DLI output from SERDES_H using the clock signal CK25R_HL. This makes it possible to generate a data signal DT25R_DLO synchronized with the clock signal CK25R_HL even if the signal line between SERDES_H and SERDES_L is long.

[0049] Figure 5 shows an example of the delay locked loop DLL_H of Figure 2 and the delay locked loop DLL_L of Figure 3. Since the delay locked loops DLL_H and DLL_L are identical circuits, only the delay locked loop DLL_H will be described in Figure 5. In the delay locked loop DLL_L, the data signals DT25T_DLI and DT25T_DLO are replaced by data signals DT25R_DLI and DT25R_DLO shown in brackets, respectively. Furthermore, the clock signals CK25T and CK25T2 are replaced by clock signals CK25R_HL and CK25R_HL2 shown in brackets, respectively.

[0050] The delay-locked loop DLL_H includes five buffers BUF0-BUF4, four variable delay circuits VDL0-VDL3, and four flip-flops FF0-FF3. The delay-locked loop DLL_H also includes selectors SEL1 and SEL2, a phase comparator PC, a charge pump CP, a selector SEL3, four low-pass filters LPF0-LPF3, and a selection control unit SELCNT. The selector SEL1 is an example of a selection circuit. The phase comparator PC, the charge pump CP, and the low-pass filters LPF0-LPF3 are an example of a delay amount determination circuit that determines the delay amounts of the variable delay circuits VDL0-VDL3.

[0051] The buffers BUF0-BUF3 output a 4-bit data signal DT25T_DLI to the variable delay circuits VDL0-VDL3, respectively. The buffer BUF4 outputs the clock signal CK25T as the clock signal CK25T2.

[0052] Each of the variable delay circuits VDL0-VDL3 adjusts the delay of the received data signal DT25T_DLOI in accordance with the voltage received from each of the low-pass filters LPF0-LPF3, and outputs the adjusted delay data signal DT to each of the flip-flops FF0-FF3. Each of the flip-flops FF0-FF3 outputs the delay-adjusted data signal DT received from each of the variable delay circuits VDL0-VDL3 as a data signal DT25T_DLO in synchronization with the clock signal CK25T2.

[0053] The selector SEL1 outputs one of the delay-adjusted data signals DT25T_DLI to the phase comparator PC in response to the selection signal SEL output from the selection control unit SELCNT. The selector SEL2 outputs the clock signal CK25T2 output from the buffer BUF4 to the phase comparator PC in response to the selection signal SEL.

[0054] The phase comparator PC operates while the enable signal CP_EN output from the selection control unit SELCNT is at an active level. The phase comparator PC compares the phase of one of the delay-adjusted data signals DT output from the selector SEL1 with that of the clock signal CK25T2 output from the selector SEL2. The phase comparator PC then outputs an advance / delay signal EL and an enable signal EL_EN indicating the phase comparison result to the charge pump CP.

[0055] The charge pump CP operates while both the enable signals CP_EN and EL_EN are at the active level, and outputs a current according to the early / late signal EL to the selector SEL3.

[0056] Selector SEL3 outputs the current output from charge pump CP to one of low-pass filters LPF0-LPF3 in response to selection signal SEL. Each of low-pass filters LPF0-LPF3 converts the current received via selector SEL3 into a voltage, smooths it, and outputs the voltage to each of variable delay circuits VDL0-VDL3.

[0057] The selection control unit SELCNT operates while the enable signal DLL_EN is at an active level, and synchronizes with the clock signal CK25T2 to sequentially update the value of the selection signal SEL for each number of clock cycles corresponding to the period indicated by the period signal DLL_TERM. The selection control unit SELCNT also sets the enable signal CP_EN to an active level while sequentially updating the value of the selection signal SEL. An example of the circuit of the selection control unit SELCNT is shown in FIG. 6, and an example of the operation of the selection control unit SELCNT is shown in FIG. 7.

[0058] Fig. 6 shows an example of the selection control unit SELCNT in Fig. 5. In Fig. 6, the selection control unit SELCNT included in the delay locked loop DLL_H is explained. The selection control unit SELCNT included in the delay locked loop DLL_L operates in synchronization with the clock signal CK25R_HL2 shown in brackets instead of the clock signal CK25T2.

[0059] The selection control unit SELCNT has flip-flops FF4-FF6, AND circuits AND11 and AND12, counters CNT1 and CNT2, and comparators CMP1 and CMP2. Flip-flop FF4 synchronizes with clock signal CK25T2 and outputs enable signal DLL_EN_D, which is delayed by one clock cycle from the enable signal DLL_EN. Flip-flop FF5 synchronizes with clock signal CK25T2 and outputs enable signal DLL_EN_D, which is delayed by one clock cycle.

[0060] The AND circuit AND11 receives the enable signal DLL_EN_D and the inverted logic of the output of the flip-flop FF5, and generates a high-level pulse signal synchronized with the rising edge of the enable signal DLL_EN_D and outputs it to the flip-flop FF6.

[0061] Flip-flop FF6 operates in synchronization with clock signal CK25T2, and sets enable signal CP_EN to high level, which is an active level, in response to a high level pulse signal from AND circuit AND11.Flip-flop FF6 also sets enable signal CP_EN to low level, which is an inactive level, in response to a high level end signal DLL_END received at reset terminal RST.

[0062] The counter CNT1 counts in synchronization with the clock signal CK25T2 while the enable signal CP_EN is at high level, and outputs the count value CNT11 obtained by the counting. The counter CNT1 resets the count value CNT11 in response to a high-level reset signal CNT1_RST received at the reset terminal RST.

[0063] The comparator CMP1 sets the reset signal CNT1_RST to a high level, which is an active level, when the count value CNT11 matches the number of clock cycles indicated by the period signal DLL_TERM. When the reset signals CNT1_RST and CNT2_RST are both at a high level, the AND circuit AND12 outputs a high level to the reset terminal RST of the counter CNT2.

[0064] The counter CNT2 counts in synchronization with the clock signal CK25T2 while the reset signal CNT1_RST is at a high active level, and outputs the count value CNT21 obtained by the count. The high active level period of the reset signal CNT1_RST corresponds to one cycle of the clock signal CK25T2, since the counter CNT1 is reset by the reset signal CNT1_RST. The count value CNT21 is output as the selection signal SEL to the selectors SEL1-SEL3 in FIG. 5. Furthermore, when the reset terminal RST receives a high signal from the AND circuit AND12, the counter CNT2 resets the count value CNT21 to "0." The comparator CMP2 sets the reset signal CNT2_RST to a high level when the count value CNT21 reaches "3."

[0065] Fig. 7 shows an example of the operation of the selection control unit SELCNT in Fig. 6. The following describes an example of the operation of the selection control unit SELCNT installed in the delay locked loop DLL_H of SERDES_H in Fig. 2. Note that the selection control unit SELCNT installed in the delay locked loop DLL_L of SERDES_L in Fig. 3 operates in synchronization with the clock signal CK25R_HL2.

[0066] The number of clock cycles indicated by the period signal DLL_TERM is assumed to be "512." In the initial state of FIG. 7, the count value CNT11 of the counter CNT1 and the count value CNT21 of the counter CNT2 are initialized to "0" (FIGS. 7(a) and 7(b)). The selection control unit SELCNT outputs the count value CNT21 as the selection signal SEL. Therefore, in the initial state, the selector SEL1 selects the data signal DT output by the variable delay circuit VDL0. Then, while the count value CNT21 is "0," the delay locked loop DLL_H is set to the VDL0 adjustment period in which the delay amount of the variable delay circuit VDL0 is adjusted (FIG. 7(c)).

[0067] The selection control unit SELCNT sets the enable signal CP_EN to high level in the clock cycle next after latching the high level of the enable signal DLL_EN (FIGS. 7(d) and (e)). The counter CNT1 operates while the enable signal CP_EN is at high level, and updates the count value CNT11 by "1" in synchronization with the clock signal CK25T2 (FIG. 7(f)).

[0068] The comparator CMP1 in FIG. 6 sets the reset signal CNT1_RST to high level based on the fact that the count value CNT11 has reached "512" (FIG. 7(g)). After this, the counter CNT1 resets the count value CNT11 to "0" due to the high level of the reset signal CNT1_RST. The comparator CMP1 sets the reset signal CNT1_RST to low level based on the change of the count value CNT11 from "512" to "0" (FIG. 7(h)). The counter CNT2 stops counting while the reset signal CNT1_RST is low level.

[0069] The counter CNT2 operates while the reset signal CNT1_RST is at a high level, and updates the count value CNT21 from "0" to "1" in synchronization with the clock signal CK25T2 (FIG. 7(i)). This causes the selection control unit SELCNT to switch the selection signal SEL from "0" to "1." The delay locked loop DLL_H ends the VDL0 adjustment period and starts the VDL1 adjustment period in which it adjusts the delay amount of the variable delay circuit VDL1 (FIG. 7(j)).

[0070] Thereafter, the count value CNT21 is incremented by "1" each time the reset signal CNT1_RST is set to high level (FIG. 7(k) and (l)). Then, the delay locked loop DLL_H sequentially starts a VDL2 adjustment period for adjusting the delay amount of the variable delay circuit VDL2 and a VDL3 adjustment period for adjusting the delay amount of the variable delay circuit VDL3 (FIG. 7(m) and (n)).

[0071] The comparator CMP3 sets the reset signal CNT2_RST to high level when the count value CNT21 reaches "3" (FIG. 7(o)). The AND circuit AND12 sets the end signal DLL_END to high level when the reset signals CNT1_RST and CNT2_RST are both high level (FIG. 7(p)). This causes the enable signal CP_EN to change to low level, and adjustment of the delay amount of each of the variable delay circuits VDL0-VDL3 is completed (FIG. 7(q)).

[0072] In this embodiment, the delay locked loops DLL_H and DLL_L sequentially adjust the delay amounts of the variable delay circuits VDL0-VDL3 in a time-division manner. Therefore, the phase of the 4-bit data DT can be adjusted using one phase comparator PC and one charge pump CP. As a result, the circuit size of the delay locked loops DLL_H and DLL_L can be reduced compared to when a phase comparator PC and a charge pump CP are provided for each 4-bit data.

[0073] 7, each of the VDL0 adjustment period through the VDL3 adjustment period can be set to any number of clock cycles indicated by the period signal DLL_TERM. For example, when the period signal DLL_TERM is set to "128," each of the VDL0 adjustment period through the VDL3 adjustment period is set to 128 clock cycles.

[0074] FIG. 8 shows an example of the phase comparator PC and charge pump CP of FIG. 5. The phase comparator PC has two-input AND circuits AND2 and AND3, flip-flops FF7-FF13, and exclusive OR circuits EOR1 and EOR2. The charge pump CP has three-input AND circuits AND4 and AND5, current sources CS1 and CS2, and switch circuits SW1 and SW2. For example, the clock signal CLK is 25 GHz.

[0075] In the phase comparator PC, the AND circuit AND2 outputs the delay-adjusted data signal DT selected by the selector SEL1 as the data signal DT1 to the flip-flops FF7, FF8, and FF9 while the enable signal CP_EN is at high level.

[0076] While the enable signal CP_EN is at a high level, the AND circuit AND3 outputs the clock signal CLK as the clock signal CLK1 to the clock terminals of the flip-flops FF7 to FF13. The clock terminals of the flip-flops FF9, FF11, FF12, and FF13 receive the inverted logic of the clock signal CLK1 output from the AND circuit AND3.

[0077] Flip-flop FF7 outputs data signal DT1 as data signal DT_D1 in synchronization with the rising edge of clock signal CLK1. Flip-flop FF8 outputs data signal DT1 as data signal DT_A in synchronization with the rising edge of clock signal CLK1. Flip-flop FF9 outputs data signal DT1 as data signal DT_C in synchronization with the falling edge of clock signal CLK1.

[0078] The flip-flop FF10 outputs the data signal DT_D1 as a data signal DT_D2 in synchronization with the rising edge of the clock signal CLK1, and the flip-flop FF11 outputs the data signal DT_A as a data signal DT_B in synchronization with the falling edge of the clock signal CLK1.

[0079] The logical OR circuit EOR1 outputs the exclusive OR of the data signals DT_D1 and DT_D2 as the transition detection signal TRAN. The logical OR circuit EOR2 outputs the exclusive OR of the data signals DT_B and DT_C as the delay signal DXOR. The flip-flop FF12 outputs the transition detection signal TRAN as the enable signal EL_EN in synchronization with the falling edge of the clock signal CLK1. The flip-flop FF13 outputs the delay signal DXOR as the early / late signal EL in synchronization with the falling edge of the clock signal CLK1.

[0080] In the charge pump CP, the AND circuit AND4 outputs a high level when the early / late signal EL is at a high level while the enable signals CP_EN and EL_EN are at a high level, and the AND circuit AND5 outputs a high level when the early / late signal EL is at a low level while the enable signals CP_EN and EL_EN are at a high level.

[0081] Current source CS1, switch circuits SW1 and SW2, and current source CS2 are connected in series between the power supply line VCC and the ground line GND. The input of the low-pass filter LPF is connected to the node between switch circuits SW1 and SW2. Switch circuit SW1 is turned on while AND circuit AND4 outputs a high level, connecting current source CS1 to the low-pass filter LPF. Switch circuit SW2 is turned on while AND circuit AND5 outputs a high level, connecting current source CS2 to the low-pass filter LPF.

[0082] As a result, when the enable signals CP_EN and EL_EN are high and the early / late signal EL is high, current flows from the current source CS1 to the input of the low-pass filter LPF. When the enable signals CP_EN and EL_EN are high and the early / late signal EL is low, current flows from the input of the low-pass filter LPF to the current source CS2.

[0083] When the phase of 4-bit data DT is adjusted in parallel, each of SERDES_H and SERDES_L has four sets of the circuit configuration shown in Fig. 8. Therefore, each of ERDES_H and SERDES_L in this embodiment can reduce the circuit scale compared to when the phase of 4-bit data DT is adjusted in parallel.

[0084] 9 shows an example of the operation of the phase comparator PC of FIG. 8 when the phase of the data signal DT is ahead of the phase of the clock signal CLK. For example, the phase of the data signal DT being ahead of the phase of the clock signal CLK means that the rising edge of the data signal DT is in the low level period of the clock signal CLK. In FIG. 9, the enable signal CP_EN is set to high level "H".

[0085] The data signal DT_D1 is set to the logic level of the data signal DT at the rising edge of the clock signal CLK (FIG. 9(a)). For example, the data signal DT_D1 is set to a high level within half a clock cycle from the rising edge of the data signal DT. The data signal DT_D2 is set to a logic level that is one clock cycle behind the data signal DT_D1 (FIG. 9(b)).

[0086] The transition detection signal TRAN is set to a high level when the levels of the consecutive data signals DT_D1 and DT_D2 are different in order to detect a transition in the data signal DT, which is the target of phase comparison (Fig. 9(c)). The enable signal EL_EN is set to a logic level that is delayed by half a clock cycle from the transition detection signal TRAN (Fig. 9(d)).

[0087] Since the enable signal CP_EN is set to high level "H", the high level period of the enable signal EL_EN is the operation period of the charge pump CP. In other words, the high level period of the enable signal EL_EN is the determination period for determining whether the phase of the data signal DT is advanced or delayed.

[0088] The data signal DT_A has the same waveform as the data signal DT_D1 (Fig. 9(e)). When the phase of the data signal DT is ahead of the phase of the clock signal CLK, the data signals DT_B and DT_C transition to a high level in synchronization with the falling edge of the clock signal CLK, and have the same waveform as each other (Fig. 9(f)).

[0089] Therefore, the delay signal DXOR and the advance / delay signal EL are maintained at low level (FIGS. 9(g) and 9(h)). The advance / delay signal EL at low level indicates that the phase of the data signal DT is ahead of the phase of the clock signal CLK.

[0090] 8 turns off switch circuit SW1 and turns on switch circuit SW2 when the early / late signal EL is low, which causes charge to be discharged from the input of the low-pass filter LPF to the ground line GND, causing the low-pass filter LPF to increase the delay amount of the corresponding variable delay circuit VDL (one of VDL0-VDL3).

[0091] Figure 10 shows an example of the operation of the phase comparator PC of Figure 8 when the phase of the data signal DT lags behind the phase of the clock signal CLK. A detailed description of the same operations as in Figure 9 will be omitted. For example, the phase of the data signal DT lags behind the phase of the clock signal CLK means that the rising edge of the data signal DT is in the high level period of the clock signal CLK. Note that in Figure 10 as well, the enable signal CP_EN is set to high level "H".

[0092] As in Figure 9, the data signal DT_D1 is set to the logic level of the data signal DT at the rising edge of the clock signal CLK (Figure 10(a)). However, the data signal DT_D1 is set to a high level half a clock cycle or later from the rising edge of the data signal DT. The timing relationships between the waveform of the data signal DT_D1 and the waveforms of the data signal DT_D2, transition detection signal TRAN, and enable signal EL_EN are the same as in Figure 9 (Figures 10(b), (c), and (d)).

[0093] The data signal DT_A has the same waveform as the data signal DT_D1 (FIG. 10(e)). That is, the data signal DT_A is set to a high level half a clock cycle after the rising edge of the data signal DT. The data signal DT_B is set to a high level half a clock cycle after the rising edge of the data signal DT_A (FIG. 10(f)).

[0094] The data signal DT transitions from low to high during the high-level period of the clock CLK. Therefore, the data signal DT_C transitions to high in synchronization with the falling edge of the clock CLK immediately after the rising edge of the data signal DT (FIG. 10(g)). In other words, the waveform of the data signal DT_C is the same as that in FIG. 9.

[0095] As a result, the high-level periods of the data signals DT_B and DT_C are shifted from each other, and the delay signal DXOR and the early / late signal EL are sequentially set to high level for two clock cycles (FIG. 10(h) and (i)). The high-level early / late signal EL indicates that the phase of the data signal DT lags behind the phase of the clock signal CLK.

[0096] 8 turns on switch circuit SW1 and turns off switch circuit SW2 while the advance / delay signal EL is at a high level, causing the input of the low-pass filter LPF to be charged, and the low-pass filter LPF reduces the delay amount of the corresponding variable delay circuit VDL (one of VDL0-VDL3).

[0097] As described above, in this embodiment, the optical module switch device 100 sequentially connects two SERDES_H and SERDES_L with different transmission speeds between the optical module OM and the logic unit LOGIC. This allows the number of wires within the package PKG to be reduced compared to when the optical module OM and the logic unit LOGIC are connected via a single SERDES, as shown in FIG. 16 (described later). As a result, the length of the wires that are wired between the optical module OM and SERDES_H and transmit the highest speed signal (100 Gb / s) within the optical module switch device 100 can be minimized. In other words, the number of wires within the package PKG can be reduced, allowing the SERDES_H to be arranged close to the optical module OM.

[0098] Since the length of the wiring transmitting the highest speed signal (100 Gb / s) can be minimized, distortion of the transmitted signal can be reduced. As a result, the circuit that corrects distortion used to correctly determine the logical value of data on the signal receiving side can be simplified, thereby reducing power consumption. Furthermore, by shortening the length of the signal line, deterioration of the waveform in the time direction of the signal transmitted to the optical module OM can be reduced. This allows the retimer function of the optical module OM to be turned off, reducing power consumption of the optical module OM. As a result, power consumption of the optical module switch apparatus 100 can be reduced.

[0099] SERDES_H has a delay locked loop DLL_H that synchronizes the phase of the signal transmitted from SERDES_L with a clock signal CK25T used within SERDES_H. SERDES_L has a delay locked loop DLL_L that synchronizes the phase of the signal transmitted from SERDES_H with a clock signal CK25R_HL used within SERDES_L. This makes it possible to align the phases (transition timing) of signals transmitted in parallel even when the signal lines connecting SERDES_H and SERDES_L are long or when manufacturing variations in the lengths of the signal lines occur.

[0100] In the case of the delay-locked loop DLL_H shown in Figure 2, the transition timing of the 4-bit data signal DT25T_DLI is adjusted to coincide with the rising edge of the clock signal CK25T. This allows the generation of a data signal DT25T_DLO synchronized with the clock signal CK25T and free of phase variations among the four bits, allowing the data signal DT25T_DLO to be correctly received by the multiplexer MUX1, which is in the same clock domain as the clock signal CK25T. In the case of the delay-locked loop DLL_L shown in Figure 3, the transition timing of the 4-bit data signal DT25R_DLI is adjusted to coincide with the rising edge of the clock signal CK25R_HL. This allows the generation of a data signal DT25R_DLO synchronized with the clock signal CK25R_HL and free of phase variations among the four bits, allowing the data signal DT25R_DLO to be correctly received by the downstream demultiplexer DMX2.

[0101] The delay locked loops DLL_H and DLL_L sequentially adjust the phase of the 4-bit data DT in a time-division manner. Therefore, the phase of the 4-bit data DT can be adjusted using one phase comparator PC and one charge pump CP. As a result, the circuit scale of the delay locked loops DLL_H and DLL_L can be reduced compared to when a phase comparator PC and a charge pump CP are provided for each 4-bit data.

[0102] Fig. 11 shows an example of an optical module switch device according to another embodiment. Elements identical or similar to those in the above-described embodiment are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The optical module switch device 100A shown in Fig. 11 has a substrate BRD on which a package PKG is mounted.

[0103] The package PKG has an organic substrate, and a plurality of optical modules OM, a plurality of SERDES_H, and a semiconductor chip SWIC mounted on the organic substrate. The plurality of optical modules OM are mounted on the periphery of the package PKG. Note that, although eight optical modules OM are arranged on each side of the rectangular package PKG in FIG. 11, in reality, 16 optical modules OM are arranged on each side of the package PKG (eight on the front side of the substrate BRD and eight on the back side of the substrate BRD). As in FIG. 1, the optical modules OM and the serializer / deserializer SERDES_H on the back side of the substrate BRD are connected via wiring formed on the substrate BRD, bumps connecting the substrate BRD and the package PKG, and wiring formed on the package PKG.

[0104] The optical module OM is disposed on the package PKG, inside the outer periphery of the package PKG. The serializer / deserializer SERDES_H is disposed in a position close to the optical module OM. The semiconductor chip SWIC is mounted in the center of the package PKG and has multiple SERDES_L and a logic unit LOGIC that performs routing processing. That is, the optical module switch device 100A has the same circuit configuration as the optical module switch device 100 in FIG. 1, except that the optical module OM is mounted in the package PKG. As shown in FIG. 11, the optical module switch device 100A has a CPO (Co-Package Optics) form.

[0105] As described above, the optical module switch apparatus 100A having the CPO configuration of this embodiment can also achieve the same effects as the above-described embodiments. For example, the length of the signal wiring connecting the SERDES_H and the optical module OM can be shortened, minimizing the length of the wiring transmitting the highest speed signal (100 Gb / s), thereby reducing distortion in the transmitted signal. As a result, the distortion correction circuit used to correctly determine the logical value of data on the signal receiving side can be simplified, thereby reducing power consumption. Furthermore, the retimer function of the optical module OM can be turned off, reducing power consumption of the optical module OM. As a result, power consumption of the optical module switch apparatus 100A can be reduced.

[0106] Fig. 12 shows an example of delay locked loops DLL_H and DLL_L mounted in the SERDES_H and SERDES_L of an optical module switch device according to another embodiment. Elements identical to or similar to those in Fig. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. The delay locked loop DLL_H (or DLL_L) shown in Fig. 12 is mounted in the SERDES_H (or SERDES_L) of the optical module switch device 100 in Fig. 1 or the optical module switch device 100A in Fig. 11.

[0107] Since the delay locked loops DLL_H and DLL_L are identical circuits, only the delay locked loop DLL_H will be described. As in Fig. 5, in the delay locked loop DLL_L, the data signals DT25T_DLI and DT25T_DLO are replaced by the data signals DT25R_DLI and DT25R_DLO shown in parentheses, respectively. Furthermore, the clock signals CK25T and CK25T2 are replaced by the clock signals CK25R_HL and CK25R_HL2 shown in parentheses, respectively.

[0108] The delay locked loop DLL_H of this embodiment has a selection control unit SELCNT2, phase comparators PC0-PC3, and charge pumps CP0-CP3 instead of the selection control unit SELCNT, phase comparator PC, and charge pump CP of FIG. 5. Furthermore, the delay locked loop DLL_H does not have the selectors SEL1, SEL2, and SEL3 shown in FIG. 5. The other configuration of the delay locked loop DLL_H is the same as or similar to that of the delay locked loop DLL_H of FIG. 5. The phase comparators PC0-PC3, charge pumps CP0-CP3, and low-pass filters LPF0-LPF3 are an example of a delay amount determination circuit that determines the delay amount of each of the variable delay circuits VDL0-VDL3.

[0109] A phase comparator PC0 and a charge pump CP0 are provided corresponding to the low-pass filter LPF0. A phase comparator PC1 and a charge pump CP1 are provided corresponding to the low-pass filter LPF1. A phase comparator PC2 and a charge pump CP2 are provided corresponding to the low-pass filter LPF2. A phase comparator PC3 and a charge pump CP3 are provided corresponding to the low-pass filter LPF3.

[0110] The configurations of the phase comparators PC0-PC3 and the charge pumps CP0-CP3 are the same as or similar to those in Figure 8. The enable signal CP_EN output by the selection control unit SELCNT2 is supplied to the phase comparators PC0-PC3 and the charge pumps CP0-CP3. This allows the delay locked loop DLL_H (or DLL_L) in Figure 12 to adjust the delay amounts of the variable delay circuits VDL0-VDL3 in parallel.

[0111] Figure 13 shows an example of the selection control unit SELCNT2 of Figure 12. Elements that are the same as or similar to those in Figure 6 are given the same reference numerals, and detailed description will be omitted. The selection control unit SELCNT2 has the same configuration as the selection control unit SELCNT of Figure 6, except that it does not have the AND circuit AND12, counter CNT2, or comparator CMP3. The reset terminal RST of the flip-flop FF6 receives a reset signal CNT1_RST.

[0112] Figure 14 shows an example of the operation of the selection control unit in Figure 13. Detailed description of operations that are the same as or similar to those in Figure 7 will be omitted. The number of clock cycles indicated by the period signal DLL_TERM is assumed to be "512." The waveforms of the clock signal CK25T2 (CK25R_HL2), the period signal DLL_TERM, and the enable signal DLL_EN_D are the same as those in Figure 7.

[0113] The selection control unit SELCNT2 sets the enable signal CP_EN to high level in response to the change of the enable signal DLL_EN to high level (FIG. 14(a)). As a result, the counter CNT1 updates the count value CNT11 by "1" in synchronization with the clock signal CK25T2 (FIG. 14(b)).

[0114] 12 operate in parallel while the enable signal CP_EN is at a high level. That is, the VDL0 adjustment period to the VDL3 adjustment period are set to overlap each other (FIG. 14(c)).

[0115] The delay locked loops DLL_H and DLL_L of this embodiment can adjust the delay amounts of the variable delay circuits VDL0-VDL3 in parallel. Therefore, the delay amounts of the variable delay circuits VDL0-VDL3 can be adjusted more frequently than the adjustment frequency by the selection control unit SELCNT shown in Figure 7. As a result, the adjustment time for the phase of the data signal DT can be shortened (one-fourth of that in Figure 5) compared to the delay locked loops DLL_H and DLL_L of Figure 5.

[0116] The phase comparators PC0-PC3 compare the phase of the data signal DT output from the variable delay circuits VDL0-VDL3 with that of the clock signal CK25T2, and output the comparison results to the charge pumps CP0-CP3, respectively. The charge pumps CP0-CP3 output voltages to the variable delay circuits VDL0-VDL3, respectively, that adjust the delay amounts according to the comparison results of the phase comparators PC0-PC3.

[0117] The comparator CMP1 sets the reset signal CNT1_RST to high level based on the fact that the count value CNT11 has reached "512" (FIG. 14(d)). As a result, the enable signal CP_EN changes to low level, and the count value CNT11 is reset to "0" (FIGS. 14(e)(f)). The change of the enable signal CP_EN to low level ends the VDL0 adjustment period-VDL3 adjustment period.

[0118] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, the length of the wiring that transmits high-speed signals (100 Gb / s) connecting the SERDES_H and the optical module OM can be minimized, thereby reducing distortion in the transmitted signal. As a result, the circuit that corrects distortion used to correctly determine the logical value of data on the signal receiving side can be simplified, thereby reducing power consumption. In addition, the retimer function of the optical module OM can be turned off, thereby reducing power consumption of the optical module OM. As a result, the power consumption of the optical module switch device can be reduced.

[0119] Furthermore, in this embodiment, since the delay amounts of the variable delay circuits VDL0-VDL3 can be adjusted in parallel, the frequency of adjustment of the delay amounts of the variable delay circuits VDL0-VDL3 can be made higher than the frequency of adjustment by the selection control unit SELCNT shown in Fig. 7. As a result, the adjustment time for the phase of the data signal DT can be made shorter than in the delay locked loops DLL_H and DLL_L of Fig. 5.

[0120] Figure 15 shows another example of an optical module switch device. Elements that are the same as or similar to those in Figure 1 are given the same reference numerals, and detailed descriptions will be omitted. The optical module switch device 100B shown in Figure 15 has a substrate BRD on which a plurality of optical modules OM and packages PKG are mounted. For example, 16 optical modules OM (8 on the front side and 8 on the back side) are mounted along each side of the rectangular substrate BRD.

[0121] The package PKG includes an organic substrate and a semiconductor chip SWIC mounted on the organic substrate. The optical module switch device 100B has an NPO configuration. The semiconductor chip SWIC includes multiple serializer / deserializers SERDES connected to multiple optical modules OM, and a logic unit LOGIC that performs routing processing. Hereinafter, the serializer / deserializer SERDES will also be simply referred to as SERDES.

[0122] The logic unit LOGIC is connected to multiple SERDES. Each SERDES is provided in place of SERDES_H and SERDES_L in Figure 1. For example, a semiconductor chip SWIC is equipped with 512 SERDES, with 128 SERDES arranged on each side of the semiconductor chip SWIC. One SERDES group, shown as a rectangle in Figure 15, contains 128 SERDES.

[0123] Each SERDES is connected to each optical module OM via a 1-bit signal line for transmission and a 1-bit signal line for reception. The transmission speed of the electrical signal that each SERDES transmits to or receives from the optical module OM is, for example, 100 Gb / s. Each optical module OM is connected to eight SERDES.

[0124] The signal lines connecting each SERDES to each optical module OM are longer than the signal lines connecting each SERDES_H in Figure 1 to each optical module OM. This increases the distortion of the fastest 100 Gb / s signal, necessitating a distortion correction circuit used to correctly determine the logical value of the data on the signal receiving side. As a result, power consumption increases compared to the optical module switching device 100 in Figure 1. In addition, the re-timer function built into the optical module OM is turned on to shape the waveform of the signal received by each optical module OM via the signal line, further increasing power consumption.

[0125] The power consumption of 64 optical modules OM with the retimer function turned on is, for example, 1250 W, and the total power consumption of the SERDES required for transmitting and receiving signals on the signal lines connecting each SERDES to each optical module OM is 250 W. Therefore, the power consumption of the optical module switching apparatus 100B is 1500 W.

[0126] On the other hand, in the optical module switch apparatus 100 shown in FIG. 1 and the optical module switch apparatus 100A shown in FIG. 11, the retimer function of the optical module OM is turned off. Furthermore, the signal lines connecting each SERDES_H to each optical module OM are shorter than the signal lines connecting each SERDES to each optical module OM in FIG. 15. Therefore, the power consumption of 64 optical modules OM is, for example, 625 W. The total power required for each SERDES_H to transmit and receive signals to and from each optical module OM is 125 W because the distortion correction circuit can be simplified. Therefore, the power consumption of each of the optical module switch apparatuses 100 and 100A is 750 W, half the power consumption of the optical module switch apparatus 100B.

[0127] Figure 16 shows another example of an optical module switch device. Elements that are the same as or similar to those in Figure 1 are given the same reference numerals, and detailed descriptions will be omitted. The optical module switch device 100C shown in Figure 16 has a substrate BRD on which multiple optical modules OM and packages PKG are mounted. For example, 16 optical modules OM (8 on the front side and 8 on the back side) are mounted along each side of the rectangular substrate BRD.

[0128] The package PKG has an organic substrate, multiple SERDES mounted on the organic substrate, and a logic chip LCHIP that performs routing processing. The logic chip LCHIP is connected to multiple serializer / deserializer SERDES. Each SERDES is provided in place of SERDES_H and SERDES_L in Figure 1. The package PKG is equipped with 512 SERDES, with 128 SERDES arranged on each side of the package PKG. One SERDES group, shown as a rectangle in Figure 16, contains 64 SERDES.

[0129] Each SERDES is connected to each optical module OM via a 1-bit signal line for transmission and a 1-bit signal line for reception. The transmission speed of the electrical signal that each SERDES transmits to or receives from the optical module OM is, for example, 100 Gb / s. Each optical module OM is connected to eight SERDES. Furthermore, the transmission speed of the electrical signal transmitted to each bit of the multi-bit signal line connecting the logic chip LCHIP and each SERDES is, for example, 3.125 Gb / s.

[0130] The wiring used to send and receive 1-bit signals between the SERDES and the logic chip LCHIP consists of six wires: two differential signal wires for sending, two differential signal wires for receiving, one shielded wire for sending, and one shielded wire for receiving. The transmission speed of signals transmitted to the 16 optical modules OM arranged on one side of the substrate BRD is 12,800 Gb / s.

[0131] To achieve this transmission speed, the number of wires wired from the logic chip LCHIP to the 128 SERDES arranged on one side of the package PKG is 24,576 (6 wires for every 4,096 signals). Therefore, it is necessary to form at least 98,304 terminals on the logic chip LCHIP, which makes it difficult to realize the logic chip LCHIP and the package PKG.

[0132] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0133] 100, 100A, 100B, 100C Optical module switch device B1, B2 buffers BRD substrate BUF0-BUF4 buffers CK25T clock signal CK25R_HL clock signal CP, CP0-CP3 charge pump CP_EN Enable signal CRU Clock Recovery Circuit DLL_EN enable signal DLL_H, DLL_L Delay Lock Loop DLL_TERM period signal DMX1, DMX2 Demultiplexer DT Data Signal DT25R_DLI, DT25R_DLO DT25T_DLI, DT25T_DLO EL early / late signal ELBUF Elastic buffer EL_EN Enable signal EQ Equalizer FDIV1, FDIV2 frequency divider FF0-FF3 flip-flops FF_H, FF_L flip-flops LCHIP Logic Chip LOGIC Logic section LPF0-LPF3 low-pass filters MUX1, MUX2 multiplexers OC Optical Cable ODRV Output Driver OM Optical Module PC, PC0-PC3 phase comparator PKG Package PLL Phase Locked Loop REFCK Reference clock signal RXDT data signal SEL1, SEL2, SEL3 selectors SELCNT, SELCNT2 selection control section SERDES Serializer / Deserializer SERDES_H, SERDES_L Serializer / Deserializer SWIC semiconductor chip TXDT Data signal VDL0-VDL3 variable delay circuits

Claims

1. a first serial-to-parallel conversion unit connected to first signal lines connected to the optical module and second signal lines, the number of which is greater than the first signal lines, and configured to transmit and receive first signals at a first transmission rate between the optical module and the first signal lines using the first signal lines; a second serial-to-parallel conversion unit connected to the second signal lines connected to the first serial-to-parallel conversion unit and to third signal lines, the number of which is greater than the second signal lines, and configured to transmit and receive second signals to and from the first serial-to-parallel conversion unit at a second transmission rate lower than the first transmission rate using each of the second signal lines; a logic unit connected to the third signal lines, transmitting and receiving third signals to and from the second serial-to-parallel conversion unit at a third transmission rate lower than the second transmission rate using each of the third signal lines, and performing routing processing based on the received third signals; the first serial-to-parallel conversion unit includes a first phase-locked loop circuit that synchronizes the second signal of multiple bits received from the second serial-to-parallel conversion unit with a first clock signal used in the first serial-to-parallel conversion unit; The second serial-to-parallel conversion unit has a second phase-locked loop circuit that synchronizes the second signal of multiple bits received from the first serial-to-parallel conversion unit with a second clock signal used in the second serial-to-parallel conversion unit. Optical module switch device.

2. The first phase locked loop circuit a plurality of variable delay circuits that adjust, for each bit, a delay amount of the second signal of multiple bits received from the second serial-to-parallel conversion unit; a selection circuit that sequentially selects any one of the bits of the second signal whose delay amount has been adjusted by the plurality of variable delay circuits; a delay amount determination circuit that compares the phase of the bit selected by the selection circuit with the phase of the first clock signal and determines the delay amount of the variable delay circuit corresponding to the bit selected by the selection circuit based on the comparison result; 2. The optical module switch device according to claim 1, further comprising:

3. The second phase locked loop circuit a plurality of variable delay circuits that adjust, for each bit, a delay amount of the second signal of multiple bits received from the first serial-to-parallel conversion unit; a selection circuit that sequentially selects any one of the bits of the second signal whose delay amount has been adjusted by the plurality of variable delay circuits; a delay amount determination circuit that compares the phase of the bit selected by the selection circuit with the phase of the second clock signal and determines the delay amount of the variable delay circuit corresponding to the bit selected by the selection circuit based on the comparison result; 2. The optical module switch device according to claim 1, further comprising:

4. The first phase locked loop circuit a plurality of variable delay circuits that adjust, for each bit, a delay amount of the second signal of multiple bits received from the second serial-to-parallel conversion unit; a delay amount determination circuit that compares in parallel the phase of each bit of the second signal, the delay amounts of which have been adjusted by the plurality of variable delay circuits, with the phase of the first clock signal, and determines the delay amounts of each of the plurality of variable delay circuits based on the comparison result; 2. The optical module switch device according to claim 1, further comprising:

5. The second phase locked loop circuit a plurality of variable delay circuits that adjust, for each bit, a delay amount of the second signal of multiple bits received from the first serial-to-parallel conversion unit; a delay amount determination circuit that compares in parallel the phase of each bit of the second signal, the delay amounts of which have been adjusted by the plurality of variable delay circuits, with the second clock signal, and determines the delay amounts of each of the plurality of variable delay circuits based on the comparison result; 2. The optical module switch device according to claim 1, further comprising:

6. a package on which the first serial-to-parallel conversion unit and a semiconductor chip including the second serial-to-parallel conversion unit and a logic unit are mounted; a substrate on which the package and the optical module are mounted, The length of the first signal line is shorter than the length of the second signal line.

6. The optical module switch device according to claim 1.

7. the first serial-to-parallel conversion unit is disposed on the package and inside the outer periphery of the package, the optical module is disposed on the substrate and outside the periphery of the package; The semiconductor chip is disposed in the center of the package.

7. The optical module switch device according to claim 6.

8. a package in which the optical module, the first serial-to-parallel conversion unit, and a semiconductor chip including the second serial-to-parallel conversion unit and a logic unit are mounted; a substrate on which the package is mounted, The length of the first signal line is shorter than the length of the second signal line.

6. The optical module switch device according to claim 1.

9. the optical module is disposed on the package and inside the outer periphery of the package; the first serial-to-parallel conversion unit is disposed in proximity to the optical module; The semiconductor chip is disposed in the center of the package.

9. The optical module switch device according to claim 8.

Images