Information processing device

Abstract

To provide a device which offers high transfer speed and yet allows easy replacement of modules.SOLUTION: An information processing device (1) is provided, comprising first modules (20) having computation circuits (22) for performing predetermined computations, and second modules (30) that can be connected in series by a serial bus (51) and is configured to allow at least one of the first modules (20) to be connected in parallel.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to an information processing device. [Background technology]

[0002] A bus is a transmission path that connects multiple modules of information processing devices and transfers data between the modules. Known communication methods for such buses include parallel buses and serial buses.

[0003] In the parallel bus type, a CPU (Central Processing Unit) module and an IO (Input / Output) module are generally mounted on a base module, and each module is connected by a parallel bus wired on the base module. The CPU module acts as the communication master and performs read / write access to the IO module via the parallel bus. The parallel bus is a bidirectional bus.

[0004] In the serial bus type, a base module is generally not required, and adjacent modules are connected via a serial bus. The CPU module acts as the communication master and sends commands to the IO module. The IO module that receives the command addressed to itself returns a response to the CPU module. The serial bus is a one-way bus, and commands and responses are transmitted in a fixed direction. When each IO module receives a command and response addressed to another station, it passes it on to the next IO module, transmitting it.

[0005] Because the parallel bus is a multi-drop circuit topology, the entire bus is occupied during access, and the next access cannot begin until the previous access is completed. Also, as the number of connected devices increases, the signal waveform becomes more likely to become distorted, making it difficult to increase the transfer speed.

[0006] Because serial buses have a point-to-point circuit topology, they provide stable signal waveforms regardless of the number of devices connected, making it easier to increase transfer speeds. They also have fewer signals than parallel buses. For these reasons, serial buses have become more popular recently. Unlike parallel buses, the entire bus is not occupied, and multiple commands and responses can be sent and received at once on a serial bus, making it possible to use the bus more efficiently than a parallel bus.

[0007] Therefore, in order to increase the transfer speed, there is a shift from parallel buses to serial buses. For example, the parallel bus PCI (Peripheral Component Interconnect) has been replaced by the serial bus PCI express, and the parallel bus ATA (Advanced Technology Attachment) has been replaced by the serial bus Serial ATA.

[0008] Patent Document 1 describes a technique relating to a configuration in which a plurality of modules are connected via a serial bus. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2019-134417 Summary of the Invention [Problem to be solved by the invention]

[0010] However, because a serial bus is configured as a point-to-point type circuit topology, module replacement is more difficult than with a parallel bus, which has a multi-drop type circuit topology.

[0011] Therefore, an object of the present disclosure is to provide a device that allows easy module replacement while achieving a high transfer speed. [Means for solving the problem]

[0012] An information processing device according to some embodiments includes a first module having an arithmetic circuit that performs a predetermined calculation, and a plurality of second modules that can be connected in series to each other via a serial bus, with at least one of the first modules being connectable in parallel to each other.

[0013] In this way, in the information processing device, multiple second modules, each connectable to at least one first module, are connected in series via a serial bus, enabling high-speed data transfer. Furthermore, the multiple second modules can each be connected in parallel to at least one first module, making it easy to replace the first module. Therefore, the information processing device allows for easy module replacement while achieving high transfer speeds.

[0014] In one embodiment, the system further includes a third module that controls the operation of the first module connected to the plurality of second modules, the third module being serially connectable via a serial bus to the second module connected to another one of the plurality of second modules. Thus, the third module controls the operation of each first module 20, allowing the first module 20 to perform an operation desired by a user.

[0015] In one embodiment, each of the second modules includes a slave communication circuit for communicating with the other second modules and the third module, and the third module includes a master communication circuit for communicating with the second modules, the master communication circuit controlling communication with the slave communication circuits of the second modules connected in series by a serial bus. With this configuration, high-speed communication between modules can be achieved by controlling the master communication circuit of the third module.

[0016] In one embodiment, the plurality of second modules have a structure that allows the plurality of first modules to be inserted and removed without interfering with each other, which makes it easier to replace the first modules.

[0017] In one embodiment, the first module and the second module are hot-swappable. With this configuration, the first module can be replaced while the information processing device 1 is operating, making it even easier to replace the first module.

[0018] In one embodiment, each of the plurality of second modules further includes an IO communication circuit for communicating between the first module and the slave communication circuit when the first module is connected to the second module. With this configuration, a first module connected to a second module can communicate with other first modules, etc., via the IO communication circuit and the slave communication circuit included in the second module. [Effects of the Invention]

[0019] According to one embodiment of the present disclosure, modules can be easily replaced while achieving a high transfer rate. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 10 is a diagram illustrating a configuration of a controller according to a comparative example. [Figure 2] FIG. 10 is a diagram illustrating a configuration of a controller according to a comparative example. [Figure 3] 2 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 1. FIG. [Figure 4] 2 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 1. FIG. [Figure 5] 2 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 1. FIG. [Figure 6]3 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 2. FIG. [Figure 7] 3 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 2. FIG. [Figure 8] 3 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 2. FIG. [Figure 9] FIG. 2 is a diagram illustrating a configuration example of a controller according to an embodiment of the present disclosure. [Figure 10] 10 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 9. FIG. [Figure 11] 10 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 9. FIG. [Figure 12] 10 is a diagram illustrating the insertion and removal of a module in the controller of FIG. 9. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0021] <Comparative Example> 1 and 2 are diagrams showing the configuration of a controller 9 (9a, 9b) according to a comparative example. Fig. 1 shows a controller 9a in which multiple modules 91, 92 (92a, 92b, 92c, 92d) are connected via a parallel bus 94. Fig. 2 shows a controller 9b in which multiple modules 91, 92 (92a, 92b, 92c, 92d) are connected via a serial bus 95.

[0022] 1, the controller 9a includes a CPU (Central Processing Unit) module 91, a plurality of IO modules 92 (92a, 92b, 92c, and 92d), a base module 93, and a parallel bus 94.

[0023] The CPU module 91 is a module that controls the overall operation of the controller 9a by integrating the various components included in the controller 9a. The CPU module 91 includes an external I / F (Interface) 911, an arithmetic circuit 912, and a master communication circuit 913. The external I / F 911 is an interface for connecting to an external device. The arithmetic circuit 912 is a processor that performs arithmetic processing based on communication with the external I / F 911 and the IO module 92. The master communication circuit 913 is a communication circuit that communicates with the IO module 92 via a parallel bus 94.

[0024] The IO modules 92 (92a, 92b, 92c, 92d) are modules that perform dedicated arithmetic processing. The IO module 92 includes an external I / F (Interface) 921, an arithmetic circuit 922, and a slave communication circuit 923. The external I / F 921 is an interface for connecting to an external device. The arithmetic circuit 922 is a processor that performs arithmetic processing based on communication with the external I / F 921, the CPU module 91, and other IO modules 92. The slave communication circuit 923 is a communication circuit that communicates with the CPU module 91 and other IO modules 92 via a parallel bus 94.

[0025] The base module 93 is a board for connecting the CPU module 91 and the IO modules 92 (92a, 92b, 92c, 92d) to the parallel bus 94.

[0026] The parallel bus 94 is a bus that connects the CPU module 91 and the IO modules 92 (92a, 92b, 92c, 92d) in parallel. The parallel bus 94 is wired on the base module 93.

[0027] 2, the controller 9b includes a CPU module 91, a plurality of IO modules 92 (92a, 92b, 92c, and 92d), and a serial bus 95.

[0028] In a configuration in which multiple modules 91, 92 (92a, 92b, 92c, 92d) are connected by a parallel bus 94 as shown in FIG. 1, a certain IO module 92 can be inserted or removed independently of the other IO modules 92. Therefore, in a configuration using the parallel bus 94, modules can be easily replaced. On the other hand, in a configuration in which multiple modules 91, 92 are connected by a serial bus 95 as shown in FIG. 2, the connection relationship between the IO modules 92 must be changed in order to insert or remove a certain IO module 92. Therefore, in a configuration using the serial bus 95, replacing modules is more difficult than in a configuration using the parallel bus 94.

[0029] The ease of inserting and removing such modules will be described with reference to Figures 3 to 8. Figures 3 to 5 are diagrams for explaining the insertion and removal of modules in the controller 9a of Figure 1. Figures 6 to 8 are diagrams for explaining the insertion and removal of modules in the controller 9b of Figure 2.

[0030] 3, in the controller 9a, the CPU module 91 and the IO modules 92 (92a, 92b, 92c, 92d) are attached to the front of the base module 93. When the CPU module 91 or the IO module 92 is attached to the base module 93, the master communication circuit 913 or the slave communication circuit 923 is connected to a parallel bus 94 wired on the base module 93, and communication with other modules connected to the parallel bus 94 becomes possible.

[0031] 4 shows a state in which the CPU module 91 and all of the IO modules 92 (92a, 92b, 92c, 92d) are attached to the base module 93. FIG. 5 shows a state in which the IO module 92b is removed from the base module 93 to which the CPU module 91 and the IO modules 92 (92a, 92b, 92c, 92d) are attached. As shown in FIG. 5, when replacing the IO module 92b, the IO module 92b is pulled out from the front of the base module 93.

[0032] 3 to 5, the insertion and removal directions of the CPU module 91 and the IO module 92 are perpendicular to the base module 93, and when these modules are attached to the base module 93, they are connected in parallel to each other. The controller 9a can operate even if an IO module 92 is not attached in a position adjacent to a certain IO module 92. Therefore, the CPU module 91 and the IO module 92 can be inserted and removed independently of each other.

[0033] On the other hand, in the controller 9b, as shown in FIG. 6, the CPU module 91 and the IO modules 92 (92a, 92b, 92c, and 92d) are connected horizontally via a serial bus 95. Each of the CPU module 91 and the IO modules 92 has a connector on its side. When these modules are connected horizontally as shown in FIG. 7, each module communicates directly with its adjacent module. As shown in FIG. 8, when replacing the IO module 92b, the IO module 92b must be separated from the IO modules 92a and 92c. To separate the IO module 92b from the IO modules 92a and 92c, the CPU module 91 and the IO module 92d must also be moved simultaneously. Thus, in a configuration in which multiple modules are connected via a serial bus 95, the modules on both sides of the module to be replaced must be separated before the module can be replaced. Therefore, when replacing modules, the serial bus-type controller 9b, which has a horizontal connection structure, is more difficult than the parallel bus-type controller 9a. This is particularly problematic when the modules are housed in a housing that occupies a certain amount of space.

[0034] On the other hand, in a configuration in which a plurality of modules are connected via a parallel bus 94, it is more difficult to increase the data transfer speed than in a configuration in which modules are connected via a serial bus 95.

[0035] <Embodiment> Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, parts having the same configuration or function are denoted by the same reference numerals. In the description of this embodiment, duplicated descriptions of the same parts may be omitted or simplified as appropriate.

[0036] A serial bus-type IO module 92 as shown in FIG. 2 includes an external I / F 921, an arithmetic circuit 922, and a slave communication circuit 923. In contrast, in a controller according to the present disclosure, these components are separated into a slave communication circuit and an IO communication circuit in the base module, and an external I / F, an arithmetic circuit, and a communication circuit in the IO module. In other words, in a controller according to the present disclosure, base modules each equipped with one or more pluggable IO modules are connected in series horizontally. One or more IO modules can be arranged vertically for each base module, and the base module can communicate in parallel with one or more IO modules. Therefore, the controller according to the present disclosure employs a serial bus-type structure, which allows for high transfer speeds throughout the device, while also allowing for easy replacement of IO modules after installation.

[0037] FIG. 9 is a diagram illustrating a configuration example of a controller 1 as an information processing device according to an embodiment of the present disclosure. As illustrated in FIG. 9, the controller 1 includes a CPU module 10, one or more IO modules 20 (20a, 20b, 20c, and 20d), and multiple base modules 30 (30a and 30b). The CPU module 10 and the base modules 30 (30a and 30b) are connected to each other via a serial bus 51. As an example of such a configuration, FIG. 9 illustrates the controller 1 including one CPU module 10, two base modules 30, each capable of mounting up to two IO modules 20, and four IO modules 20. In the example illustrated in FIG. 9, two IO modules 20a and 20b are mounted in parallel to the base module 30a. Two IO modules 20c and 20d are mounted in parallel to the base module 30b.

[0038] The number of CPU modules 10, the number of IO modules 20, and the number of base modules 30 included in the controller 1, as well as the number of IO modules 20 that can be attached to the base modules 30, may all be any number equal to or greater than one. The number of IO modules 20 that can be attached to the base modules 30 may differ for each base module 30. For example, a maximum of one IO module 20 may be connectable to the base module 30a, and a maximum of three IO modules 20 may be connectable to the base module 30b. The controller 1 may also include types of modules other than the CPU modules 10 and the IO modules 20.

[0039] The CPU module 10, which serves as a third module, is a module that manages the components included in the controller 1 and controls the overall operation of the controller 1. The CPU module 10 may operate based on any real-time operating system (OS), including, for example, Linux and VxWorks. The CPU module 10 includes an external I / F 11, an arithmetic circuit 12, and a master communication circuit 13. As shown in FIG. 9 , in this embodiment, the CPU module 10 is serially connected via a serial bus 51 to a base module 30a, which is connected to another base module (e.g., base module 30b) among a plurality of base modules 30 connected in series.

[0040] The external I / F 11 is an interface for connecting to an external device. Such an external device may include an input / output device such as a personal computer (PC) or a tablet terminal, a keyboard, a pointing device, or a display. The external I / F 11 may be connected to such an external device via any network including the Internet.

[0041] The arithmetic circuit 12 is a processor that performs arithmetic processing based on communication with the external I / F 11 and the IO module 20. The arithmetic circuit 12 is, for example, but not limited to, a general-purpose processor or a dedicated processor specialized for a specific process. The arithmetic circuit 12 may also include a memory for storing data required for the arithmetic processing.

[0042] The master communication circuit 13 is a communication circuit that communicates with the base modules 30 (30a, 30b) via a serial bus 51. The master communication circuit 13 is connected in series to each base module 30 via the serial bus 51. Communication between the CPU module 10 and the base modules 30 is performed under the control of the master communication circuit 13.

[0043] The IO modules 20 (20a, 20b, 20c, and 20d) as first modules are modules that perform dedicated arithmetic processing. The arithmetic processing performed by the IO modules 20 may include, for example, connection to specific networks such as a CAN (Controller Area Network), Ethernet, and Modbus, input / output of digital signals, pulse signals, and analog signals, temperature control such as temperature adjustment, temperature monitoring, and disconnection detection, data collection, counters for specific signals, and positioning. The IO modules 20 include an external I / F (Interface) 21, an arithmetic circuit 22, and a communication circuit 23.

[0044] The external I / F 21 is an interface for connecting to an external device. For example, the external I / F 21 of the IO module 20 that monitors temperature may be connected to a temperature sensor and receive an electrical signal indicating the temperature. Alternatively, the external I / F 21 of the IO module 20 that operates as a counter may be connected to a device that outputs a specific signal (e.g., a pulse signal) in response to detection of a predetermined operation.

[0045] The arithmetic circuit 22 is a processor that performs arithmetic processing based on communications with the external I / F 21, the CPU module 10, and other IO modules 20. For example, the arithmetic circuit 22 of an IO module 20 that monitors temperature may generate information indicating temperature based on an electrical signal received from a temperature sensor and output the information to the CPU module 10 via the base module 30. Furthermore, the arithmetic circuit 22 of an IO module 20 that monitors temperature may output control information, including a sampling period or temperature resolution, to the temperature sensor via the external I / F 21 based on an instruction from the CPU module 10. Alternatively, for example, the arithmetic circuit 22 of an IO module 20 that operates as a counter may count the number of times a specific signal is received from an external device. Furthermore, the arithmetic circuit 22 may include a memory for storing data necessary for arithmetic processing.

[0046] The communication circuit 23 is a communication circuit that communicates with the CPU module 10 and other IO modules 20 via the base module 30. In the controller 1, the IO module 20 is insertable into and removable from the base module 30. When the IO module 20 is attached to the base module 30, the communication circuit 23 is electrically connected to an IO communication circuit 31 of the base module 30 (described later), enabling communication between the IO module 20 and the base module 30. For example, the communication circuit 23 of the IO module 20 that monitors the temperature may transmit information indicating the monitored temperature to the CPU module 10 via the IO communication circuit 31. Alternatively, the communication circuit 23 of the IO module 20 that monitors the temperature may receive control information for the temperature sensor from the CPU module 10 via the IO communication circuit 31.

[0047] The base modules 30 (30a, 30b) as second modules are boards for connecting the CPU module 10 and the IO modules 20 (20a, 20b, 20c, 20d) to each other. The base modules 30 include one or more IO communication circuits 31 and a slave communication circuit 32. In FIG. 9, as an example of such a configuration, each of the base modules 30 (30a, 30b) includes two IO communication circuits 31, and up to two IO modules 20 can be attached.

[0048] The IO communication circuit 31 is a communication circuit that allows the base module 30 to connect and communicate with the IO module 20. An IO communication circuit 31 may be provided at each connection position of the IO module 20 in the base module 30. When the IO module 20 is attached to the base module 30, the communication circuit 23 of the IO module 20 and the IO communication circuit 31 are electrically connected, enabling communication between the IO module 20 and the base module 30. In other words, the IO module 20 connected to the base module 30 can communicate with other IO modules 20 and the CPU module 10 via the IO communication circuit 31 and the slave communication circuit 32 provided in the base module 30. The communication circuit 23 and the IO communication circuit 31 of the IO module 20 may have shapes that allow them to engage with each other.

[0049] The slave communication circuit 32 is a communication circuit that communicates with the CPU module 10 and other base modules 30 via the serial bus 51 and with the IO module 20 via the IO communication circuit 31. The slave communication circuit 32 is connected in series to the CPU module 10 and other base modules 30 via the serial bus 51. The slave communication circuit 32 can communicate with the CPU module 10 and other base modules 30 via the serial bus 51 even if no IO module 20 is connected to the base module 30. For example, assume that no IO module 20 is connected to the base module 30a and only the IO module 20c is connected to the base module 30b. In this case, the CPU module 10 and the IO module 20c can communicate with each other via the slave communication circuit 32 of the base module 30a and the slave communication circuit 32 and IO communication circuit 31 of the base module 30b.

[0050] The CPU module 10, the IO module 20, and the base module 30 operate by receiving power from a power supply (not shown). However, for example, when the IO module 20 is connected to the base module 30, it may receive power from the base module 30 via the communication circuit 23 and the IO communication circuit 31. Furthermore, the CPU module 10 and each base module 30 may operate by receiving power from another device via the serial bus 51.

[0051] 9, the master communication circuit 13 of the CPU module 10, the slave communication circuit 32 of the base module 30a, and the slave communication circuit 32 of the base module 30b are connected by a serial bus 51. Therefore, high-speed communication can be performed between the CPU module 10 and the base module 30 to which the IO modules 20 are connected, and high-speed arithmetic processing can be performed by the CPU module 10 and one or more IO modules 20.

[0052] Furthermore, the IO modules 20 mounted on each base module 30 are connected in parallel. An IO module 20 can be inserted or removed independently of other IO modules 92. Therefore, in the controller 1, modules can be easily replaced.

[0053] 10 to 12 are diagrams for explaining insertion and removal of the IO module 20 in the controller 1 of FIG.

[0054] As shown in FIG. 10, in the controller 1, the CPU module 10 and base modules 30 (30a, 30b) are connected horizontally via a serial bus 51. Each of the CPU module 10 and base module 30 has a connector on its side, and when these are connected horizontally as shown in FIG. 11, each module communicates directly with the adjacent module. Each base module 30a, 30b has a structure that prevents interference with other IO modules 20 when inserting or removing the IO modules 20. For example, the IO modules 20a, 20b are attached to the base module 30a from the front when used. The IO modules 20c, 20d are attached to the base module 30b from the front when used.

[0055] As shown in FIG. 11, when the CPU module 10, the IO modules 20 (20a, 20b, 20c, 20d), and the base modules 30 (30a, 30b) are connected, the CPU module 10 and the IO modules 20 can perform calculations.

[0056] 12 shows how an IO module 20b is removed from a base module 30a. As shown in FIG. 12, when replacing an IO module 20b, the IO module 20b is pulled out from the front of the base module 30a. In this way, each base module 30a, 30b has a structure that prevents interference with other IO modules 20 when inserting or removing an IO module 20, so that the IO module 20b can be inserted or removed independently of the other IO modules 20a, 20c, and 20d. Therefore, modules can be easily replaced in the controller 1.

[0057] As described above, the controller 1 includes an IO module 20 and a plurality of base modules 30. The IO module 20 includes an arithmetic circuit 22 that performs a predetermined arithmetic operation. At least one of the plurality of base modules 30 can be connected in parallel with each other, and can also be connected in series with other base modules 30 via a serial bus 51.

[0058] In this way, in the controller 1, multiple base modules 30, each connectable to at least one IO module 20, are connected by the serial bus 51, enabling high-speed data transfer. Furthermore, the multiple base modules 30 can each be individually connected in parallel to at least one IO module 20, making it easy to replace the IO modules 20. In other words, the IO modules 20 can be replaced without removing or attaching the modules (CPU module 10, base module 30) that are serially connected to the serial bus 51. Therefore, even if these modules are housed in a housing or the like, the IO modules 20 can be easily replaced. Therefore, the controller 1 allows for easy module replacement while achieving high transfer speeds.

[0059] As described above, for the sake of simplicity, FIGS. 9 to 12 illustrate an example in which a maximum of two IO modules 20 can be replaced per base module 30. However, any number of IO modules 20 can be connected to each base module 30. Also, although FIGS. 9 to 12 illustrate two base modules 30 connected to one CPU module 10 via a serial bus 51, any number of base modules 30 can be connected to the CPU module 10. Furthermore, in at least one of the multiple base modules 30, a location where an IO module 20 would normally be installed may be left empty as a reserve. With this configuration, when a specific function becomes necessary after the controller 1 is operational, it is possible to add an IO module 20 to realize that function without replacing the IO module 20.

[0060] The controller 1 may further include a CPU module 10 that controls the operation of the IO modules 20 connected to the base modules 30 and that can be connected to the base modules 30 via a serial bus 51. With this configuration, the CPU module 10 can control the operation of each IO module 20 to perform the operation desired by the user. Furthermore, because the CPU module 10 is connected to the base modules 30 via the serial bus 51, high-speed data transfer is possible.

[0061] Furthermore, each of the multiple base modules 30 may include a slave communication circuit 32 for communicating with the other base modules 30 and the CPU module 10. The CPU module 10 may include a master communication circuit 13 for communicating with the multiple base modules 30. The master communication circuit 13 may control communication with the slave communication circuits 32 included in the multiple base modules 30 connected via the serial bus 51. With this configuration, high-speed communication between modules is possible under the control of the master communication circuit 13 of the CPU module 10.

[0062] The module incorporating the master communication circuit 13 may be a communication module (for example, the base module 30a) other than the CPU module 10. With this configuration, communication between modules connected to the serial bus 51 can be led by a module other than the CPU module 10.

[0063] Furthermore, the multiple base modules 30 may have a structure that allows the multiple IO modules 20 to be inserted and removed without interfering with each other. Such a configuration makes it easier to replace the IO modules 20. In the examples of FIGS. 10 to 12, each base module 30 (30a, 30b) has a flat rectangular shape, and the CPU module 10 and the base module 30 are configured to be connected to each other laterally at their edges, but this configuration is not limited to this. For example, the base module 30 may have a box-like, U-shaped, or L-shaped shape. Furthermore, the CPU module 10 and the base module 30 may be connected to each other to form a box-like, U-shaped, or L-shaped shape as a whole. Therefore, the controller 1 can have an appropriate shape to suit the space in which it is used.

[0064] The IO module 20 and the base module 30 may be hot-swappable. This configuration allows the IO module 20 to be replaced while the controller 1 (or the CPU module 10) is running, making it even easier to replace the IO module 20. This configuration also allows other devices to connect to the controller 1 via communication and perform online maintenance while the IO module 20 is being replaced.

[0065] The controller 1 according to an embodiment of the present disclosure may be applied to any information processing device including, for example, a power distribution board, a real-time OS (Operating System) controller, or a programmable controller.

[0066] The controller 1 enables a reduction in the number of slave circuits compared to a conventional serial bus-type horizontal connection configuration, which is expected to reduce component costs and power consumption. In other words, by realizing communication between multiple IO modules 20 using a single slave communication circuit 32 as shown in Figure 9, the number of components and power consumption can be reduced compared to a configuration in which a corresponding slave communication circuit 32 is provided for each IO module 20.

[0067] The following additional notes are provided regarding example embodiments of the present disclosure. [1] a first module including an arithmetic circuit for performing a predetermined operation; At least one of the first modules can be connected in parallel to a plurality of second modules that can be connected in series to one another via a serial bus; An information processing device comprising: [2] The information processing device described in [1] further includes a third module that controls the operation of the first module connected to the plurality of second modules, and that can be connected in series via a serial bus to the second module connected to another one of the plurality of second modules. [3] each of the plurality of second modules includes a slave communication circuit for communicating with other second modules and the third module; the third module includes a master communication circuit for communicating with the plurality of second modules; the master communication circuit controls communication with the slave communication circuits provided in the second modules connected in series via a serial bus; [2] The information processing device according to [2]. [4] The information processing device according to any one of [1] to [3], wherein the plurality of second modules have a structure that allows the plurality of first modules to be inserted and removed without interfering with each other. [5] The information processing device according to any one of [1] to [4], wherein the first module and the second module are hot-pluggable. [6] The information processing device described in [3], wherein each of the plurality of second modules further includes an IO communication circuit for communication between the first module and the slave communication circuit when the first module is connected to the second module.

[0068] The present disclosure is not limited to the above-described embodiments, and modifications are possible within the scope of the present disclosure. [Explanation of symbols]

[0069] 1 Controller 10 CPU modules 11 External I / F 12 Arithmetic circuit 13 Master communication circuit 20 IO Modules 21 External I / F 22 Arithmetic circuit 23 Communication Circuit 30 bass modules 31 IO communication circuit 32 Slave communication circuit 51 Serial Bus 9 Controller (Comparative Example) 91 CPU module 911 External I / F 912 Arithmetic circuit 913 Master communication circuit 92 IO Module 921 External I / F 922 Arithmetic circuit 923 Slave communication circuit 93 Bass Module 94 parallel bus 95 Serial Bus

Claims

1. a first module including an arithmetic circuit for performing a predetermined operation; a plurality of second modules connectable in series to each other via a serial bus, which allows at least two of the first modules to be connected in parallel to each other; Equipped with each of the plurality of second modules includes a connector on a side surface thereof for connecting laterally with another of the second modules; each of the plurality of second modules includes at least two connectors on a front surface thereof for connecting at least two of the first modules from the front surface thereof; Information processing device.

2. 2. The information processing device according to claim 1, further comprising a third module that controls the operation of the first module connected to the plurality of second modules, the third module being serially connectable via a serial bus to the second module connected to another one of the plurality of second modules.

3. each of the plurality of second modules includes a slave communication circuit for communicating with other second modules and the third module; the third module includes a master communication circuit for communicating with the plurality of second modules; the master communication circuit controls communication with the slave communication circuits provided in the second modules connected in series via a serial bus; The information processing device according to claim 2 .

4. The information processing apparatus according to claim 1 , wherein the plurality of second modules have a structure that allows the plurality of first modules to be inserted and removed without interfering with each other.

5. The information processing apparatus according to claim 1 , wherein the first module and the second module are hot-pluggable.

6. 4. The information processing device according to claim 3, wherein each of the plurality of second modules further comprises an IO communication circuit for communicating between the first module and the slave communication circuit when the first module is connected to the second module.

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