Driver circuit that generates DSB-SC modulated signals

Abstract

To provide a driving circuit producing a DSB-SC modulation signal.SOLUTION: A driving circuit comprises a first capacitor. During a sampling operation, the first capacitor is coupled between first and second input terminals. During a transferring operation, an end of the first capacitor receives a voltage, and another end of the first capacitor is coupled to a load. The driving circuit produces a first driving signal to drive the load, the first driving signal comprises a plurality of first portions with a first polarity, and a plurality of second portions with a second polarity opposite to the first polarity. The plurality of first portions and the plurality of second portions form a generalized DSB-SC modulated component of the first driving signal, which is modulated according to an input signal between the first input terminal and the second input terminal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] 1. Field of the Invention

[0002] The present application relates to a driver circuit, and more particularly to a driver circuit capable of generating a DSB-SC modulated signal. [Background technology]

[0003] 2. Description of the Prior Art Double sideband with suppressed carrier (DSB-SC) is a type of amplitude modulation (AM) that is more efficient than traditional AM modulation schemes and is widely used in analog communication systems.

[0004] Outside of analog communications, DSB-SC modulated signals can be used as drive signals in a variety of applications, for example, they may be used to drive air-pulse generating (APG) devices, which may be used as sound generating devices in audio applications.

[0005] However, frequently used amplifiers in audio applications that generate analog output signals, such as class AB, class H, or class D amplifiers, do not generate DSB-SC modulated signals.

[0006] Therefore, there is a need in the field to convert signals from any kind of amplifier with analog output into DSB-SC modulation format. Summary of the Invention [Problem to be solved by the invention]

[0007] SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a driver circuit capable of generating a DSB-SC modulated signal. [Means for solving the problem]

[0008] One embodiment of the present invention provides a drive circuit including a first capacitor. During a sampling operation, the first capacitor is coupled between a first input terminal and a second input terminal of the drive circuit. During a transfer operation, one end of the first capacitor receives a voltage, and the other end of the first capacitor is coupled to a load. The drive circuit generates a first drive signal for driving the load, the first drive signal including a plurality of first portions having a first polarity and a plurality of second portions having a second polarity, the second polarity being opposite to the first polarity, and the first and second polarities being related to the voltage. The plurality of first portions and the plurality of second portions form a generalized double sideband with suppressed carrier (DSB-SC) modulation component of the first drive signal that is modulated in response to an input signal between the first and second input terminals.

[0009] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of a waveform of a generalized DSB-SC signal according to an embodiment of the present invention.

[0011] [Figure 2] FIG. 2 is a diagram showing an enlarged waveform of a signal shown in FIG.

[0012] [Figure 3] 1 shows a schematic diagram of a driver circuit 10 according to an embodiment of the present invention.

[0013] [Figure 4] 3 shows a schematic diagram of control signals according to an embodiment of the present invention;

[0014] [Figure 5] 2 shows an enlarged waveform of the signal shown in FIG. 1.

[0015] [Figure 6] 3 shows a schematic diagram of control signals according to an embodiment of the present invention;

[0016] [Figure 7] 1 shows a schematic diagram of an amplifier.

[0017] [Figure 8] 1 shows a schematic diagram of a drive circuit according to an embodiment of the present invention;

[0018] [Figure 9] 1 shows a schematic diagram of a drive signal with polarity transitions according to an embodiment of the present invention;

[0019] [Figure 10] 1 shows a schematic diagram of a drive circuit according to an embodiment of the present invention;

[0020] [Figure 11] 1 shows a schematic diagram of drive and control signals according to an embodiment of the present invention;

[0021] [Figure 12] 1 shows a schematic diagram of a drive circuit according to an embodiment of the present invention;

[0022] [Figure 13] 1 shows a schematic diagram of a load according to an embodiment of the present invention.

[0023] [Figure 14] 1 shows a schematic diagram of a drive circuit according to an embodiment of the present invention;

[0024] [Figure 15] 1 shows a schematic diagram of a demodulation signal generator according to an embodiment of the present invention;

[0025] [Figure 16] 3 shows a schematic diagram of demodulation signals and control signals according to an embodiment of the present invention;

[0026] [Figure 17] 1 shows a schematic diagram of a drive circuit according to an embodiment of the present invention;

[0027] [Figure 18] 2 shows a schematic diagram of modulated and demodulated signals according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0028] In the present invention, the term "coupled" can refer to a direct or indirect connection. "Component A is coupled to component B" can indicate that component A is directly connected to component B, or that component A is connected to component B via some component C.

[0029] Not all features in one diagram / embodiment are essential, and some of them may be omitted. The technical features described in the following embodiments may be mixed or combined in various ways unless there is a contradiction.

[0030] 1 shows a waveform of a drive signal SM (corresponding to a solid line) modulated according to an input signal VoP-VoN (dotted line) or its sign-inverted form VoN-VoP (dashed line) relative to a voltage Vcom (corresponding to a thick solid line) according to an embodiment of the present application. In FIG. 1, the drive signal SM is DSB-SC modulated according to a 6 kHz sine wave signal (VoP-VoN or VoN-VoP) with a carrier frequency of 192 kHz. In this application, VoP-VoN or VoN-VoP is used to indicate the input signal for the drive circuit to generate the drive signal.

[0031] As shown in Fig. 1, the drive signal SM includes a DSB-SC (Double Sideband with Suppressed Carrier) modulation component. A typical DSB-SC modulation, which is a type of amplitude modulation, adds a carrier frequency f csinusoidal signal cos(2πf c t) and modulate it by m(t)cos(2πf c A typical DSB-SC modulated signal, which may be represented by m(t), would have a waveform similar to the solid line shown in Figure 1, and the dotted / dashed line in the context of a typical DSB-SC may be considered a baseband signal m(t). In this application, "modulation" generally refers to the process of modulating a baseband signal with a carrier frequency f c This refers to the act of forwarding data upward to the bandwidth around

[0032] A typical DSB-SC modulated signal oscillates sinusoidally. However, in this application, a DSB-SC modulated signal may have an oscillation pattern other than a sinusoidal one. In general, a) the polarity of the signal components is such that the carrier frequency f c One cycle T corresponds to CY b) two changes / transitions within one cycle T CY A signal component is considered to be DSB-SC modulated or generalized DSB-SC modulated when the (peak) amplitude of the signal component in reaches, approaches, achieves, or is proportional to / related to the amplitude of the modulated signal (e.g., baseband signal m(t) or the input signal of a modulating signal generator or driver circuit such as VoP-VoN or VoN-VoP).

[0033] To illustrate the amplitude (modulated) relationship between the modulated signal (e.g., SM) and the unmodulated signal (e.g., VoP-VoN or VoN-VoP), the waveforms of the drive signal SM and voltage Vcom in Figure 1 may be shifted / biased by a certain amount, and the shifted / biased amount may be the voltage Vcom in Figure 1. Thus, in Figure 1, the solid line actually represents the waveform of SM-Vcom, and the thick solid line actually represents the waveform of Vcom-Vcom.

[0034] Specifically, Figure 2 shows an enlarged version or expanded waveform of the signal / voltage within the dashed rectangle shown in Figure 1 to illustrate the oscillation pattern of the DSB-SC modulated signal component generated by one embodiment of the present invention. As can be seen from Figure 2, the DSB-SC modulated signal component (or SM) approaches the amplitude of the modulated signal VoP-VoN or VoN-VoP in an exponential or exponentially similar manner, unlike a sinusoid.

[0035] From another perspective, the DSB-SC modulated signal component (or SM) includes a signal portion above the voltage Vcom (corresponding to SM-Vcom>0) and a signal portion below the voltage Vcom (corresponding to SM-Vcom<0). The signal portion above the voltage Vcom is referred to as a first portion, and the signal portion below the voltage Vcom is referred to as a second portion. The first portion may have a first polarity or be biased toward a first polarity, and the second portion may have a second polarity or be biased toward a second polarity. The first polarity and the second polarity are opposite to each other. The first and second polarities are considered relative to the voltage Vcom.

[0036] In other words, the drive signal SM may be considered to include a plurality of first portions and a plurality of second portions, and the plurality of first portions and the plurality of second portions form the generalized DSB-SC modulated components of the drive signal SM, which are divided into one cycle T CY (where T CY is the carrier frequency f c means that within the polarity (which may be the reciprocal of the polarity), the drive signal SM includes one first portion trending towards a first polarity and one second portion trending towards a second polarity opposite to the first polarity.

[0037] A first duty period T corresponding to the first portion having a first polarity D1 During the second duty period T, the drive circuit generates a drive signal SM that tends to approach one of VoP-VoN and VoN-VoP, for example, VoP-VoN as shown in FIG. D2During this period, the drive circuit generates a drive signal SM that attempts to approach the other of VoP-VoN and VoN-VoP, for example VoN-VoP as shown in FIG.

[0038] 3 shows a schematic diagram of a driver circuit 10 according to one embodiment of the present invention. The driver circuit 10 includes a first input terminal VoP, a second input terminal VoN, a capacitor Caux, and a sampling switch S. amp,1 ~S amp,2 and transfer switch S tf,1 ~S tf,4 The drive circuit 10 includes a load C L The drive signal SM is configured to generate a drive signal SM for driving the

[0039] The connections between the circuit components are shown in FIG. 3 and will not be described here for the sake of brevity.

[0040] In this application, VoP / VoN are used to denote the first / second input terminals of the driver circuit 10 and to denote the voltage levels at the first / second input terminals. The input signal for the driver circuit of the present invention is carried by the two input terminals, i.e., is the voltage difference between the two input terminals, and can be expressed as either VoP-VoN or VoN-VoP. The input signal for the driver circuit may also be considered as a signal to be modulated. The notation of a switch also refers to its control signal. For example, S amp,1 ~S amp,2 and S tf,1 ~S tf,4 are used to denote switches and also to denote the on-off control signals for them.

[0041] FIG. 4 illustrates an on-off control signal S for the drive circuit 10 according to one embodiment of the present invention. amp,1 ~S amp,2 and S tf,1 ~S tf,4 A high level of the control signal indicates on / conduction, and a low level of the control signal indicates off / cutoff. As can be seen from Figure 4, the sampling operation (sampling switch S amp,1 ~Samp,2 is conducting) and transfer operation (transfer switch S tf,1 ~S tf,2 or transfer switch S tf,3 ~S tf,2 The sampling operation refers to a capacitor (e.g., Caux) sampling an input signal (e.g., VoP-VoN) at a specific time, while the transfer operation refers to a capacitor (e.g., Caux) transferring the sampled input signal corresponding to the specific time to a load C L Figure 4 also shows the control signal S when VoP-VoN>0. amp,1 ~S amp,2 , S tf,1 ~S tf,4 The waveforms of the input and output signals of the driving circuit 10 corresponding to the waveforms are also shown.

[0042] Specifically, T D1 The first sampling operation (time T shown in FIG. 4) SP1 ) during which a first portion with a first polarity is generated, sampling switch S amp,1 ~S amp,2 is conductive (thereby coupling a first end of capacitor Caux to the first input terminal VoP and a second end of capacitor Caux to the second input terminal VoN), and capacitor Caux has a voltage difference between its two ends as VoP-VoN. During the first transfer operation, transfer switch S tf,1 ~S tf,2 is turned on (thereby connecting the first end of the capacitor Caux to the load C L , and the second end of the capacitor Caux receives the voltage Vcom), the capacitor Caux transfers the voltage difference as VoP-VoN together with the voltage Vcom to the load. TF1 The first sampling operation and the first transfer operation will have a voltage of Vcom+VoP-VoN at (the end of) T D1 may be repeated several times, alternating between T D1The amplitude of the first portion of the drive signal SM having the first polarity in T D1 The amplitude of the input signal VoP-VoN corresponding to the amplitude of the input signal VoP-VoN is close to that of the input signal VoP-VoN corresponding to the amplitude of the input signal VoP-VoN, and satisfies the requirement b) of the DSB-SC modulated signal components mentioned above.

[0043] Similarly, T D2 The second sampling operation (time T shown in FIG. 4) SP2 ), during which a second portion with a second polarity is generated, sampling switch S amp,1 ~S amp,2 is turned on, so that, as a first sampling operation, the first end of the capacitor Caux is connected to the first input terminal VoP, the second end of the capacitor Caux is connected to the second input terminal VoN, and the capacitor Caux has a voltage difference of VoP-VoN between its two ends. tf,3 ~S tf,4 is turned on (so that a first end of the capacitor Caux receives the voltage Vcom and a second end of the capacitor Caux is connected to the load C L ), the capacitor Caux transfers the voltage difference as VoP-VoN together with the voltage Vcom to the load. Thus, the drive signal SM is substantially TF2 The second sampling operation and the second transfer operation are performed at the end of T D2 may be repeated several times, alternating between T D2 The amplitude of the second portion of the drive signal SM having the second polarity in T D2 The amplitude of the input signal corresponding to (VoN-VoP) approaches that of the input signal corresponding to (VoN-VoP) and satisfies requirement b) of the generalized DSB-SC modulated signal components described above.

[0044] Also, T D1 Inner movement and T D2 The actions in the figure are also repeated over a long period of time. D1 Operation and T D2 The operation of the carrier frequency f c, the drive signal SM generated by the drive circuit 10 satisfies requirement a) of a generalized DSB-SC modulated signal.

[0045] Note that Figures 2 and 4 show the case where VoP-VoN>0. When VoP-VoN<0 or VoN-VoP>0, the corresponding waveforms are shown in Figures 5 and 6. The operation (principle) is the same as in the above paragraph and will not be described for brevity.

[0046] In one respect, the capacitor Caux in the driver circuit can be considered a flying capacitor because neither end of the capacitor Caux is grounded. The driver circuit 10 utilizes the flying capacitor Caux to store and transfer energy to generate the generalized DSB-SC modulated signal.

[0047] Therefore, the drive signal SM generated by the drive circuit can be considered to include a generalized DSB-SC modulated component, or the first and second portions can be considered to form a generalized DSB-SC modulated component. Also, the AC (alternating current) component of the drive signal SM generated by the drive circuit can be considered to be generalized DSB-SC modulated.

[0048] The drive signal of the present invention may receive a balanced or unbalanced signal. The drive signal of the present invention may be coupled to an (external) amplifier with either a single-ended or differential output. The amplifier may be, but is not limited to, a Class AB, Class H, or Class D amplifier.

[0049] That is, by utilizing a capacitor(s) and a switch, the driver circuit of the present invention can convert any type of analog signal from any type of amplifier into a DSB-SC modulated signal. In other words, the driver circuit of the present invention has the flexibility to be integrated with any type of (external / analog) amplifier and / or to receive any type of analog input signal and generate a DSB-SC modulated signal. In one respect, the driver circuit 10 can be considered as a modulated signal generator capable of generating a DSB-SC modulated signal.

[0050] In one embodiment, one input terminal of the driver circuit may be coupled to an output terminal of an (external / analog) amplifier, and another input terminal of the driver circuit may be coupled to another output terminal of the amplifier (shown on the left in FIG. 7), may be coupled to ground (shown on the right in FIG. 7), or may receive a constant voltage.

[0051] In one embodiment, the load C L may be a capacitive load. In some embodiments, an energy recycling operation may be utilized in the transition between the first polarity and the second polarity.

[0052] 8 shows a schematic diagram of a driver circuit 20 according to an embodiment of the present invention. In addition to the driver circuit 10, the driver circuit 20 includes a capacitive element C SM,ER , inductor L SM,ER and switch S SM,ER The capacitor element C SM,ER may be a capacitor or other component that is capacitive or has capacitance. SM,ER and switch S SM,ER is the capacitive load C L and the capacitive element C SM,ER The switch S is connected between SM,ER is the inductor L as shown in Figure 8. SM,ER The switch S is not limited to being coupled to the left end of the SM,ER is the inductor L SM,ER may be attached to the right end of

[0053] The concept of energy recycling is introduced in U.S. Patent Nos. 11,290,015, 11,057,692, and U.S. Patent Application No. 18 / 396,678. SM,ER As shown in Figure 9, T D1 (corresponding to the first part) and T D2 (corresponding to the second part) between the energy recycling period T ER Conduction continues for a while.

[0054] capacitive load C L If the voltage at (for example, SM) is SM,ER (e.g., Vcom, where in one embodiment, the voltage at the capacitive element C SM,ER 9, which is greater than the conduction period T ER,12 At the beginning of L,SM is the capacitive load C L from the capacitive element C SM,ER The capacitive load C L The voltage at L The electrical energy stored in the capacitive element C SM,ER will be forwarded to.

[0055] On the other hand, capacitive load C L If the voltage at (for example, SM) is SM,ER 9, which is lower than the voltage (e.g., Vcom) at ER,21 At the beginning of L,SM is the capacitive element C SM,ER to the capacitive load C L The capacitive load C L The voltage at the capacitive element C SM,ER The electrical energy stored in the capacitive load C L will be forwarded to.

[0056] Over multiple energy recycling periods, the electrical energy is transferred to the capacitive load C L and the capacitive element CSM,ER This means that electrical energy is transferred back and forth between T ER,12 Between them is a capacitive element C SM,ER recycled into T ER,21 A capacitive load C L Note that the overall power consumption of the driver circuit is significantly reduced and the power efficiency of the driver circuit is improved.

[0057] As can be seen from Figure 9 (also with reference to Figures 2 and 5), the capacitive element C SM,ER The polarity of the drive signal changes via the transfer of electrical energy from / to inductor L. SM,ER and the capacitive element C SM,ER performs the polarity transition between the first polarity and the second polarity, and the switch S SM,ER is the polarity transition (or polarity transition period, e.g., T ER , where T ER may be considered to be conductive during the polarity transition period.

[0058] 10 shows a schematic diagram of a drive circuit 30 according to one embodiment of the present invention. In addition to drive circuits 10 and 20, which have a single flying capacitor Caux, drive circuit 30 has two / dual (flying) capacitors Caux1, Caux2 and their corresponding switches S amp,11 ~S amp,12 , S amp,21 ~S amp,22 , S tf,11 ~S tf,14 and S tf,21 ~S tf,24 The connection and timing of the switches and the control signal S amp,11 ~S amp,12 , S amp,21 ~S amp,22 , S tf,11 ~S tf,14 and S tf,21 ~S tf,24 10 and 11 can be seen. The sampling and transfer operations of the capacitors Caux1 and Caux2 are similar to the sampling and transfer operations of the capacitor Caux.

[0059] 10 and 11, the sampling and transfer operations of capacitors Caux1 and Caux2 occur synchronously. For example, capacitor Caux1 performs a transfer operation when capacitor Caux2 performs a sampling operation, and / or capacitor Caux1 performs a sampling operation when capacitor Caux2 performs a transfer operation.

[0060] Specifically, in one embodiment, the operating period T ST1 During this time, switch S amp,21 ~S amp,22 , S tf,11 ~S tf,12 is turned on and the remaining switches are turned off; during the operation period T ST2 During this time, switch S amp,11 ~S amp,12 , S tf,21 ~S tf,22 is conducting and the remaining switches are blocking.

[0061] As shown in FIG. 11, by using dual capacitors, the drive signal SM generated by the drive circuit 30 has a duty period T D1 or T D2 within the signal line, which is smoother than that produced by the driver circuit 10 / 20.

[0062] In one embodiment, cycle T CY may correspond to a rate of 192KHz (e.g., T CY = 1 / 192KHz, or carrier frequency f c may be 192KHz), the operating period T ST (For example, T ST1 or T ST2 ) may correspond to a rate of 16×192=3072KHz (e.g., TST=1 / 3.072MHz), and the duty period (e.g., T D1 or T D2 ) may occupy 6 operating periods (e.g., T D1 =6 T ST or TD2 =6 T ST ), energy recycling period T ER may be two or less operating periods (e.g., T ER ≦2·T ST ), but is not limited to this.

[0063] Note that the present invention is not limited to having an energy recycling circuit. For example, a drive circuit 40 having a dual flying capacitor without an energy recycling circuit as shown in FIG. 12 is also an embodiment of the present invention.

[0064] In one embodiment, the load C L may be, but is not limited to, an air pulse generator (APG) device as taught in U.S. Patent Nos. 11,445,279, 11,943,585 or U.S. Patent Application No. 18 / 321,757.

[0065] FIG. 13 illustrates a load C L A schematic diagram of the load C is shown. L is an APG device as taught in U.S. Pat. No. 11,943,585 or U.S. patent application Ser. No. 18 / 321,757. Load C L The optical transducer includes a membrane structure 11. As taught in U.S. Pat. No. 11,943,585, the membrane structure 11 can be driven by a modulated drive signal (e.g., drive signal SM) to perform common mode motion. The membrane structure 11 can also be driven by a demodulated drive signal +SV and a demodulated drive signal −SV to perform differential mode motion. In this application, the terms “modulated (demodulated) drive signal” and “modulated (demodulated) signal” are used interchangeably.

[0066] Further, the membrane structure 11 comprises a flap pair 102, which includes flaps 101 and 103. In the embodiment shown in Figure 13, the flap pair 102 can be driven by a modulation drive signal SM to perform common mode motion and driven by demodulation drive signals ±SV to perform differential mode motion to achieve co-location of modulation and demodulation or in-situ modulation and demodulation, which means that both modulation and demodulation are performed by the same part / position of the membrane structure.

[0067] Specifically, load C L may include an actuator 101A disposed on the flap 101 and an actuator 103A disposed on the flap 103. Each of the actuators 101A and 103A includes an upper electrode and a lower electrode.

[0068] In the embodiment shown in FIG. 13, the bottom electrode is optionally connected to a bias voltage V BIAS The upper electrodes of the actuators 101A and 103A may receive modulated drive signals SM shifted by 1 V, and the upper electrodes of the actuators 101A and 103A may receive demodulated drive signals +SV and −SV to perform differential mode motion, but are not limited to this. As long as the flap pair receives modulated drive signals SM to perform common mode motion for modulation operation and receives demodulated drive signals ±SV to perform differential mode motion for demodulation operation, it is within the scope of the present invention.

[0069] In one embodiment, V BIAS The bias voltage V can be, but is not limited to, +Vcom or -Vcom. BIAS As long as is constant, it is within the scope of the present invention.

[0070] It should be noted that the driver circuit of the present invention is not limited to being applied to an APG with in-situ modulation and demodulation, but may also be applied to the APG devices of U.S. Patent Nos. 11,445,279 or 11,943,585 that do not have in-situ modulation and demodulation.

[0071] 14 shows a schematic diagram of a drive circuit 50 according to one embodiment of the present invention. The drive circuit 50 comprises a modulation signal generator 52 configured to generate a modulated drive signal SM, and a demodulation signal generator 54 configured to generate demodulated (drive) signals ±SV.

[0072] The modulation signal generator 52 may be realized by the driver circuit 10, 20, 30, or 40 disclosed in the present invention (S amp,1 ~S amp,2 , S amp,11 ~S amp,12 , S amp,21 ~S amp,22 , S tf,1 ~S tf,4 , S tf,11 ~S tf,14 , S tf,21 ~S tf,24 (Switches such as and the control signals therein may be considered modulating switches and modulating control signals.) Demodulation signal generator 54 may be implemented by the demodulation signal generator described in U.S. patent application Ser. No. 18 / 396,678.

[0073] For example, Figure 15 shows a schematic diagram of a demodulation signal generator 60 according to one embodiment of the present invention. The demodulation signal generator 60 includes a switch SW 1H , S.W. 1L , S.W. 2H , S.W. 2L , S.W. SV,ER and inductor L SV,ER SW 1H , S.W. 1L is coupled to node N101, and SW 2H , S.W. 2L is coupled to node N103. Switch SW 1H , S.W. 2H is (high) voltage V H Switch SW 1L , S.W. 2L is the (low) voltage V L Switch SW SV,ER and inductor L SV,ERis coupled between nodes N101 and N103, and nodes N101 / N103 are coupled to the (top) electrodes of flaps 101 / 103. Demodulation signal generator 60 produces a demodulation signal +SV at node N101 and a demodulation drive signal −SV at node N103, where the demodulation drive signals ±SV have opposite polarities. The demodulation drive signals ±SV and the control signal SW 1H , S.W. 1L , S.W. 2H , S.W. 2L , S.W. SV,ER The waveform of is shown in Figure 16 (where SW 1H , S.W. 1L , S.W. 2H , S.W. 2L , S.W. SV,ER may be considered as a demodulation switch and a demodulation control signal).

[0074] For details of the demodulation signal generator, reference may be made to, for example, U.S. Patent Application No. 18 / 396,678. For details of the APG device (its modulation and demodulation principles), reference may be made to U.S. Patent Nos. 11,445,279, 11,943,585, or U.S. Patent Application No. 18 / 321,757. The contents of U.S. Patent Nos. 11,445,279, 11,943,585, U.S. Patent Application No. 18 / 396,678, and Application No. 18 / 321,757 are incorporated herein by reference.

[0075] Due to the differential motion of the demodulation operation, the demodulation frequency of the demodulation drive signals ±SV can be half the modulation frequency of the modulation drive signal SM. The modulation frequency can be the carrier frequency of the DSB-SC modulation component, or 1 / T CY In one embodiment, the modulation frequency (e.g., 1 / T CY ) may be 192 KHz, and the demodulation frequency (for example, 1 / (T1+T12+T2+T21)) may be 96 KHz, but is not limited thereto.

[0076] Additionally, in some embodiments, a modulated control signal (e.g., S amp,1 ~S amp,2 , S amp,11 ~S amp,12, S amp,21 ~S amp,22 , S tf,1 ~S tf,4 , S tf,11 ~S tf,14 , S tf,21 ~S tf,24 ) and demodulation control signals (e.g., SW 1H , S.W. 1L , S.W. 2H , S.W. 2L , S.W. SV,ER ) may be synchronized. To achieve synchronous modulation and demodulation control signals, in some embodiments, the modulation frequency may be an integer multiple of the demodulation frequency. To achieve synchronous modulation and demodulation control signals, in some embodiments, the (modulation) clock signal for generating the modulation control signal and the (demodulation) clock signal for generating the modulation control signal may be synchronized. The modulation clock signal and the demodulation clock signal may correspond to the same clock frequency, or the modulation clock frequency f of the modulation clock signal may be synchronized. CLK,mod and the (demodulation) clock frequency f of the demodulation clock signal CLK,demod may have a rational relation (i.e., M f CLK,mod =N f CLK,demod (There are suitable integers M, N such that M = 1 / N.) Synchronous modulation and demodulation control signals have the advantage of mitigating noise / interference introduced by the switches and / or preventing undesired noise / interference from entering the baseband (e.g., audio band), which will improve the user experience.

[0077] Furthermore, in the embodiment shown in FIG. 18 (load C L In the APG device of FIG. 13 (an abstract symbol of which is shown in the upper right portion of FIG. 18), the energy recycling period or transition (T SM,ER ) is the energy recycle period or transition (T SV,ER This allows for more efficient energy recycling of the modulation signal generator. SM,ER and inductor L SM,ERIt is proposed that the polarity transition performed by occurs when the demodulation signal SV is maintained as a constant voltage, i.e., during the period T SM,ER and T SV,ER are proposed to be non-overlapping, or equivalently interleaved, as shown in Figure 18, where T SM,ER / T SV,ER may represent the transition of the modulation / demodulation signal SM / SV.

[0078] In particular, the above-described embodiments are used to illustrate the concept of the present invention. Those skilled in the art can make appropriate modifications and changes, and are not limited thereto. For example, FIG. 17 shows a schematic diagram of a driving circuit 70 according to an embodiment of the present invention. The driving circuit 70 includes a sampling switch S amp,1 '~S amp,2 ' and transfer switch S tf,1 '~S tf,2 The operating principle (and purpose) of the driver circuit 70 is similar to that of the driver circuit 10. As with the driver circuit 10, sampling and transfer operations are alternated during the duty period.

[0079] Unlike the driving circuit 10, during the first sampling operation corresponding to the first polarity, the sampling switch S amp,1 ' closes the connection between the first end of the capacitor Caux and the input terminal VoP, and the sampling switch S amp,2 ' makes the connection between the second end of the capacitor Caux and the input terminal VoN conductive; during the second sampling operation corresponding to the second polarity, the sampling switch S amp,1 ' closes the connection between the first end of the capacitor Caux and the input terminal VoN, and the sampling switch S amp,2 ' conducts the connection between the second end of the capacitor Caux and the input terminal VoP.

[0080] In summary, the driver circuit of the present invention utilizes flying capacitors to convert any analog signal into a generalized DSB-SC modulated signal via a sample-and-forward operation. The driver circuit of the present invention has the flexibility / capability to be integrated with any type of external analog amplifier (such as a Class AB, Class H, or Class D amplifier) ​​and / or to receive any form of analog signal (such as single-ended, differential, balanced, or unbalanced) to generate the generalized DSB-SC modulated signal.

[0081] Those skilled in the art will readily recognize that numerous modifications and variations of the apparatus and method may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A drive circuit having a first capacitor, During a sampling operation, the first capacitor is coupled between a first input terminal and a second input terminal of the drive circuit; During a transfer operation, one end of the first capacitor receives a voltage and the other end of the first capacitor is coupled to a load; the drive circuit generates a first drive signal for driving the load, the first drive signal including a plurality of first portions having a first polarity and a plurality of second portions having a second polarity, the second polarity being opposite to the first polarity, and the first polarity and the second polarity being polarities defined with reference to the voltage; the plurality of first portions and the plurality of second portions form a generalized DSB-SC (Double Sideband with Suppressed Carrier) modulated component of the first drive signal modulated in response to an input signal between the first input terminal and the second input terminal; Drive circuit.

2. a first sampling switch coupled to a first end of the first capacitor; a second sampling switch coupled to a second end of the first capacitor; The drive circuit of claim 1 .

3. the first sampling switch is coupled between the first end of the first capacitor and the first input terminal; the second sampling switch is coupled between the second end of the first capacitor and the second input terminal; 3. The drive circuit according to claim 2.

4. 3. The drive circuit of claim 2, wherein the first and second sampling switches are conductive during the sampling operation.

5. 3. The drive circuit of claim 2, wherein during the sampling operation, the first sampling switch provides conduction between the first end of the first capacitor and the first input terminal, and the second sampling switch provides conduction between the second end of the first capacitor and the second input terminal.

6. During a first sampling operation corresponding to the first polarity, the first sampling switch provides conduction between the first end of the first capacitor and the first input terminal, and the second sampling switch provides conduction between the second end of the first capacitor and the second input terminal; During a second sampling operation corresponding to the second polarity, the first sampling switch provides conduction between the first end of the first capacitor and the second input terminal, and the second sampling switch provides conduction between the second end of the first capacitor and the first input terminal.

3. The drive circuit according to claim 2.

7. During a first transfer operation corresponding to a first portion of the plurality of first portions having the first polarity, a first end of the first capacitor receives the voltage and a second end of the first capacitor is coupled to the load; During a second transfer operation corresponding to a second portion of the plurality of second portions having the second polarity, the second end of the first capacitor receives the voltage and the first end of the first capacitor is coupled to the load. The drive circuit of claim 1 .

8. a first transfer switch connected to the first capacitor and receiving the voltage; a second transfer switch coupled between the first capacitor and the load; The drive circuit of claim 1 .

9. the first and second transfer switches are conductive during the transfer operation; 9. The drive circuit of claim 8.

10. a third transfer switch coupled to the first capacitor and receiving the voltage; a fourth transfer switch coupled between the first capacitor and the load.

9. The drive circuit of claim 8.

11. a first end of the first transfer switch coupled to a first end of the first capacitor, and a second end of the first transfer switch receiving the voltage; a first end of the third transfer switch coupled to a second end of the first capacitor, the second end of the third transfer switch receiving the voltage; The drive circuit of claim 10.

12. the first and second transfer switches are conductive during a first transfer operation corresponding to a first portion of the plurality of first portions having the first polarity; The third and fourth transfer switches are conductive during a second transfer operation corresponding to a second portion of the plurality of second portions having the second polarity. The drive circuit of claim 10.

13. 10. The drive circuit of claim 1, further comprising a second capacitor: the first capacitor performs a first sampling operation and a first transferring operation; the second capacitor performs a second sampling operation and a second transferring operation; During the second sampling operation, the second capacitor is coupled between the first input terminal and the second input terminal of the drive circuit; During the second transfer operation, one end of the second capacitor receives the voltage and the other end of the second capacitor is coupled to the load. The drive circuit of claim 1 .

14. 14. The drive circuit of claim 13, wherein when the second capacitor performs the second sampling operation, the first capacitor performs the first transfer operation, and when the second capacitor performs the second transfer operation, the first capacitor performs the first sampling operation.

15. a first transfer switch coupled to the first capacitor and receiving the voltage; a second transfer switch coupled between the first capacitor and the load; a first sampling switch coupled between the second capacitor and the first input terminal; a second sampling switch coupled between the second capacitor and the second input terminal; When the first and second sampling switches are conducting, the first and second transfer switches are conducting.

14. The drive circuit of claim 13.

16. a third sampling switch coupled between the first capacitor and the first input terminal; a fourth sampling switch coupled between the first capacitor and the second input terminal; a third transfer switch coupled to the second capacitor and receiving the voltage; a fourth transfer switch coupled between the second capacitor and the load; During a first operating period, the first and second transfer switches and the first and second sampling switches are conductive, and the third and fourth sampling switches and the third and fourth transfer switches are blocked.

16. The drive circuit of claim 15.

17. During a second operating period, the first and second transfer switches and the first and second sampling switches are blocked, and the third and fourth sampling switches and the third and fourth transfer switches are conductive.

17. The drive circuit of claim 16.

18. a capacitive element; an inductor coupled between the load and the capacitive element; 10. The drive circuit of claim 1 further comprising: the inductor and the capacitive element undergo polarity transitions between the first polarity and the second polarity; The drive circuit of claim 1 .

19. a switch coupled to the inductor; the switch is conductive during the polarity transition; 19. The drive circuit of claim 18.

20. 2. The drive circuit of claim 1, wherein the load is a capacitive load.

21. 2. The drive circuit of claim 1, wherein the first input terminal of the drive circuit is coupled to a first output terminal of an amplifier.

22. 22. The drive circuit of claim 21, wherein the second input terminal of the drive circuit is coupled to a second output terminal of the amplifier.

23. 10. The driver circuit of claim 1, further comprising a demodulation signal generator, the demodulation signal generator comprising: a first switch, a second switch, a third switch, and a fourth switch, the first and second switches coupled to a first node, the third and fourth switches coupled to a second node, the first and third switches receiving a first voltage, and the second and fourth switches receiving a second voltage; a fifth switch and an inductor coupled between the first node and the second node; It has the demodulation signal generator generates a first demodulation signal at the first node and a second demodulation signal at the second node, the first demodulation signal and the second demodulation signal having opposite polarities; Drive circuit.

24. 24. The drive circuit of claim 23, wherein the frequency of the first demodulated signal is half the frequency of the first drive signal.

25. 24. The drive circuit of claim 23, wherein transitions of the first demodulated signal and transitions of the drive signal are interleaved with one another.

26. the drive circuit having a plurality of modulation switches coupled to the first capacitor, the plurality of modulation switches being controlled by a plurality of modulation control signals; the drive circuit includes a demodulation signal generator, the demodulation signal generator includes a plurality of demodulation switches, the plurality of demodulation switches being controlled by a plurality of demodulation control signals; the plurality of modulation control signals and the plurality of demodulation control signals are synchronized. The drive circuit of claim 1 .

27. The load includes a membrane structure. the drive circuit generates the first drive signal to drive the membrane structure to perform a common mode motion; the drive circuit generates a first demodulated drive signal and a second demodulated drive signal to drive the membrane structure to perform a differential mode motion; The drive circuit of claim 1 .

28. the membrane structure includes a flap pair including a first flap and a second flap; the drive circuit generates the first drive signal to drive the pair of flaps to perform the common mode motion; the drive circuit generates the first demodulated drive signal and the second demodulated drive signal to drive the pair of flaps to perform the differential mode movement.

28. The drive circuit of claim 27.

29. the load has a first actuator disposed on the first flap; the first actuator having a first electrode and a second electrode; the first electrode receives the drive signal and the second electrode receives the first demodulated drive signal; 29. The drive circuit of claim 28.

30. the load has a second actuator disposed on the second flap; the second actuator has a third electrode and a fourth electrode; the third electrode receives the drive signal and the fourth electrode receives the second demodulated drive signal; 30. The drive circuit of claim 29.

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