Power supply device

Abstract

To provide a power supply device that can increase the degree of freedom of the number of connected inverters, and can achieve various forms of output configuration.SOLUTION: The power supply device includes a control circuit electrically connected via a first signal line, and a plurality of inverters. The control circuit outputs a reference signal changing in a certain cycle to the first signal line. Each of the plurality of inverters outputs an AC voltage synchronized with rise or fall of a reference signal at a phase having been set or instructed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a power supply device. [Background technology]

[0002] Patent Document 1 describes an inverter generator in which a plurality of inverters are connected in series and parallel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-244698 Summary of the Invention [Problem to be solved by the invention]

[0004] In the inverter generator described in Patent Document 1, one inverter acts as a master machine and the remaining inverters act as slave machines and are synchronized. Therefore, in the inverter generator described in Patent Document 1, wiring is required between the multiple inverters.

[0005] As the number of inverters increases, so does the amount of wiring, and the number of signal line connectors mounted on each of the inverters. Therefore, if signal line connectors corresponding to the expected number of inverters (e.g., three) are mounted on each of the inverters, it is not possible to increase the number of inverters (e.g., six) later. In other words, the inverter generator described in Patent Document 1 has limited flexibility in the number of inverters that can be connected.

[0006] To prevent this, it is necessary to determine the maximum number of inverters that can be expected in advance, and to mount signal line connectors in the number corresponding to the maximum number of inverters on each of the inverters.

[0007] An object of the present invention is to provide a power supply device that can increase the degree of freedom in the number of inverters that can be connected and can realize a variety of output configurations. [Means for solving the problem]

[0008] A power supply device according to one aspect of the present invention comprises: a control circuit and a plurality of inverters electrically connected via a first signal line; Including, The control circuit a reference signal that changes at a constant period is output to the first signal line; Each of the plurality of inverters outputting an AC voltage synchronized with a set or specified phase relative to the rising or falling edge of the reference signal; It is characterized by:

[0009] In the power supply device, The control circuit included in any one of the plurality of inverters, It is characterized by:

[0010] In the power supply device, the control circuit and the plurality of inverters are electrically connected via a second signal line; The control circuit outputting a voltage output start instruction signal, which is a signal instructing the start of output of an AC voltage, to the second signal line in synchronization with the first reference signal; Each of the plurality of inverters start outputting an AC voltage synchronized with a set or specified phase relative to the rising or falling edge of the second reference signal after the first reference signal; It is characterized by:

[0011] In the power supply device, Each of the plurality of inverters outputting, within a certain period of time starting from the time of receiving the voltage output start instruction signal, a participation signal indicating participation in the AC voltage output operation and including a preset identifier, and an acknowledge signal to the second signal line; The control circuit outputting the second reference signal to the first signal line after receiving the acknowledge signal from an inverter participating in the output operation of the AC voltage; Each of the plurality of inverters start outputting an AC voltage synchronized with a set or specified phase relative to the rising or falling edge of the second reference signal; It is characterized by:

[0012] In the power supply device, The control circuit an output voltage instruction signal, which is a signal that instructs an output voltage and whose destination is specified by the identifier, is output to the second signal line; Each of the plurality of inverters outputting an AC voltage corresponding to the output voltage instruction signal whose destination is the identifier of the device itself; It is characterized by:

[0013] In the power supply device, Among the plurality of inverters, an inverter that outputs an AC voltage at a phase other than 0° with respect to the reference signal is A soft start is performed to change the output voltage at a constant rate until the target AC voltage is reached. It is characterized by:

[0014] In the power supply device, the plurality of inverters include a first inverter to a sixth inverter, the first inverter and the second inverter output an AC voltage having a phase of 0° with respect to the reference signal; the third inverter and the fourth inverter output an AC voltage having a phase delay of 120° with respect to the reference signal; The fifth inverter and the sixth inverter output AC voltages whose phases are 120° ahead of the reference signal. It is characterized by:

[0015] In the power supply device, the plurality of inverters include a first inverter to a sixth inverter, The first inverter to the sixth inverter output AC voltages having a phase of 0° with respect to the reference signal. It is characterized by: [Effects of the Invention]

[0016] ADVANTAGEOUS EFFECT OF THE INVENTION A power supply device according to one embodiment of the present invention has an advantage in that it is possible to increase the degree of freedom in the number of inverters that can be connected, and to realize a variety of output configurations. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram showing the configuration of a power supply device of a comparative example. [Figure 2] FIG. 2 is a diagram illustrating the configuration of the power supply device according to the first embodiment. [Figure 3] FIG. 3 is a flowchart showing the operation at the time of start-up of the power supply device according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an AC output voltage waveform at the time of startup of the power supply device according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing a waveform of an AC output voltage in a steady state of the power supply device according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating the configuration of a power supply device according to the second embodiment. [Figure 7] FIG. 7 is a diagram illustrating a first connection example of the terminal module of the power supply device according to the second embodiment. [Figure 8] FIG. 8 is a diagram illustrating a second connection example of the terminal module of the power supply device according to the second embodiment. [Figure 9]FIG. 9 is a diagram illustrating a third connection example of the terminal module of the power supply device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0019] First Embodiment The first embodiment will be described below, but to facilitate understanding of the first embodiment, a comparative example will be described first.

[0020] (Comparative Example) 1 is a diagram showing the configuration of a power supply device of a comparative example. The power supply device 100 includes a control circuit 101 and first to third inverters 102 to 104.

[0021] Of the first inverter 102 to the third inverter 104, the first inverter 102 is the master, and the second inverter 103 and the third inverter 104 are slaves.

[0022] The control circuit 101 includes a communication unit 101a. The communication unit 101a is electrically connected to the first inverter 102 to the third inverter 104 via a signal line 111. The communication unit 101a communicates with the first inverter 102 to the third inverter 104 via the signal line 111.

[0023] The first inverter 102 includes a control unit 102a and a power conversion unit 102e. The control unit 102a includes a communication unit 102b, a first synchronization signal generation unit 102c, and a second synchronization signal generation unit 102d.

[0024] The communication unit 102b is electrically connected to the communication unit 101a via a signal line 111 and communicates with the communication unit 101a. The control unit 102a controls the power conversion unit 102e based on a signal received from the communication unit 101a. Under the control of the control unit 102a, the power conversion unit 102e converts the DC voltage DCIN into an R-phase AC voltage and outputs it.

[0025] The first synchronization signal generator 102c generates a first synchronization signal that is delayed by 120° from the zero-cross position of the R-phase AC voltage.

[0026] The first synchronization signal generation unit 102c is electrically connected to the second inverter 103 via a signal line 112, and is electrically connected to the third inverter 104 via a signal line 113. The first synchronization signal generation unit 102c outputs a first synchronization signal to the second inverter 103 via the signal line 112, and to the third inverter 104 via the signal line 113.

[0027] The second synchronization signal generator 102d generates a second synchronization signal that is 120° ahead of the zero-cross position of the R-phase AC voltage.

[0028] The second synchronization signal generation unit 102d is electrically connected to the second inverter 103 via a signal line 114, and is electrically connected to the third inverter 104 via a signal line 115. The second synchronization signal generation unit 102d outputs the second synchronization signal to the second inverter 103 via the signal line 114, and to the third inverter 104 via the signal line 115.

[0029] The second inverter 103 includes a control unit 103a and a power conversion unit 103e. The control unit 103a includes a communication unit 103b, a first synchronization signal receiving unit 103c, and a second synchronization signal receiving unit 103d.

[0030] The communication unit 103b is electrically connected to the communication unit 101a via a signal line 111 and communicates with the communication unit 101a.

[0031] The first synchronization signal receiver 103c receives the first synchronization signal from the first synchronization signal generator 102c of the first inverter 102 via the signal line 112. The control unit 103a controls the power converter 103e in synchronization with the first synchronization signal. Under the control of the control unit 103a, the power converter 103e converts the DC voltage DCIN into an S-phase AC voltage and outputs it.

[0032] The second synchronization signal receiving unit 103d receives the second synchronization signal from the second synchronization signal generating unit 102d of the first inverter 102 via the signal line 114.

[0033] The third inverter 104 includes a control unit 104a and a power conversion unit 104e. The control unit 104a includes a communication unit 104b, a first synchronization signal receiving unit 104c, and a second synchronization signal receiving unit 104d.

[0034] The communication unit 104b is electrically connected to the communication unit 101a via a signal line 111 and communicates with the communication unit 101a.

[0035] The first synchronization signal receiving unit 104c receives the first synchronization signal from the first synchronization signal generating unit 102c of the first inverter 102 via the signal line 113.

[0036] The second synchronization signal receiver 104d receives the second synchronization signal from the second synchronization signal generator 102d of the first inverter 102 via the signal line 115. The control unit 104a controls the power converter 104e in synchronization with the second synchronization signal. Under the control of the control unit 104a, the power converter 104e converts the DC voltage DCIN into a T-phase AC voltage and outputs it.

[0037] When the AC outputs from the first inverter 102 to the third inverter 104 are connected in series-parallel, the AC outputs from the first inverter 102 to the third inverter 104 must be synchronized. In the power supply device 100, the first inverter 102, which is the master, transmits a first synchronization signal and a second synchronization signal to the second inverter 103 and the third inverter 104, thereby synchronizing the AC outputs from the first inverter 102 to the third inverter 104.

[0038] In this case, the second inverter 103 and the third inverter 104 need to receive the first and second synchronization signals at a speed that is sufficiently faster than the control speed. Therefore, the second inverter 103 is electrically connected to the first inverter 102 via signal lines 112 and 114. The third inverter 104 is electrically connected to the first inverter 102 via signal lines 113 and 115.

[0039] As the number of inverters increases, the amount of wiring also increases, and the number of signal line connectors mounted on each of the first inverter 102 to the third inverter 104 also increases. Therefore, if signal line connectors corresponding to the expected number of inverters (e.g., three) are mounted on each of the first inverter 102 to the third inverter 104, it is not possible to increase the number of inverters (e.g., six) later. In other words, the power supply device 100 has limited flexibility in the number of inverters that can be connected.

[0040] To prevent this, it is necessary to determine the maximum number of inverters (e.g., six) in advance and mount the same number of signal line connectors on each of the first inverter 102 to the third inverter 104. This increases the mounting space and costs.

[0041] (First embodiment) [composition] 2 is a diagram showing the configuration of a power supply device according to the first embodiment. The power supply device 1 includes a control circuit 2 and first to third inverters 3 to 5.

[0042] In the first embodiment, the control circuit 2 is separate from the first inverter 3 to the third inverter 5, but the present disclosure is not limited to this. The control circuit 2 may be mounted on (built into) any of the first inverter 3 to the third inverter 5. This allows the power supply device 1 to reduce installation space and costs.

[0043] In the first embodiment, the number of inverters is three, but the present disclosure is not limited to this. The number of inverters may be two or four or more.

[0044] In the first embodiment, unlike the comparative example, the first inverter 3 to the third inverter 5 are not divided into masters or slaves.

[0045] The control circuit 2 includes a communication unit 2 a and a synchronization signal transmission unit 2 b. When the control circuit 2 is separate from the first inverter 3 to the third inverter 5, it is exemplified as an ECU (Engine Control Unit), but the present disclosure is not limited thereto.

[0046] The communication unit 2a is electrically connected to the first inverter 3 to the third inverter 5 via a signal line 11. The signal line 11 is exemplified by a CAN (Controller Area Network, ISO 11898), but the present disclosure is not limited thereto. The communication unit 2a communicates with the first inverter 3 to the third inverter 5 via the signal line 11.

[0047] The signal line 11 corresponds to an example of a "second signal line" in the present disclosure.

[0048] The synchronization signal transmitter 2b is electrically connected to the first inverter 3 to the third inverter 5 via a signal line 12. The synchronization signal transmitter 2b transmits a synchronization signal that changes at a constant period to the first inverter 3 to the third inverter 5 via the signal line 12. The synchronization signal is exemplified by a 50 Hz square wave signal with a 50% duty, but the present disclosure is not limited to this.

[0049] The signal line 12 corresponds to an example of a "first signal line" in the present disclosure. The synchronization signal corresponds to an example of a "reference signal" in the present disclosure.

[0050] The first inverter 3 includes a control unit 3a and a power conversion unit 3e. The control unit 3a includes a communication unit 3b, a synchronization signal receiving unit 3c, and an ID setting unit 3d.

[0051] The ID setting unit 3d is preset with an identifier that uniquely identifies the first inverter 3. The ID setting unit 3d is exemplified by a nonvolatile memory (for example, a flash memory (registered trademark)), a DIP switch, etc., but the present disclosure is not limited thereto.

[0052] The communication unit 3b is electrically connected to the communication unit 2a via a signal line 11 and communicates with the communication unit 2a. When communicating, the communication unit 3b uses the identifier set in the ID setting unit 3d.

[0053] The synchronization signal receiving unit 3c is electrically connected to the synchronization signal transmitting unit 2b via a signal line 12 and receives the synchronization signal. The control unit 3a controls the power conversion unit 3e at a timing according to the synchronization signal. Under the control of the control unit 3a, the power conversion unit 3e converts the DC voltage DCIN into an R-phase AC voltage and outputs it.

[0054] The second inverter 4 includes a control unit 4a and a power conversion unit 4e. The control unit 4a includes a communication unit 4b, a synchronization signal receiving unit 4c, and an ID setting unit 4d.

[0055] An identifier that uniquely identifies the second inverter 4 is set in advance in the ID setting unit 4d.

[0056] The communication unit 4b is electrically connected to the communication unit 2a via a signal line 11 and communicates with the communication unit 2a. When communicating, the communication unit 4b uses the identifier set in the ID setting unit 4d.

[0057] The synchronization signal receiving unit 4c is electrically connected to the synchronization signal transmitting unit 2b via a signal line 12 and receives the synchronization signal. The control unit 4a controls the power conversion unit 4e at a timing according to the synchronization signal. Under the control of the control unit 4a, the power conversion unit 4e converts the DC voltage DCIN into an S-phase AC voltage and outputs it.

[0058] The third inverter 5 includes a control unit 5a and a power conversion unit 5e. The control unit 5a includes a communication unit 5b, a synchronization signal receiving unit 5c, and an ID setting unit 5d.

[0059] An identifier that uniquely identifies the third inverter 5 is set in advance in the ID setting unit 5d.

[0060] The communication unit 5b is electrically connected to the communication unit 2a via a signal line 11 and communicates with the communication unit 2a. When communicating, the communication unit 5b uses the identifier set in the ID setting unit 5d.

[0061] The synchronization signal receiving unit 5c is electrically connected to the synchronization signal transmitting unit 2b via a signal line 12 and receives the synchronization signal. The control unit 5a controls the power conversion unit 5e at a timing according to the synchronization signal. Under the control of the control unit 5a, the power conversion unit 5e converts the DC voltage DCIN into a T-phase AC voltage and outputs it.

[0062] Note that a default value of the output voltage (for example, 100 V, 240 V, etc.) may be set in advance for the first inverter 3 to the third inverter 5. Then, when it is necessary to change the output voltage from the default value, the control circuit 2 may instruct the first inverter 3 to the third inverter 5 of the output voltage via the signal line 11.

[0063] Similarly, default values ​​for the phase (for example, 0°, 120° lag, 120° lead, etc.) may be set in advance for the first inverter 3 to the third inverter 5. Then, when it is necessary to change the phase from the default value, the control circuit 2 may instruct the first inverter 3 to the third inverter 5 of the phase via the signal line 11.

[0064] [Startup behavior] FIG. 3 is a flowchart showing the operation at the time of start-up of the power supply device according to the first embodiment.

[0065] In step S100, the synchronization signal transmitter 2b of the control circuit 2 outputs a first synchronization signal to the first inverter 3 to the third inverter 5 via the signal line 12. The first synchronization signal is exemplified by the first synchronization signal output by the synchronization signal transmitter 2b, but the present disclosure is not limited thereto.

[0066] The communication unit 2a of the control circuit 2 transmits, in synchronization with the rising or falling edge of the first synchronization signal, a plurality of voltage output start instruction signals, each including an identifier of the first inverter 3 to the third inverter 5 participating in the AC voltage output operation, to the communication units 3b to 5b of the first inverter 3 to the third inverter 5 via the signal line 11.

[0067] At this time, the communication unit 2a of the control circuit 2 may also transmit, from the first inverter 3 to the third inverter 5, an output voltage instruction signal (e.g., 100V instruction, 240V instruction, etc.) which is a signal indicating the output voltage and whose destination is specified by an identifier, a phase instruction signal which is a signal indicating the phase and whose destination is specified by an identifier, etc.

[0068] In step S200, within a certain period of time starting from the time of receiving the voltage output start instruction signal, the communication unit 3b of the first inverter 3 transmits a participation signal, which indicates participation in the AC voltage output operation and includes the identifier set in the ID setting unit 3d, to the communication unit 2a via the signal line 11. As a result, the first inverter 3 participates in the AC voltage output operation. The communication unit 4b of the second inverter 4 transmits a participation signal, which includes the identifier set in the ID setting unit 4d, to the communication unit 2a via the signal line 11. As a result, the second inverter 4 participates in the AC voltage output operation. The communication unit 5b of the third inverter 5 transmits a participation signal, which includes the identifier set in the ID setting unit 5d, to the communication unit 2a via the signal line 11. As a result, the third inverter 5 participates in the AC voltage output operation.

[0069] The control circuit 2 can recognize the inverters that will participate in the AC voltage output operation based on the participation signals transmitted from the first inverter 3 to the third inverter 5. This allows the control circuit 2 to recognize that it needs to receive acknowledge signals from the first inverter 3 to the third inverter 5.

[0070] In step S202, within a certain period of time starting from the time of receiving the voltage output start instruction signal, the communication units 3b to 5b of the first to third inverters 3 to 5 transmit an acknowledge signal including an identifier to the communication unit 2a of the control circuit 2 via the signal line 11. The acknowledge signal indicates that an AC voltage will be output from the rising or falling timing of the next reference signal (second reference signal).

[0071] When the synchronization signal transmitting unit 2b of the control circuit 2 receives acknowledge signals from the first inverter 3 to the third inverter 5, in step S102, at the timing when the period of the first synchronization signal ends, the synchronization signal transmitting unit 2b outputs the next synchronization signal (second synchronization signal) to the signal line 12. The second synchronization signal output by the synchronization signal transmitting unit 2b is exemplified as the second synchronization signal, but the present disclosure is not limited thereto.

[0072] When the control units 3a to 5a of the first inverter 3 to the third inverter 5 receive the rising or falling edge of the second synchronization signal, in step S204 they perform control to start outputting AC voltages synchronized with the rising or falling edge of the second synchronization signal at the set or instructed phase.

[0073] As a result, the first inverter 3 to the third inverter 5 can start outputting AC voltage at the rising or falling edge of the second synchronization signal.

[0074] 4 is a diagram showing an AC output voltage waveform at the time of start-up of the power supply device according to the first embodiment, in which timing t0 represents the rising (or falling) timing of the second synchronization signal.

[0075] Waveform 201 represents the R-phase voltage output by the first inverter 3. Waveform 202 represents the S-phase voltage output by the second inverter 4. Waveform 202 lags behind waveform 201 by 120°. Waveform 203 represents the T-phase voltage output by the third inverter 5. Waveform 203 leads waveform 201 by 120°.

[0076] A waveform 204 represents the target (ideal) voltage of the S phase. A waveform 205 represents the target (ideal) voltage of the T phase.

[0077] When the reference signal is 50 Hz, one cycle of the reference signal is 20 ms. It takes about 1 ms to 2 ms for the control circuit 2 to transmit an instruction signal to the first inverter 3 to the third inverter 5, and for the first inverter 3 to the third inverter 5 to transmit an acknowledge signal to the control circuit 2. Therefore, the first inverter 3 to the third inverter 5 can simultaneously output voltages from the rising edge of the second reference signal t0.

[0078] Therefore, the second inverter 4 outputs a voltage that changes at a constant rate of change until point 206 when the output voltage reaches the target (ideal) voltage, and can output an S-phase AC voltage after point 206. The third inverter 5 outputs a voltage that changes at a constant rate of change until point 207 when the output voltage reaches the target (ideal) voltage, and can output a T-phase AC voltage after point 207.

[0079] In other words, the power supply device 1 can achieve a soft start.

[0080] FIG. 5 is a diagram showing a waveform of an AC output voltage in a steady state of the power supply device according to the first embodiment.

[0081] A waveform 211 shows a synchronization signal. As shown in the waveform 211, the synchronization signal is generated at timing t 10 Rise at timing t 11 Falling edge at timing t 12 and stand up.

[0082] Timing t 10 From timing t 12 This is one cycle of the AC voltage.

[0083] A waveform 212 represents the R-phase voltage output from the first inverter 3. As shown by the waveform 212, the R-phase voltage rises at a timing t 10 It crosses zero at time t 11 It crosses zero at time t 12 Zero crossing occurs.

[0084] A waveform 213 represents the S-phase voltage output by the second inverter 4. As shown by the waveform 213, the S-phase voltage 10 The phase is -120° at time t 11 The phase is 60° at time t 12 and the phase is -120°.

[0085] A waveform 214 represents the T-phase voltage output by the third inverter 5. As shown by the waveform 214, the T-phase voltage 10 The phase is 120° at time t 11 The phase is 300° at time t 12 The phase is 120°.

[0086] In addition, each inverter corrects the discrepancy between the phase of the voltage it is outputting and the set or instructed phase at the timing of the rising (or falling) edge of the synchronization signal, thereby obtaining an output with a stable phase.

[0087] In the above description, the first inverter 3 to the third inverter 5 output AC voltages with phases of 0°, -120°, and 120° relative to the rising edge of the synchronization signal, but the present disclosure is not limited to this. The first inverter 3 to the third inverter 5 may also output AC voltages with phases of 0°, -120°, and 120° relative to the falling edge of the synchronization signal.

[0088] Furthermore, if any trouble occurs in any of the first inverter 3 to the third inverter 5, a notification signal indicating the occurrence of the trouble may be sent to the control circuit 2 via the signal line 11. When the control circuit 2 receives the notification signal indicating the occurrence of the trouble, it may send an instruction signal to stop the AC voltage output to the first inverter 3 to the third inverter 5 via the signal line 11. In this way, the power supply device 1 can stop the first inverter 3 to the third inverter 5 even if a trouble occurs in any of the first inverter 3 to the third inverter 5.

[0089] [summary] [1] In the power supply device 1, it is sufficient that the first inverter 3 to the third inverter 5 are electrically connected to the signal lines 11 and 12. In other words, it is sufficient that the first inverter 3 to the third inverter 5 have two signal line connectors. Therefore, even if the number of inverters increases later, it is not necessary to increase the number of signal line connectors between the first inverter 3 and the third inverter 5. This allows the power supply device 1 to have a high degree of freedom in the number of inverters that can be connected.

[0090] [2] In Patent Document 1, the master outputs an AC voltage → 120° elapses (zero cross) → one slave outputs an AC voltage → 120° elapses (zero cross) → another slave outputs an AC voltage. In other words, in Patent Document 1, it takes time for the three-phase voltages to appear. Also, in Patent Document 1, the three-phase voltages start appearing at different times, so a breaker must be provided in the subsequent stage, and the breaker must be turned on when the three-phase voltages appear. In other words, in Patent Document 1, a breaker is required in the subsequent stage.

[0091] On the other hand, in the power supply 1, when the synchronization signal is 50 Hz, one cycle of the synchronization signal is 20 ms. Transmission of command signals from the control circuit 2 to the first inverter 3 to the third inverter 5 and transmission of acknowledge signals from the first inverter 3 to the third inverter 5 to the control circuit 2 can be completed in approximately 1 ms to 2 ms. Therefore, as shown at timing t0 in Figure 4, the first inverter 3 to the third inverter 5 can simultaneously output voltage from the rising edge of the second reference signal. This allows the power supply 1 to achieve a soft start. Furthermore, the power supply 1 does not require a circuit breaker in the downstream stage.

[0092] <Second embodiment> FIG. 6 is a diagram illustrating the configuration of a power supply device according to the second embodiment.

[0093] Compared to the power supply device 1 of the first embodiment, the power supply device 1A of the second embodiment further includes a fourth inverter 6 to a sixth inverter 8.

[0094] The internal configuration of the fourth inverter 6 to the sixth inverter 8 is similar to the internal configuration of the first inverter 3 to the third inverter 5 (see FIG. 2), and therefore illustration and description thereof will be omitted.

[0095] The output terminals of the first inverter 3 to the sixth inverter 8 are electrically connected to the terminal module 21. The terminal module 21 can change the connection relationship of the output terminals of the first inverter 3 to the sixth inverter 8.

[0096] The terminal module 21 may be configured to change the connection relationship of the output terminals of the first inverter 3 to the sixth inverter 8 in response to a control signal supplied from the outside.

[0097] 7 is a diagram showing a first connection example of the terminal module of the power supply device according to the second embodiment. In the first connection example, the phase of the output voltages of the first inverter 3 and the second inverter 4 is instructed or set to 0°, the phase of the output voltages of the third inverter 5 and the fourth inverter 6 is instructed or set to 120° lag, and the phase of the output voltages of the fifth inverter 7 and the sixth inverter 8 is instructed or set to 120° lead.

[0098] The terminal module 21 electrically connects one end of the first inverter 3 and one end of the second inverter 4 to a node N1. The terminal module 21 electrically connects the other end of the first inverter 3 and the other end of the second inverter 4 to a node N2.

[0099] The terminal module 21 electrically connects one end of the third inverter 5 and one end of the fourth inverter 6 to a node N2. The terminal module 21 electrically connects the other end of the third inverter 5 and the other end of the fourth inverter 6 to a node N3.

[0100] The terminal module 21 electrically connects one end of the fifth inverter 7 and one end of the sixth inverter 8 to the node N2. The terminal module 21 electrically connects the other end of the fifth inverter 7 and the other end of the sixth inverter 8 to the node N4.

[0101] That is, the terminal module 21 connects the first inverter 3 and the second inverter 4, the third inverter 5 and the fourth inverter 6, and the fifth inverter 7 and the sixth inverter 8 in a three-phase Y (star) configuration.

[0102] As a result, an R-phase AC voltage is output from node N1, an S-phase AC voltage is output from node N3, and a T-phase AC voltage is output from node N4.

[0103] 8 is a diagram showing a second connection example of the terminal module of the power supply device according to the second embodiment. In the second connection example, the phase of the output voltages of the first inverter 3 and the second inverter 4 is instructed or set to 0°, the phase of the output voltages of the third inverter 5 and the fourth inverter 6 is instructed or set to 120° lag, and the phase of the output voltages of the fifth inverter 7 and the sixth inverter 8 is instructed or set to 120° lead.

[0104] The terminal module 21 electrically connects one end of the third inverter 5 and one end of the fourth inverter 6 to a node N5. The terminal module 21 electrically connects the other end of the third inverter 5 and the other end of the fourth inverter 6 to a node N6.

[0105] The terminal module 21 electrically connects one end of the fifth inverter 7 and one end of the sixth inverter 8 to a node N6. The terminal module 21 electrically connects the other end of the fifth inverter 7 and the other end of the sixth inverter 8 to a node N7.

[0106] That is, the terminal module 21 connects the third inverter 5 and the fourth inverter 6, and the fifth inverter 7 and the sixth inverter 8 in a three-phase V-connection.

[0107] As a result, an R-phase AC voltage is output from node N5, an S-phase AC voltage is output from node N6, and a T-phase AC voltage is output from node N7.

[0108] The terminal module 21 electrically connects one end of the first inverter 3 and one end of the second inverter 4 to a node N8. The terminal module 21 electrically connects the other end of the first inverter 3 and the other end of the second inverter 4 to a node N9.

[0109] In other words, the terminal module 21 connects the first inverter 3 and the second inverter 4 in parallel.

[0110] As a result, an R'-phase AC voltage is output from node N8, and an S'-phase AC voltage is output from node N9.

[0111] 9 is a diagram showing a third connection example of the terminal module of the power supply device according to the second embodiment. In the third connection example, the phases of the output voltages from the first inverter 3 to the sixth inverter 8 are instructed or set to 0°.

[0112] The terminal module 21 electrically connects one end of the first inverter 3 and one end of the second inverter 4 to a node N10. The terminal module 21 electrically connects the other end of the first inverter 3 and the other end of the second inverter 4 to a node N11.

[0113] The terminal module 21 electrically connects one end of the third inverter 5 and one end of the fourth inverter 6 to a node N11. The terminal module 21 electrically connects the other end of the third inverter 5 and the other end of the fourth inverter 6 to a node N12.

[0114] That is, the terminal module 21 connects the first inverter 3 and the second inverter 4, and the third inverter 5 and the fourth inverter 6 together in a single-phase three-wire configuration.

[0115] As a result, an R-phase AC voltage is output from node N10, an N-phase AC voltage is output from node N11, and an S-phase AC voltage is output from node N12.

[0116] The terminal module 21 electrically connects one end of the fifth inverter 7 and one end of the sixth inverter 8 to a node N13. The terminal module 21 electrically connects the other end of the fifth inverter 7 and the other end of the sixth inverter 8 to a node N14.

[0117] That is, the terminal module 21 connects the fifth inverter 7 and the sixth inverter 8 in parallel.

[0118] As a result, an R'-phase AC voltage is output from node N13, and an S'-phase AC voltage is output from node N14.

[0119] In this way, the power supply device 1A can obtain various wiring connections and various output voltages by having the first inverter 3 to the sixth inverter 8 output AC voltages at set or instructed phases.

[0120] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0121] 1, 1A, 100 power supply 2, 101 control circuit 3a, 4a, 5a, 102a, 103a, 104a control section 2a, 3b, 4b, 5b, 101a, 102b, 103b, 104b Communication Department 2b Synchronization signal transmitter 3, 102 1st inverter 3c, 4c, 5c Synchronous signal receiver 3d, 4d, 5d ID setting section 3e, 4e, 5e, 102e, 103e, 104e power conversion section 4, 103 Second inverter 5, 104 3rd inverter 6 4th inverter 7 5th inverter 8 6th inverter 11, 12, 111, 112, 113, 114, 115 signal lines 21 Terminal Module 102c First synchronization signal generation section 102d Second synchronization signal generation unit 103c, 104c First synchronization signal receiving unit 103d, 104d Second synchronization signal receiving unit

Claims

1. a control circuit and a plurality of inverters electrically connected via a first signal line; Including, The control circuit a reference signal that changes at a constant period is output to the first signal line; Each of the plurality of inverters outputting an AC voltage synchronized with a set or specified phase relative to the rising or falling edge of the reference signal; the control circuit and the plurality of inverters are electrically connected via a second signal line; The control circuit outputting a voltage output start instruction signal, which is a signal instructing to start outputting an AC voltage, to the second signal line in synchronization with a first reference signal, which is a signal of a first period among a plurality of periods of the reference signal; Each of the plurality of inverters start outputting an AC voltage synchronized with a set or specified phase relative to a rising or falling edge of a second reference signal, which is a signal of a second period among the plurality of periods of the reference signal; Each of the plurality of inverters outputting, to the second signal line, a participation signal that indicates participation in an AC voltage output operation from the timing of a rise or fall of the second reference signal within a certain period of time starting from the time of receiving the voltage output start instruction signal and before the second reference signal is output; and the participation signal includes a preset identifier; The control circuit By receiving the participation signal from the inverter participating in the output operation of the AC voltage, it is determined that an acknowledge signal needs to be received from the inverter participating in the output operation of the AC voltage; Each of the plurality of inverters outputting the acknowledge signal to the second signal line within a certain period of time starting from the time when the voltage output start instruction signal is received, after outputting the participation signal, and before outputting the second reference signal; The control circuit outputting the second reference signal to the first signal line; Each of the plurality of inverters starting to output an AC voltage synchronized with a set or specified phase relative to the rising or falling edge of the second reference signal; Among the plurality of inverters, an inverter that outputs an AC voltage at a phase of 0° with respect to the rising or falling edge of the reference signal is outputting an AC voltage from the rising or falling edge of the second reference signal; Among the plurality of inverters, an inverter that outputs an AC voltage at a phase other than 0° with respect to the rising or falling edge of the reference signal is a soft start is performed to change the output voltage at a constant rate of change from the rising or falling edge of the second reference signal until the output voltage reaches a target AC voltage, and after the output voltage reaches the target AC voltage, an AC voltage is output. A power supply device comprising:

2. The control circuit included in any one of the plurality of inverters, 2. The power supply device according to claim 1 .

3. The control circuit an output voltage instruction signal, which is a signal instructing an output voltage and whose destination is specified by the identifier, is output to the second signal line; Each of the plurality of inverters outputting an AC voltage corresponding to the output voltage instruction signal whose destination is the identifier of the device itself; 2. The power supply device according to claim 1 .

4. the plurality of inverters include a first inverter to a sixth inverter, the first inverter and the second inverter output an AC voltage having a phase of 0° with respect to a rising edge or a falling edge of the reference signal; the third inverter and the fourth inverter output an AC voltage having a phase delay of 120° with respect to a rising edge or a falling edge of the reference signal, the fifth inverter and the sixth inverter output AC voltages whose phases lead 120° with respect to the rising or falling edge of the reference signal; 4. The power supply device according to claim 1, wherein the power supply device comprises:

5. the plurality of inverters include a first inverter to a sixth inverter, The first inverter to the sixth inverter output an AC voltage having a phase of 0° with respect to the rising or falling edge of the reference signal.

4. The power supply device according to claim 1, wherein the power supply device comprises:

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