Test chip, method of using the same, and reaction system

Abstract

The test chip (100) includes a first substrate (10), a microcavity-defining layer (11), and a heating electrode (12). The microcavity-defining layer (11) is located on the first substrate (10) and defines a plurality of microreaction chambers (111). The heating electrode (12) is located on the first substrate (10) and is closer to the first substrate (10) than the microcavity-defining layer (11). The heating electrode (12) is configured to release heat after energization. The heating electrode (12) includes a plurality of sub-electrodes, and the orthogonal projections of the plurality of microreaction chambers (111) on the first substrate (10) overlap with the orthogonal projections of at least two of the sub-electrodes on the first substrate (10). At least two of the sub-electrodes generate different amounts of heat per unit time after energization. The test chip (100) can improve temperature uniformity and reduce the area of ​​edge cold regions.

Description

[Technical Field]

[0001] This application claims priority to Chinese patent application No. 202010367934.4, filed on April 30, 2020, the entire contents of which are incorporated herein by reference.

[0002] SUMMARY OF THE INVENTION The embodiments of the present disclosure relate to a test chip, a method for using the same, and a reaction system. [Background technology]

[0003] Polymerase chain reaction (PCR) is a molecular biology technique for amplifying specific DNA segments, enabling the replication of minute amounts of deoxyribonucleic acid (DNA) to significantly increase their quantity. Unlike traditional PCR, digital PCR (dPCR) chip technology dilutes nucleic acid samples sufficiently to ensure that each reaction unit contains no more than one target molecule (i.e., DNA template). Each reaction unit then performs PCR amplification for each target molecule. After amplification, statistical analysis of the fluorescent signals from each reaction unit is performed, enabling absolute quantitative testing of single DNA molecules. Due to its advantages of high sensitivity, strong specificity, high-throughput testing, and accurate quantification, dPCR has been widely used in clinical diagnosis, genetic instability analysis, single-cell gene expression, environmental microbial detection, and prenatal testing. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a test chip, the test chip including: a first substrate; a microcavity defining layer located on the first substrate and defining a plurality of microreaction chambers; and a heating electrode located on the first substrate closer to the first substrate than the microcavity defining layer, the heating electrode configured to release heat after being energized. The heating electrode includes a plurality of sub-electrodes, wherein orthogonal projections of the plurality of microreaction chambers on the first substrate overlap with orthogonal projections of at least two of the sub-electrodes, and at least two of the sub-electrodes have different amounts of heat generated per unit time after being energized.

[0005] For example, in an inspection chip according to one embodiment of the present disclosure, the heating electrode allows current to flow along a first direction after being energized, the plurality of sub-electrodes are spaced apart along a second direction, the second direction is perpendicular to the first direction, any of the plurality of sub-electrodes has both sides facing the second direction, the plurality of sub-electrodes include a first sub-electrode and at least one second sub-electrode, the first sub-electrode has a sub-electrode adjacent to only one of the two sides, the second sub-electrode has a sub-electrode adjacent to both of the two sides, and the resistance value of the second sub-electrode is greater than the resistance value of the first sub-electrode.

[0006] For example, in a test chip according to an embodiment of the present disclosure, the width of the second sub-electrode along the second direction is smaller than the width of the first sub-electrode along the second direction.

[0007] For example, in an inspection chip according to one embodiment of the present disclosure, the at least one second sub-electrode includes a plurality of second sub-electrodes, which are spaced apart along the second direction, and the resistance values ​​of the plurality of second sub-electrodes decrease sequentially in the second direction, extending from the center of the heating electrode to the edge of the heating electrode.

[0008] For example, in an inspection chip according to one embodiment of the present disclosure, the widths of the plurality of second sub-electrodes along the second direction increase in order in the direction extending from the center of the heating electrode to the edge of the heating electrode.

[0009] For example, in an inspection chip according to one embodiment of the present disclosure, the at least one second sub-electrode includes a plurality of second sub-electrodes, which are spaced apart along the second direction, and the resistance values ​​of the plurality of second sub-electrodes are basically equal.

[0010] For example, in a test chip according to an embodiment of the present disclosure, the widths of the second sub-electrodes along the second direction are essentially equal.

[0011] For example, in a test chip according to one embodiment of the present disclosure, the spacing distance between adjacent sub-electrodes is 1-200 microns.

[0012] For example, in a test chip according to an embodiment of the present disclosure, the cross-sectional shape of at least one of the plurality of sub-electrodes is rectangular, trapezoidal, triangular, or wavy, and the cross-section is parallel to the first substrate.

[0013] For example, in the test chip according to one embodiment of the present disclosure, the number of the plurality of sub-electrodes is three or more.

[0014] For example, in an inspection chip according to one embodiment of the present disclosure, the orthogonal projections of the multiple sub-electrodes on the first substrate overlap in order, the orthogonal projections of the sub-electrodes other than the sub-electrode located at the center of the heating electrode are ring-shaped, and the multiple sub-electrodes are insulated from each other.

[0015] For example, in a test chip according to an embodiment of the present disclosure, the sub-electrodes are located on different layers or on the same layer.

[0016] For example, in a test chip according to an embodiment of the present disclosure, the cross-sectional shape of at least one of the plurality of sub-electrodes is a rectangular ring, a circular ring, or an elliptical ring, and the cross-section is parallel to the first substrate.

[0017] For example, in the test chip according to one embodiment of the present disclosure, the number of the plurality of sub-electrodes is two or more.

[0018] For example, in the test chip according to one embodiment of the present disclosure, the material of the heating electrode is a transparent conductive material.

[0019] For example, the test chip according to one embodiment of the present disclosure further includes a receiving chamber, the plurality of micro-reaction chambers are located in the receiving chamber, and the receiving chamber has an arc-shaped boundary.

[0020] For example, in an inspection chip according to one embodiment of the present disclosure, the microcavity defining layer further defines an inlet channel and an outlet channel, both of which communicate with the accommodating chamber, and the arcuate boundary of the accommodating chamber is located at the point where the accommodating chamber connects to the inlet channel and the outlet.

[0021] For example, in the test chip according to one embodiment of the present disclosure, the arcuate boundary has a curvature of π / 2 or less.

[0022] For example, in an inspection chip according to one embodiment of the present disclosure, the arc-shaped boundaries are located on opposite sides of the accommodating chamber, the arc-shaped boundaries include a first arc-shaped boundary and a second arc-shaped boundary, the inlet channel is connected to the accommodating chamber at the first arc-shaped boundary, and the outlet channel is connected to the accommodating chamber at the second arc-shaped boundary.

[0023] For example, in a test chip according to one embodiment of the present disclosure, the length of the inlet channel is 1000-10000 microns, and the length of the outlet channel is 1000-10000 microns.

[0024] For example, an inspection chip according to one embodiment of the present disclosure further includes a control circuit layer and a first insulating layer stacked on the first substrate, the control circuit layer including a control circuit, the first insulating layer including a via hole, the heating electrode provided on the first insulating layer, the control circuit electrically connected to the heating electrode by the via hole, and the control circuit configured to apply an electrical signal to the heating electrode to energize the heating electrode.

[0025] For example, in a test chip according to one embodiment of the present disclosure, the control circuit layer further includes at least one connection electrode, which is not covered by the first insulating layer and is exposed to air.

[0026] For example, in an inspection chip according to one embodiment of the present disclosure, when the orthogonal projections of the plurality of sub-electrodes on the first substrate overlap in order, the at least one connection electrode includes a plurality of connection electrodes, the plurality of connection electrodes are divided into a plurality of sets, the connection electrodes of the plurality of sets correspond one-to-one to the plurality of sub-electrodes, and the connection electrodes of each set are configured to transfer an electrical signal to the corresponding sub-electrode by the control circuit.

[0027] For example, in a test chip according to an embodiment of the present disclosure, the electrical signals transferred by the plurality of sets of connection electrodes are different from one another.

[0028] For example, in a test chip according to an embodiment of the present disclosure, each set of connection electrodes includes two connection electrodes, which are located on opposite sides of the test chip.

[0029] For example, the test chip according to an embodiment of the present disclosure further includes a reaction area and a peripheral area, the heating electrode and the plurality of micro-reaction chambers are located in the reaction area, and the connecting electrode is located in the peripheral area.

[0030] For example, an inspection chip according to one embodiment of the present disclosure further includes a hydrophilic layer and a second insulating layer, wherein the hydrophilic layer covers at least the side walls and bottom of each of the plurality of micro-reaction chambers, and the second insulating layer is disposed between the heating electrode and the micro-cavity limiting layer.

[0031] For example, a test chip according to an embodiment of the present disclosure further includes a second substrate, and the second substrate and the first substrate are disposed opposite to each other.

[0032] For example, in a test chip according to an embodiment of the present disclosure, the first substrate and the second substrate both include a glass substrate.

[0033] For example, a test chip according to an embodiment of the present disclosure further includes a hydrophobic layer, which covers the side of the second substrate facing the first substrate.

[0034] For example, the test chip according to one embodiment of the present disclosure further includes an inlet and an outlet, both of which penetrate the second substrate and the hydrophobic layer and are located on opposite sides of the plurality of micro-reaction chambers.

[0035] For example, an inspection chip according to one embodiment of the present disclosure further includes a bonding layer, the bonding layer being located between the first substrate and the second substrate, and the space surrounded by the bonding layer, the second substrate and the microcavity-defining layer is the containing chamber.

[0036] For example, in a test chip according to an embodiment of the present disclosure, the material of the bonding layer is a thermosetting adhesive or a photosensitive adhesive containing a spacer.

[0037] At least one embodiment of the present disclosure further provides a reaction system including a control device and a test chip described in any one of the embodiments of the present disclosure, wherein the control device is electrically connected to the test chip and configured to apply an electrical signal to the test chip.

[0038] At least one embodiment of the present disclosure further provides a method for using the test chip described in any one embodiment of the present disclosure, which includes introducing a reaction system solution into the multiple micro-reaction chambers and energizing the heating electrode to release heat. [Brief explanation of the drawings]

[0039] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. Needless to say, the drawings described below are only related to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0040] [Figure 1] FIG. 1 is a schematic block diagram of a test chip according to some embodiments of the present disclosure. [Figure 2] 1 is a schematic plan view of a test chip according to some embodiments of the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view of the test chip shown in FIG. 2 taken along line AA'. [Figure 4] FIG. 3 is a cross-sectional schematic view taken along line BB' of the test chip shown in FIG. [Figure 5] FIG. 2 is a schematic plan view of a heating electrode of a test chip according to some embodiments of the present disclosure. [Figure 6] FIG. 10 is a schematic plan view of a heating electrode of another test chip according to some embodiments of the present disclosure. [Figure 7A] FIG. 10 is a schematic plan view of a heating electrode of another test chip according to some embodiments of the present disclosure. [Figure 7B] FIG. 10 is a schematic plan view of a heating electrode of another test chip according to some embodiments of the present disclosure. [Figure 8A] FIG. 1 is a schematic diagram showing a surface hydrophilicity / hydrophobicity test performed on a microreaction chamber before surface modification according to an embodiment of the present disclosure. [Figure 8B] FIG. 1 is a schematic diagram showing a surface hydrophilicity / hydrophobicity test performed on a microreaction chamber after surface modification according to some embodiments of the present disclosure. [Figure 9] 10A and 10B are cross-sectional schematic diagrams of other test chips according to some embodiments of the present disclosure. [Figure 10]1 is a schematic diagram of a thermal effect simulation of a test chip according to some embodiments of the present disclosure; [Figure 11] 1 is a schematic plan view of a test chip according to some embodiments of the present disclosure. [Figure 12A] FIG. 12 is a schematic plan view of a heating electrode of the test chip shown in FIG. [Figure 12B] FIG. 12B is a cross-sectional view taken along the line CC' of the heating electrode shown in FIG. 12A. [Figure 12C] FIG. 10 is a schematic plan view of a heating electrode of another test chip according to some embodiments of the present disclosure. [Figure 13A] FIG. 1 is a plan view of a containing chamber of a test chip according to some embodiments of the present disclosure. [Figure 13B] FIG. 1 is a front view of a receiving chamber of a test chip according to some embodiments of the present disclosure. [Figure 14] FIG. 10 is a comparison diagram of simulations of remaining air amounts in test chips according to some embodiments of the present disclosure. [Figure 15] FIG. 1 is a schematic block diagram of a reaction system according to some embodiments of the present disclosure. [Figure 16] FIG. 1 is a flow diagram illustrating a method for using a test chip according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0041] In order to more clearly explain the objectives, technical solutions and advantages of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the described embodiments of the present disclosure, any other embodiments that a person skilled in the art can obtain without creative work are all within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, technical or scientific terms used in this disclosure should have their ordinary meanings as understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but merely distinguish between different components. Similarly, similar terms such as "one," "an," "the," and the like do not denote a quantity limitation, but rather indicate the presence of at least one. Similar terms such as "comprise" and "comprises" mean that the element or item listed before the term includes the element or item listed after the term and their equivalents, but do not exclude other elements or items. Similar terms such as "connected" and "connected to each other" are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," and "right" are merely used to indicate relative positions, and if the absolute position of the described object is changed, the relative positions may change accordingly.

[0043] During PCR, the double-stranded structure of the DNA segment is denatured to a single-stranded structure at high temperatures, and then the primers bind to the single strand according to the complementary base pairing rules at low temperatures. The bases then bind and elongate at the optimal temperature for the DNA polymerase. This process is called the denaturation-annealing-extension temperature cycling process. Through multiple denaturation-annealing-extension temperature cycling processes, the DNA segment can be replicated in large quantities.

[0044] To achieve the temperature cycling process, a series of external equipment is usually required to heat the test chip, which increases the equipment volume, complicates operation, and significantly increases costs. Conventional dPCR products often use silicon processing, which makes large-scale industrial production difficult, resulting in high test chip costs and complex processing. To increase integration, a temperature-control film layer (e.g., a heating electrode) may be integrated into the test chip. However, such test chips have problems such as poor thermal conductivity and uneven heat dissipation, resulting in a high temperature at the center and a low temperature at the edges. To position the microreaction chambers containing the reaction solution in a uniformly controlled temperature area, it is necessary to design large blank areas. These blank areas are low-temperature areas at the edges, which increases the size of the test chip, restricts the number of microreaction chamber arrays, and makes it difficult to achieve good temperature control.

[0045] In addition, since the test chip is usually micron-scale structure, the surface tension effect is significant during the introduction process, and residual air is obvious. During the temperature rise and fall process of the test chip, the residual air will cause disturbances in the reaction solution, which will interfere with the detection results and reduce the accuracy of the detection results.

[0046] At least one embodiment of the present disclosure provides a test chip, a method for using the same, and a reaction system. The test chip can achieve effective, precise, and uniform temperature control, improve temperature uniformity, reduce the area of ​​the edge cold zone, effectively reduce the chip size, increase the number of micro-reaction chambers, and be applied to semiconductor production lines to achieve large-scale standardized production. At least some embodiments of the test chip can achieve uniform introduction and reduce or avoid residual gas, thereby reducing or avoiding bubble interference with detection results.

[0047] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings, in which it should be noted that the same reference numerals in different drawings refer to the same elements described.

[0048] At least one embodiment of the present disclosure provides a test chip, the test chip including a first substrate, a microcavity-defining layer, and a heating electrode. The microcavity-defining layer is located on the first substrate and defines a plurality of microreaction chambers. The heating electrode is located on the first substrate and closer to the first substrate than the microcavity-defining layer, and is configured to release heat after energization. The heating electrode includes a plurality of sub-electrodes, and orthogonal projections of the plurality of microreaction chambers on the first substrate overlap with orthogonal projections of at least two of the sub-electrodes, and at least two of the plurality of sub-electrodes have different amounts of heat generation per unit time after energization.

[0049] 1 is a schematic block diagram of a test chip according to some embodiments of the present disclosure. For example, as shown in FIG. 1, the test chip 100 includes a first substrate 10, a microcavity-defining layer 11, and a heating electrode 12. The first substrate 10 serves functions such as protection and support, and may be, for example, a glass substrate. The microcavity-defining layer 11 is located on the first substrate 10 and defines a plurality of microreaction chambers 111. The heating electrode 12 is located on the first substrate 10 and is closer to the first substrate 10 than the microcavity-defining layer 11, and is configured to release heat after electricity is applied.

[0050] For example, the heating electrode 12 includes multiple sub-electrodes. Orthogonal projections of the multiple microreaction chambers 111 on the first substrate 10 overlap with orthogonal projections of at least two sub-electrodes on the first substrate 10. For example, at least two of the multiple sub-electrodes have different amounts of heat generated per unit time after being energized. Here, the amount of heat generated per unit time refers to the amount of heat emitted by the sub-electrode per unit time. The unit time may be 1 second, 10 seconds, 1 minute, 10 minutes, etc., and the embodiments of the present disclosure are not limited to this. For example, among the multiple sub-electrodes, there may be only two sub-electrodes with different amounts of heat generated per unit time, or there may be three or four sub-electrodes with different amounts of heat generated per unit time. The amounts of heat generated per unit time of all the sub-electrodes may be different, and the embodiments of the present disclosure are not limited to this.

[0051] For example, it is possible to vary the amount of heat generated by the sub-electrodes per unit time using a variety of methods. For example, in some examples, the resistance values ​​of the sub-electrodes may be varied to vary the amount of heat generated by the sub-electrodes per unit time when they receive the same electrical signal. In other examples, the electrical signals received by each sub-electrode may be varied to control each sub-electrode independently and vary the amount of heat generated by each sub-electrode per unit time. Of course, the embodiments of the present disclosure are not limited thereto, and other suitable methods may be used to vary the amount of heat generated by the sub-electrodes per unit time, which may be determined according to actual needs.

[0052] By varying the heat generation amount per unit time of the sub-electrodes, the temperature at different points on the test chip 100 can be adjusted, and effective, accurate and uniform temperature control can be achieved, improving the temperature uniformity, reducing the area of ​​the edge low temperature region, effectively reducing the chip size and increasing the number of micro-reaction chambers.

[0053] For example, the test chip 100 can be used to perform a polymerase chain reaction (e.g., digital polymerase chain reaction) and can also be used for post-reaction detection. For example, the micro-reaction chamber 111 is for containing a reaction solution, and the heating electrode 12, when energized, emits heat to heat the reaction solution in the micro-reaction chamber 111 and cause an amplification reaction.

[0054] Figure 2 is a schematic plan view of a test chip according to some embodiments of the present disclosure, Figure 3 is a schematic cross-sectional view of the test chip shown in Figure 2 taken along line AA', and Figure 4 is a schematic cross-sectional view of the test chip shown in Figure 2 taken along line BB'.

[0055] For example, as shown in FIGS. 2, 3, and 4, in the test chip 100, a microcavity-defining layer 11 is located on a first substrate 10 and defines a plurality of microreaction chambers 111. Adjacent microreaction chambers 111 are spaced apart (e.g., by partition walls) at least in part. Each of the plurality of microreaction chambers 111 includes, for example, a sidewall 111a and a bottom 111b. The microreaction chambers 111 provide a space for containing a reaction solution, and droplets of the reaction solution that enter the microcavity-defining layer 11 and move to the microreaction chambers 111 are relatively stably retained in the microreaction chambers 111. The microreaction chambers 111 may be, for example, microreaction grooves, depressions, etc., as long as they have a space for containing a reaction solution, and the embodiments of the present disclosure are not limited thereto. The depth of the microreaction grooves or depressions may be, for example, about 10 microns or any other suitable value.

[0056] For example, the shapes of the multiple microreaction chambers 111 may be the same, and the three-dimensional shape of each microreaction chamber 111 may be, for example, an approximately truncated cone, that is, as shown in Figures 3, 4 and the partially enlarged view N in Figure 2, the cross section in the direction perpendicular to the first substrate 10 is an approximately trapezoid, and the cross section in the plane parallel to the first substrate 10 is an approximately circular. Note that the shapes of at least some of the microreaction chambers 111 may not be the same.

[0057] In the embodiments of the present disclosure, the shape of the microreaction chambers 111 is not limited and may be designed according to actual needs. For example, the shape of each microreaction chamber 111 may be any suitable shape such as a cylinder, a rectangular parallelepiped, a polygonal prism, a sphere, an ellipsoid, etc. For example, the cross-sectional shape of the microreaction chambers 111 in a plane parallel to the first substrate 10 may be an ellipse, a triangle, a polygon, an irregular shape, etc., and the cross-sectional shape in a direction perpendicular to the first substrate 10 may be a square, a circle, a parallelogram, a rectangle, etc.

[0058] For example, as shown in FIG. 2, the micro-reaction chambers 111 are uniformly distributed on the first substrate 10. For example, the micro-reaction chambers 111 are arranged in an array on the first substrate 10. In this manner, when optical inspection is performed on the test chip 100 in a subsequent step, the fluorescent image obtained is regular and orderly, and detection results can be obtained quickly and accurately. Of course, the embodiments of the present disclosure are not limited thereto, and the micro-reaction chambers 111 may be distributed unevenly on the first substrate 10 or arranged in other manners, but the embodiments of the present disclosure are not limited thereto.

[0059] It should be noted that in the embodiments of the present disclosure, the size and number of the micro-reaction chambers 111 may be determined according to actual needs, and the size and number of the micro-reaction chambers 111 are related to the size of the test chip 100 and the first substrate 10. When the size of the micro-reaction chambers 111 remains the same, the larger the number of the micro-reaction chambers 111, the larger the size of the test chip 100 and the first substrate 10. For example, in the current manufacturing process, the number of micro-reaction chambers 111 can reach hundreds of thousands to millions in an area of ​​tens of square centimeters, and the test throughput of the test chip 100 is high.

[0060] The material of the microcavity defining layer 11 is, for example, photoresist, and may be, for example, a photoresist that can be processed into a thick film, such as a PS resist. The photoresist is formed on the first substrate 10 by spin coating, and has a large thickness. For example, the microcavity defining layer 11 may be patterned and etched to obtain a plurality of microreaction chambers 111, which are spaced apart from one another.

[0061] For example, as shown in FIGS. 2, 3, and 4, the heating electrode 12 is located on the first substrate 10, and the heating electrode 12 is closer to the first substrate 10 than the microcavity-defining layer 11. The heating electrode 12 is configured to allow a current to flow along a first direction after being energized, thereby releasing heat. For example, both ends of the heating electrode 12 along the first direction can receive an electric signal (e.g., a voltage signal or a current signal), thereby generating a current flowing in the heating electrode 12 along the first direction. When a current flows through the heating electrode 12, thermal energy is generated, and the thermal energy is conducted to at least some of the microreaction chambers 111 and used for the polymerase chain reaction.

[0062] In the embodiments of the present disclosure, the first direction is not limited to the direction shown in FIG. 2 and may be other directions. When the position of the heating electrode 12 receiving the electrical signal changes, the first direction changes accordingly, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto. The current flowing along the first direction means that the current flows approximately along the first direction, i.e., the actual flow direction of the current approximately coincides with the first direction, for example, the included angle between the actual flow direction of the current and the first direction is an acute angle.

[0063] For example, the heating electrode 12 can be manufactured using a conductive material with high resistivity, which generates a lot of heat when a small electrical signal is applied, thereby increasing the energy conversion rate. The heating electrode 12 can be manufactured using, for example, a transparent conductive material, such as indium tin oxide (ITO) or tin oxide. These transparent conductive materials not only have a higher resistivity than metallic materials but also have transparency, which allows for heating and subsequent optical inspection. Of course, embodiments of the present disclosure are not limited thereto, and the heating electrode 12 can be manufactured using other applicable materials, such as metals, and embodiments of the present disclosure are not limited thereto.

[0064] For example, the heating electrode 12 includes multiple sub-electrodes, such as sub-electrodes 121a, 121b, 122a, 122b, and 122c. These sub-electrodes are, for example, planar electrodes. The multiple sub-electrodes are spaced apart along a second direction, which is perpendicular to the first direction. In this example, the sub-electrodes 121a, 122a, 122b, 122c, and 121b are sequentially distributed in the second direction, with gaps between them. For example, the spacing between adjacent sub-electrodes is 1 to 200 microns, e.g., 1 to 20 microns, 1 to 15 microns, 1 to 10 microns, or 1 to 5 microns. Because the spacing between the sub-electrodes is smaller than the dimensions of the sub-electrodes themselves, the gaps between the sub-electrodes are indicated by black lines in FIG. 2. In this example, there are five sub-electrodes. In other examples, the number of sub-electrodes may be any number such as three, four, six, etc., and is not limited to five, as long as the number of sub-electrodes is three or more, and the embodiments of the present disclosure are not limited to this.

[0065] For example, the orthogonal projections of the multiple microreaction chambers 111 on the first substrate 10 overlap with the orthogonal projections of at least two sub-electrodes on the first substrate 10. Here, "orthogonal projection" refers to the projection on the first substrate 10 in a direction perpendicular to the first substrate 10. For example, in this example, the orthogonal projections of the multiple microreaction chambers 111 on the first substrate 10 overlap with the orthogonal projections of all of the sub-electrodes 121a, 121b, 122a, 122b, and 122c. Of course, the embodiments of the present disclosure are not limited thereto, and in other examples, the orthogonal projections of the multiple microreaction chambers 111 on the first substrate 10 overlap with the orthogonal projections of any two, any three, or any four of the sub-electrodes 121a, 121b, 122a, 122b, and 122c.

[0066] For example, each of the plurality of sub-electrodes has opposite sides facing in the second direction. For example, as shown in FIG. 2, the opposite sides are the left and right sides of each sub-electrode. The plurality of sub-electrodes include first sub-electrodes 121a and 121b and second sub-electrodes 122a, 122b, and 122c. The first sub-electrodes 121a and 121b have sub-electrodes adjacent to only one of the sides, and the second sub-electrodes 122a, 122b, and 122c have sub-electrodes adjacent to both of the sides.

[0067] For example, in this example, as shown in FIG. 2, the first sub-electrode 121a has an adjacent sub-electrode only on its right side, which is the second sub-electrode 122a. The first sub-electrode 121b has an adjacent sub-electrode only on its left side, which is the second sub-electrode 122c. The second sub-electrode 122a has adjacent sub-electrodes on both its left and right sides, which are the first sub-electrode 121a and the second sub-electrode 122b. The second sub-electrode 122b has adjacent sub-electrodes on both its left and right sides, which are the second sub-electrode 122a and the second sub-electrode 122c. The second sub-electrode 122c has adjacent sub-electrodes on both its left and right sides, which are the second sub-electrode 122b and the first sub-electrode 121b.

[0068] In the embodiment of the present disclosure, the terms "first sub-electrode" and "second sub-electrode" are used to distinguish sub-electrodes located at different positions. As shown in FIG. 2, the leftmost sub-electrode 121a and the rightmost sub-electrode 121b are referred to as the "first sub-electrode," and the other sub-electrodes 122a, 122b, and 122c are referred to as the "second sub-electrodes." That is, the sub-electrodes located on the outer side are referred to as the "first sub-electrode," and the sub-electrodes not located on the outer side are referred to as the "second sub-electrode." For example, the number of first sub-electrodes is two because, after multiple sub-electrodes are spaced apart, two sub-electrodes are located on the outer side, e.g., the leftmost and rightmost (when the first and second directions change, the outer orientation also changes accordingly). For example, the number of second sub-electrodes may be one or more. This may be determined according to actual needs, and the embodiment of the present disclosure is not limited thereto.

[0069] For example, the resistance value of the second sub electrode is greater than the resistance value of the first sub electrode. For example, the resistance value of any one of the second sub electrodes 122a, 122b, and 122c may be greater than the resistance value of any one of the first sub electrodes 121a and 121b. The resistance values ​​of the second sub electrodes 122a, 122b, and 122c may be equal or unequal, and the resistance values ​​of the first sub electrodes 121a and 121b may be equal or unequal. By making the resistance value of the second sub electrode greater than the resistance value of the first sub electrode, the amount of heat generated by the second sub electrode per unit time can be made different from the amount of heat generated by the first sub electrode per unit time. For example, the amount of heat generated by the second sub electrode per unit time can be made smaller than the amount of heat generated by the first sub electrode per unit time. In this case, the second sub electrode and the first sub electrode can receive the same electrical signal, for example.

[0070] For example, the width L2 of the second sub - electrode along the second direction is smaller than the width L1 of the first sub - electrode along the second direction. For example, in this example, as shown in FIG. 2, the widths of the second sub - electrodes 122a, 122b, and 122c along the second direction are all equal and are L2, the widths of the first sub - electrodes 121a and 121b along the second direction are all equal and are L1, and L2 < L1. By making the width of the second sub - electrode smaller than the width of the first sub - electrode, when the thickness of the film layer is made the same using the same material, the resistance value of the second sub - electrode can be made larger than the resistance value of the first sub - electrode. Thereby, the production process can be simplified and the production cost can be reduced.

[0071] Note that in the embodiments of the present disclosure, it is not limited to the above - mentioned method, and the resistance value of the second sub - electrode may be made larger than the resistance value of the first sub - electrode by other methods. For example, in some examples, by manufacturing the first sub - electrode and the second sub - electrode using conductive materials with different resistivity, the resistance value of the second sub - electrode can be made larger than the resistance value of the first sub - electrode. At this time, the widths, thicknesses, etc. of the first sub - electrode and the second sub - electrode may be the same. For example, in some other examples, after manufacturing the first sub - electrode and the second sub - electrode using the same conductive material (e.g., ITO), the second sub - electrode is processed by a material processing process (e.g., ion doping process) to increase the resistance value of the second sub - electrode. At this time, the widths, thicknesses, etc. of the first sub - electrode and the second sub - electrode may be the same. For example, in some other examples, the first sub - electrode and the second sub - electrode are arranged in different layers and manufactured with different parameters. For example, by using different materials and setting different widths and thicknesses, etc., the resistance value of the second sub - electrode can be made larger than the resistance value of the first sub - electrode. The specific implementation methods for making the resistance value of the second sub - electrode larger than the resistance value of the first sub - electrode are not limited to the methods described above, and any appropriate method may be used. The embodiments of the present disclosure do not limit this.

[0072] When an electrical signal is applied to the heating electrode 12, the first sub-electrodes 121a and 121b have a low resistance and can therefore emit more heat. This increases the amount of heat generated per unit time of the first sub-electrodes 121a and 121b, thereby reducing the edge heat dissipation effect and increasing the edge temperature of the heating electrode 12. The second sub-electrodes 122a, 122b, and 122c have a high resistance and can therefore emit less heat. This reduces the amount of heat generated per unit time of the second sub-electrodes 122a, 122b, and 122c, thereby preventing the center temperature of the heating electrode 12 from becoming too high. In this case, the electrical signals received by multiple sub-electrodes may be the same, reducing the number of signals.

[0073] As a result, the test chip 100 according to the embodiment of the present disclosure can achieve effective, accurate, and uniform temperature control, improve temperature uniformity, and solve the problem of a typical test chip having a high center temperature but a low edge temperature. This reduces the area of ​​the edge low-temperature region, effectively reducing the chip dimensions and increasing the number of microreaction chambers. Furthermore, the test chip 100 according to the embodiment of the present disclosure can allow multiple microreaction chambers 111 to receive uniform heat, which not only helps to improve the efficiency of the amplification reaction within the test chip 100 but also helps to improve the accuracy of the detection results. The test chip 100 can test nucleic acid molecules extracted from body fluids such as blood and urine with easier, more sensitive, and non-invasive methods, thereby realizing auxiliary medical treatments in fields such as single-cell analysis, early cancer diagnosis, and prenatal diagnosis.

[0074] FIG. 5 is a schematic plan view of a heating electrode of a test chip according to some embodiments of the present disclosure. For example, in some examples, as shown in FIG. 5, at least one second sub-electrode includes multiple second sub-electrodes, each of which is a second sub-electrode 122a, a second sub-electrode 122b, and a second sub-electrode 122c. The multiple second sub-electrodes 122a, a second sub-electrode 122b, and a second sub-electrode 122c are spaced apart along the second direction. In the second direction, extending from the center of the heating electrode 12 to the edge of the heating electrode 12, the resistance values ​​of the multiple second sub-electrodes gradually decrease. That is, the resistance value of the second sub-electrode 122b is greater than the resistance value of the second sub-electrode 122c, and the resistance value of the second sub-electrode 122b is greater than the resistance value of the second sub-electrode 122a. For example, as shown in FIG. 5, the resistance values ​​of the second sub-electrodes gradually decrease along the direction extending from the center of the heating electrode 12 to the left edge. Similarly, the resistance values ​​of the second sub-electrodes gradually decrease along the direction extending from the center of the heating electrode 12 to the right edge. The resistance value of the second sub-electrode (i.e., second sub-electrode 122b) located at the center of the heating electrode 12 is the largest. The resistance value of any one of the second sub-electrodes 122a, 122b, and 122c is greater than the resistance value of any one of the first sub-electrodes 121a and 121b.

[0075] For example, the widths of the multiple second sub-electrodes along the second direction increase sequentially from the center of the heating electrode 12 to the edge of the heating electrode 12. That is, the width L2b of the second sub-electrode 122b is smaller than the width L2c of the second sub-electrode 122c, and the width L2b of the second sub-electrode 122b is smaller than the width L2a of the second sub-electrode 122a. For example, the width L2a of the second sub-electrode 122a and the width L2c of the second sub-electrode 122c may be equal or unequal. For example, as shown in FIG. 5, the widths of the second sub-electrodes increase sequentially from the center of the heating electrode 12 to the left edge. Similarly, the widths of the second sub-electrodes increase sequentially from the center of the heating electrode 12 to the right edge. The width L2b of the second sub-electrode located at the center of the heating electrode 12 (i.e., the second sub-electrode 122b) is smallest. The width of any one of the second sub-electrodes 122a, 122b and 122c (i.e., any one of L2a, L2b and L2c) is smaller than the width of any one of the first sub-electrodes 121a and 121b (i.e., any one of L1a and L1b).

[0076] FIG. 6 is a schematic plan view of a heating electrode of another test chip according to some embodiments of the present disclosure. For example, in some examples, as shown in FIG. 6, at least one second sub-electrode includes a plurality of second sub-electrodes, each of which is second sub-electrode 122a, 122b, and 122c, and the plurality of second sub-electrodes 122a, 122b, and 122c are spaced apart along the second direction. For example, the resistances of the plurality of second sub-electrodes 122a, 122b, and 122c are essentially equal. Here, "essentially equal" means that the difference between any two of the resistances of second sub-electrode 122a, second sub-electrode 122b, and second sub-electrode 122c is smaller than a certain range, for example, less than 5% or 10%. Of course, "essentially equal" can also mean that the resistances of second sub-electrode 122a, second sub-electrode 122b, and second sub-electrode 122c are completely equal. For example, the resistance value of any one of the second sub-electrodes 122a, 122b, and 122c is greater than the resistance value of any one of the first sub-electrodes 121a and 121b.

[0077] For example, the widths of the second sub-electrodes 122a, 122b, and 122c in the second direction are essentially equal. That is, the width L2a of the second sub-electrode 122a, the width L2b of the second sub-electrode 122b, and the width L2c of the second sub-electrode 122c are essentially equal. Here, "essentially equal" means that the difference between any two of the widths L2a, L2b, and L2c is smaller than a certain range, for example, less than 5% or 10%. Of course, "essentially equal" also means that the widths L2a, L2b, and L2c are completely equal. For example, the width of any one of the second sub-electrodes 122a, 122b, and 122c (i.e., any one of L2a, L2b, and L2c) is smaller than the width of any one of the first sub-electrodes 121a and 121b (i.e., any one of L1a and L1b).

[0078] In addition, in the embodiments of the present disclosure, the magnitude relationship between the resistance values ​​of multiple second sub-electrodes and the magnitude relationship between the resistance values ​​of two first sub-electrodes can both be determined according to actual needs, and the embodiments of the present disclosure do not limit this, but simply ensure that the resistance value of any one of the second sub-electrodes is greater than the resistance value of any one of the first sub-electrodes.

[0079] For example, the cross-sectional shape of at least one of the multiple sub-electrodes is rectangular, trapezoidal, triangular, or wavy, and the cross-section is parallel to the first substrate 10. For example, in some examples, as shown in FIGS. 2, 5, and 6, the cross-sectional shape of each sub-electrode is rectangular, that is, a rectangular division design is adopted when patterning the heating electrode 12. For example, in other examples, as shown in FIG. 7A, the heating electrode 12 includes four sub-electrodes, each of which has a trapezoidal cross-sectional shape (e.g., a right-angled trapezoid), with the first sub-electrodes 121a and 121b having a large average width and the second sub-electrodes 122a and 122b having a small average width. For example, in other examples, as shown in FIG. 7B, the heating electrode 12 includes three sub-electrodes, each of which has a wavy cross-sectional shape, with the first sub-electrodes 121a and 121b having a large width and the second sub-electrode 122a having a small width.

[0080] In the embodiments of the present disclosure, the cross-sectional shape of the sub-electrodes is not limited and may be any regular or irregular shape, i.e., the heating electrode 12 may be patterned and divided in any suitable manner, which may be determined according to actual needs. The cross-sectional shapes of multiple sub-electrodes may be the same or different, and the embodiments of the present disclosure do not limit this. The dimensions of the sub-electrodes are also not limited and may be determined according to actual needs, for example, by the dimensions of the test chip.

[0081] For example, in some embodiments, as shown in Figures 2, 3 and 4, the test chip 100 further includes a control circuit layer 13 and a first insulating layer 14 integrated on the first substrate 10, and further includes a hydrophilic layer 15, a second insulating layer 16, at least one inlet 31 and at least one outlet 32.

[0082] For example, the control circuit layer 13 is provided on the first substrate 10. The control circuit layer 13 includes a control circuit 131, which is configured to apply an electric signal to the heating electrode 12 to energize the heating electrode 12. After the heating electrode 12 receives the electric signal, the electric signal generates heat to heat the microreaction chamber 111. For example, the control circuit 131 may include one or more components of a switch transistor, a conductive wire, an amplifier circuit, a processing circuit, or any other suitable circuit elements and structures, and the embodiments of the present disclosure are not limited thereto.

[0083] 3 and 4, the control circuit layer 13 (control circuit 131) is shown as multiple separate parts (e.g., multiple shaded block regions shown in the figures). However, this does not represent the actual structure of the control circuit layer 13, but merely indicates that the control circuit layer 13 can include multiple different circuit elements and structures. For example, the control circuit layer 13 may actually have a multi-layer structure, and the multi-layer structure may include switch transistors, conductive lines, resistors, capacitors, or other applicable circuit structures. This may be determined based on actual needs, and the embodiments of the present disclosure are not limited thereto. The control circuit layer 13 may be manufactured using any suitable material, such as metal, transparent conductive material, semiconductor material, or insulating material. The control circuit layer 13 and the control circuit 131 therein may be formed by forming a multi-layer structure using these materials through multiple processes.

[0084] The first insulating layer 14 is disposed on the first substrate 10 and covers the control circuit layer 13. The heating electrode 12 is disposed on the first insulating layer 14. The first insulating layer 14 includes via holes 141 penetrating the first insulating layer 14, and the control circuit 131 is electrically connected to the heating electrode 12 through the via holes 141. The shape of the via holes 141 may be cylindrical, truncated conical, or the like. For example, the specific location of the via holes 141 is not limited and may be determined by actual needs, such as the layout design of the control circuit 131. The first insulating layer 14 provides necessary insulation and isolation between the control circuit layer 13 and the heating electrode 12 and also provides a flat surface to facilitate mounting the heating electrode 12 on the first insulating layer 14. The first insulating layer 14 can be manufactured using an inorganic insulating material or an organic insulating material. For example, the material of the first insulating layer 14 is silica or silicon nitride, etc.

[0085] 2 and 4, the control circuit layer 13 further includes at least one connection electrode 132, which is not covered by the first insulating layer 14 and is exposed to air. The connection electrode 132 is electrically connected to a separately provided device to receive an electrical signal and transmit the electrical signal to the control circuit 131. For example, when the connection electrode 132 is made of a metal material, the connection electrode 132 can be subjected to a process such as electroplating, thermal spraying, or vacuum deposition plating to form a metal protective layer on the surface of the connection electrode 132, which prevents the connection electrode 132 from being oxidized and does not affect its conductive properties.

[0086] 2 , the control circuit layer 13 includes four connection electrodes 132. The leftmost connection electrode 132 and the rightmost connection electrode 132 are each connected to a conductor surrounding the heating electrode 12, and the conductor is electrically connected to one end of the heating electrode 12 through one or some via holes in the first insulating layer 14. The two intermediate connection electrodes 132 are electrically connected to the other end of the heating electrode 12 through one or some via holes in the first insulating layer 14. When an electrical signal is applied, a current flows in a first direction in the heating electrode 12.

[0087] For example, the connection electrode 132 may further include a contact portion 132a (e.g., a pad area as shown in FIG. 2), which is also not covered by the first insulating layer 14. For example, the contact portion 132a may be a large rectangular shape, so that it can contact and connect with a probe or electrode of a separately provided device, and the contact area is large, allowing for stable reception of electrical signals. This method enables plug-and-play operation of the test chip 100, making it easy to operate and convenient to use.

[0088] It should be noted that in the embodiments of the present disclosure, the number of connecting electrodes 132 is not limited and may be one or more, which may be determined according to actual needs, for example, the number of signals to be received and the reliability to be achieved.

[0089] For example, as shown in Figure 2, the test chip 100 includes a reaction region 21 and a peripheral region 22. The heating electrode 12 and the multiple micro-reaction chambers 111 are located in the reaction region 21, and the connecting electrode 132 is located in the peripheral region 22. For example, the reaction region 21 and the peripheral region 22 are complementary, and the peripheral region 22 is the region of the test chip 100 excluding the reaction region 21.

[0090] 3 and 4, the hydrophilic layer 15 covers at least each sidewall 111a and bottom 111b of the plurality of microreaction chambers 111, and the hydrophilic layer 15 has hydrophilic and lipophobic properties. For example, the hydrophilic layer 15 may cover the area between the plurality of microreaction chambers 111 in the microcavity-defined layer 11. The hydrophilic layer 15 is provided on the surface of the microreaction chambers 111 (i.e., the sidewall 111a and bottom 111b), thereby improving the hydrophilicity of the microreaction chambers 111. When no external driving force is applied to the reaction solution, the reaction solution automatically and gradually flows into each microreaction chamber 111 based on capillary action, thereby realizing automatic introduction and sample filling.

[0091] For example, the material of the hydrophilic layer 15 is silicon oxide or silicon oxynitride that has been surface-alkali-treated, and the silicon oxide is, for example, silica (SiO2). The surface alkali treatment refers to immersing the silicon oxide or silicon oxynitride in an alkaline solution to modify the surface and form the hydrophilic layer 15. For example, the alkaline solution used for the surface alkali treatment is a potassium hydroxide (KOH) solution, with a mass fraction of the potassium hydroxide solution being approximately 0.4%. For example, the silicon oxide or silicon oxynitride in the sidewalls 111a and bottom 111b of the microreaction chambers 111 is immersed in the potassium hydroxide solution for approximately 15 minutes, followed by washing, drying, and other operations to achieve modification and form the hydrophilic layer 15. The surface alkali treatment is simple, the reagents used are inexpensive and easily available, and no complicated external equipment is required, improving treatment efficiency.

[0092] In the embodiments of the present disclosure, the alkaline solution for the surface alkaline treatment is not limited to potassium hydroxide solution, and other suitable alkaline solutions may be used, and the concentration (e.g., mass fraction) of the alkaline solution is not limited and may be determined according to actual needs.

[0093] In the embodiments of the present disclosure, the hydrophilic layer 15 may be manufactured using other suitable inorganic or organic materials, and other suitable surface modification methods may be used, as long as the hydrophilic layer 15 is hydrophilic. For example, the hydrophilic layer 15 may be manufactured directly using a hydrophilic material. Alternatively, the hydrophilic layer 15 may be manufactured using a material that does not have hydrophilic properties. In this case, it is necessary to hydrophilize the surface of the hydrophilic layer 15 away from the microcavity-defining layer 11 by performing a hydrophilization treatment on the surface of the hydrophilic layer 15 away from the microcavity-defining layer 11. For example, if a non-hydrophilic material such as silicon nitride is used, it can be hydrophilized. For example, a gelation modification method, an ultraviolet radiation method, a plasma method, or the like can be selectively used to introduce hydrophilic groups into the surface of a non-hydrophilic material, thereby making it hydrophilic.

[0094] 8A is a schematic diagram showing a surface hydrophilicity test for a microreaction chamber before surface modification according to some embodiments of the present disclosure, and FIG. 8B is a schematic diagram showing a surface hydrophilicity test for a microreaction chamber after surface modification according to some embodiments of the present disclosure. Here, "microreaction chamber before surface modification" refers to a microreaction chamber when no hydrophilic layer is provided on the bottom and sidewall of the microreaction chamber, hereinafter referred to as the first microreaction chamber, and "microreaction chamber after surface modification" refers to a microreaction chamber when a hydrophilic layer is provided on the bottom and sidewall of the microreaction chamber, i.e., the microreaction chamber 111 in the test chip 100 according to the embodiments of the present disclosure, hereinafter referred to as the second microreaction chamber.

[0095] For example, in the test process shown in Figures 8A and 8B, deionized water is used as a test droplet to test the contact angle of the droplet on the surface (bottom or sidewall) of the microreaction chamber. As shown in Figure 8A, the volume of the first test droplet is 9.92 L, and for the first microreaction chamber, the left contact angle θ1 between the first test droplet and the surface of the first microreaction chamber is about 50.21°, and the right contact angle θ2 between the first test droplet and the surface of the first microreaction chamber is about 50.38°, so the average contact angle between the first test droplet and the surface of the first microreaction chamber is about 50.29°. 8B, the volume of the second test droplet is 3.19 L, and for the second micro-reaction chamber, the left contact angle θ3 between the second test droplet and the surface of the second micro-reaction chamber is about 13.50°, and the right contact angle θ4 between the second test droplet and the surface of the second micro-reaction chamber is about 12.57°, so that the average contact angle between the second test droplet and the surface of the second micro-reaction chamber is about 13.03°. Therefore, in some embodiments of the present disclosure, the hydrophilic layer 15 is provided on the surface of the micro-reaction chamber 111, which greatly improves hydrophilicity and reduces the contact angle between the droplet and the surface of the micro-reaction chamber 111.

[0096] For example, as shown in FIGS. 3 and 4, the second insulating layer 16 is disposed between the heating electrode 12 and the microcavity-defining layer 11. The second insulating layer 16 protects the heating electrode 12, provides insulation, prevents the heating electrode 12 from being corroded by liquid, reduces aging of the heating electrode 12, and can also perform a planarization function. For example, the second insulating layer 16 may be made of an inorganic insulating material or an organic insulating material. For example, the material of the second insulating layer 16 may be silica or silicon nitride, etc. For example, the material of the second insulating layer 16 may be the same as or different from the material of the first insulating layer 14.

[0097] For example, as shown in FIG. 2, the inlet 31 and outlet 32 ​​are located on opposite sides of the plurality of microreaction chambers 111, for example, on both sides of the plurality of microreaction chambers 111 along a first direction. For example, the inlet 31 is a passage through which the reaction solution can be injected, and the outlet 32 ​​is a passage through which the excess reaction solution can be discharged or the sample stock solution can be separated. For example, the reaction solution is injected into the inlet 31 by a microinjection pump or a pipette, and then enters each microreaction chamber 111 by self-priming. The reaction solution that has not entered the microreaction chambers 111 is discharged from the test chip 100 through the outlet 32. For example, the inlet 31 and the outlet 32 ​​are symmetrically distributed with respect to the central axis of the test chip 100, which makes the flow of the reaction solution within the test chip 100 more uniform and makes it easier for the reaction solution to enter each microreaction chamber 111.

[0098] 9 is a schematic cross-sectional view of another test chip according to some embodiments of the present disclosure. For example, as shown in FIG. 9, the test chip 100 according to this embodiment is basically the same as the test chip 100 shown in FIGS. 2, 3, and 4, except that it further includes a second substrate 17, a hydrophobic layer 18, and a binding layer 19.

[0099] In this embodiment, the second substrate 17 is disposed opposite the first substrate 10 and serves to protect, support, isolate, etc. There is a gap between the second substrate 17 and the first substrate 10. For example, the second substrate 17 may be a glass substrate.

[0100] Since the first substrate 10 and the second substrate 17 can both be glass substrates, and the microcavity defining layer 11 can be manufactured using photoresist, the test chip 100 can be manufactured using a microfabrication method for bonding a glass substrate with a semiconductor, which is applicable to semiconductor production lines, is simple to manufacture, has low production costs, and is useful for realizing large-scale standardized production.

[0101] In the embodiments of the present disclosure, the first substrate 10 and the second substrate 17 may further be other suitable substrates, and the embodiments of the present disclosure do not limit this. For example, the shapes of the first substrate 10 and the second substrate 17 may be rectangular or other suitable shapes, and the embodiments of the present disclosure do not limit this.

[0102] For example, the hydrophobic layer 18 covers the side of the second substrate 17 facing the first substrate 10. The hydrophobic layer 18 has hydrophobic and lipophilic properties, and by providing the hydrophobic layer 18, the reaction system solution can more easily enter each microreaction chamber 111. For example, the material of the hydrophobic layer 18 is silicon nitride that has been subjected to a plasma modification treatment. Of course, the embodiments of the present disclosure are not limited thereto. The hydrophobic layer 18 may be made of a resin or other suitable inorganic or organic material, as long as the side of the hydrophobic layer 18 facing the microcavity-defining layer 11 has hydrophobic properties. For example, the hydrophobic layer 18 may be directly manufactured using a hydrophobic material. Alternatively, for example, the hydrophobic layer 18 may be manufactured using a material that does not have hydrophobic properties. In this case, the hydrophobic layer 18 needs to be made hydrophobic by performing a hydrophobic treatment on the surface of the hydrophobic layer 18 facing the microcavity-defining layer 11.

[0103] In the embodiment of the present disclosure, the hydrophilic layer 15 and the hydrophobic layer 18 cooperate to adjust the surface contact angle of the droplet of the reaction solution, thereby realizing self-priming and oil sealing in the test chip 100. For example, in the test chip 100, the hydrophobic layer 18 improves the hydrophobic performance of the outer surface of the micro-reaction chamber 111, and the inner surface of the micro-reaction chamber 111 has good hydrophilicity, so that the reaction solution can infiltrate from the outside of the micro-reaction chamber 111 into the inside of the micro-reaction chamber 111. Therefore, the cooperative action of the hydrophilic layer 15 and the hydrophobic layer 18 makes it easier for the reaction solution to enter each micro-reaction chamber 111.

[0104] For example, the inlet 31 and outlet 32 ​​both penetrate the second substrate 17 and the hydrophobic layer 18 (not shown in FIG. 9 ) to facilitate the inflow and outflow of liquid into the test chip 100. For example, the inlet 31 and outlet 32 ​​may be formed by laser drilling.

[0105] For example, the bonding layer 19 is located between the first substrate 10 and the second substrate 17, for example, on the edge of the test chip 100. The bonding layer 19 connects the first substrate 10 and the second substrate 17 to form a box and maintains the distance between the first substrate 10 and the second substrate 17. For example, the material of the bonding layer 19 is a thermosetting adhesive or a photosensitive adhesive containing a spacer. For example, when a thermosetting adhesive is used, the thickness of the film layer formed on the thermosetting adhesive is 50-500 microns. When a photosensitive adhesive containing a spacer is used, the dimension of the spacer is 50-500 microns (when the spacer is spherical, the diameter of the spacer is 50-500 microns). For example, the photosensitive adhesive may be an ultraviolet (UV) curable propylene resin. The spacer may be spherical, cylindrical, or elliptical in shape. In this case, the spacer is mixed uniformly in a photosensitive adhesive, and then hardened and sealed to form a cassette from the first substrate 10 and the second substrate 17.

[0106] For example, the space surrounded by the bonding layer 19, the second substrate 17, and the microcavity-defining layer 11 is a storage chamber. For example, by designing the distribution position and shape of the bonding layer 19, a storage chamber of a desired shape can be formed simultaneously when the first substrate 10 and the second substrate 17 are combined into a cassette. The top surface of the storage chamber is, for example, defined by the second substrate 17, the bottom surface of the storage chamber is, for example, defined by the microcavity-defining layer 11, and the side surface of the storage chamber is, for example, defined by the bonding layer 19. For example, the storage chamber is an empty chamber of the test chip 100. During use of the test chip 100, the storage chamber is filled with a continuous phase (e.g., mineral oil), and the reaction system solution enters each microreaction chamber 111 as a discrete phase. The storage chamber will be described in detail below, but this detailed description will be omitted here.

[0107] For example, bonding layer 19 may be fabricated by any suitable process to cassette first substrate 10 and second substrate 17 to form a containment chamber of a desired shape.

[0108] For example, in some cases, the manufacturing process for the bonding layer 19 is as follows: UV adhesive doped with spacers (e.g., 100 microns in diameter) is placed in a dispenser. After parameters such as the packaging geometry and application speed are set, the adhesive is applied to the first substrate 10 (which at this time already has various film layers formed on it, such as the control circuit layer 13, heating electrode 12, and microcavity definition layer 11, which are not described here one by one). After application is complete, the second substrate 17 is moved by a chuck (which at this time has a hydrophobic layer 18 formed on the second substrate 17). After alignment, the first substrate 10 is bonded to the second substrate 17, and then immediately irradiated with UV light to harden the UV adhesive.

[0109] For example, in some other examples, the manufacturing process of the bonding layer 19 is as follows: A thermosetting adhesive film material approximately 100 microns thick is die-cut or laser-cut into the desired shape (e.g., the shape of the receiving chamber). After peeling off the hard release film, the thermosetting adhesive film is bonded to the second substrate 17 (at this time, the second substrate 17 has a hydrophobic layer 18 formed thereon) using a clipper. The thermosetting adhesive film is heated to 120°C, making the thermosetting adhesive film viscous and bonding it to the second substrate 17. After cooling, the soft release film is removed and peeled off. The first substrate 10 (at this time, the first substrate 10 has various film layers formed thereon, such as the control circuit layer 13, the heating electrode 12, and the microcavity-defining layer 11, which are not described here one by one) is aligned, and the heating process is repeated to form the first substrate 10 and the second substrate 17 into a cassette using the thermosetting adhesive film material.

[0110] For example, in some embodiments, as shown in FIG. 9 , the test chip 100 may further include a temperature sensor 20. The temperature sensor 20 is disposed on the side of the first substrate 10 away from the microcavity-defining layer 11 and is configured to sense the temperature of the reaction region 21 of the test chip 100, thereby achieving a more accurate temperature control process. The temperature sensor 20 may be any type of temperature sensor, and the embodiments of the present disclosure are not limited thereto. Of course, the test chip 100 may omit the temperature sensor 20, and a temperature sensor may be provided by appropriate control or mounting equipment during use, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0111] 10 is a schematic diagram of a thermal effect simulation of a test chip according to some embodiments of the present disclosure. For example, the test chip 100 is the test chip shown in FIG. 2, where the width ratio between the first sub-electrode and the second sub-electrode is 1.25:1. As shown in FIG. 10, the temperature distribution in the reaction region 21 of the test chip 100 is uniform not only in the first direction but also in the second direction. The good temperature uniformity in the reaction region 21 of the test chip 100 allows for effective, precise, and uniform temperature control, which reduces the area of ​​the edge low-temperature region, effectively reduces the chip size, and increases the number of micro-reaction chambers.

[0112] Fig. 11 is a schematic plan view of a test chip according to some examples of the present disclosure, and Fig. 12A is a schematic plan view of a heating electrode of the test chip shown in Fig. 11. For example, as shown in Fig. 11 and Fig. 12A, the test chip 100 according to this example is basically the same as the test chip 100 shown in Figs. 2 to 4, except for the arrangement of the heating electrode 12 and the connection electrode.

[0113] For example, in this embodiment, the heating electrode 12 includes multiple sub-electrodes, such as sub-electrodes 123, 124, and 125. The orthogonal projections of the multiple sub-electrodes 123, 124, and 125 on the first substrate 10 overlap in order. The orthogonal projections of the sub-electrodes other than the sub-electrode located at the center of the heating electrode 12 are ring-shaped. That is, the orthogonal projection of the sub-electrode 124 surrounds the orthogonal projection of the sub-electrode 123, and the orthogonal projection of the sub-electrode 125 surrounds the orthogonal projection of the sub-electrode 124. The orthogonal projections of the other sub-electrodes (i.e., sub-electrodes 124 and 125) other than the sub-electrode 123 located at the center of the heating electrode 12 are ring-shaped. The orthogonal projection of the sub-electrode 123 forms a solid pattern. For example, there may be a gap between the orthogonal projections of the sub-electrodes 123, 124, and 125, and the gap may be, for example, 25 microns or more. Furthermore, the size of the gap may be determined according to actual needs, for example, the size of the gap may be 0, that is, there may be no gap between the orthogonal projections of the sub-electrodes 123, 124, and 125, and the embodiments of the present disclosure do not limit this.

[0114] For example, the sub-electrodes 123, 124, and 125 are insulated from one another. For example, the sub-electrodes 123, 124, and 125 may be insulated from one another by being provided on different layers. For example, the sub-electrodes 123, 124, and 125 may be insulated from one another by being provided on the same layer and maintaining a certain gap between them.

[0115] Because the sub-electrodes 123, 124, and 125 are insulated from one another, different electrical signals can be provided to the sub-electrodes 123, 124, and 125, respectively, to cause the sub-electrodes 123, 124, and 125 to generate different amounts of heat per unit time. For example, in some cases, providing a large electrical signal (e.g., a high voltage value) to the sub-electrode 125 can cause the sub-electrode 125 to emit more heat, increasing the amount of heat generated per unit time, reducing the edge heat dissipation effect, and increasing the edge temperature of the heating electrode 12. On the other hand, providing a small electrical signal (e.g., a low voltage value) to the sub-electrode 123 can cause the sub-electrode 123 to emit less heat, reducing the amount of heat generated per unit time, and preventing the center temperature of the heating electrode 12 from becoming too high. For example, the magnitude of the electrical signal provided to the sub-electrode 124 can be between the above two.

[0116] As a result, the test chip 100 according to the embodiment of the present disclosure can achieve effective, accurate, and uniform temperature control, improving temperature uniformity and solving the problem of a typical test chip having a high center temperature but a low edge temperature, thereby reducing the area of ​​the low-temperature region at the edge, effectively reducing the chip dimensions, and increasing the number of microreaction chambers. Furthermore, the test chip 100 according to the embodiment of the present disclosure can ensure that the multiple microreaction chambers 111 are uniformly heated, which not only improves the efficiency of the amplification reaction of the test chip 100 but also helps to increase the accuracy of the detection results. The test chip 100 can more easily, sensitively, and non-invasively test nucleic acid molecules extracted from body fluids such as blood and urine, thereby realizing auxiliary medical treatments in fields such as single-cell analysis, early cancer diagnosis, and prenatal diagnosis.

[0117] Fig. 12B is a schematic cross-sectional view of the heating electrode 12 taken along line CC' in Fig. 12A. Note that Fig. 12B only shows the cross section of the heating electrode 12, but does not show other structures in the test chip 100.

[0118] 12B, in some cases, the sub-electrodes 123, 124, and 125 are located in different layers. For example, the sub-electrodes 123, 124, and 125 are located in three different film layers. An interlayer insulating layer 126 is provided between the sub-electrodes 123 and 124 and between the sub-electrodes 124 and 125, and the interlayer insulating layer 126 insulates the sub-electrodes 123, 124, and 125 from each other. The interlayer insulating layer 126 can be made of, for example, an inorganic insulating material or an organic insulating material.

[0119] In this example, the heating electrode 12 has a multi-layer structure, and a multi-layer ITO film is formed by processes such as sputtering, etching, and deposition to obtain the heating electrode 12 having sub-electrodes 123, 124, and 125. The sub-electrodes 123, 124, and 125 are located on different layers and are insulated from each other by the interlayer insulating layer 126, so there is no need for gaps between the orthogonal projections of the sub-electrodes 123, 124, and 125 on the first substrate 10, which reduces the difficulty of the process.

[0120] In the embodiments of the present disclosure, the sub-electrodes may be located on different layers or on the same layer, depending on actual needs, and the embodiments of the present disclosure are not limited thereto. For example, in another example, the sub-electrodes 123, 124, and 125 may be located on the same layer, with gaps provided to maintain insulation between the sub-electrodes 123, 124, and 125. In this case, the heating electrode 12 has a single-layer structure, reducing the thickness of the chip and making it lighter. For example, when the sub-electrodes 123, 124, and 125 are located on different layers, the specific order of the layers is not limited.

[0121] For example, the cross-sectional shape of at least one of the plurality of sub-electrodes is a square ring, a circular ring, or an elliptical ring, and the cross-section is parallel to the first substrate 10. For example, in some examples, as shown in Figure 12A, the cross-sectional shapes of the sub-electrodes 124 and 125 are square rings, and the cross-sectional shape of the sub-electrode 123 is correspondingly rectangular or square. For example, in other examples, as shown in Figure 12C, the cross-sectional shapes of the sub-electrodes 124 and 125 are circular rings, and the cross-sectional shape of the sub-electrode 123 is correspondingly circular.

[0122] For example, by coordinating the cross-sectional shape of the sub-electrode with the shape of the array formed by the multiple microreaction chambers 111, it is possible to improve the temperature uniformity of the region in the microreaction chamber 111. For example, when the heating electrode 12 has the shape shown in FIG. 12A, the multiple microreaction chambers 111 can form, for example, a rectangular array. When the heating electrode 12 has the shape shown in FIG. 12C, the multiple microreaction chambers 111 can form, for example, a circular array.

[0123] It should be noted that in this embodiment, the number of sub-electrodes may be determined according to actual needs, for example, two, three, four, or other numbers, as long as the number of sub-electrodes is ensured to be two or more, and the embodiments of the present disclosure are not limited thereto.

[0124] 11 and 12A, in the test chip 100, the control circuit layer 13 includes a plurality of connection electrodes, such as connection electrodes 134a, 134b, 135a, 135b, 136a, and 136b. These connection electrodes are divided into a plurality of sets. For example, the connection electrodes 134a and 134b form a first set, the connection electrodes 135a and 135b form a second set, and the connection electrodes 136a and 136b form a third set, with each set including two connection electrodes.

[0125] The multiple sets of connection electrodes correspond one-to-one to the multiple sub-electrodes, and each set of connection electrodes is configured by the control circuit 131 to transmit an electrical signal to the corresponding sub-electrode. For example, the number of sets of connection electrodes is equal to the number of sub-electrodes. For example, the first set of connection electrodes 134a, 134b corresponds to the sub-electrode 125 and is configured by the control circuit 131 to transmit a first electrical signal to the sub-electrode 125. The second set of connection electrodes 135a, 135b corresponds to the sub-electrode 123 and is configured by the control circuit 131 to transmit a second electrical signal to the sub-electrode 123. The third set of connection electrodes 136a, 136b corresponds to the sub-electrode 124 and is configured by the control circuit 131 to transmit a third electrical signal to the sub-electrode 124. Note that, here, conductors 137 in the control circuit 131 are used to indicate the electrical connection relationship between the connection electrodes and the corresponding sub-electrodes. This does not represent the actual connection structure between the connection electrodes and the corresponding sub-electrodes, but is merely a schematic representation.

[0126] For example, the electrical signals transmitted by the multiple sets of connecting electrodes may be different from one another. That is, the first, second, and third electrical signals may be different from one another. For example, by providing independent first, second, and third electrical signals to the multiple sets of connecting electrodes, the heating power of each sub-electrode may be independently controlled, and the amount of heat generated by each sub-electrode per unit time may be different. For example, in some cases, a large first electrical signal (e.g., a high voltage) may cause the sub-electrode 125 to emit more heat, resulting in a large amount of heat generated per unit time, thereby reducing the edge heat dissipation effect and increasing the edge temperature of the heating electrode 12. For example, a small second electrical signal (e.g., a low voltage) may cause the sub-electrode 123 to emit less heat, resulting in a small amount of heat generated per unit time, preventing the center temperature of the heating electrode 12 from becoming too high. For example, the third electrical signal may be smaller than the first electrical signal and larger than the second electrical signal.

[0127] The fact that the electrical signals transferred by the plurality of sets of connection electrodes are different from one another does not mean that the electrical signals transferred by the plurality of sets of connection electrodes are not the same, i.e., that these electrical signals are different from one another at each time, but that these electrical signals are different at at least one time. For example, at some times, the electrical signals transferred by the plurality of sets of connection electrodes may be similar, for example, at the initial time when the test chip 100 is used, the electrical signals transferred by the plurality of sets of connection electrodes may be similar, and at this time, the electrical signals are large so that the test chip 100 heats up quickly.

[0128] For example, for the same set of connection electrodes, two connection electrodes are respectively located on opposite sides of the testing chip 100. For example, connection electrode 134a of the first set of connection electrodes, connection electrode 135a of the second set of connection electrodes, and connection electrode 136a of the third set of connection electrodes are located on one side of the testing chip 100, and connection electrode 134b of the first set of connection electrodes, connection electrode 135b of the second set of connection electrodes, and connection electrode 136b of the third set of connection electrodes are located on the other side of the testing chip 100. This allows a uniform current to flow through each sub-electrode.

[0129] The number of connection electrodes in each set of connection electrodes is not limited, and may be two, three, four, or any other number, and may be determined according to actual needs. The installation positions of the connection electrodes in each set of connection electrodes are also not limited, and may be determined according to actual needs.

[0130] For example, when using the test chip 100, a temperature measurement device (e.g., an infrared thermometer) is used to monitor and measure the front image of the test chip 100 in real time to obtain real-time temperature information. For example, as shown in FIG. 12A, temperature information T1, T2, and T3 at locations Q1, Q2, and Q3 are detected and stored, where the temperature information T1, T2, and T3 reflect the real-time temperatures of the sub-electrodes 125, 124, and 123, respectively. Then, a PID (Proportion Integral Differential) algorithm is used to determine the signal power provided to the first set of connecting electrodes 134a and 134b, the third set of connecting electrodes 136a and 136b, and the second set of connecting electrodes 135a and 135b, respectively, based on the differences between T1, T2, and T3 and the first target temperature. A multiple detection-calculation cycle is performed until each temperature reaches the first target temperature. Each temperature is then maintained until the first-stage reaction in the test chip 100 is completed.

[0131] When the temperature of the test chip 100 needs to be reduced to the second target temperature, the power is turned off and a separate cooling unit (e.g., a fan) is activated to cool the back of the test chip 100, while the infrared thermometer continues to monitor the temperature to obtain real-time temperature information. When the temperature of the test chip 100 is reduced to near the second target temperature, the signal power provided to the first set of connecting electrodes 134a and 134b, the third set of connecting electrodes 136a and 136b, and the second set of connecting electrodes 135a and 135b is determined by a PID algorithm based on the differences between T1, T2, and T3 and the second target temperature. Each temperature is then maintained until the second-stage reaction in the test chip 100 is completed.

[0132] For other structures and components of the test chip 100 of this embodiment, reference can be made to the test chip 100 shown in FIGS. 2 to 4, and detailed descriptions of similar structures will be omitted here.

[0133] 13A is a plan view of a receiving chamber of a test chip according to some embodiments of the present disclosure, and FIG. 13B is a front view of the receiving chamber of a test chip according to some embodiments of the present disclosure. Note that because the receiving chamber is a cavity within the test chip, in order to embody the shape of the receiving chamber, FIGS. 13A and 13B omit other structures surrounding the receiving chamber in the test chip, but mainly show the outer shape of the receiving chamber.

[0134] For example, in some embodiments, as shown in Figures 13A and 13B, the test chip 100 further includes a storage chamber 21. For example, the storage chamber 21 is a cavity in the test chip 100, and the multiple microreaction chambers 111 are located within the storage chamber 21. During use of the test chip 100, a liquid fills the storage chamber 21, for example, as a continuous phase (e.g., mineral oil), and the reaction system solution enters each microreaction chamber 111 as a discrete phase. For example, the storage chamber 21 is a space surrounded by the binding layer 19, the second substrate 17, and the microcavity-defining layer 11. For example, the binding layer 19 surrounds the periphery of the array of the multiple microreaction chambers 111, thereby allowing the multiple microreaction chambers 111 to be located within the storage chamber 21.

[0135] For example, the microcavity-defining layer 11 further includes an inlet channel 112a and an outlet channel 112b, both of which are connected to the receiving chamber 21. For example, the inlet channel 112a is further connected to the inlet 31, allowing liquid to flow from the inlet 31 through the inlet channel 112a into the receiving chamber 21. For example, the outlet channel 112b is further connected to the outlet 32, allowing liquid to flow from the receiving chamber 21 through the outlet channel 112b and the outlet 32 ​​and out of the test chip 100. For example, the shapes of the inlet channel 112a and the outlet channel 112b may be any shape, such as a straight shape, a bent shape, or a curved shape, which may be determined according to actual needs and is not limited thereto by the embodiments of the present disclosure. For example, the length of the inlet channel 112a may be 1000-10000 microns, and the length of the outlet channel 112b may be 1000-10000 microns, and the lengths of the inlet channel 112a and the outlet channel 112b may be equal or unequal. In another example, the inlet channel 112a and the outlet channel 112b may be omitted, and the inlet 31 and the outlet 32 ​​may be directly provided at the boundary of the containing chamber 21.

[0136] 13A and 13B, for example, the accommodating chamber 21 has an arc-shaped boundary Cur, which is a curved surface, and the curved surface is not only curved along a locus in a plane parallel to the first substrate 10, but also along a locus in a plane perpendicular to the first substrate 10. For example, the arc-shaped boundary Cur includes a first arc-shaped boundary Cur1 and a second arc-shaped boundary Cur2. The first arc-shaped boundary Cur1 and the second arc-shaped boundary Cur2 are located on opposite sides of the accommodating chamber 21. For example, the arc-shaped boundary Cur of the accommodating chamber 21 is located at a connection point between the accommodating chamber 21 and the inlet channel 112a and the outlet channel 112b. For example, in this example, the inlet channel 112a and the outlet channel 112b are located on opposite sides of the storage chamber 21, with the inlet channel 112a communicating with the storage chamber 21 at a first arc-shaped boundary Cur1, and the outlet channel 112b communicating with the storage chamber 21 at a second arc-shaped boundary Cur2.

[0137] For example, the arc degree of the arc-shaped boundary Cur is π / 2 or less, i.e., the circular angle corresponding to the arc-shaped boundary Cur is 90° or less. For example, the arc degrees of the first arc-shaped boundary Cur1 and the second arc-shaped boundary Cur2 are both π / 2 or less, and the arc degrees of the first arc-shaped boundary Cur1 and the second arc-shaped boundary Cur2 may be equal to or unequal to each other.

[0138] In addition, in the embodiments of the present disclosure, the arc-shaped boundary Cur is a curved surface, and the curved surface may have a curved trajectory only in a plane parallel to the first substrate 10, or may have a curved trajectory only in a plane perpendicular to the first substrate 10, or may have a curved trajectory in both a plane parallel to the first substrate 10 and a plane perpendicular to the first substrate 10, and the embodiments of the present disclosure are not limited to this.

[0139] In the test chip 100 according to the embodiment of the present disclosure, an arc-shaped boundary Cur is provided to achieve uniform introduction, effectively preventing air from entering the containing chamber 21 and creating bubbles, and reducing or avoiding residual gas, thereby reducing or avoiding interference with the detection results of bubbles.

[0140] FIG. 14 is a comparison diagram of the residual air volume in a test chip according to some embodiments of the present disclosure. As shown in FIG. 14, in a typical test chip 01, the containing chamber is generally cuboidal, i.e., the containing chamber does not have an arc-shaped boundary. After liquid is injected, air bubbles are likely to form in the containing chamber of the test chip 01, with the residual air volume being, for example, 1.71%. These air bubbles, for example, gather at the corners of the containing chamber, interfering with the detection results. However, in the test chip 100 according to the embodiments of the present disclosure, the containing chamber 21 is configured to have an arc-shaped boundary Cur, thereby preventing the formation of air bubbles and, for example, reducing the residual air volume to zero. Therefore, the test chip 100 according to the embodiments of the present disclosure effectively prevents air from entering the containing chamber 21, reducing or avoiding residual gas, thereby reducing or avoiding interference with the detection results due to air bubbles.

[0141] It should be noted that in the embodiments of the present disclosure, the test chip 100 may further include more or fewer components, but is not limited to the components described above, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0142] The following is a schematic description of a manufacturing process flow for the test chip 100 according to some embodiments of the present disclosure. For example, the test chip 100 can be manufactured by processes such as sputtering, plasma enhanced chemical vapor deposition (PECVD), reactive ion etching (RIE etch), and photolithography in a semiconductor production line.

[0143] First, the first substrate 10 (e.g., a glass substrate) is cleaned. For example, the thickness of the first substrate 10 is 500 microns. Next, a metal material is deposited on the first substrate 10 at 240°C to form the control circuit layer 13. For example, the material of the control circuit layer 13 is an integrated structure of molybdenum-neodymium aluminum alloy-molybdenum (Mo-AlNd-Mo), and the thicknesses of each single layer are 200 Å, 3000 Å, and 800 Å, respectively.

[0144] Then, a first insulating layer 14 is deposited at 200° C. The material of the first insulating layer 14 is silica, and the thickness is 3000 Å or 4000 Å. Subsequently, a via hole 141 is formed in the first insulating layer 14 by an etching process. For example, in the etching process, the process parameters may be set to be 150mt / 800w / 400, O2 / 10s, 60mt / 800w / 200, CF4 / 50, O2 / 200s, 130mt / 800w / 400, O2 / 40, CF4 / 30s, and 60mt / 800w / 200, CF4 / 50, O2 / 160s, in this order.

[0145] Next, the heating electrode 12 is formed by deposition. The material of the heating electrode 12 may be ITO, and the thickness may be 560 Å, 900 Å, or 1800 Å. The heating electrode 12 may be, for example, the heating electrode shown in FIG. 2 , and the heating electrode 12 may include multiple sub-electrodes, for example, a first sub-electrode and a second sub-electrode, and the width of the second sub-electrode is smaller than the width of the first sub-electrode so that the resistance value of the second sub-electrode is greater than the resistance value of the first sub-electrode. For example, in another example, the heating electrode 12 shown in FIG. 12A may be formed by a similar process.

[0146] Thereafter, a second insulating layer 16 is formed by deposition. The material of the second insulating layer 16 is silicon nitride, and the thickness is 3000 Å or 4000 Å. Alternatively, the second insulating layer 16 may be an integrated structure of silica and silicon nitride, where the thickness of the silica is 1000 Å and the thickness of the silicon nitride is 2000 Å.

[0147] Next, the microcavity defining layer 11 is formed. A PS adhesive is coated using a spin coating process, with process parameters of 30 Kpa / 300 rpm*10 s, followed by pre-baking at 90°C for 120 s. After repeating the spin coating and pre-baking steps twice, exposure is performed, development is performed for 100 s, and then post-baking is performed at 230°C for 30 minutes. This forms the microcavity defining layer 11 with a plurality of micro-reaction chambers 111.

[0148] Then, a hydrophilic layer 15 is formed. A silica layer is deposited at 200°C to a thickness of 3000 Å. PR adhesive is coated, aligned, exposed, and developed to expose the micro-reaction chamber 111. The exposed micro-reaction chamber 111 is immersed in a potassium hydroxide (KOH) solution with a mass fraction of about 0.4% for about 15 minutes to modify the silica covering the sidewalls 111a and bottom 111b of the micro-reaction chamber 111, thereby obtaining the hydrophilic layer 15.

[0149] Next, a hydrophobic layer 18 is formed on the second substrate 17. Silicon nitride is spin-coated, and the process parameters are 300 rpm*10 s, pre-baking is performed at 90°C for 120 s, and post-baking is performed at 230°C for 30 minutes. A surface modification treatment is performed using a plasma modification method to modify the silicon nitride, thereby forming the hydrophobic layer 18.

[0150] Finally, the second substrate 17 and the first substrate 10 are bonded together in a bonding process to form a cassette structure having a receiving chamber 21, thereby obtaining the test chip 100. For example, the second substrate 17 and the first substrate 10 are bonded together using a thermosetting adhesive or a photosensitive adhesive including a spacer. The specific bonding method can be found in the previous section, and a detailed description thereof will be omitted here.

[0151] It should be noted that in the embodiments of the present disclosure, the manufacturing process flow of the test chip 100 may further include more steps and operations, and the order of execution of each step is not limited and may be determined according to actual needs.

[0152] At least one embodiment of the present disclosure further provides a reaction system, which includes a control device and the test chip described in any one of the embodiments of the present disclosure. The reaction system can achieve effective, precise, and uniform temperature control, improve temperature uniformity, reduce the area of ​​the edge cold region of the test chip, effectively reduce the chip size, increase the number of micro-reaction chambers, and the test chip can be applied to semiconductor production lines to achieve large-scale standardized production. The reaction system according to at least some embodiments can achieve uniform introduction and reduce or avoid residual gas, thereby reducing or avoiding interference with the detection results of gas bubbles.

[0153] FIG. 15 is a schematic block diagram of a reaction system according to some embodiments of the present disclosure. For example, as shown in FIG. 15, the reaction system 200 includes a control device 210 and a test chip 220. The control device 210 is electrically connected to the test chip 220 and configured to apply an electrical signal to the test chip 220. For example, the test chip 220 may be a test chip according to any one of the embodiments of the present disclosure, such as the test chip 100 described above. For example, the multiple reaction chambers of the test chip 220 may contain a reaction solution. The control device 210 applies an electrical signal to the connection electrodes of the test chip 220, which is transferred to a control circuit of the test chip 220. The control circuit then applies the electrical signal to the heating electrodes of the test chip 220, causing the heating electrodes to release heat and controlling the temperature of the reaction region of the test chip 220. The reaction solution contained in the multiple reaction chambers of the test chip 220 undergoes an amplification reaction at an appropriate temperature.

[0154] For example, the control device 210 may be implemented as general or dedicated hardware, software, firmware, etc., and may further include, for example, a central processing unit (CPU), an embedded processing unit, a programmable logic controller (PLC), etc., although embodiments of the present disclosure are not limited thereto.

[0155] In addition, in the embodiments of the present disclosure, the reaction system 200 may include more components, such as a temperature sensor, an optical unit, a cooling unit, a communication unit, a power supply, etc., but the embodiments of the present disclosure are not limited thereto. For a detailed description and technical effects of the reaction system 200, please refer to the description of the test chip 100 above, and therefore a detailed description will be omitted here.

[0156] At least one embodiment of the present disclosure further provides a method for using a test chip, which can be used to operate the test chip according to any embodiment of the present disclosure. This method can achieve effective, precise, and uniform temperature control, improve temperature uniformity, reduce the area of ​​the edge cold region of the test chip, effectively reduce the chip size, and increase the number of micro-reaction chambers. The method of use according to at least some embodiments can achieve uniform inflow and reduce or avoid residual gas, thereby reducing or avoiding interference with gas bubble detection results.

[0157] 16 is a flow diagram of a method for using a test chip according to some embodiments of the present disclosure. For example, as shown in FIG. 16, the method for using the test chip includes the following steps: Step S310 of introducing the reaction system solution into the plurality of micro-reaction chambers 111; and step S320 of energizing the heating electrode 12 to release heat.

[0158] For example, in step S310, the reaction system solution is injected into the inlet 31 by a microinjection pump or pipette and then self-primes into each micro-reaction chamber 111. For example, in step S320, the heating electrode 12 is energized to emit heat. In some cases, the resistance of the second sub-electrode in the heating electrode 12 is greater than that of the first sub-electrode, so the second sub-electrode emits less heat and the first sub-electrode emits more. In other cases, the heating electrode 12 includes multiple sub-electrodes, each of which can be independently controlled, so the middle sub-electrodes emit less heat and the edge sub-electrodes emit more heat. This reduces the edge heat dissipation effect, increases the edge temperature of the heating electrode 12, and prevents the center temperature of the heating electrode 12 from becoming too high. This achieves effective, precise, and uniform temperature control, improves temperature uniformity, reduces the area of ​​the low-temperature area at the edge, effectively reduces the chip size, and increases the number of micro-reaction chambers. The multiple micro-reaction chambers 111 can receive uniform heat, which helps to improve the accuracy of the detection results.

[0159] In addition, in the embodiments of the present disclosure, the above-mentioned method of use may further include more steps and operations, and the order of execution of each step is not limited and may be determined according to actual needs. For a detailed description and technical effects of the method of use, please refer to the description of the test chip 100 above, and therefore a detailed description will be omitted here.

[0160] The following should be explained: (1) The drawings relating to the embodiments of the present disclosure only relate to the structures of the embodiments of the present disclosure, and other structures may refer to conventional designs. (2) Unless there is a conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0161] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and should be in accordance with the scope of protection of the claims. [Explanation of symbols]

[0162] 10 First board 11 Microcavity Limited Layer 12 Heating electrode 13 Control circuit layer 14 First insulating layer 15 Hydrophilic layer 16 Second insulating layer 17 Second board 18 Hydrophobic layer 19 Connecting layer 20 Temperature Sensor 21 Reaction area, containment chamber 22 Surrounding Areas 31 Introduction 32 Outlet 100 test chips 111 Microreaction Room 111a side wall 111b bottom 112a Inflow Channel 112b Outflow Channel 121a, 121b First sub-electrodes 122a, 122b, 122c Second sub-electrodes 123 Sub-electrode 124 Sub-electrode 125 sub-electrodes 126 Interlayer insulation layer 131 Control circuit 132 connecting electrode 132a Contact part 134a, 134b First set of connecting electrodes 135a, 135b Second set of connecting electrodes 136a, 136b Third pair of connecting electrodes 137 Conductor 141 Beer Hall

Claims

1. a first substrate; a microcavity defining layer located on the first substrate and defining a plurality of microreaction chambers; a heating electrode located on the first substrate and closer to the first substrate than the microcavity-defining layer, the heating electrode configured to emit heat after being energized, the heating electrode includes a plurality of sub-electrodes, wherein orthogonal projections of the plurality of microreaction chambers on the first substrate overlap with orthogonal projections of at least two of the sub-electrodes on the first substrate, and at least two of the plurality of sub-electrodes have different amounts of heat generation per unit time after being energized; the test chip further includes a control circuit layer and a first insulating layer stacked on the first substrate; the control circuit layer includes a control circuit, and the control circuit layer further includes a plurality of connection electrodes; At least one connection electrode among the plurality of connection electrodes is not covered by the first insulating layer and is exposed to air, orthogonal projections of the plurality of sub-electrodes on the first substrate overlap in order, and the plurality of connection electrodes are divided into a plurality of sets of connection electrodes excluding the at least one connection electrode of the first insulating layer; The plurality of sets of connection electrodes correspond one-to-one to the plurality of sub-electrodes, and each set of connection electrodes is configured to transfer an electrical signal to the corresponding sub-electrode by the control circuit; The electrical signals transferred by the plurality of sets of connection electrodes are different from one another, The test chip, wherein each set of connection electrodes includes two connection electrodes, the two connection electrodes being located on opposite sides of the test chip, respectively.

2. 10. The probe chip of claim 1, wherein the spacing distance between adjacent sub-electrodes is 1-200 microns.

3. 3. An inspection chip according to claim 1, wherein the orthogonal projections of the plurality of sub-electrodes on the first substrate overlap in order, the orthogonal projections of the sub-electrodes other than the sub-electrode located at the center of the heating electrode are ring-shaped, and the plurality of sub-electrodes are insulated from each other.

4. The probe chip according to claim 3 , wherein the plurality of sub-electrodes are located on different layers or on the same layer.

5. The probe chip according to claim 3 or 4, wherein a cross section of at least one of the plurality of sub-electrodes has a rectangular ring shape, a circular ring shape, or an elliptical ring shape, and the cross section is parallel to the first substrate.

6. The test chip according to claim 3 , wherein the number of the plurality of sub-electrodes is two or more.

7. The test chip according to claim 1 , wherein the material of the heating electrode is a transparent conductive material.

8. The test chip according to claim 1 , further comprising a holding chamber, wherein the plurality of micro-reaction chambers are located within the holding chamber, and the holding chamber has an arc-shaped boundary.

9. the microcavity defining layer further defines an inlet channel and an outlet channel, both of which communicate with the receiving chamber; The probe chip of claim 8 , wherein the arcuate boundary of the containing chamber is located where the containing chamber connects to the inlet channel and the outlet channel.

10. The test chip of claim 9 , wherein the arcuate boundary has a curvature of π / 2 or less.

11. the inlet channel and the outlet channel are located on opposite sides of the receiving chamber; 11. The test chip of claim 9 or claim 10, wherein the arcuate boundary includes a first arcuate boundary and a second arcuate boundary, the inlet channel communicates with the storage chamber at the first arcuate boundary, and the outlet channel communicates with the storage chamber at the second arcuate boundary.

12. 11. The probe chip of claim 9, wherein the length of the inlet channel is 1000-10000 microns, and the length of the outlet channel is 1000-10000 microns.

13. An inspection chip described in any one of claims 1 to 12, wherein the first insulating layer includes a via hole, the heating electrode is provided in the first insulating layer, the control circuit is electrically connected to the heating electrode by the via hole, and the control circuit is configured to apply an electrical signal to the heating electrode to energize the heating electrode.

14. further comprising a reaction region and a peripheral region; The test chip according to claim 1 , wherein the heating electrode and the plurality of microreaction chambers are located in the reaction region, and the connecting electrode is located in the peripheral region.

15. further comprising a hydrophilic layer and a second insulating layer; the hydrophilic layer covers at least the sidewalls and bottoms of each of the plurality of microreaction chambers; 15. The test chip according to claim 1, wherein the second insulating layer is provided between the heating electrode and the microcavity defining layer.

16. The probe chip according to claim 8 , further comprising a second substrate, the second substrate and the first substrate being provided opposite to each other.

17. The test chip of claim 16 , wherein the first substrate and the second substrate both comprise glass substrates.

18. further comprising a hydrophobic layer; 18. The test chip according to claim 16 or 17, wherein the hydrophobic layer covers the side of the second substrate facing the first substrate.

19. Further including an inlet and an outlet, The test chip according to claim 18 , wherein the inlet and outlet both penetrate the second substrate and the hydrophobic layer and are located on opposite sides of the plurality of micro-reaction chambers.

20. further comprising a tie layer; 18. The test chip according to claim 16 or 17, wherein the bonding layer is located between the first substrate and the second substrate, and the space surrounded by the bonding layer, the second substrate, and the microcavity defining layer is the containing chamber.

21. The test chip of claim 20 , wherein the material of the bonding layer is a thermosetting adhesive or a photosensitive adhesive containing a spacer.

22. A reaction system comprising a control device and the test chip according to any one of claims 1 to 21, The controller is electrically connected to the test tip and configured to apply an electrical signal to the test tip.

23. Allowing a reaction system solution to enter the plurality of microreaction chambers; energizing the heating electrode to release heat; A method for using the test chip according to any one of claims 1 to 21, comprising:

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