Semiconductor Devices

Abstract

This semiconductor equipment comprises: a first die pad that has a first main surface facing in a z-direction; a second die pad that is located apart from the first die pad and that has a second main surface facing in the z-direction; a first semiconductor element that is mounted on the first main surface; a second semiconductor element that is mounted on the second main surface; an insulating element that is mounted on the first main surface or on the second main surface and that is positioned between the first semiconductor element and the second semiconductor element in an x-direction and that relays signals while insulating these semiconductor elements from each other; and a wire that is joined to the first semiconductor element and to the first main surface. The first die pad comprises: a first joint part to which the wire is joined; and a first opening part that is located between the first joint part and the first semiconductor element in a y-direction and that has an opening end in the first main surface.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices equipped with isolation elements are used in inverter devices used in electric vehicles (including hybrid vehicles) and home appliances. The inverter device includes, for example, the semiconductor device and a power semiconductor such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device includes a control element, an isolation element, and a drive element. In the inverter device, a control signal output from an ECU (Engine Control Unit) is input to the control element of the semiconductor device. The control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits it to the drive element via the isolation element. The drive element switches the power semiconductor at desired timing based on the PWM control signal. By switching the six power semiconductors at desired timings, three-phase AC power for driving a motor is generated from DC power of an on-board battery. For example, Patent Document 1 discloses an example of a semiconductor device equipped with isolation elements.

[0003] In the semiconductor device disclosed in Patent Document 1, the control element, the insulating element, and the driving element are each mounted on a die pad. Some of the pads of the control element and the driving element are conductively connected to pad portions connected to the die pad by bonding wires. Depending on the semiconductor device, it may be impossible to arrange pad portions connected to the die pad, or it may be difficult to bond bonding wires to the pad portions due to the positional relationship between the pads of the control element and the driving element. In these cases, the bonding wires are directly bonded to the die pad. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-207714 Summary of the Invention [Problem to be solved by the invention]

[0005] Each element is bonded to the die pad by a bonding layer. During the manufacturing process, during the heat treatment to bond each element to the die pad, the molten material of the bonding layer may flow out and spread to the position where the bonding wire on the die pad is to be bonded. In this case, it becomes difficult to bond the bonding wire to the die pad.

[0006] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can prevent a bonding layer from interfering with bonding of a bonding wire. [Means for solving the problem]

[0007] The semiconductor device provided by the present disclosure comprises: a first die pad having a first main surface facing a thickness direction; a second die pad disposed apart from the first die pad in a first direction perpendicular to the thickness direction and having a second main surface facing the thickness direction; a first semiconductor element mounted on the first main surface; a second semiconductor element mounted on the second main surface; an insulating element mounted on the first main surface or the second main surface and positioned between the first semiconductor element and the second semiconductor element in the first direction, and insulating the first semiconductor element and the second semiconductor element from each other while relaying signals between the first semiconductor element and the second semiconductor element; a first wire bonded to the first semiconductor element and the first main surface; and a sealing resin covering the first semiconductor element, the second semiconductor element, and the insulating element. The first die pad is located on a first side of the first semiconductor element in a second direction perpendicular to the thickness direction and the first direction, and includes a first bonding portion to which the first wire is bonded, and a first opening portion disposed between the first bonding portion and the first semiconductor element in the second direction and having an opening end on the first main surface. [Effects of the Invention]

[0008] According to the above configuration, in the semiconductor device, it is possible to prevent the bonding layer from interfering with the bonding of the bonding wire.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device of FIG. 1, seen through the sealing resin. [Figure 3] FIG. 3 is a front view showing the semiconductor device of FIG. [Figure 4] FIG. 4 is a rear view showing the semiconductor device of FIG. [Figure 5] FIG. 5 is a left side view showing the semiconductor device of FIG. [Figure 6] FIG. 6 is a right side view showing the semiconductor device of FIG. [Figure 7] FIG. 7 is a partially enlarged view of FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a partially enlarged view of FIG. [Figure 12] FIG. 12 is a partially enlarged view of FIG. [Figure 13] 13A to 13C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 14] 14A to 14C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 15] FIG. 15 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 16] FIG. 16 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 17] FIG. 17 is a partially enlarged plan view showing the semiconductor device according to the third embodiment of the present disclosure, seen through the sealing resin. [Figure 18] FIG. 18 is a partially enlarged plan view showing the semiconductor device according to the fourth embodiment of the present disclosure, seen through the sealing resin. [Figure 19] FIG. 19 is a partially enlarged plan view showing the semiconductor device according to the fifth embodiment of the present disclosure, seen through the sealing resin. [Figure 20] FIG. 20 is a partially enlarged plan view showing the semiconductor device according to the sixth embodiment of the present disclosure, seen through the sealing resin. [Figure 21] FIG. 21 is a plan view showing a semiconductor device according to a seventh embodiment of the present disclosure, seen through a sealing resin. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0012] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Additionally, unless otherwise specified, "something A overlaps something B when viewed from a certain direction" includes "something A overlaps the entirety of something B" and "something A overlaps part of something B."

[0013] 1 to 12 show an example of a semiconductor device according to the first embodiment. The semiconductor device A10 of this embodiment includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a conductive support member 2, a plurality of wires 61 to 64, and a sealing resin 7. The conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of input terminals 51, a plurality of output terminals 52, a plurality of pad portions 53 and 55, a pair of connecting portions 54, and a pair of connecting portions 56. The semiconductor device A10 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The application and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is a small outline package (SOP). However, the package format of the semiconductor device A10 is not limited to an SOP.

[0014] FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. FIG. 3 is a front view showing the semiconductor device A10. FIG. 4 is a rear view showing the semiconductor device A10. FIG. 5 is a left side view showing the semiconductor device A10. FIG. 6 is a right side view showing the semiconductor device A10. FIG. 7 is a partial enlarged view of FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. FIG. 10 is a cross-sectional view taken along line XX in FIG. 2. FIG. 11 is a partial enlarged view of FIG. 9. FIG. 12 is a partial enlarged view of FIG. 10.

[0015] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For ease of explanation, the thickness direction (plan view) of the semiconductor device A10 is defined as the z direction, the direction along one side of the semiconductor device A10 perpendicular to the z direction (the left-right direction in FIGS. 1 and 2) is defined as the x direction, and the direction perpendicular to the z direction and the x direction (the up-down direction in FIGS. 1 and 2) is defined as the y direction. The x direction is an example of a "first direction," and the y direction is an example of a "second direction," but the present disclosure is not limited thereto. The shape and dimensions of the semiconductor device A10 are not limited thereto.

[0016] The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are elements that are the core of the function of the semiconductor device A10.

[0017] 2, the second semiconductor element 12 is mounted on a part of the conductive support member 2 (a second die pad 4 described later) and is disposed in the center of the semiconductor device A10 in the y direction, closer to the x1 side in the x direction. The second semiconductor element 12 has a rectangular shape that is long in the y direction when viewed in the z direction. The second semiconductor element 12 is a control element. The second semiconductor element 12 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the first semiconductor element 11, and a reception circuit that receives an electrical signal from the first semiconductor element 11.

[0018] 2, the first semiconductor element 11 is mounted on a part of the conductive support member 2 (first die pad 3 described below) and is disposed in the center of the semiconductor device A10 in the y direction, closer to the x2 side in the x direction. The first semiconductor element 11 has a rectangular shape that is long in the y direction when viewed in the z direction. The first semiconductor element 11 is a driving element. The first semiconductor element 11 has a receiving circuit that receives a PWM control signal transmitted from the second semiconductor element 12, a circuit (gate driver) that generates and outputs a driving signal for a switching element (such as an IGBT or MOSFET) based on the received PWM control signal, and a transmitting circuit that transmits an electrical signal to the second semiconductor element 12.

[0019] As shown in FIG. 2 , the insulating element 13 is mounted on a portion (first die pad 3) of the conductive support member 2 and is disposed at the center of the semiconductor device A10 in the y direction. The insulating element 13 is located on the x1 side of the first semiconductor element 11 in the x direction and on the x2 side of the second semiconductor element 12 in the x direction. That is, the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12 in the x direction. When viewed in the z direction, the insulating element 13 has a rectangular shape that is elongated in the y direction. The insulating element 13 is an element for transmitting PWM control signals and other electrical signals in an insulated state. The insulating element 13 receives a PWM control signal from the second semiconductor element 12 via the wire 63 and transmits the received PWM control signal to the first semiconductor element 11 via the wire 64 in an insulated state. The insulating element 13 also receives an electrical signal from the first semiconductor element 11 via the wire 64 and transmits the received electrical signal to the second semiconductor element 12 via the wire 63 in an insulated state. In other words, insulating element 13 relays signals between first semiconductor element 11 and second semiconductor element 12, while insulating first semiconductor element 11 and second semiconductor element 12 from each other.

[0020] In this embodiment, the insulating element 13 is an inductively coupled insulating element. An inductively coupled insulating element transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The insulating element 13 has a substrate made of Si, and an inductor made of Cu is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, and these inductors are stacked on top of each other in the thickness direction (z direction) of the insulating element 13. A dielectric layer made of SiO2 or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. In this embodiment, the insulating element 13 is of an inductive type, but the insulating element 13 may also be of a capacitive type. An example of a capacitive insulating element is a capacitor.

[0021] The second semiconductor element 12 transmits a PWM control signal to the first semiconductor element 11 via the insulating element 13. Note that the second semiconductor element 12 may transmit a signal other than the PWM control signal to the first semiconductor element 11. The first semiconductor element 11 transmits an electrical signal to the second semiconductor element 12 via the insulating element 13. Note that the information indicated by the electrical signal transmitted from the first semiconductor element 11 to the second semiconductor element 12 is not limited.

[0022] Motor driver circuits in inverter devices, such as those used in hybrid vehicles, typically use half-bridge circuits, in which low-side and high-side switching elements are connected in a totem-pole configuration. In an isolated gate driver, only one of the low-side or high-side switching elements is turned on at any given time. In the high-voltage region, the source of the low-side switching element and the reference potential of the isolated gate driver that drives the low-side switching element are connected to ground, so the gate-source voltage operates with respect to ground. Meanwhile, the source of the high-side switching element and the reference potential of the isolated gate driver that drives the high-side switching element are connected to the output node of the half-bridge circuit. The potential of the output node of the half-bridge circuit changes depending on whether the low-side or high-side switching element is on, which in turn changes the reference potential of the isolated gate driver that drives the high-side switching element. When the high-side switching element is on, the reference potential becomes a voltage equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). When the semiconductor device A10 is used as an isolated gate driver that drives a high-side switching element, the first semiconductor element 11 and the second semiconductor element 12 are grounded separately to ensure insulation, and therefore a voltage of 600 V or more is transiently applied to the first semiconductor element 11 compared to the ground of the second semiconductor element 12. Because a significant potential difference occurs between the first semiconductor element 11 and the second semiconductor element 12, in the semiconductor device A10, the input side circuit including the second semiconductor element 12 and the output side circuit including the first semiconductor element 11 are insulated by an insulating element 13. In other words, the insulating element 13 insulates the input side circuit, which has a relatively low potential, from the output side circuit, which has a relatively high potential.

[0023] A plurality of electrodes (not shown) are provided on the upper surface (surface facing the z1 side) of the first semiconductor element 11. Similarly, a plurality of electrodes (not shown) are provided on the upper surface (surface facing the z1 side) of the second semiconductor element 12. Furthermore, a plurality of electrodes (not shown) are provided on the upper surface (surface facing the z1 side) of the insulating element 13.

[0024] In the semiconductor device A10, the conductive support member 2 is a member that forms a conductive path between the first semiconductor element 11 and the second semiconductor element 12 and the wiring board of the inverter device. The conductive support member 2 is made of, for example, an alloy containing Cu. The conductive support member 2 is formed from a lead frame 81, which will be described later. The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are mounted on the conductive support member 2. As shown in FIG. 2 , the conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of input terminals 51, a plurality of output terminals 52, a plurality of pad portions 53 and 55, a pair of connecting portions 54, and a pair of connecting portions 56.

[0025] The first die pad 3 is disposed in the center of the semiconductor device A10 in the y direction, closer to the x2 side in the x direction. The second die pad 4 is disposed on the x1 side of the first die pad 3 in the x direction, spaced apart from the first die pad 3.

[0026] As shown in FIGS. 2 and 7 to 9, the first die pad 3 has a first semiconductor element 11 and an insulating element 13 mounted thereon. The first die pad 3 is electrically connected to the first semiconductor element 11 and is one element of the output circuit described above. The first die pad 3 has, for example, a rectangular (or substantially rectangular) shape when viewed in the z direction. The first die pad 3 has a first main surface 31 and a first back surface 32. The first main surface 31 and the first back surface 32 are spaced apart in the z direction as shown in FIGS. 8 and 9. The first main surface 31 faces the z1 side, and the first back surface 32 faces the z2 side. The first main surface 31 and the first back surface 32 are both flat (or substantially flat). As shown in FIGS. 8 and 9, the first semiconductor element 11 is bonded to the first main surface 31 of the first die pad 3 by a bonding layer 69. The bonding layer 69 is formed by solidifying a metal paste such as Ag paste. The bonding layer 69 is not limited to any particular material and may be solder, sintered metal, or insulating paste.

[0027] In this embodiment, the first die pad 3 includes a first bonding portion 33, a plurality of second bonding portions 34, a first opening 35, and a second opening 36. As shown in FIGS. 7, 9, and 11, the first bonding portion 33 is a portion to which a wire 62a (described later) is bonded, and is located on the y1 side of the first semiconductor element 11 in the y-direction. As shown in FIGS. 7 and 9, each of the second bonding portions 34 is a portion to which a plurality of wires 62b (described later) is bonded, and is located on the y2 side of the first semiconductor element 11 in the y-direction. The first main surface 31 of the first die pad 3 may be plated around the first bonding portion 33 and the second bonding portions 34. The plating layer formed by this plating process is made of a metal containing, for example, Ag. The plating layer enhances the bonding strength of the wires 62a and 62b while protecting the lead frame 81 (described later) from impacts during wire bonding of the wires 62a and 62b.

[0028] As shown in FIGS. 2, 7, 9, and 11, the first opening 35 is an opening having an open end in the first main surface 31. In this embodiment, the first opening 35 is a groove recessed from the first main surface 31 in the z direction. As shown in FIG. 7, the first opening 35 extends in the x direction. As viewed in the z direction, both ends of the first opening 35 in the x direction are located inside the outer edge of the first main surface 31. In other words, the first opening 35 does not extend to the outer edge of the first main surface 31. In this embodiment, the distance between each end of the first opening 35 in the x direction and the outer edge of the first main surface 31 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. In addition, in this embodiment, the x2-side end of the first opening 35 is located between the x2-side end face 11a of the first semiconductor element 11 and the x2-side outer edge 31a of the first main surface 31 in the x direction. The x1-side end of the first opening 35 is located between the x1-side end face 13a of the insulating element 13 and the x1-side outer edge 31b of the first main surface 31 in the x direction. That is, the first opening 35 overlaps the entire first semiconductor element 11 and the entire insulating element 13 when viewed in the y direction. As shown in FIGS. 7 and 11, the first opening 35 is located between the first bonding portion 33 and the first semiconductor element 11 in the y direction. In this embodiment, the first opening 35 is located closer to the first bonding portion 33 than the first semiconductor element 11. That is, in the y direction, the first distance W1 between the first opening 35 and the first semiconductor element 11 is greater than the second distance W2 between the first opening 35 and the first bonding portion 33. As shown in FIG. 11, the depth dimension (dimension in the z direction) D1 of the first opening 35 is approximately half the thickness dimension (dimension in the z direction) D2 of the first die pad 3. The width dimension (y-direction dimension) W3 of the first opening 35 is approximately the same as the depth dimension D1. In this embodiment, the thickness dimension D2 of the first die pad 3 is approximately 220 μm, and the depth dimension D1 and width dimension W3 of the first opening 35 are approximately 110 μm. If the width dimension W3 of the first opening 35 is too small, the effects described below are less likely to be achieved. On the other hand, if the width dimension W3 is too large, the area for bonding the wire 62a becomes narrow. Therefore, it is desirable that the width dimension W3 of the first opening 35 be 100 μm or more and 250 μm or less. The shape, arrangement position, and dimensions of the first opening 35 are not limited to those described above.

[0029] As shown in FIGS. 2, 7, and 9, the second opening 36 is an opening having an open end in the first main surface 31. In this embodiment, the second opening 36 is a groove recessed from the first main surface 31 in the z direction. As shown in FIG. 7, the second opening 36 extends in the x direction. As viewed in the z direction, both ends of the second opening 36 in the x direction are located inside the outer edge of the first main surface 31. In other words, the second opening 36 does not extend to the outer edge of the first main surface 31. In this embodiment, the distance between each end of the second opening 36 in the x direction and the outer edge of the first main surface 31 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. In addition, in this embodiment, the x2-side end of the second opening 36 is located between the x2-side end face 11a of the first semiconductor element 11 and the x2-side outer edge 31a of the first main surface 31 in the x direction. The x1-side end of the second opening 36 is located between the x1-side end face 13a of the insulating element 13 and the x1-side outer edge 31b of the first main surface 31 in the x direction. That is, the second opening 36 overlaps the entire first semiconductor element 11 and the entire insulating element 13 when viewed in the y direction. As shown in FIGS. 7 and 9 , the second opening 36 is located between the multiple second bonding portions 34 and the first semiconductor element 11 in the y direction. In this embodiment, the second opening 36 is located closer to each second bonding portion 34 than the first semiconductor element 11. That is, the distance between the second opening 36 and the first semiconductor element 11 in the y direction is greater than the distance between the second opening 36 and each second bonding portion 34 in the y direction. The depth dimension (dimension in the z direction) of the second opening 36 is approximately the same as the depth dimension D1 of the first opening 35 and is approximately half the thickness dimension D2 of the first die pad 3. The width dimension (dimension in the y direction) of second opening 36 is approximately the same as width dimension W3 of first opening 35. Note that the shape, arrangement position, and dimensions of second opening 36 are not limited to those described above.

[0030] As shown in FIGS. 2, 7, 8, and 10, the second die pad 4 has a second semiconductor element 12 mounted thereon. The second die pad 4 is electrically connected to the second semiconductor element 12 and is one element of the input circuit described above. The second die pad 4 has, for example, a rectangular (or substantially rectangular) shape when viewed in the z direction. The second die pad 4 has a second main surface 41 and a second back surface 42. The second main surface 41 and the second back surface 42 are spaced apart in the z direction as shown in FIGS. 8 and 10. The second main surface 41 faces the z1 side, and the second back surface 42 faces the z2 side. The second main surface 41 and the second back surface 42 are both flat (or substantially flat). The second semiconductor element 12 is bonded to the second main surface 41 of the second die pad 4 by a bonding layer 69 as shown in FIGS. 8 and 10.

[0031] In this embodiment, the second die pad 4 includes a third bonding portion 43, a fourth bonding portion 44, a third opening 45, and a fourth opening 46. As shown in FIGS. 10 and 12 , the third bonding portion 43 is a portion to which a wire 61a (described later) is bonded, and is located on the y1 side in the y direction with respect to the second semiconductor element 12. As shown in FIG. 10 , the fourth bonding portion 44 is a portion to which a wire 61b (described later) is bonded, and is located on the y2 side in the y direction with respect to the second semiconductor element 12. As with the second main surface 41, a plating layer (e.g., a metal containing Ag) may be formed on the second main surface 41 of the second die pad 4, including the periphery of the third bonding portion 43 and the periphery of the fourth bonding portion 44.

[0032] As shown in FIGS. 2, 7, 10, and 12, the third opening 45 is an opening having an open end in the second main surface 41. In this embodiment, the third opening 45 is a groove recessed from the second main surface 41 in the z direction. As shown in FIG. 7, the third opening 45 extends in the x direction. As viewed in the z direction, both ends of the third opening 45 in the x direction are located inside the outer edge of the second main surface 41. In other words, the third opening 45 does not extend to the outer edge of the second main surface 41. In this embodiment, the distance between each end of the third opening 45 in the x direction and the outer edge of the second main surface 41 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. In addition, in this embodiment, the x2-side end of the third opening 45 is located between the x2-side end face of the second semiconductor element 12 and the x2-side outer edge of the second main surface 41 in the x direction. The x1-side end of the third opening 45 is located between the x1-side end face of the second semiconductor element 12 and the x1-side outer edge of the second main surface 41 in the x direction. That is, the third opening 45 overlaps the entire second semiconductor element 12 when viewed in the y direction. As shown in FIGS. 7 and 12, the third opening 45 is located between the third bonding portion 43 and the second semiconductor element 12 in the y direction. In this embodiment, the third opening 45 is located closer to the third bonding portion 43 than the second semiconductor element 12. That is, in the y direction, the first distance W1' between the third opening 45 and the second semiconductor element 12 is greater than the second distance W2' between the third opening 45 and the third bonding portion 43. As shown in FIG. 12, the depth dimension (dimension in the z direction) D1' of the third opening 45 is approximately half the thickness dimension (dimension in the z direction) D2' of the second die pad 4. The width dimension (y-direction dimension) W3' of the third opening 45 is approximately the same as the depth dimension D1'. In this embodiment, the thickness dimension D2' of the second die pad 4 is approximately 220 μm, and the depth dimension D1' and width dimension W3' of the third opening 45 are approximately 110 μm. If the width dimension W3' of the third opening 45 is too small, the effects described below are difficult to achieve. On the other hand, if the width dimension W3' is too large, the area for bonding the wire 61a becomes narrow. Therefore, it is desirable that the width dimension W3' of the third opening 45 be 100 μm or more and 250 μm or less. The shape, arrangement position, and dimensions of the third opening 45 are not limited to those described above.

[0033] As shown in FIGS. 2, 7, and 10, the fourth opening 46 is an opening having an open end in the second main surface 41. In this embodiment, the fourth opening 46 is a groove recessed from the second main surface 41 in the z direction. As shown in FIG. 7, the fourth opening 46 extends in the x direction. As viewed in the z direction, both ends of the fourth opening 46 in the x direction are located inside the outer edge of the second main surface 41. In other words, the fourth opening 46 does not extend to the outer edge of the second main surface 41. In this embodiment, the distance between each end of the fourth opening 46 in the x direction and the outer edge of the second main surface 41 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. In addition, in this embodiment, the x2-side end of the fourth opening 46 is located between the x2-side end face of the second semiconductor element 12 and the x2-side outer edge of the second main surface 41 in the x direction. Furthermore, the x1-side end of the fourth opening 46 is located between the x1-side end face of the second semiconductor element 12 and the x1-side outer edge of the second main surface 41 in the x direction. That is, the fourth opening 46 overlaps the entire second semiconductor element 12 when viewed in the y direction. As shown in FIGS. 7 and 10 , the fourth opening 46 is located between the fourth bonding portion 44 and the second semiconductor element 12 in the y direction. In this embodiment, the fourth opening 46 is located closer to the fourth bonding portion 44 than the second semiconductor element 12. That is, the distance between the fourth opening 46 and the second semiconductor element 12 in the y direction is greater than the distance between the fourth opening 46 and the fourth bonding portion 44 in the y direction. The depth dimension (dimension in the z direction) of the fourth opening 46 is approximately the same as the depth dimension D1′ of the third opening 45 and is approximately half the thickness dimension D2′ of the second die pad 4. The width dimension (dimension in the y direction) of fourth opening 46 is approximately the same as width dimension W3' of third opening 45. Note that the shape, arrangement position, and dimensions of fourth opening 46 are not limited to those described above.

[0034] The input terminals 51 are bonded to a wiring board of an inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each input terminal 51 is electrically connected to the second semiconductor element 12 and is an element of the aforementioned input circuit. As shown in FIGS. 1, 2, and 5, the input terminals 51 are spaced apart from one another and arranged at equal intervals along the y direction. Each of the input terminals 51 is located on the x1 side of the second die pad 4 in the x direction and protrudes from the sealing resin 7 (a first side surface 73 described below) toward the x1 side in the x direction. The input terminals 51 include a power supply terminal to which a voltage is supplied, a ground terminal, an input terminal to which a control signal is input, an input terminal to which other electrical signals are input, and an output terminal to which other electrical signals are output. In this embodiment, the semiconductor device A10 has eight input terminals 51. The number of input terminals 51 is not limited. Furthermore, the signals input and output by each input terminal 51 are not limited.

[0035] Each input terminal 51 has a rectangular shape extending along the x direction and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 8 , the portion of the input terminal 51 exposed from the sealing resin 7 is bent into a gull-wing shape. The portion of the input terminal 51 exposed from the sealing resin 7 may be plated. The plating layer formed by the plating process is made of an alloy containing Sn, such as solder, and covers the portion exposed from the sealing resin 7. The plating layer improves solder adhesion to the exposed portion and prevents erosion of the exposed portion due to soldering when the semiconductor device A10 is surface-mounted on a wiring board of an inverter device by soldering. The multiple input terminals 51 include input terminal 51a and input terminal 51b. Of the multiple input terminals 51, input terminal 51a is located closest to the y1 side in the y direction. Of the multiple input terminals 51, input terminal 51b is located closest to the y2 side in the y direction.

[0036] The pads 53 are connected to the input terminals 51 other than the input terminals 51a and 51b on the x2 side in the x direction. The shape of each pad 53 as viewed in the z direction is not limited, but in this embodiment, it is a rectangle elongated in the y direction. The top surface (the surface facing the z1 side) of each pad 53 is flat (or substantially flat) and is bonded to a wire 61 (described later). The top surface of each pad 53 may be plated. A plating layer formed by this plating process is made of a metal containing Ag, for example, and covers the top surface of the pad 53. The plating layer enhances the bonding strength of the wire 61 while protecting a lead frame 81 (described later) from impacts during wire bonding of the wire 61. The entire surface of the pad 53 is covered with a sealing resin 7.

[0037] Each of the pair of connection portions 54 is connected to the input terminal 51a or the input terminal 51b and the second die pad 4. Each connection portion 54 includes a linking portion 541 and a coupling portion 543. The coupling portion 541 is connected to the y-direction end of the second die pad 4 and extends from the second die pad 4 in the y-direction. The coupling portion 543 is connected to the linking portion 541 and the x2 side of the input terminal 51a or the input terminal 51b in the x-direction. The coupling portion 543 has a rectangular (or approximately rectangular) shape when viewed in the z-direction, and includes a through-hole 543a that penetrates through the center in the z-direction. In this way, the input terminal 51a and the input terminal 51b are connected to the second die pad 4 via the pair of connection portions 54 and support the second die pad 4.

[0038] Like the input terminals 51, the output terminals 52 are bonded to the wiring board of the inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each output terminal 52 is electrically connected to the first semiconductor element 11 and is one element of the output circuit described above. As shown in FIGS. 1, 2, and 6, the output terminals 52 are spaced apart from one another and arranged at equal intervals along the y direction. Each output terminal 52 is located on the x2 side of the second die pad 4 in the x direction and protrudes from the sealing resin 7 (the second side surface 74 described below) toward the x2 side in the x direction. The output terminals 52 include a power supply terminal for supplying a voltage, a ground terminal, an output terminal for outputting a drive signal, an input terminal for inputting other electrical signals, and an output terminal for outputting other electrical signals. In this embodiment, the semiconductor device A10 has eight output terminals 52. The number of output terminals 52 is not limited. Furthermore, the signals input and output by each output terminal 52 are not limited.

[0039] Each output terminal 52 has a rectangular shape extending along the x direction and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 8 , the portion of the output terminal 52 exposed from the sealing resin 7 is bent into a gull-wing shape. As with the first semiconductor element 11, a plating layer (e.g., an alloy containing Sn, such as solder) may be formed on the portion of the output terminal 52 exposed from the sealing resin 7. The multiple output terminals 52 include output terminal 52a and output terminal 52b. Of the multiple output terminals 52, output terminal 52a is located closest to the y1 side in the y direction. Of the multiple output terminals 52, output terminal 52b is located closest to the y2 side in the y direction. The multiple output terminals 52 are an example of a "multiple terminals." The output terminals 52a and output terminal 52b are an example of a "pair of outer terminals."

[0040] The pads 55 are connected to the x1 side of the output terminals 52 other than the output terminals 52a and 52b in the x direction. The shape of each pad 55 as viewed in the z direction is not limited, but in this embodiment, it is a rectangle that is long in the y direction. The top surface of each pad 55 (the surface facing the z1 side) is flat (or approximately flat), and a wire 62 (described later) is bonded to it. The top surface of each pad 55 may be covered with a plating layer (e.g., a metal containing Ag), similar to the top surface of the pad 53. The pads 55 are entirely covered with a sealing resin 7.

[0041] Each of the pair of connection portions 56 is connected to the output terminal 52a or the output terminal 52b and the first die pad 3. Each connection portion 56 includes a first linking portion 561, a second linking portion 562, and a joining portion 563. The first linking portion 561 is connected to a position closer to the x2 side of the y-direction end of the first die pad 3 and extends in the y-direction from the first die pad 3 to the joining portion 563. The second linking portion 562 is connected to a position closer to the x1 side of the x-direction end of the first die pad 3. The second linking portion 562 includes a first portion 562a and a second portion 562b. The first portion 562a extends in the y-direction from the first die pad 3. The second portion 562b is connected to the first portion 562a and the joining portion 563 and extends in a direction oblique to the y-direction. The coupling portion 563 is connected to the first connecting portion 561 and the second connecting portion 562 and the x1 side of the output terminal 52a or the output terminal 52b in the x direction. The coupling portion 563 is rectangular (or approximately rectangular) when viewed in the z direction, and has a through-hole 563a that penetrates in the z direction at its center. In this way, the output terminal 52a and the output terminal 52b are connected to the first die pad 3 via the pair of connecting portions 56 and support the first die pad 3.

[0042] 2, the plurality of wires 61-64, together with the conductive support member 2, form a conductive path for the first semiconductor element 11 and the second semiconductor element 12 to perform predetermined functions. The material of each of the plurality of wires 61-64 is a metal containing, for example, Au, Cu, or Al.

[0043] As shown in FIGS. 2, 8, and 10, the multiple wires 61 form a conductive path between the second semiconductor element 12 and the multiple input terminals 51. The multiple wires 61 electrically connect the second semiconductor element 12 to at least one of the multiple input terminals 51. The multiple wires 61 are elements of the input circuit described above. As shown in FIG. 2, each of the multiple wires 61 is bonded to one of the electrodes of the second semiconductor element 12. The multiple wires 61 include wire 61a and wire 61b. As shown in FIGS. 10 and 12, wire 61a extends from the second semiconductor element 12 in the y-direction y1 and is bonded to a region of the second main surface 41 of the second die pad 4 on the y-direction y1 side of the third opening 45. The portion of the second main surface 41 to which wire 61a is bonded is the third bonding portion 43. Wire 61a is an example of a "third wire." As shown in FIG. 10 , the wire 61b extends from the second semiconductor element 12 toward the y2 side in the y-direction and is bonded to a region of the second main surface 41 of the second die pad 4 on the y2 side of the fourth opening 46 in the y-direction. The portion of the second main surface 41 to which the wire 61b is bonded is the fourth bonding portion 44. The wire 61b is an example of a "fourth wire." Note that the number of wires 61a and 61b is not limited. As shown in FIGS. 2 and 8 , the wires 61 other than the wires 61a and 61b each extend from the second semiconductor element 12 toward the x1 side in the x-direction and are bonded to one of the pad portions 53. Note that the number of wires 61 bonded to each pad portion 53 is not limited.

[0044] As shown in FIGS. 2, 8, and 9, the multiple wires 62 form a conductive path between the first semiconductor element 11 and the multiple output terminals 52. The multiple wires 62 electrically connect the first semiconductor element 11 to at least one of the multiple output terminals 52. The multiple wires 62 are elements of the output circuit described above. As shown in FIG. 2, each of the multiple wires 62 is bonded to one of the electrodes of the first semiconductor element 11. The multiple wires 62 include a wire 62a and multiple wires 62b. As shown in FIGS. 9 and 11, the wire 62a extends from the first semiconductor element 11 in the y-direction y1 and is bonded to a region of the first main surface 31 of the first die pad 3 on the y-direction y1 side of the first opening 35. The portion of the first main surface 31 to which the wire 62a is bonded is the first bonding portion 33. The wire 62a is an example of a "first wire." As shown in FIGS. 7 and 9, the multiple wires 62b each extend from the first semiconductor element 11 toward the y2-direction and are bonded to a region of the first main surface 31 of the first die pad 3 on the y2-direction side of the second opening 36. The portion of the first main surface 31 to which each wire 62b is bonded is the second bonding portion 34. Each of the multiple wires 62b is an example of a "second wire." The number of wires 62a and wires 62b is not limited. The wires 62 other than the wires 62a and 62b each extend from the first semiconductor element 11 toward the x2-direction and are bonded to one of the pad portions 55, as shown in FIGS. 2 and 8. The number of wires 62 bonded to each pad portion 55 is not limited.

[0045] 2 and 8, the plurality of wires 63 form a conductive path between the second semiconductor element 12 and the insulating element 13. The second semiconductor element 12 and the insulating element 13 are electrically connected to each other by the plurality of wires 63. The plurality of wires 63 is one element of the input side circuit described above. Each of the plurality of wires 63 is joined to one of the electrodes of the second semiconductor element 12 and one of the electrodes of the insulating element 13, as shown in FIG.

[0046] 2 and 8, the plurality of wires 64 form a conductive path between the first semiconductor element 11 and the insulating element 13. The first semiconductor element 11 and the insulating element 13 are electrically connected to each other by the plurality of wires 64. The plurality of wires 64 are one element of the output side circuit described above. Each of the plurality of wires 64 is joined to one of the electrodes of the first semiconductor element 11 and one of the electrodes of the insulating element 13, as shown in FIG.

[0047] As shown in FIG. 1 , the sealing resin 7 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 3, the second die pad 4, the pair of connecting portions 54, the pair of connecting portions 56, the plurality of pad portions 53 and 55, the plurality of wires 61 to 64, and a portion of each of the plurality of input terminals 51 and output terminals 52. The sealing resin 7 has electrical insulation properties. The sealing resin 7 is made of a material containing, for example, black epoxy resin. When viewed in the z direction, the sealing resin 7 has a rectangular shape that is elongated in the y direction. In this embodiment, the dimension of the sealing resin 7 in the x direction is approximately 700 to 800 μm, the dimension in the y direction is approximately 1000 to 1100 μm, and the dimension in the z direction is approximately 200 to 300 μm. Note that these dimensions are not limited.

[0048] As shown in FIGS. 3 to 6, the sealing resin 7 has a top surface 71, a bottom surface 72, a first side surface 73, a second side surface 74, a third side surface 75, and a fourth side surface .

[0049] The top surface 71 and the bottom surface 72 are located apart from each other in the z direction. The top surface 71 and the bottom surface 72 face opposite each other in the z direction. The top surface 71 is located on the z1 side in the z direction and faces the z1 side, just like the first main surface 31 of the first die pad 3. The bottom surface 72 is located on the z2 side in the z direction and faces the z2 side, just like the first back surface 32 of the first die pad 3. Each of the top surface 71 and the bottom surface 72 is flat (or approximately flat).

[0050] The first side surface 73, the second side surface 74, the third side surface 75, and the fourth side surface 76 are each connected to the top surface 71 and the bottom surface 72 and are sandwiched between the top surface 71 and the bottom surface 72 in the z direction. The first side surface 73 and the second side surface 74 are spaced apart from each other in the x direction. The first side surface 73 and the second side surface 74 face opposite each other in the x direction. The first side surface 73 is located on the x1 side in the x direction, and the second side surface 74 is located on the x2 side in the x direction. The third side surface 75 and the fourth side surface 76 are spaced apart from each other in the y direction and are connected to the first side surface 73 and the second side surface 74. The third side surface 75 and the fourth side surface 76 face opposite each other in the y direction. The third side surface 75 is located on the y2 side in the y direction, and the fourth side surface 76 is located on the y1 side in the y direction.

[0051] 1, a portion of each of the plurality of input terminals 51 protrudes from the first side surface 73. A portion of each of the plurality of output terminals 52 protrudes from the second side surface 74. The conductive support member 2 is not exposed from the third side surface 75 and the fourth side surface 76.

[0052] As shown in FIGS. 3 to 5 , the first side surface 73 includes a first region 731, a second region 732, and a third region 733. One end of the first region 731 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the third region 733. The first region 731 is inclined with respect to the top surface 71. One end of the second region 732 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the third region 733. The second region 732 is inclined with respect to the bottom surface 72. One end of the third region 733 in the z direction is connected to the first region 731, and the other end in the z direction is connected to the second region 732. The third region 733 extends in both the z direction and the y direction. When viewed in the z direction, the third region 733 is located outward from the top surface 71 and the bottom surface 72. From the third region 733, a portion of each of the input terminals 51 is exposed.

[0053] As shown in FIGS. 3, 4, and 6, the second side surface 74 includes a fourth region 741, a fifth region 742, and a sixth region 743. One end of the fourth region 741 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the sixth region 743. The fourth region 741 is inclined with respect to the top surface 71. One end of the fifth region 742 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the sixth region 743. The fifth region 742 is inclined with respect to the bottom surface 72. One end of the sixth region 743 in the z direction is connected to the fourth region 741, and the other end in the z direction is connected to the fifth region 742. The sixth region 743 extends in both the z direction and the y direction. When viewed in the z direction, the sixth region 743 is located outward from the top surface 71 and the bottom surface 72. From the sixth region 743, a portion of each of the plurality of output terminals 52 is exposed.

[0054] As shown in FIGS. 3, 5, and 6, the third side surface 75 includes a seventh region 751, an eighth region 752, and a ninth region 753. One end of the seventh region 751 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the ninth region 753. The seventh region 751 is inclined with respect to the top surface 71. One end of the eighth region 752 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the ninth region 753. The eighth region 752 is inclined with respect to the bottom surface 72. One end of the ninth region 753 in the z direction is connected to the seventh region 751, and the other end in the z direction is connected to the eighth region 752. The ninth region 753 extends along both the z direction and the y direction. When viewed in the z direction, the ninth region 753 is located outward from the top surface 71 and the bottom surface 72.

[0055] As shown in FIGS. 4 to 6 , the fourth side surface 76 includes a tenth region 761, an eleventh region 762, and a twelfth region 763. The tenth region 761 has one end in the z direction connected to the top surface 71 and the other end in the z direction connected to the twelfth region 763. The tenth region 761 is inclined with respect to the top surface 71. The eleventh region 762 has one end in the z direction connected to the bottom surface 72 and the other end in the z direction connected to the twelfth region 763. The eleventh region 762 is inclined with respect to the bottom surface 72. The twelfth region 763 has one end in the z direction connected to the tenth region 761 and the other end in the z direction connected to the eleventh region 762. The twelfth region 763 extends in both the z direction and the y direction. When viewed in the z direction, the twelfth region 763 is located outward from the top surface 71 and the bottom surface 72.

[0056] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to Figures 13 and 14. Figures 13 and 14 are plan views showing steps in the method for manufacturing the semiconductor device A10. Note that the x, y, and z directions shown in these figures are the same as those in Figures 1 to 12.

[0057] First, as shown in FIG. 13 , a lead frame 81 is prepared. The lead frame 81 is a plate-shaped material. In this embodiment, the base material of the lead frame 81 is Cu. The lead frame 81 may be formed by etching a metal plate or by punching a metal plate. In this embodiment, the lead frame 81 is formed by etching. The lead frame 81 has a main surface 81A and a back surface 81B spaced apart in the z direction. The lead frame 81 also includes an outer frame 811, a first die pad 812A, a second die pad 812B, a plurality of first leads 813, a plurality of second leads 814, a plurality of connection portions 815, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10. The first die pad 812A is a portion that will later become the first die pad 3. The second die pad 812B is a portion that will later become the second die pad 4. The plurality of first leads 813 are portions that will later become the plurality of input terminals 51 and pad portions 53. The plurality of second leads 814 are portions that will later become the plurality of output terminals 52 and pad portions 55. The plurality of connection portions 815 are portions that will later become the pair of connection portions 54 and the pair of connection portions 56. A first opening 35 and a second opening 36 are formed in the first die pad 812A. The first opening 35 and the second opening 36 are formed by half-etching. A third opening 45 and a fourth opening 46 are formed in the second die pad 812B. The third opening 45 and the fourth opening 46 are formed by half-etching. Note that the method of forming the first opening 35, the second opening 36, the third opening 45, and the fourth opening 46 (hereinafter, may be collectively referred to as "openings 35, 36, 45, 46") is not limited. Each of the openings 35, 36, 45, 46 may be formed by stamping, for example, so as to be recessed from the main surface 81A.

[0058] Next, as shown in FIG. 14 , the first semiconductor element 11 and the insulating element 13 are bonded to the first die pad 812A by the bonding layer 69, and the second semiconductor element 12 is bonded to the second die pad 812B by the bonding layer 69. In this bonding process, a paste-like bonding material, which is the bonding layer 69 before solidification, is first applied to the area of ​​the first die pad 812A where the first semiconductor element 11 and the insulating element 13 are to be disposed and to the area of ​​the second die pad 812B where the second semiconductor element 12 is to be disposed. Next, the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are placed on the applied bonding material. Next, a reflow process is performed to melt the bonding material and then solidify it. At this time, even if the molten bonding material flows out, the openings 35, 36, 45, and 46 prevent the bonding material from flowing outside.

[0059] Next, as shown in FIG. 14, each of the multiple wires 61 to 64 is formed by wire bonding. In the process of forming the wires 61 other than wires 61a and 61b, first, the capillary is lowered toward the second semiconductor element 12, and the tip of the wire is pressed against a predetermined electrode. At this time, the weight of the capillary and the action of ultrasonic waves emitted from the capillary cause the tip of the wire to be pressed against the electrode, thereby performing a first bond. Next, the capillary is raised while feeding out the wire, thereby forming a ball bond on the electrode. Next, the capillary is moved directly above one of the portions of the first lead 813 that will become pad portion 53, and the capillary is further lowered, thereby pressing the tip of the capillary against the bonding surface. As a result, the wire is sandwiched between the tip of the capillary and the bonding surface and is pressed against the bonding surface, thereby performing a second bond. Next, the capillary is raised, and the wire is cut.

[0060] In the process of forming wire 61a, first bonding is performed on the electrode of second semiconductor element 12, and second bonding is performed in the region between the end of second die pad 812B on the y1 side in the y direction and third opening 45. In the process of forming wire 61b, first bonding is performed on the electrode of second semiconductor element 12, and second bonding is performed in the region between the end of second die pad 812B on the y2 side in the y direction and fourth opening 46.

[0061] In the process of forming wires 62 other than wires 62a and 62b, first bonding is performed on the electrode of the first semiconductor element 11, and second bonding is performed on a portion of the second lead 814 that will become a pad portion 55. In the process of forming wire 62a, first bonding is performed on the electrode of the first semiconductor element 11, and second bonding is performed in a region between the end of first die pad 812A on the y1 side in the y-direction and first opening 35. In the process of forming each wire 62b, first bonding is performed on the electrode of the first semiconductor element 11, and second bonding is performed in a region between the end of first die pad 812A on the y2 side in the y-direction and second opening 36.

[0062] In the process of forming wire 63, first bonding is performed on the electrode of insulating element 13, and second bonding is performed on the electrode of second semiconductor element 12. In the process of forming wire 64, first bonding is performed on the electrode of insulating element 13, and second bonding is performed on the electrode of first semiconductor element 11. Note that the first bonding and second bonding of each of wires 61 to 64 may be reversed.

[0063] Next, the sealing resin 7 is formed. The sealing resin 7 is formed by transfer molding. In this process, the lead frame 81 is placed in a mold having multiple cavities. At this time, the portion of the lead frame 81 that is the conductive support member 2 covered by the sealing resin 7 in the semiconductor device A10 is placed in one of the multiple cavities. Then, fluidized resin is poured from the pot via a runner into each of the multiple cavities. After the fluidized sealing resin 7 solidifies in the multiple cavities, resin burrs located outside each of the multiple cavities are removed using high-pressure water or the like. This completes the formation of the sealing resin 7.

[0064] Thereafter, dicing is performed to separate the semiconductor device into individual pieces, thereby appropriately separating the first leads 813 and the second leads 814 that were connected to each other by the outer frame 811 and the dam bar 816. By going through the steps described above, the semiconductor device A10 is manufactured.

[0065] Next, the effects of the semiconductor device A10 will be described.

[0066] According to this embodiment, the first die pad 3 includes a first opening 35 disposed between the first bonding portion 33 and the first semiconductor element 11 in the y direction. Even if the molten bonding material flows out when bonding the first semiconductor element 11 and the insulating element 13 to the first die pad 812A during the manufacturing process, the first opening 35 can prevent the bonding material from flowing toward the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3 due to stress caused by heat generated from the first semiconductor element 11 and the insulating element 13, the first opening 35 can prevent the peeling from spreading to the first bonding portion 33.

[0067] Furthermore, according to this embodiment, the first die pad 3 includes second openings 36 disposed between the plurality of second bonding portions 34 and the first semiconductor element 11 in the y direction. Even if the molten bonding material flows out when bonding the first semiconductor element 11 and the insulating element 13 to the first die pad 812A during the manufacturing process, the second openings 36 can prevent the bonding material from flowing toward the plurality of second bonding portions 34. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wires 62b. Furthermore, even if the sealing resin 7 peels off from the first die pad 3 due to stress caused by heat generated from the first semiconductor element 11 and the insulating element 13, the second openings 36 can prevent the peeling from spreading to the plurality of second bonding portions 34.

[0068] Furthermore, according to this embodiment, the second die pad 4 includes a third opening 45 disposed between the third bonding portion 43 and the second semiconductor element 12 in the y direction. Even if the molten bonding material flows out when bonding the second semiconductor element 12 to the second die pad 812B during the manufacturing process, the third opening 45 can prevent the bonding material from flowing toward the third bonding portion 43. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wires 61a. Furthermore, even if the sealing resin 7 peels off from the second die pad 4 due to stress caused by heat generated by the second semiconductor element 12, the third opening 45 can prevent the peeling from spreading to the third bonding portion 43.

[0069] Furthermore, according to this embodiment, the second die pad 4 includes a fourth opening 46 disposed between the fourth bonding portion 44 and the second semiconductor element 12 in the y direction. Even if the molten bonding material flows out when bonding the second semiconductor element 12 to the second die pad 812B during the manufacturing process, the fourth opening 46 can prevent the bonding material from flowing toward the fourth bonding portion 44. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 61b. Furthermore, even if the sealing resin 7 peels off from the second die pad 4 due to stress caused by heat generated by the second semiconductor element 12, the fourth opening 46 can prevent the peeling from spreading to the fourth bonding portion 44.

[0070] Furthermore, in this embodiment, the first opening 35 overlaps the entire first semiconductor element 11 when viewed in the y direction. Therefore, compared to when the first opening 35 does not overlap the entire first semiconductor element 11, this is more effective in suppressing the outflow of the bonding material that bonds the first semiconductor element 11 and the spread of peeling of the sealing resin 7. Furthermore, the first opening 35 overlaps the entire insulating element 13 when viewed in the y direction. Therefore, compared to when the first opening 35 does not overlap the entire insulating element 13, this is more effective in suppressing the outflow of the bonding material that bonds the insulating element 13 and the spread of peeling of the sealing resin 7. The same is true for the second opening 36, the third opening 45, and the fourth opening 46.

[0071] Furthermore, in this embodiment, the first opening 35 does not extend to the outer edge of the first main surface 31. Therefore, the strength of the first die pad 3 can be increased compared to when the first opening 35 extends to the outer edge of the first main surface 31. The same applies to the second opening 36, the third opening 45, and the fourth opening 46.

[0072] Furthermore, in this embodiment, the first opening 35 is disposed at a position closer to the first bonding portion 33 than the first semiconductor element 11. In this case, compared to when the first opening 35 is closer to the first semiconductor element 11, it is more effective in preventing the outflow of the bonding material that bonds the first semiconductor element 11. The same is true for the second opening 36, the third opening 45, and the fourth opening 46.

[0073] Furthermore, in this embodiment, the width dimension W3 of the first opening 35 is approximately 110 μm, which is between 100 μm and 250 μm. This is therefore suitable for preventing the outflow of the bonding material and the spread of peeling of the sealing resin 7. Furthermore, even if the dimension of the first main surface 31 in the y direction is small, an area for bonding the wire 62a can be ensured. The same is true for the second opening 36, the third opening 45, and the fourth opening 46.

[0074] Furthermore, according to this embodiment, the openings 35, 36, 45, and 46 are grooves recessed in the z direction from the first main surface 31 or the second main surface 41, respectively. Therefore, the dimension in the y direction can be made smaller than when the openings are drilled through the first die pad 3 or the second die pad 4. This is particularly effective when the dimension in the y direction of the first die pad 3 and the second die pad 4 is small.

[0075] In the present embodiment, the first die pad 3 has the first opening 35 and the second opening 36, and the second die pad 4 has the third opening 45 and the fourth opening 46, but this is not limiting. The semiconductor device A10 does not need to have all of the openings 35, 36, 45, and 46, and it is sufficient if it has at least one of them.

[0076] 15 to 21 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment.

[0077] 15 and 16 are diagrams for explaining a semiconductor device A20 according to a second embodiment of the present disclosure. Fig. 15 is a partially enlarged cross-sectional view showing the semiconductor device A20 and corresponds to Fig. 11. Fig. 16 is a partially enlarged cross-sectional view showing the semiconductor device A20 and corresponds to Fig. 12. The semiconductor device A20 of this embodiment differs from the first embodiment in the shapes of the openings 35, 36, 45, and 46.

[0078] In this embodiment, the first opening 35 penetrates the first die pad 3 in the z direction, as shown in FIG. 15 . Similarly, the second opening 36 also penetrates the first die pad 3 in the z direction. In this embodiment, the width dimension W3 of the first opening 35 is approximately the same as the thickness dimension D2 of the first die pad 3. In this embodiment, the thickness dimension D2 of the first die pad 3 is approximately 220 μm, and the width dimension W3 of the first opening 35 is also approximately 220 μm. The width dimension of the second opening 36 is approximately the same as the width dimension W3 of the first opening 35. Note that the dimensions of the first opening 35 and the second opening 36 are not limited to those described above.

[0079] In this embodiment, the third opening 45 penetrates the second die pad 4 in the z-direction, as shown in FIG. 16 . Similarly, the fourth opening 46 also penetrates the second die pad 4 in the z-direction. In this embodiment, the width dimension W3' of the third opening 45 is approximately the same as the thickness dimension D2' of the second die pad 4. In this embodiment, the thickness dimension D2' of the second die pad 4 is approximately 220 μm, and the width dimension W3' of the third opening 45 is also approximately 220 μm. The width dimension of the fourth opening 46 is approximately the same as the width dimension W3' of the third opening 45. Note that the dimensions of the third opening 45 and the fourth opening 46 are not limited to those described above.

[0080] In this embodiment, even if the molten bonding material flows out during the manufacturing process, the first opening 35 can prevent the bonding material from flowing to the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3, the first opening 35 can prevent the peeling from spreading to the first bonding portion 33. The same applies to the second opening 36, the third opening 45, and the fourth opening 46. Furthermore, the semiconductor device A20 has a common configuration with the semiconductor device A10, thereby achieving the same effects as the semiconductor device A10. Furthermore, according to this embodiment, the openings 35, 36, 45, and 46 penetrate the first die pad 3 or the second die pad 4, respectively, in the z-direction. Therefore, the openings 35, 36, 45, and 46 are more effective in preventing the outflow of the bonding material than openings that do not penetrate the first die pad 3 or the second die pad 4.

[0081] 17 is a diagram illustrating a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 17 is a partially enlarged plan view showing the semiconductor device A30, and corresponds to FIG. 7. For ease of understanding, FIG. 17 shows the sealing resin 7 through which the semiconductor device A30 is viewed. The semiconductor device A30 of this embodiment differs from the first embodiment in that the dimensions of the first opening 35 and the second opening 36 in the x direction are small, and the semiconductor device A30 further includes a fifth opening 37 and a sixth opening 38.

[0082] In this embodiment, the first opening 35 has a smaller dimension in the x direction than in the first embodiment. The x1-side end of the first opening 35 in this embodiment is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. That is, the first opening 35 overlaps the entire first semiconductor element 11 but does not overlap the insulating element 13 when viewed in the y direction. The first die pad 3 also includes a fifth opening 37. Like the first opening 35, the fifth opening 37 is an opening having an opening end on the first main surface 31. In this embodiment, the fifth opening 37 is a groove recessed from the first main surface 31 in the z direction. The fifth opening 37 extends in the x direction. The x2-side end of the fifth opening 37 is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. Furthermore, the x1-side end of fifth opening 37 is located in the x direction between the x1-side end face of insulating element 13 and the x1-side outer edge of first main surface 31. That is, fifth opening 37 overlaps the entire insulating element 13 when viewed in the y direction. The first opening 35 and fifth opening 37 of this embodiment are obtained by dividing the first opening 35 of the first embodiment into two parts in the x direction.

[0083] Similarly, in this embodiment, the second opening 36 has a smaller dimension in the x direction than in the first embodiment. The x1-side end of the second opening 36 in this embodiment is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. That is, the second opening 36 overlaps the entire first semiconductor element 11 but does not overlap the insulating element 13 when viewed in the y direction. The first die pad 3 also includes a sixth opening 38. Like the second opening 36, the sixth opening 38 is an opening having an opening end on the first main surface 31. In this embodiment, the sixth opening 38 is a groove recessed from the first main surface 31 in the z direction. The sixth opening 38 extends in the x direction. The x2-side end of the sixth opening 38 is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. Furthermore, the x1-side end of sixth opening 38 is located in the x direction between the x1-side end face of insulating element 13 and the x1-side outer edge of first main surface 31. That is, sixth opening 38 overlaps the entire insulating element 13 when viewed in the y direction. The second opening 36 and sixth opening 38 of this embodiment are obtained by dividing the second opening 36 of the first embodiment into two parts in the x direction.

[0084] In this embodiment, even if the molten bonding material flows out during the manufacturing process, the first opening 35 and the fifth opening 37 can prevent the bonding material from flowing to the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3, the first opening 35 and the fifth opening 37 can prevent the peeling from spreading to the first bonding portion 33. The same applies to the second opening 36 and the sixth opening 38. Furthermore, the semiconductor device A30 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0085] 18 is a diagram illustrating a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 18 is a partially enlarged plan view showing the semiconductor device A40, and corresponds to FIG. 7. For ease of understanding, FIG. 18 shows the sealing resin 7 through which the semiconductor device A40 is viewed. The semiconductor device A40 of this embodiment differs from the first embodiment in that the dimensions of the first opening 35 and the second opening 36 in the x direction are smaller.

[0086] In this embodiment, the first opening 35 has a smaller dimension in the x direction than in the first embodiment. The x1-side end of the first opening 35 in this embodiment is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. That is, the first opening 35 overlaps the entire first semiconductor element 11 but does not overlap the insulating element 13 when viewed in the y direction. Similarly, in this embodiment, the second opening 36 has a smaller dimension in the x direction than in the first embodiment. The x1-side end of the second opening 36 in this embodiment is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. That is, the second opening 36 overlaps the entire first semiconductor element 11 but does not overlap the insulating element 13 when viewed in the y direction.

[0087] In this embodiment, even if the molten bonding material flows out during the manufacturing process, the first opening 35 can prevent the bonding material from flowing toward the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3, the first opening 35 can prevent the peeling from spreading to the first bonding portion 33. The same applies to the second opening 36. Furthermore, the semiconductor device A40 has a common configuration with the semiconductor device A10, thereby achieving the same effects as the semiconductor device A10. Furthermore, according to this embodiment, the dimensions of the first opening 35 and the second opening 36 in the x direction are smaller than in the first embodiment, and therefore the strength of the first die pad 3 and the second die pad 4 can be increased.

[0088] Fig. 19 is a diagram illustrating a semiconductor device A50 according to a fifth embodiment of the present disclosure. Fig. 19 is a partially enlarged plan view showing the semiconductor device A50, and corresponds to Fig. 7. For ease of understanding, Fig. 19 shows the sealing resin 7 through which the semiconductor device A50 is viewed. The semiconductor device A50 of this embodiment differs from the first embodiment in that the dimensions of each of the openings 35, 36, 45, and 46 in the x direction are small.

[0089] In this embodiment, the dimensions of each of the openings 35, 36, 45, and 46 in the x direction are smaller than those in the first embodiment. The x1-side end of the first opening 35 in this embodiment is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. The x2-side end of the first opening 35 is located near the center (or approximately the center) of the first semiconductor element 11 in the x direction. Similarly, the x1-side end of the second opening 36 in this embodiment is located between the x1-side end face of the first semiconductor element 11 and the x2-side end face of the insulating element 13 in the x direction. The x2-side end of the second opening 36 is located near the center (or approximately the center) of the first semiconductor element 11 in the x direction.

[0090] Furthermore, the x2-side end of the third opening 45 of this embodiment is located between the x2-side end face of the second semiconductor element 12 and the x2-side outer edge of the second main surface 41 in the x direction. Furthermore, the x1-side end of the third opening 45 is located near the center (or approximately the center) of the second semiconductor element 12 in the x direction. Similarly, the x2-side end of the fourth opening 46 of this embodiment is located between the x2-side end face of the second semiconductor element 12 and the x2-side outer edge of the second main surface 41 in the x direction. Furthermore, the x1-side end of the fourth opening 46 is located near the center (or approximately the center) of the second semiconductor element 12 in the x direction.

[0091] In this embodiment, even if the molten bonding material flows out during the manufacturing process, the first opening 35 can prevent the bonding material from flowing toward the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3, the first opening 35 can prevent the peeling from spreading to the first bonding portion 33. The same applies to the second opening 36, the third opening 45, and the fourth opening 46. Furthermore, the semiconductor device A50 has a common configuration with the semiconductor device A10, thereby achieving the same effects as the semiconductor device A10. Furthermore, in this embodiment, the dimensions of the openings 35, 36, 45, and 46 in the x direction are smaller than in the first embodiment, thereby increasing the strength of the first die pad 3 and the second die pad 4.

[0092] Fig. 20 is a diagram illustrating a semiconductor device A60 according to a sixth embodiment of the present disclosure. Fig. 20 is a partially enlarged plan view showing the semiconductor device A60, and corresponds to Fig. 7. For ease of understanding, Fig. 20 shows the sealing resin 7 through which the semiconductor device A60 of this embodiment is formed. The semiconductor device A60 of this embodiment differs from the first embodiment in the shapes of the openings 35, 36, 45, and 46.

[0093] In this embodiment, the first opening 35 has a smaller dimension in the x direction than in the first embodiment. The first die pad 3 of this embodiment also includes additional openings 35a and 35b. The additional openings 35a and 35b are both openings having an open end in the first main surface 31 and, in this embodiment, are grooves recessed from the first main surface 31 in the z direction. The additional opening 35a extends from the end of the first opening 35 on the x2 side in the x direction to the y1 side in the y direction, with its tip located inside the outer edge of the first main surface 31. The additional opening 35b extends from the end of the first opening 35 on the x1 side in the x direction to the y1 side in the y direction, with its tip located inside the outer edge of the first main surface 31. In this embodiment, the distance between the tip of each of the additional openings 35a and 35b and the outer edge of the first main surface 31 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. The depth dimension (dimension in the z direction) of additional opening 35a and additional opening 35b is approximately the same as depth dimension D1 of first opening 35, and the width dimension (dimension in the x direction) is approximately the same as width dimension W3 of first opening 35. First opening 35, additional opening 35a, and additional opening 35b surround first joint portion 33 when viewed in the z direction.

[0094] Similarly, the second opening 36 has a smaller dimension in the x direction than in the first embodiment. The first die pad 3 also includes additional openings 36a and 36b. The additional openings 36a and 36b are both openings with open ends in the first main surface 31, and in this embodiment, are grooves recessed from the first main surface 31 in the z direction. The additional opening 36a extends from the end of the second opening 36 on the x2 side in the x direction to the y2 side in the y direction, with its tip located inside the outer edge of the first main surface 31. The additional opening 36b extends from the end of the second opening 36 on the x1 side in the x direction to the y2 side in the y direction, with its tip located inside the outer edge of the first main surface 31. In this embodiment, the distance between the tip of each of the additional openings 36a and 36b and the outer edge of the first main surface 31 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. The depth dimension (dimension in the z direction) of the additional opening 36a and the additional opening 36b is approximately the same as the depth dimension of the second opening 36, and the width dimension (dimension in the x direction) is approximately the same as the width dimension of the second opening 36. The second opening 36, the additional opening 36a, and the additional opening 36b surround all of the multiple second joints 34 when viewed in the z direction.

[0095] In this embodiment, the third opening 45 has a smaller dimension in the x direction than in the first embodiment. The second die pad 4 of this embodiment also includes additional openings 45a and 45b. The additional openings 45a and 45b are both openings with open ends in the second main surface 41 and, in this embodiment, are grooves recessed from the second main surface 41 in the z direction. The additional opening 45a extends from the end of the third opening 45 on the x2 side in the x direction to the y1 side in the y direction, with its tip located inside the outer edge of the second main surface 41. The additional opening 45b extends from the end of the third opening 45 on the x1 side in the x direction to the y1 side in the y direction, with its tip located inside the outer edge of the second main surface 41. In this embodiment, the distance between the tip of each of the additional openings 45a and 45b and the outer edge of the second main surface 41 is, for example, approximately 150 μm, in the range of 50 μm to 200 μm. The depth dimension (dimension in the z direction) of additional opening 45a and additional opening 45b is approximately the same as depth dimension D1' of third opening 45, and the width dimension (dimension in the x direction) is approximately the same as width dimension W3' of third opening 45. Third opening 45, additional opening 45a, and additional opening 45b surround third joint portion 43 when viewed in the z direction.

[0096] Similarly, the fourth opening 46 has a smaller dimension in the x direction than in the first embodiment. The second die pad 4 further includes additional openings 46a and 46b. The additional openings 46a and 46b are both openings with open ends in the second main surface 41, and in this embodiment, are grooves recessed from the second main surface 41 in the z direction. The additional opening 46a extends from the end of the fourth opening 46 on the x2 side in the x direction to the y2 side in the y direction, with its tip located inside the outer edge of the second main surface 41. The additional opening 46b extends from the end of the fourth opening 46 on the x1 side in the x direction to the y2 side in the y direction, with its tip located inside the outer edge of the second main surface 41. In this embodiment, the distance between the tip of each of the additional openings 46a and 46b and the outer edge of the second main surface 41 is, for example, approximately 150 μm, and is not less than 50 μm and not more than 200 μm. The depth dimension (dimension in the z direction) of the additional opening 46a and the additional opening 46b is approximately the same as the depth dimension of the fourth opening 46, and the width dimension (dimension in the x direction) is approximately the same as the width dimension of the fourth opening 46. The fourth opening 46, the additional opening 46a, and the additional opening 46b surround the fourth joint portion 44 when viewed in the z direction.

[0097] According to this embodiment, even if the molten bonding material flows out during the manufacturing process, the first opening 35, the additional opening 35a, and the additional opening 35b can prevent the bonding material from flowing toward the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3, the first opening 35, the additional opening 35a, and the additional opening 35b can prevent the peeling from spreading to the first bonding portion 33. Similarly, the second opening 36, the additional opening 35a, and the additional opening 35b can prevent the bonding material from flowing toward the multiple second bonding portions 34, and can prevent the peeling of the sealing resin 7 from spreading to the multiple second bonding portions 34. Similarly, the third opening 45, the additional opening 45a, and the additional opening 45b can prevent the bonding material from flowing toward the third bonding portion 43, and can prevent the peeling of the sealing resin 7 from spreading to the third bonding portion 43. Similarly, the fourth opening 46, the additional opening 46a, and the additional opening 46b can prevent the bonding material from flowing toward the fourth bonding portion 44 and prevent peeling of the sealing resin 7 from spreading to the fourth bonding portion 44. Furthermore, the semiconductor device A60 has a configuration common to the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10. Furthermore, in this embodiment, the x-direction dimensions of the openings 35, 36, 45, and 46 are smaller than in the first embodiment, thereby increasing the strength of the first die pad 3 and the second die pad 4. Furthermore, the additional openings can prevent the bonding material from flowing around the x-direction ends of the openings 35, 36, 45, and 46 and the peeling of the sealing resin 7 from spreading around the x-direction ends of the openings 35, 36, 45, and 46.

[0098] 21 is a diagram illustrating a semiconductor device A70 according to a seventh embodiment of the present disclosure. FIG. 21 is a plan view showing the semiconductor device A70, and corresponds to FIG. 2. In FIG. 21, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A70 of this embodiment differs from the first embodiment in that the insulating element 13 is mounted on the second die pad 4.

[0099] In this embodiment, the second die pad 4 has a larger x-direction dimension than in the first embodiment. On the other hand, the first die pad 3 has a smaller x-direction dimension than in the first embodiment. The pair of connection portions 54 are connected to the second die pad 4, which has a larger x-direction dimension, and have the same shape as the pair of connection portions 56 in the first embodiment. On the other hand, the pair of connection portions 56 are connected to the first die pad 3, which has a smaller x-direction dimension, and have the same shape as the pair of connection portions 54 in the first embodiment. In other words, the conductive support member 2 in this embodiment has a shape obtained by inverting the conductive support member 2 in the first embodiment in the x direction with the y direction as the axis. In this embodiment, an insulating element 13 is mounted on the second die pad 4.

[0100] In this embodiment, even if the molten bonding material flows out during the manufacturing process, the first opening 35 can prevent the bonding material from flowing to the first bonding portion 33. This prevents the bonding layer 69, which is the solidified bonding material, from interfering with the bonding of the wire 62a. Furthermore, even if the sealing resin 7 peels off from the first die pad 3, the first opening 35 can prevent the peeling from spreading to the first bonding portion 33. The same applies to the second opening 36, the third opening 45, and the fourth opening 46. Furthermore, the semiconductor device A70 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0101] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.

[0102] Appendix 1. a first die pad having a first main surface facing in a thickness direction; a second die pad that is spaced apart from the first die pad in a first direction perpendicular to the thickness direction and has a second main surface facing the thickness direction; a first semiconductor element mounted on the first main surface; a second semiconductor element mounted on the second main surface; an insulating element mounted on the first main surface or the second main surface, positioned between the first semiconductor element and the second semiconductor element in the first direction, and insulating the first semiconductor element and the second semiconductor element from each other while relaying signals between the first semiconductor element and the second semiconductor element; a first wire bonded to the first semiconductor element and the first main surface; a sealing resin that covers the first semiconductor element, the second semiconductor element, and the insulating element; Equipped with The first die pad is a first bonding portion located on a first side of the first semiconductor element in a second direction perpendicular to the thickness direction and the first direction, and to which the first wire is bonded; a first opening portion disposed between the first bonding portion and the first semiconductor element in the second direction and having an opening end in the first main surface; The semiconductor device comprises: Appendix 2. the second semiconductor element is a control element; 2. The semiconductor device according to claim 1, wherein the first semiconductor element is a drive element that receives a signal from the control element via the isolation element, and generates and outputs a drive signal. Appendix 3. a plurality of terminals arranged along the second direction, at least one of which is electrically connected to the first semiconductor element; A pair of connecting portions; Furthermore, the plurality of terminals includes a pair of outer terminals arranged at both ends in the second direction among the plurality of terminals, 3. The semiconductor device according to claim 1, wherein each of the pair of connecting portions is connected to one of the pair of outer terminals and the first die pad. Appendix 4. Each of the pair of connecting portions is a first connecting portion and a second connecting portion connected to the first die pad; a coupling portion connected to one of the pair of outer terminals, the first coupling portion, and the second coupling portion; It is equipped with the first connecting portion extends in the second direction from the first die pad to the bonding portion; the second connecting portion includes a first portion extending from the first die pad in the second direction, and a second portion connected to the first portion and the joining portion and extending in a direction inclined with respect to the second direction; The semiconductor device according to claim 3, wherein the coupling portion has a through-hole penetrating in the thickness direction. Appendix 5. 5. The semiconductor device according to claim 1, wherein the first opening extends in the first direction. Appendix 6. 6. The semiconductor device according to claim 1, wherein the first opening overlaps the entire first semiconductor element when viewed in the second direction. Appendix 7. 7. The semiconductor device according to claim 1, wherein, when viewed in the thickness direction, both ends of the first opening in the first direction are located inside an outer edge of the first main surface. Appendix 8. 8. The semiconductor device according to claim 1, wherein the dimension of the first opening in the second direction is not less than 100 μm and not more than 250 μm. Appendix 9. 9. The semiconductor device according to any one of claims 1 to 8, wherein in the second direction, a first distance between the first opening and the first semiconductor element is greater than a second distance between the first opening and the first junction. Appendix 10. 10. The semiconductor device according to any one of claims 1 to 9, wherein the first opening is a groove recessed from the first main surface in the thickness direction. Appendix 11. 10. The semiconductor device according to claim 1, wherein the first opening penetrates the first die pad in the thickness direction. Appendix 12. a second wire bonded to the first semiconductor element and the first main surface; The first die pad is a second bonding portion located on a second side in the second direction with respect to the first semiconductor element and to which the second wire is bonded; a second opening portion disposed between the second bonding portion and the first semiconductor element in the second direction and having an opening end in the first main surface; 12. The semiconductor device according to any one of claims 1 to 11, comprising: Appendix 13. a third wire bonded to the second semiconductor element and the second main surface; The second die pad is a third bonding portion located on the first side in the second direction with respect to the second semiconductor element and to which the third wire is bonded; a third opening portion disposed between the third bonding portion and the second semiconductor element in the second direction and having an opening end in the second main surface; 13. The semiconductor device according to any one of claims 1 to 12, comprising: Appendix 14. 14. The semiconductor device according to claim 13, wherein the third opening extends in the first direction. Appendix 15. 15. The semiconductor device according to claim 13, wherein, when viewed in the second direction, the third opening overlaps the entire second semiconductor element. Appendix 16. 16. The semiconductor device according to claim 13, wherein, when viewed in the thickness direction, both ends of the third opening in the first direction are located inside an outer edge of the second main surface. Appendix 17. a fourth wire bonded to the second semiconductor element and the second main surface; The second die pad is a fourth bonding portion located on the second side in the second direction with respect to the second semiconductor element and to which the fourth wire is bonded; a fourth opening portion disposed between the fourth bonding portion and the second semiconductor element in the second direction and having an opening end in the second main surface; 17. The semiconductor device according to any one of appendices 13 to 16, comprising: Appendix 18. a bonding layer interposed between the first die pad and the first semiconductor element; 18. The semiconductor device according to any one of claims 1 to 17, wherein the bonding layer is an Ag paste. Appendix 19. 19. The semiconductor device according to any one of claims 1 to 18, wherein the insulating element is mounted on the first main surface. [Explanation of symbols]

[0103] A10, A20, A30, A40, A50, A60, A70: Semiconductor device 11: First semiconductor element 11a: End face 12: Second semiconductor element 13: Isolation element 13a: end surface 2: conductive support member 3: First die pad 31: First main surface 31a, 31b: outer edge 32: first back surface 33: 1st joint 34: 2nd joint 35: 1st opening 35a, 35b: Additional opening 36: Second opening 36a, 36b: Additional opening 37: 5th opening 38: 6th opening 4: Second die pad 41: Second main surface 42: 2nd back side 43: 3rd joint part 44: 4th joint 45: 3rd opening 45a, 45b: Additional opening 46: 4th opening 46a, 46b: Additional openings 51, 51a, 51b: Input terminals 53: Pad section 54: Connection section 541: Connecting part 543: Joining part 543a: Through hole 52, 52a, 52b: Output terminals 55: Pad section 56: Connection section 561: 1st connection part 562: 2nd connection part 562a: Part 1 562b: Part 2 563: Joint part 563a: Through hole 61, 61a, 61b, 62, 62a, 62b, 63, 64: Wires 69: Bonding layer 7: Sealing resin 71:Top 72:Bottom 73: 1st side 731: 1st area 732: 2nd area 733: 3rd area 74:Second side 741:Fourth area 742: 5th area 743: 6th area 75: Third aspect 751: Seventh area 752: 8th area 753: 9th area 76: 4th aspect 761: 10th area 762: 11th area 763: 12th area 81: Lead frame 81A: Main surface 81B: Back 811: Outer frame 812A: First die pad 812B: Second die pad 813: 1st lead 814: 2nd lead 815: Connection part 816: Dam bar

Claims

1. a first die pad having a first main surface facing in a thickness direction; a second die pad that is spaced apart from the first die pad in a first direction perpendicular to the thickness direction and has a second main surface facing the thickness direction; a first semiconductor element mounted on the first main surface; a second semiconductor element mounted on the second main surface; an insulating element mounted on the first main surface or the second main surface, positioned between the first semiconductor element and the second semiconductor element in the first direction, and insulating the first semiconductor element and the second semiconductor element from each other while relaying signals between the first semiconductor element and the second semiconductor element; a first wire bonded to the first semiconductor element and the first main surface; a sealing resin that covers the first semiconductor element, the second semiconductor element, and the insulating element; a plurality of terminals arranged along a second direction perpendicular to the thickness direction and the first direction, at least one of which is electrically connected to the first semiconductor element; A pair of connecting portions; Equipped with The first die pad is a first bonding portion located on a first side in the second direction with respect to the first semiconductor element and to which the first wire is bonded; a first opening portion disposed between the first bonding portion and the first semiconductor element in the second direction and having an opening end in the first main surface; Equipped with the plurality of terminals includes a pair of outer terminals arranged at both ends in the second direction among the plurality of terminals, each of the pair of connection portions is connected to one of the pair of outer terminals and the first die pad; Each of the pair of connecting portions is a first connecting portion and a second connecting portion connected to the first die pad; a coupling portion connected to one of the pair of outer terminals, the first coupling portion, and the second coupling portion; It is equipped with the first connecting portion extends in the second direction from the first die pad to the bonding portion; the second connecting portion includes a first portion extending from the first die pad in the second direction, and a second portion connected to the first portion and the joining portion and extending in a direction inclined with respect to the second direction; The coupling portion has a through hole penetrating in the thickness direction. Semiconductor device.

2. the second semiconductor element is a control element; 2. The semiconductor device according to claim 1, wherein the first semiconductor element is a drive element that receives a signal from the control element via the isolation element, and generates and outputs a drive signal.

3. The semiconductor device according to claim 1 , wherein the first opening extends in the first direction.

4. The semiconductor device according to claim 1 , wherein the first opening overlaps the entire first semiconductor element when viewed in the second direction.

5. 5 . The semiconductor device according to claim 1 , wherein both ends of said first opening in said first direction are located inside an outer edge of said first main surface when viewed in said thickness direction.

6. 6. The semiconductor device according to claim 1, wherein the dimension of said first opening in said second direction is not less than 100 [mu]m and not more than 250 [mu]m.

7. 7. The semiconductor device according to claim 1, wherein a first distance between the first opening and the first semiconductor element in the second direction is greater than a second distance between the first opening and the first joint portion.

8. 8. The semiconductor device according to claim 1, wherein said first opening is a groove recessed from said first main surface in said thickness direction.

9. 8. The semiconductor device according to claim 1, wherein the first opening penetrates the first die pad in the thickness direction.

10. a second wire bonded to the first semiconductor element and the first main surface; The first die pad is a second bonding portion located on a second side in the second direction with respect to the first semiconductor element and to which the second wire is bonded; a second opening portion disposed between the second bonding portion and the first semiconductor element in the second direction and having an opening end in the first main surface; 10. The semiconductor device according to claim 1, further comprising:

11. a third wire bonded to the second semiconductor element and the second main surface; The second die pad is a third bonding portion located on the first side in the second direction with respect to the second semiconductor element and to which the third wire is bonded; a third opening portion disposed between the third bonding portion and the second semiconductor element in the second direction and having an opening end in the second main surface; 11. The semiconductor device according to claim 1, comprising:

12. The semiconductor device according to claim 11 , wherein the third opening extends in the first direction.

13. The semiconductor device according to claim 11 , wherein the third opening overlaps the entire second semiconductor element when viewed in the second direction.

14. 14 . The semiconductor device according to claim 11 , wherein both ends of said third opening in said first direction are located inside an outer edge of said second main surface when viewed in said thickness direction.

15. a fourth wire bonded to the second semiconductor element and the second main surface; The second die pad is a fourth bonding portion located on the second side in the second direction with respect to the second semiconductor element and to which the fourth wire is bonded; a fourth opening portion disposed between the fourth bonding portion and the second semiconductor element in the second direction and having an opening end in the second main surface; 15. The semiconductor device according to claim 11, comprising:

16. a bonding layer interposed between the first die pad and the first semiconductor element; 16. The semiconductor device according to claim 1, wherein the bonding layer is made of Ag paste.

17. 17. The semiconductor device according to claim 1, wherein the insulating element is mounted on the first main surface.

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