Semiconductor Devices

Abstract

To suppress the occurrence of distortion in a main electrode of a semiconductor chip included in a semiconductor device.SOLUTION: A semiconductor device 1 includes a semiconductor chip 20a having a main electrode on a front surface, and an N-connection terminal 44 having a rectangular and flat plate shape in a plan view, including a main electrode bonding part 44a including a bonding surface, and bonded to the main electrode through an upper solder 52 on the bonding surface. One end surface 44c among four outer peripheral surfaces included in the main electrode bonding part 44a is inclined sharply to the bonding surface. Thus, creeping up of the upper solder 52 onto the end surface 44c due to heat generation of the semiconductor chip 20a in a power cycle test or the like can be suppressed and the fillet shape of the upper solder 52 can be kept a suitable shape that obtains a stress relieving effect with a high possibility. Accordingly, the occurrence of distortion in the main electrode can be suppressed.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device Place Regarding. [Background technology]

[0002] There are semiconductor devices that include power devices and are used as power conversion devices. Examples of power devices include IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In the semiconductor device, a semiconductor chip including the power device and an insulating circuit board are sealed with a sealing member. Furthermore, the main electrodes of the semiconductor chip are electrically connected to connection terminals (sometimes called lead frames) via solder.

[0003] One test for evaluating the reliability of power devices is the power cycle test, in which the semiconductor chip is repeatedly heated and cooled to evaluate the bonding reliability of each part of the semiconductor device against thermal stress. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-204525 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-114571 Summary of the Invention [Problem to be solved by the invention]

[0005] During power cycle testing, thermal stress is applied to the connection terminals, solder, and semiconductor chip. In addition to deformation of the connection terminals themselves, the difference in thermal expansion coefficient between the materials of the connection terminals and semiconductor chip can cause distortion in the main electrodes of the semiconductor chip that are bonded to the connection terminals. In particular, distortion can be significant at the tip of the connection terminal if the solder fillet shape, which acts as a stress reliever, is not appropriate.

[0006] The present invention has been made in view of the above points, and provides a semiconductor device capable of suppressing the occurrence of distortion in the main electrodes of a semiconductor chip. Place The purpose is to provide. [Means for solving the problem]

[0007] According to one aspect of the present invention, a main electrode a wiring portion provided on the main electrode and extending to an outer periphery of the main electrode; and a connection terminal that is rectangular and flat in plan view and includes a bonding portion having a bonding surface, and is bonded to the main electrode at the bonding surface via solder, and among four outer peripheral surfaces included in the bonding portion, , located in the outer periphery to which the wiring portion extends in a plan view. The semiconductor device is provided in which the tip surface of the first electrode is inclined at an acute angle with respect to the bonding surface. [Effects of the Invention]

[0009] According to the disclosed technique, it is possible to suppress the occurrence of distortion in the main electrodes of the semiconductor chip included in the semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a plan view of a semiconductor unit included in the semiconductor device according to the embodiment. [Figure 3] 3 is a cross-sectional view showing a joint portion between a semiconductor chip included in the semiconductor device of the embodiment and an N connection terminal and an insulating circuit board. FIG. [Figure 4]1 is a front view showing a joint portion between a semiconductor chip included in the semiconductor device of the embodiment and an N connection terminal and an insulating circuit board. FIG. [Figure 5] 1 is a cross-sectional view of a semiconductor chip included in a semiconductor device according to an embodiment; [Figure 6] 10 is a cross-sectional view showing the joints between a semiconductor chip, an N-connection terminal, and an insulating circuit board included in a semiconductor device of a comparative example. FIG. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor chip included in a semiconductor device of a comparative example. [Figure 8] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 10A to 10C are diagrams illustrating a terminal bonding step included in the manufacturing method of the semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor unit included in a semiconductor device according to a first modified example of the embodiment. [Figure 11] 10 is a front view showing the joints between the semiconductor chip, the N connection terminal, and the insulating circuit board included in the semiconductor device according to the first modification of the embodiment. FIG. [Figure 12] FIG. 10 is a plan view of a semiconductor unit included in a semiconductor device according to a second modification of the embodiment. [Figure 13] 10 is a cross-sectional view showing a joint portion between a semiconductor chip, an N-connection terminal, and an insulating circuit board included in a semiconductor device according to a second modification of the embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the surface facing upward (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "up" refers to the upward direction (+Z direction) in the semiconductor device 1 shown in the drawings. The terms "back surface" and "lower surface" refer to the surface facing downward (-Z direction) in the semiconductor device 1 shown in the drawings. Similarly, the term "lower" refers to the downward direction (-Z direction) in the semiconductor device 1 shown in the drawings. Similar directions will be used in other drawings as necessary. The terms "front surface," "upper surface," "upper," "back surface," "lower surface," "lower," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. In other words, the "upper" and "lower" directions are not limited to the direction of gravity.

[0012] Hereinafter, a semiconductor device 1 according to an embodiment will be described with reference to the drawings using FIGS. FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment, and FIG. 2 is a plan view of semiconductor unit 10a among semiconductor units 10a, 10b, and 10c included in semiconductor device 1 according to an embodiment. The other semiconductor units 10b and 10c have the same configuration as semiconductor unit 10a, and therefore their description will be omitted. FIG. 3 is a cross-sectional view showing a bonding portion between semiconductor chip 20a, N-connection terminal 44, and insulating circuit board 11 included in semiconductor device 1 according to an embodiment. FIG. 4 is a front view showing a bonding portion between semiconductor chip 20a, N-connection terminal 44, and insulating circuit board 11 included in semiconductor device 1 according to an embodiment, and FIG. 5 is a cross-sectional view of semiconductor chip 20a included in semiconductor device 1 according to an embodiment. FIG. 3 is a cross-sectional view taken along dash-dotted line XX in FIG. 2, and FIG. 5 is a cross-sectional view taken along dash-dotted line YY in FIG. 2.

[0013] The semiconductor device 1 functions as, for example, a three-phase inverter device. As shown in Fig. 1, the semiconductor device 1 includes three semiconductor units 10a, 10b, and 10c housed in a case 30. These three semiconductor units 10a, 10b, and 10c are used to realize, for example, arms of U-phase, V-phase, and W-phase.

[0014] The case 30 includes a frame 31 and has a substantially rectangular shape in plan view. The case 30 has a pair of long frame sides 31a and 31c and a pair of short frame sides 31b and 31d. The case 30 has storage sections 32a, 32b, and 32c along the pair of long frame sides 31a and 31c. The storage sections 32a, 32b, and 32c are separated by partitions 32d and 32e, respectively. The partitions 32d and 32e are arranged parallel to the pair of short frame sides 31b and 31d and perpendicular to the pair of long frame sides 31a and 31c. Therefore, each of the storage sections 32a, 32b, and 32c has a substantially rectangular shape in plan view. The storage section 32a stores the semiconductor unit 10a, the storage section 32b stores the semiconductor unit 10b, and the storage section 32c stores the semiconductor unit 10c. Although not shown, the semiconductor units 10a, 10b, and 10c are each sealed with a sealing member.

[0015] Case 30 has input terminals arranged on long frame side 31a. Specifically, P terminals 33a, 33b, and 33c and N terminals 34a, 34b, and 34c are arranged along long frame side 31a. Case 30 has output terminals arranged on the front surface of case 30, on the side of long frame side 31c opposite the side on which the input terminals are arranged. Specifically, U terminal 35a, V terminal 35b, and W terminal 35c are arranged along long frame side 31c. P terminal 33a, N terminal 34a, and U terminal 35a are arranged on either side of storage section 32a. P terminal 33b, N terminal 34b, and V terminal 35b are arranged on either side of storage section 32b. P terminal 33c, N terminal 34c, and W terminal 35c are arranged on either side of storage section 32c.

[0016] The P terminals 33a, 33b, 33c, the N terminals 34a, 34b, 34c, the U terminal 35a, the V terminal 35b, and the W terminal 35c are electrically connected to main electrodes of the semiconductor chips described below of the semiconductor unit 10 housed in the housing sections 32a, 32b, 32c, respectively.

[0017] The main electrodes include an emitter electrode (or source electrode) and a collector electrode (or drain electrode). P terminals 33a, 33b, and 33c, N terminals 34a, 34b, and 34c, U terminal 35a, V terminal 35b, and W terminal 35c are electrically connected to the main electrodes via a lead frame. The lead frame includes, for example, a P connection terminal 43, an N connection terminal 44, an output terminal 45, and an internal connection terminal 46.

[0018] These lead frames are made of a metal with excellent conductivity. The metal with excellent conductivity is, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, the surfaces of the P connection terminal 43, the N connection terminal 44, the output terminal 45, and the internal connection terminal 46 may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0019] One end of P connection terminal 43 is mechanically and electrically connected to the front surface of circuit pattern 13b (see FIG. 2), which will be described later, by, for example, soldering, laser welding, ultrasonic welding, etc. The other end of P connection terminal 43 is located above (in the +Z direction) one end of P connection terminal 43, and is electrically connected to P terminal 33a.

[0020] A main electrode joint portion 44a, which is one end portion of the N connection terminal 44, is solder-joined to the front surface of a main electrode 22a (see FIG. 2) of the semiconductor chip 20a, which will be described later. The other end portion of the N connection terminal 44 is located above (in the +Z direction) the one end portion of the N connection terminal 44, and is electrically connected to the N terminal 34a.

[0021] One end of output terminal 45 is mechanically and electrically connected to the front surface of circuit pattern 13a (see FIG. 2) described below, for example, by soldering, laser welding, ultrasonic welding, etc. The other end of output terminal 45 is located above (in the +Z direction) one end of output terminal 45 and is electrically connected to U-terminal 35a.

[0022] One end of the internal connection terminal 46 is mechanically and electrically connected to the front surface of the circuit pattern 13a by, for example, soldering, laser welding, ultrasonic welding, etc. The other end of the internal connection terminal 46, which is a main electrode joint portion 46a, is solder-joined to the front surface of a main electrode 22b of the semiconductor chip 20b, which will be described later.

[0023] Each of the P connection terminal 43, the N connection terminal 44, the output terminal 45, and the internal connection terminal 46 has a leg (see, for example, leg 44b in FIG. 3) connecting one end to the other end. Each leg extends vertically upward (in the +Z direction) or diagonally upward from one end of the P connection terminal 43, the N connection terminal 44, the output terminal 45, and the internal connection terminal 46, and is connected to the other end. Note that one end and the other end of the P connection terminal 43, the N connection terminal 44, the output terminal 45, and the internal connection terminal 46 may be at the same height.

[0024] The following describes the semiconductor unit 10a in Fig. 1. The semiconductor units 10b and 10c have the same configuration as the semiconductor unit 10a, so their description will be omitted. 2, the semiconductor unit 10a includes an insulating circuit board 11 and semiconductor chips 20a and 20b. The semiconductor chips 20a and 20b are disposed on the front surface (upper surface) of the insulating circuit board 11.

[0025] Insulated circuit board 11 has a rectangular shape in a plan view. Insulated circuit board 11 includes insulating plate 12, circuit pattern 13 (including circuit patterns 13a and 13b) provided on the front surface (top surface) of insulating plate 12, and metal plate 14 (see FIGS. 3 and 4) provided on the back surface (bottom surface) of insulating plate 12. Semiconductor chips 20a and 20b are mechanically and electrically connected to the front surfaces (top surfaces) of circuit patterns 13a and 13b by bottom solder 51 (see FIGS. 3 and 4).

[0026] The insulating plate 12 has a rectangular shape in a plan view. The corners of the insulating plate 12 may be rounded or chamfered. The insulating plate 12 is made of ceramics with good thermal conductivity. The ceramics may be made of a material containing aluminum oxide, aluminum nitride, or silicon nitride as a main component, for example. The thickness of the insulating plate 12 is, for example, 0.2 mm or more and 2.0 mm or less.

[0027] The edges of circuit patterns 13a and 13b on the outer periphery side of insulating plate 12 preferably overlap the edges of metal plate 14 on the outer periphery side of insulating plate 12 in a plan view. Therefore, insulated circuit board 11, a stress balance with metal plate 14 on the back surface of insulating plate 12 is maintained, and damage to insulating plate 12 such as excessive warping and cracking is suppressed.

[0028] The thickness of the circuit patterns 13a, 13b is, for example, 0.1 mm or more and 2.0 mm or less. The circuit patterns 13a, 13b are made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, the surfaces of the circuit patterns 13a, 13b may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The circuit patterns 13a, 13b for the insulating plate 12 are obtained by forming a metal plate on the front surface of the insulating plate 12 and then subjecting this metal plate to a process such as etching. Alternatively, the circuit patterns 13a, 13b may be cut out from a metal plate in advance and then pressure-bonded to the front surface of the insulating plate 12. Note that the circuit patterns 13a, 13b are merely examples. The number, shape, size, and other characteristics of the circuit patterns may be appropriately selected as needed.

[0029] The metal plate 14 has a rectangular shape in a plan view. The corners may be rounded or chamfered. The metal plate 14 is smaller than the insulating plate 12 and is formed on the entire surface of the insulating plate 12 except for the edges. The metal plate 14 is mainly composed of a metal with excellent thermal conductivity. The metal may be, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plate 14 is, for example, 0.1 mm or more and 2.0 mm or less. The metal plate 14 may be plated to improve its corrosion resistance. Examples of the plating material used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. As such an insulating circuit board 11, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board can be used.

[0030] The semiconductor chips 20a and 20b include switching elements made of silicon, silicon carbide, or gallium nitride, such as IGBTs and power MOSFETs.

[0031] Furthermore, main electrodes 22a and 22b are provided on the front surfaces of the semiconductor chips 20a and 20b. When the semiconductor chips 20a and 20b are IGBTs, the main electrodes 22a and 22b are emitter electrodes, and when the semiconductor chips 20a and 20b are power MOSFETs, the main electrodes 22a and 22b are source electrodes. The cross sections of the semiconductor chips 20a and 20b are layered, for example, as shown in FIG. 5. Note that FIG. 5 shows the cross section of the semiconductor chip 20a. The semiconductor chip 20b also has a layered structure similar to the semiconductor chip 20a.

[0032] The main electrodes 22a and 22b are formed of, for example, an alloy of silicon and aluminum. Furthermore, in the example of Fig. 5, a layer-like plating portion 22a1 is formed on the layer-like main electrode 22a (see Fig. 5). A similar plating portion 22a1 may also be formed on the main electrode 22b.

[0033] The plating portion 22a1 is provided to facilitate soldering when the main electrodes 22a, 22b are made of a material that is difficult to solder, such as aluminum. The plating portion 22a1 is formed mainly from, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The plating portion 22a1 is formed on the main electrodes 22a, 22b except for the temperature-sensing elements 24a, 24b and the wiring portions 25a, 25b (described later).

[0034] Although not shown, the semiconductor chips 20a and 20b also have main electrodes on their rear surfaces. If the semiconductor chips 20a and 20b are IGBTs, the main electrodes on the rear surfaces are collector electrodes, and if the semiconductor chips 20a and 20b are power MOSFETs, the main electrodes on the rear surfaces are drain electrodes.

[0035] 2, the front surface of semiconductor chip 20a is provided with control electrodes 21a1, 21a2, 21a4, and 21a5 and detection electrode 21a3, and the front surface of semiconductor chip 20b is provided with control electrodes 21b1, 21b2, 21b4, and 21b5 and detection electrode 21b3. Control electrodes 21a1, 21a2, 21a4, and 21a5 are gate electrodes of switching elements included in semiconductor chip 20a. Control electrodes 21b1, 21b2, 21b4, and 21b5 are gate electrodes of switching elements included in semiconductor chip 20b.

[0036] Furthermore, the semiconductor chips 20a, 20b include temperature-sensing units 23a, 23b for detecting the temperatures of the semiconductor chips 20a, 20b. The temperature-sensing unit 23a includes a temperature-sensing element 24a and a wiring portion 25a. The temperature-sensing element 24a is provided on the main electrode 22a. The temperature-sensing element 24a outputs a current corresponding to the temperature of the main electrode 22a. The wiring portion 25a is provided on the main electrode 22a, and one end is connected to the temperature-sensing element 24a and extends to the outer periphery of the main electrode 22a in the +Y direction. The wiring portion 25a conducts the current output from the temperature-sensing element 24a. The other end of the wiring portion 25a is electrically connected to the detection electrode 21a3. The temperature of the main electrode 22a can be detected based on the current obtained from the detection electrode 21a3 and conducted from the wiring portion 25a.

[0037] The temperature sensing unit 23b includes a temperature sensing element 24b and a wiring portion 25b. The temperature sensing element 24b is provided on the main electrode 22b. The temperature sensing element 24b outputs a current corresponding to the temperature of the main electrode 22b. The wiring portion 25b is provided on the main electrode 22b, and one end is connected to the temperature sensing element 24b and extends to the outer periphery of the main electrode 22b in the +Y direction. The wiring portion 25b conducts the current output from the temperature sensing element 24b. The other end of the wiring portion 25b is electrically connected to the detection electrode 21b3. The temperature of the main electrode 22b can be detected based on the current conducted from the wiring portion 25b, which is obtained from the detection electrode 21b3.

[0038] 2, the temperature sensing element 24a is provided, for example, in the center of the main electrode 22a, and the wiring portion 25a extends to the center of the outer periphery of the main electrode 22a. Similarly, the temperature sensing element 24b is provided, for example, in the center of the main electrode 22b, and the wiring portion 25b extends to the center of the outer periphery of the main electrode 22b.

[0039] The temperature sensitive elements 24a and 24b can be realized by, for example, PN junction diodes. The wiring portions 25a and 25b include, for example, wirings (anode wiring and cathode wiring) covered with polyimide. Note that the semiconductor chips 20a and 20b may be RC (Reverse-Conducting)-IGBTs that combine the functions of IGBTs and FWDs.

[0040] 1 is connected mechanically and electrically to the main electrode 22a on the front surface of the semiconductor chip 20a via upper solder 52 (see FIGS. 3 to 5). In FIG. 2, the main electrode joint 44a is indicated by a dotted line.

[0041] Furthermore, a main electrode joint 46a at one end of an internal connection terminal 46 shown in Fig. 1 is mechanically and electrically joined to the main electrode 22b on the front surface of the semiconductor chip 20b via solder. The main electrode joint 46a is indicated by a dotted line in Fig. 2.

[0042] In addition, one end of a bonding wire is mechanically and electrically joined to each of the control electrodes 21a1, 21a2, 21a4, 21a5, 21b1, 21b2, 21b4, and 21b5 and the detection electrodes 21a3 and 21b3, respectively, and the other end of the bonding wire is connected to a circuit board on the case 30 side.

[0043] 2 shows an example in which two semiconductor chips 20a and 20b are provided in one semiconductor unit 10a, but the present invention is not limited to this. The number of semiconductor chips provided may depend on the specifications of the semiconductor device 1.

[0044] 3, in the semiconductor device 1 of this embodiment, one tip surface 44c of the four outer peripheral surfaces included in the main electrode joint portion 44a of the N connection terminal 44 is inclined at an acute angle (angle β in FIG. 3) with respect to the joint surface. Furthermore, in the semiconductor device 1 of this embodiment, the tip surface 44c is located at the outer peripheral portion of the main electrode 22a to which the wiring portion 25a extends in a plan view (see FIG. 2).

[0045] The upper solder 52 covers the entire tip surface 44c without overlapping the inclined tip surface 44c with the front surface of the terminal opposite the joining surface of the main electrode joining portion 44a. In addition, as shown in Fig. 3, the angle α of the line connecting the tip of the upper solder 52 to the end of the tip surface 44c on the front surface side of the terminal with respect to the joining surface is equal to or greater than 25° and less than 45°.

[0046] By forming the tip surface 44c side of the main electrode joint portion 44a of the upper solder 52 into such a fillet shape, the stress relief effect of the upper solder 52 works more appropriately at the tip portion of the main electrode joint portion 44a, thereby suppressing the occurrence of distortion in the main electrode 22a.

[0047] In this way, by making the tip surface 44c inclined at an acute angle relative to the joining surface, it is possible to prevent the upper solder 52 from creeping up to the tip surface 44c due to heat generated by the semiconductor chip 20a during a power cycle test, etc. This is because if the amount of creeping up is large, it is difficult to control the fillet shape to have the angle α as described above.

[0048] Although not shown, the main electrode junction 46a of the internal connection terminal 46 may have, like the main electrode junction 44a, a tip surface located on the outer periphery of the main electrode 22b to which the wiring portion 25b connected to the temperature-sensing element 24b extends, which may have the same shape as the tip surface 44c in FIG. 3. FIG. 5 shows a cross-sectional view taken along the dashed dotted line YY in FIG. 2 when an IGBT is used as a switching element included in the semiconductor chip 20a.

[0049] The semiconductor chip 20a includes, for example, a silicon substrate 20a1. A P-type well 20a3, which is an emitter region sandwiched between trench layers 20a2, is formed in the silicon substrate 20a1, and a gate runner 20a4 is provided thereon. An insulating layer 20a5 and a main electrode 22a are stacked on top of this structure.

[0050] The P-type well 20a3 is electrically connected to the main electrode 22a by a via 20a6 made of tungsten or the like. A wiring section 25a including wiring (anode wiring and cathode wiring) coated with polyimide is formed on a part of the main electrode 22a and on a part of the main electrode 22a. A plating section 22a1 is formed on the main electrode 22a so as to avoid the wiring section 25a (and the temperature sensing element 24a shown in FIG. 2). The plating section 22a1 is joined to the main electrode joining section 44a via the upper solder 52. A gap is generated between the plating portion 22a1 and the wiring portion 25a (the portion surrounded by the dotted line in FIG. 5), and the upper solder 52 enters the gap.

[0051] Here, a comparative example to the semiconductor device 1 will be described with reference to Figures 6 and 7. Figure 6 is a cross-sectional view showing the bonding portion between the semiconductor chip included in the semiconductor device of the comparative example and the N-connection terminal and insulating circuit board. Figure 7 shows a cross-sectional view of the semiconductor chip included in the semiconductor device of the comparative example. Note that Figures 6(A) and 6(B) show cross sections corresponding to the cross section shown in Figure 3, and Figure 7 shows a cross section corresponding to the cross section shown in Figure 5.

[0052] 6(A) and 6(B) show the case where the tip surface of the main electrode joint portion 44a1 is inclined at an angle β, which is an acute angle relative to the joint surface as in FIG. 3, but is inclined at an angle of 90° relative to the joint surface. FIG. 6(A) shows the state during manufacturing, and FIG. 6(B) shows the state during a power cycle test.

[0053] As shown in FIG. 6A, in the initial manufacturing state before a power cycle test, the upper solder 52 has an appropriate fillet shape. The semiconductor chip 20a is then heated and cooled between predetermined temperatures, and a power cycle test is performed on the semiconductor chip 20a. Due to differences in thermal expansion coefficients between the main electrode joint 44a1 of the N-connection terminal 44, the upper solder 52, and the semiconductor chip 20a, warping occurs between the main electrode joint 44a1 and the semiconductor chip 20a. For example, at a high temperature of 175°C, the main electrode joint 44a1 is merely bonded to the upper solder 52 and extends beyond the upper solder 52 and the semiconductor chip 20a. As a result, warping occurs between the main electrode joint 44a1 and the semiconductor chip 20a, as shown in FIG. 6B. This warping applies stress to the semiconductor chip 20a directly below the tip of the main electrode joint 44a1. At this time, the fillet shape of the upper solder 52 at the tip of the main electrode joint 44a1 is no longer maintained. As a result, a large strain occurs in the main electrode 22a on the semiconductor chip 20a directly below the tip portion of the main electrode joint 44a1.

[0054] If such distortion occurs, for example, as shown in FIG. 7, cracks may occur in the direction of the arrow from the gap between the plating portion 22a1 and the wiring portion 25a, which may cause failure in the wiring portion 25a, etc.

[0055] In contrast, in the semiconductor device 1 of this embodiment, as shown in FIG. 3, the tip surface 44c of the main electrode joint portion 44a of the N-connection terminal 44 is inclined at an acute angle relative to the joint surface, thereby suppressing creeping of the top solder 52 to the tip surface 44c. This increases the likelihood that the fillet shape of the top solder 52 can be maintained in the appropriate shape described above. Maintaining the fillet shape of the top solder 52 suppresses the main electrode joint portion 44a from expanding in response to temperature changes, thereby reducing warping of the main electrode joint portion 44a. As a result, stress on the semiconductor chip 20a directly below the tip portion of the main electrode joint portion 44a is reduced. Furthermore, the stress relief effect of the top solder 52 can suppress distortion in the main electrode 22a. Therefore, failures of the wiring portion 25a and other components can be suppressed.

[0056] (Method of manufacturing semiconductor device 1) 8 is a flowchart showing a method for manufacturing the semiconductor device 1 according to the embodiment. In FIG. 8, a flow of an example of a manufacturing process of the semiconductor device 1 is shown.

[0057] Step S1: A process is performed to prepare the components of the semiconductor device 1. The components include, for example, semiconductor chips 20a and 20b, an insulating circuit board 11, a case 30, connection terminals (P connection terminal 43, N connection terminal 44, output terminal 45, internal connection terminal 46), a sealing member (not shown), and the like.

[0058] Step S2: A chip bonding process is performed. In the chip bonding process, semiconductor chips 20a and 20b are bonded onto circuit patterns 13a and 13b of insulating circuit board 11 as shown in FIG. 2 using bottom solder 51 (see FIGS. 3 and 4). This produces semiconductor unit 10a as shown in FIG. 2. Semiconductor units 10b and 10c are also produced in the same manner.

[0059] Step S3: A storing step is performed. In the storing step, the semiconductor units 10a, 10b, and 10c are stored in the storage sections 32a, 32b, and 32c of the case 30 as shown in FIG.

[0060] Step S4: A terminal bonding step is performed. In the terminal bonding step, the N connection terminal 44 is bonded to the main electrode 22a of the semiconductor chip 20a, and the internal connection terminal 46 is bonded to the main electrode 22b of the semiconductor chip 20b.

[0061] Here, the bonding of the N connection terminal 44 to the semiconductor chip 20a will be described as an example with reference to FIG. 9. FIG. 9 is a diagram showing a terminal bonding step included in the manufacturing method of the semiconductor device 1 according to the embodiment. FIG. 9 illustrates the terminal bonding step for obtaining the structure shown in the cross-sectional view of FIG. 3. As shown in FIG. 9, first, a placement step is performed in which the bonding surface of the main electrode bonding portion 44a is placed on the main electrode 22a via upper solder 52, which is a plate solder longer in the Y direction than the main electrode bonding portion 44a of the N connection terminal 44. Then, a bonding step is performed in which the upper solder 52 is heated to bond the bonding surface of the main electrode bonding portion 44a to the main electrode 22a.

[0062] Here, we will explain the case where the lengths of the main electrode joint 44a and the top solder 52 in the Y direction are the same. If the wettability of the top solder 52 is uneven between the main electrode 22a and the main electrode joint 44a, the fillet angle may be too steep. For example, the angle α of the fillet shape of the top solder 52 formed when the plate solder 52 is heated, as shown in FIG. 3, may be 45° or more, making it impossible to obtain an appropriate fillet shape. With such an top solder 52, it may not be possible to reliably maintain the expansion of the main electrode joint 44a in response to temperature changes.

[0063] In contrast, by using upper solder 52 that is longer in the Y direction than main electrode joint portion 44a, the likelihood of obtaining an appropriate fillet shape increases even when the wettability is uneven. For example, by making length B from the end of main electrode joint portion 44a to the end of upper solder 52 at least one time the thickness A from main electrode 22a to the front surface of the terminal opposite the joint surface of main electrode joint portion 44a, it is highly likely that a fillet shape with angle α of 25° or more and less than 45° will be obtained.

[0064] More specifically, when the minimum thickness of the upper solder 52 is 100 μm and the thickness of the main electrode joint portion 44a is 500 μm (i.e., when A=600 μm), the fillet shape with the angle α described above can be obtained by setting the length B to 600 μm or more. The main electrode joint portion 46a of the internal connection terminal 46 is joined to the main electrode 22b by a process similar to that described above.

[0065] Step S5: A wiring process is performed. In the wiring process, control electrodes 21a1-21a5, 21b1-21b5 (see FIG. 2) of semiconductor chips 20a, 20b of semiconductor unit 10a housed in case 30 are wired with bonding wires to the circuit board on the case 30 side. A similar process is performed for semiconductor units 10b, 10c.

[0066] Step S6: A sealing process is performed. In the sealing process, the semiconductor units 10a, 10b, and 10c housed in the housing portions 32a, 32b, and 32c of the case 30 are sealed with a sealing member. The sealing member may be a two-component resin containing a base agent and a curing agent. For example, an epoxy resin base agent and a curing agent such as a polyamine-based curing agent, an acid anhydride-based curing agent, a phenol-based curing agent, or a thiol-based curing agent may be used. For example, a dispenser supplies the base agent and the curing agent from separate tubes into the same syringe, mixes them, and dispenses them. Through the steps described above, the semiconductor device 1 is manufactured. Next, two modifications of the shape of the tip end surface of the main electrode joint portion 44a will be described.

[0067] [Variation 1] Fig. 10 is a plan view of a semiconductor unit 10 included in a semiconductor device according to the first modification of the embodiment. Fig. 11 is a front view showing the bonding portion between a semiconductor chip 20a included in the semiconductor device 10 according to the first modification of the embodiment and an N-connection terminal 44 and an insulating circuit board 11. In Figs. 10 and 11, the same elements as those shown in Figs. 2 and 4 are designated by the same reference numerals.

[0068] In the semiconductor device of Modification 1, main electrode joints 61a, 61b joined to main electrodes 22a, 22b have tip portions with shapes different from those of main electrode joints 44a, 46a shown in Fig. 2. In a plan view as shown in Fig. 10, one tip surface of main electrode joints 61a, 61b is inclined not over the entire tip surface of main electrode joints 61a, 61b in the X direction, but over inclined portions 62a, 62b intersecting with wiring portions 25a, 25b (see Fig. 2), as shown in Fig. 3.

[0069] Therefore, the front view shown in FIG. 11 differs from FIG. 4 in that the upper solder 52 appears to be more abundant in the inclined portion 62a that intersects the wiring portion 25a extending in the Y direction with the X direction than in other portions.

[0070] The semiconductor device of the first modification as described above also achieves the same effects as the semiconductor device 1. Specifically, by inclining the inclined portions 62a, 62b of the leading edge surfaces of the main electrode bonding portions 61a, 61b at an acute angle relative to the bonding surface, creeping up of the top solder 52 to the leading edge surface is suppressed. This increases the likelihood that the fillet shape of the top solder 52 can be maintained in the appropriate shape described above. Maintaining the fillet shape of the top solder 52 suppresses the main electrode bonding portion 44a from expanding in response to temperature changes, thereby reducing warping of the main electrode bonding portion 44a. As a result, stress on the semiconductor chip 20a directly below the leading edge of the main electrode bonding portion 44a is reduced. Furthermore, the stress relief effect of the top solder 52 can suppress distortion in the main electrodes 22a, 22b. This, in turn, can suppress failures of the wiring portions 25a, 25b, etc.

[0071] [Variation 2] Fig. 12 is a plan view of a semiconductor unit 10 included in a semiconductor device according to a second modification of the embodiment. Fig. 13 is a cross-sectional view showing a joint between a semiconductor chip 20a, an N-connection terminal 44, and an insulating circuit board 11 included in the semiconductor device according to the second modification of the embodiment. Fig. 13 is a cross-sectional view taken along dashed line XX in Fig. 12, and shows a cross section corresponding to the cross section shown in Fig. 3. In Figs. 12 and 13, the same elements as those shown in Figs. 2 and 3 are designated by the same reference numerals.

[0072] In the semiconductor device of variant 2, as in the semiconductor device of variant 1, the main electrode joints 71a and 71b joined to the main electrodes 22a and 22b have tip portions with shapes different from those of the main electrode joints 44a and 46a shown in FIG.

[0073] As shown in Fig. 12, recessed portions 72a, 72b are formed on one end surface of the main electrode joints 71a, 71b at locations where the main electrode joints 71a, 71b intersect with the wiring portions 25a, 25b (see Fig. 2) in a plan view. Note that the recessed portions 72a, 72b have a semicircular shape in a plan view. However, the recessed portions 72a, 72b are not limited to this, and may have a rectangular or triangular shape as long as they are recessed in a plan view. Furthermore, if the recessed portions 72a, 72b have a rectangular or triangular shape, the corners may be rounded.

[0074] In the example of Figure 13, the portion of the tip surface 71c of the main electrode joint 71a other than the recessed portion 72a is inclined at an acute angle with respect to the joint surface (shown by dotted lines), but the recessed portion 72a may also be inclined at an acute angle.

[0075] The semiconductor device of Modification 2 described above also achieves the same effects as those of Semiconductor Device 1. Specifically, by inclining the tip surfaces of the main electrode bonding portions 71a and 71b at an acute angle relative to the bonding surface, creeping up of the top solder 52 onto the tip surfaces is suppressed. This increases the likelihood that the fillet shape of the top solder 52 can be maintained in the appropriate shape described above. Maintaining the fillet shape of the top solder 52 suppresses the main electrode bonding portion 71a from expanding in response to temperature changes, thereby reducing warping of the main electrode bonding portion 71a. As a result, stress on the semiconductor chip 20a directly below the tip portion of the main electrode bonding portion 71a is reduced. This also reduces distortion of the main electrode 22a on the semiconductor chip 20a directly below the tip portion of the main electrode bonding portion 71a. The stress-relieving effect of the top solder 52 can suppress distortion of the main electrodes 22a and 22b. Furthermore, by providing the recessed portions 72a and 72b as described above, the influence of stress on the wiring portions 25a and 25b can be further suppressed.

[0076] As described above, the semiconductor device of the present invention has been described based on the embodiments. Place Although one aspect has been described, these are merely examples and are not intended to be limiting. [Explanation of symbols]

[0077] 1. Semiconductor device 10, 10a, 10b, 10c semiconductor unit 11 Insulated circuit board 12 Insulating plate 13, 13a, 13b Circuit pattern 14 Metal plate 20a, 20b Semiconductor chip 20a1 silicon substrate 20a2 trench layer 20a3 P-type well 20a4 Gate Runner 20a5 insulating layer 20a6 via 21a1, 21a2, 21a4, 21a5, 21b1, 21b2, 21b4, 21b5 Control electrodes 21a3, 21b3 Detection electrodes 22a,22b Main electrode 22a1 Plating Department 23a,23b Temperature sensing part 24a, 24b Thermosensor 25a,25b wiring section 30 cases 31 Frame 31a, 31c Frame length side 31b, 31d Short side of frame 32a, 32b, 32c storage section 32d, 32e Partition 33a,33b,33c P terminal 34a,34b,34c N terminal 35a U terminal 35b V terminal 35c W terminal 43 P connection terminal 44 N connection terminal 44a,46a,44a1,61a,61b,71a,71b Main electrode junction 44b Legs 44c,71c Tip surface 45 Output terminal 46 Internal connection terminal 51 Bottom solder 52 Top solder 62a,62b Sloped part 72a, 72b recessed portion

Claims

1. a semiconductor chip including a main electrode on a front surface thereof and a wiring portion provided on the main electrode and extending to an outer periphery of the main electrode; a connection terminal having a rectangular, flat plate shape in a plan view, including a joining portion having a joining surface, the connection terminal being joined to the main electrode at the joining surface via solder; Including, Among the four outer peripheral surfaces included in the joint portion, one tip surface located on the outer peripheral portion to which the wiring portion extends in a plan view is inclined at an acute angle with respect to the joint surface. Semiconductor device.

2. The solder covers the entire tip end surface without covering a front surface of the terminal on the opposite side of the inclined tip end surface of the joint portion. The semiconductor device according to claim 1 .

3. the semiconductor chip further includes a temperature sensing element provided on the main electrode, and a plating portion formed on the main electrode excluding the temperature sensing element and the wiring portion; 3. The semiconductor device according to claim 1.

4. The tip surface has a portion that intersects with the wiring portion in a plan view, the portion being inclined. The semiconductor device according to claim 3 .

5. the temperature-sensing element is provided in the center of the main electrode, and the wiring portion extends to the center of the outer periphery. The semiconductor device according to claim 4 .

6. a portion of the joint portion that intersects with the wiring portion in a plan view is recessed; 6. The semiconductor device according to claim 3.

7. The entire tip surface of the joint is inclined.

6. The semiconductor device according to claim 1.

8. When viewed from the side, an angle of a line connecting the tip end of the solder to the end of the tip surface on the front surface side of the terminal with respect to the joining surface is equal to or greater than 25° and less than 45°.

8. The semiconductor device according to claim 1.

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