Methods for forming structures for MRAM applications

Abstract

To provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures for use in hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications.SOLUTION: One or more magnetic tunnel junction structures 450 disposed on a substrate 402 comprise: a tunneling barrier layer 410; a first ferromagnetic layer 412 and a second ferromagnetic layer 408 between which the tunneling barrier layer is interposed; a spin orbit torque (SOT) layer 424 formed in a third insulating structure 420; and an additional interconnection structure 432 disposed on the SOT layer 424 and forming a back end structure.SELECTED DRAWING: Figure 4K

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to methods for fabricating structures used in magnetoresistive random access memory (MRAM) applications, and more particularly, to methods for fabricating magnetic tunnel junction structures for MRAM applications. [Background technology]

[0002] Magnetoresistive random access memory (MRAM) is a type of memory device that includes an array of MRAM cells that store data using resistance instead of electrical charge. Generally, each MRAM cell includes a magnetic tunnel junction (MTJ) structure. The MTJ structure can have a tunable resistance to represent a logic state "0" or "1." The MTJ structure typically includes a stack of magnetic layers, consisting of two ferromagnetic layers separated by a thin non-magnetic dielectric, such as an insulating tunnel layer. Top and bottom electrodes sandwich the MTJ structure, allowing current to flow between the top and bottom electrodes.

[0003] One ferromagnetic layer, e.g., the reference layer, is characterized by a magnetization with a fixed direction. The other ferromagnetic layer, e.g., the storage layer, is characterized by a change in the direction of magnetization when the device is written, such as by applying a magnetic field. In some devices, an insulator material, such as a dielectric oxide layer, may be formed as a thin tunnel barrier layer sandwiched between the ferromagnetic layers. These layers are typically deposited sequentially as overlying blanket films. The ferromagnetic layers and insulator material are then patterned by various etching processes, in which one or more layers are partially or completely removed to form device features.

[0004] When the magnetizations of the reference and storage layers are antiparallel, the resistance of the magnetic tunnel junction is high, with a resistance value R corresponding to a high logic state “1.” maxOn the other hand, when the magnetizations are parallel, the resistance of the magnetic tunnel junction is low, i.e., the resistance value R corresponds to the low logic state "0". min The logic state of an MRAM cell is determined by dividing its resistance by a reference resistance R ref This reference resistance R is read by comparing it with ref is derived from a reference cell or group of reference cells and represents a resistance value midway between a high logic state "1" and a low logic state "0".

[0005] Spin-transfer torque magnetic random access memory (STT MRAM) and spin-orbit torque magnetic random access memory (SOT MRAM) are different chip architectures with their own unique electrical performance and energy efficiency. Demand for hybrid and integrated spin-orbit torque magnetic random access memory (SOT-STT MRAM) has recently increased due to its combined advantages. However, how to fabricate SOT-STT MRAM with desirable production yield and well-integrated deposition scheme for magnetic tunnel junction (MTJ) structures remains a challenge.

[0006] Therefore, there is a need for improved methods and apparatus for fabricating MTJ structures for MRAM applications. Summary of the Invention

[0007] Embodiments of the present disclosure provide a method and apparatus for fabricating a magnetic tunnel junction (MTJ) structure on a substrate together with a back-end interconnect structure for MRAM applications, particularly hydride spin-orbit torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the interconnect structure includes a magnetic tunnel junction structure disposed on a substrate. The magnetic tunnel junction structure includes first and second ferromagnetic layers sandwiching a tunnel barrier layer, a spin-orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back-end structure disposed on the spin-orbit torque (SOT) layer.

[0008] In another embodiment, a method of forming an interconnect structure includes forming a film stack on a substrate, the film stack having a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunnel barrier layer; forming a patterned hard mask layer on the film stack; patterning the film stack using the patterned hard mask layer as an etch mask layer; forming a first insulating material to cover the patterned hard mask layer and the film stack on the substrate; polishing the first insulating material until a top surface of the hard mask layer is exposed; forming a spin-orbit torque (SOT) layer on the top surface of the hard mask layer; and forming a back-end interconnect structure on the spin-orbit torque (SOT) layer.

[0009] In yet another embodiment, an interconnect structure for a memory device includes a plurality of magnetic tunnel junction structures connected to SOT layers, where the magnetic tunnel junction structures have capping layers fabricated from the same material as the SOT layers connecting the SOT layers and dual damascene back-end structures connected to the SOT layers.

[0010] So that the foregoing features of the present disclosure can be understood in detail, a more particular description of the disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] An embodiment of a cluster processing system for implementing an embodiment of the present disclosure [Figure 2] Another embodiment of a cluster processing system for implementing an embodiment of the present disclosure [Figure 3] 1 is a flow diagram illustrating a method for fabricating a magnetic tunnel junction (MTJ) structure together with a back-end interconnect structure according to one embodiment of the present disclosure. [Figure 4A] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4B] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4C] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4D] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4E] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4F] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4G] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4H] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4I] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4J] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 4K] 4A and 4B are cross-sectional views of a substrate at various stages of the method of FIG. 3; [Figure 5] 1 is a cross-sectional view of another example magnetic tunnel junction (MTJ) structure with a back-end interconnect structure formed on a substrate; [Figure 6] 1 is a cross-sectional view of yet another example of a magnetic tunnel junction (MTJ) structure with a back-end interconnect structure formed on a substrate; [Figure 7] 4A-4I, 5, or 6. FIG. 6 is a cross-sectional view of an example of a magnetic tunnel junction (MTJ) structure used in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] To facilitate understanding, wherever possible, like reference numerals are used to designate like elements common to the figures, and it is contemplated that elements disclosed in one embodiment can be beneficially utilized in other embodiments without specific recitation.

[0013] It should be noted, however, that the present disclosure may also allow for other equally effective embodiments, and therefore the accompanying drawings illustrate only typical embodiments of the disclosure and should not be considered as limiting the scope of the disclosure.

[0014] Embodiments of the present disclosure generally provide apparatus and methods for forming an MTJ structure and a back-end interconnect structure electrically connected to the MTJ structure disposed on a substrate for MRAM applications. The embodiments of the present disclosure can be used for spin-transfer torque magnetic random access memory (STT MRAM), spin-orbit torque magnetic random access memory (SOT MRAM), and / or hybrid (also called integrated) spin-orbit torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, a hard mask can be utilized while patterning a film stack to form the MTJ structure. Such a hard mask layer can be the same material as a spin-orbit torque (SOT) layer disposed on the MTJ structure. In some examples, the hard mask layer can also function as the spin-orbit torque (SOT) layer when the MTJ structure is patterned and formed. After the MTJ structure and the SOT layer thereon are formed, a back-end (e.g., single damascene or dual damascene) interconnect structure can be formed on the SOT layer such that the back-end interconnect structure is in electrical communication with the MTJ structure. A chemical mechanical polishing process (CMP) can be used to form the MTJ structure and the back-end interconnect structure. The MTJ structure and the back-end interconnect structure can be integrally formed in a cluster processing system without removing the substrate from the system and without breaking vacuum. In some examples, multiple MTJ structures can be connected to a SOT layer that is further electrically connected to a back-end (e.g., single damascene or dual damascene) interconnect structure.

[0015] 1 is a schematic top view of an exemplary cluster processing system 100 including one or more of processing chambers 111, 121, 132, 128, 120 incorporated and integrated therein. In one embodiment, cluster processing system 100 may be a Centura® or Endura® integrated processing system commercially available from Applied Materials, Inc. of Santa Clara, Calif. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from the present disclosure.

[0016] The cluster processing system 100 includes a vacuum-tight processing platform 104, a factory interface 102, and a system controller 144. The platform 104 includes multiple processing chambers 111, 121, 132, 128, 120 and at least one load lock chamber 122 coupled to a vacuum substrate transfer chamber 136. Two load lock chambers 122 are shown in Figure 1. The factory interface 102 is coupled to the transfer chamber 136 by the load lock chamber 122.

[0017] In one embodiment, the factory interface 102 includes at least one docking station 108 and at least one factory interface robot 114 to facilitate transfer of substrates. The docking station 108 is configured to receive one or more front-opening unified pods (FOUPs). Two FOUPs 106A-B are shown in the embodiment of FIG. 1 . The factory interface robot 114, having a blade 116 disposed at one end of the robot 114, is configured to transfer substrates from the factory interface 102 to the processing platform 104 for processing via a load lock chamber 122. Optionally, one or more metrology stations 118 can be connected to terminals 126 of the factory interface 102 to facilitate measurements of substrates from the FOUPs 106A-B.

[0018] Each of the load lock chambers 122 has a first port coupled to the factory interface 102 and a second port coupled to the transfer chamber 136. The load lock chambers 122 are coupled to a pressure control system (not shown) that pumps down and vents the load lock chambers 122 to facilitate passage of substrates between the vacuum environment of the transfer chambers 136 and the substantially ambient (e.g., atmospheric) environment of the factory interface 102.

[0019] The transfer chamber 136 has a vacuum robot 130 disposed therein. The vacuum robot 130 has a blade 134 capable of transferring substrates 124 between the load lock chamber 122, the metrology system 110, and the processing chambers 111, 121, 132, 128, and 120.

[0020] In one embodiment of the cluster processing system 100, the cluster processing system 100 can include one or more processing chambers 111, 121, 132, 128, 120, which can be a deposition chamber (e.g., a physical vapor deposition chamber, a chemical vapor deposition chamber, or other deposition chamber), an annealing chamber (e.g., a high-pressure annealing chamber, an RTP chamber, a laser annealing chamber), an etch chamber, a cleaning chamber, a curing chamber, a lithography exposure chamber, or other similar type of semiconductor processing chamber. In some embodiments of the cluster processing system 200, at least one of one or more of the processing chambers 111, 121, 132, 128, 120, the transfer chamber 136, the factory interface 102, and / or the load lock chamber 122.

[0021] A system controller 144 is coupled to the cluster processing system 100. The system controller 144, which may include the computing device 101 or may be included within the computing device 101, controls the operation of the cluster processing system 100 using direct control of the processing chambers 111, 121, 132, 128, 120 of the cluster processing system 100. Alternatively, the system controller 144 may control computers (or controllers) associated with the processing chambers 111, 121, 132, 128, 120 and the cluster processing system 100. During operation, the system controller 144 also enables data collection and feedback from each chamber to optimize performance of the cluster processing system 100.

[0022] System controller 144, similar to computing device 101 described above, generally includes a central processing unit (CPU) 138, memory 140, and support circuits 142. CPU 138 may be any form of general-purpose computer processor that can be used in an industrial environment. Support circuits 142 are conventionally coupled to CPU 138 and may include cache, clock circuits, input / output subsystems, power supplies, etc. Software routines transform CPU 138 into a special-purpose computer (controller) 144. Software routines may also be stored and / or executed by a second controller (not shown) located remotely from cluster processing system 100.

[0023] 2 is a plan view of another example of a cluster processing system 200 in which the methods described herein may be implemented. One processing system that may be adapted to benefit from the present disclosure is a 300 mm or 450 mm PRODUCER® processing system, commercially available from Applied Materials, Inc., Santa Clara, Calif., USA. The cluster processing system 200 generally includes a front platform 202 on which substrate cassettes 218 contained in FOUPs 214 are supported and from which substrates are loaded and unloaded into and from load lock chambers 209, a transfer chamber 211 that houses a substrate handler 213, and a series of tandem processing chambers 206 attached to the transfer chamber 211.

[0024] Each of the tandem processing chambers 206 includes two processing regions for processing substrates. The two processing regions share a common gas supply, common pressure control, and a common process gas exhaust / pumping system. The modular design of the system allows for rapid conversion from one configuration to any other. The arrangement and combination of chambers can be varied to perform specific processing steps. Any of the tandem processing chambers 206 can include a lid according to aspects of the present disclosure, described below, including one or more chamber configurations. It should be noted that the cluster processing system 200 can be configured to perform deposition processes, etching processes, curing processes, lithography exposure processes, or heating / annealing processes, as desired.

[0025] In one implementation, cluster processing system 200 can be adapted to one or more tandem processing chambers with supporting chamber hardware known to accommodate a variety of other known processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, etching, curing, lithography exposure, or heating / annealing processes. For example, cluster processing system 200 can be configured with one of processing chambers 206 as a chemical vapor deposition processing chamber or physical vapor deposition chamber for forming a passivation layer, or a metal-containing dielectric layer, metal layer, or insulating material formed on a substrate. Such a configuration can enhance R&D manufacturing utilization and, if desired, substantially eliminate exposure of etched films to the atmosphere.

[0026] To facilitate control of the processes of the present disclosure, a controller 240 including a central processing unit (CPU) 244, memory 242, and support circuits 246 are coupled to the various components of the cluster processing system 200. The memory 242 can be any computer-readable medium, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote to the cluster processing system 200 or the CPU 244. The support circuits 246 are coupled to the CPU 244 for supporting the CPU in a conventional manner. These circuits include cache, power supplies, clock circuits, input / output circuits and subsystems, etc. A software routine or series of program instructions stored in the memory 242, when executed by the CPU 244, runs the tandem processing chamber 206.

[0027] FIG. 3 is a flow diagram illustrating a process 300 for fabricating an MTJ structure and a back-end interconnect structure on a substrate for MRAM applications according to one embodiment of the present disclosure. It should be noted that the process 300 for fabricating an MTJ structure and a back-end interconnect structure can be utilized for spin-transfer torque magnetic random access memory (STT MRAM), spin-orbit torque magnetic random access memory (SOT MRAM), and / or hybrid (also called integrated) spin-orbit torque magnetic spin transfer torque magnetic random access memory (SOT-STT MRAM) applications, particularly hybrid (also called integrated) spin-orbit torque magnetic spin transfer torque magnetic random access memory (SOT-STT MRAM) applications. FIGS. 4A-4K are schematic cross-sectional views of an interconnect structure 450 formed on a substrate 402 at various stages of the process of FIG. 3 . It is contemplated that the process 300 can be performed in any suitable processing chamber, including a deposition chamber, an etch chamber, or any other suitable processing chamber incorporated into the cluster processing systems 100 or 200 shown in FIGS. 1 and 2 . It should also be noted that the process 300 can be performed in any suitable processing chamber, including those from other manufacturers.

[0028] The process 300 begins at operation 302 by providing a substrate, such as substrate 402 having a first interconnect structure 407 formed within a first insulating structure 404, as shown in FIG. 4A. The first interconnect structure 407 and the first insulating structure 404 may be formed within one or more processing chambers incorporated into the cluster processing systems 100 or 200 shown in FIGS. 1 and 2. In one embodiment, the substrate 402 may be formed from a metal or glass, silicon, a dielectric bulk material, and a metal alloy or composite glass, crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, including silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 402 may have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameters, and may be a rectangular or square panel. Unless otherwise specified, the examples described herein are implemented on substrates with a diameter of 200 mm, 300 mm, or 450 mm. In one embodiment, the substrate 402 includes a first interconnect structure 407 formed within a first insulating structure 404 disposed on the substrate 402, as shown in FIG. 4A.

[0029] The first insulating structure 404 may include a dielectric material such as SiN, SiCN, SiO2, SiON, SiC, amorphous carbon, SiOC, or other suitable low-k material. The first interconnect structure 407 includes a metal-containing material such as aluminum, tungsten, copper, nickel, etc. In one example, the first insulating structure 404 includes a low-k dielectric material such as SiOC, and the first interconnect structure 407 includes copper.

[0030] In operation 304, as shown in FIG. 4B, a film stack 406 and a hard mask layer 414 are disposed on the substrate 402. The film stack 406 and the hard mask layer 414 may be formed in one or more processing chambers incorporated into the cluster processing systems 100 or 200 shown in FIGS. 1 and 2. The film stack 406 further includes a first ferromagnetic layer 412 and a second ferromagnetic layer 408 sandwiching a tunnel barrier layer 410. It should be noted that while the film stack 406 depicted in FIGS. 4B-4K includes only three layers, additional or multiple film layers may be further formed in the film stack 406, as desired. One example of additional or multiple film layers formed in the film stack 406 is further described below with reference to FIG. 7. The tunnel barrier layer 410 may be an oxide barrier layer in the case of a tunnel junction magnetoresistive (TMR) sensor or a conductive layer in the case of a giant magnetoresistive (GMR) sensor. When the film stack 406 is configured to form a TMR sensor, the tunnel barrier layer 410 may be made of any of a variety of materials, including MgO, HfO2, TiO2, TaO x , Al2O3, or other suitable materials. In the embodiment shown in Figures 4B-4K, the tunnel barrier layer 410 may include MgO having a thickness of about 1 to about 15 angstroms, such as about 10 angstroms.

[0031] The first and second ferromagnetic layers 412, 408 can be metal-containing or magnetic materials, such as Mo, Ir, Ru, Ta, MgO, Hf, CoFe, CoFeB, etc. It should be noted that the first and second ferromagnetic layers 412, 408 can be fabricated from the same material or different materials, as desired.

[0032] A hard mask layer 414 is disposed on the film stack 406 and is later utilized as an etch mask layer during subsequent patterning and / or etching processes. The hard mask layer 414 is formed from a material similar to or the same as the spin-orbit torque (SOT) layer 424 (shown in FIG. 4I) that will be later formed thereon. In one example, the hard mask layer 414 is fabricated from CoFeB, MgO, Ta, W, Pt, CuBi, Mo, Ru, alloys thereof, or combinations thereof.

[0033] In operation 304, a patterning process, e.g., an etching process, is first performed to pattern the hard mask layer 414 and form opening regions 416 in the hard mask layer 414, as shown in FIG. 4C. The first patterning process can be performed in one or more processing chambers incorporated into the cluster processing systems 100 or 200 shown in FIGS. 1 and 2. The opening regions 416 formed in the hard mask layer 414 expose portions of the film stack 406 for patterning to form magnetic tunnel junction (MTJ) structures 452 (shown in FIG. 4D) having desired dimensions from the film stack 406.

[0034] In operation 308, a second patterning process is performed to pattern (e.g., etch) the film stack 406 exposed by the patterned hard mask layer 414 until the underlying first insulating material 404 is exposed, as shown in FIG. 4D , to form a magnetic tunnel junction (MTJ) structure 452. The second patterning process can be performed in one or more processing chambers incorporated into the cluster processing system 100 or 200 shown in FIGS. 1 and 2 . Note that the patterned hard mask layer 414 remains on the film stack 406 and is intended to be formed as part of the magnetic tunnel junction (MTJ) structure 452 after the patterning process performed in operation 308. Therefore, no additional ashing or stripping process is required to remove the hard mask layer 414 after the second patterning process. The second patterning process for patterning the film stack 406 can include several steps or different strategies configured to supply different gas mixtures or etchants to etch different layers according to the materials contained in each layer.

[0035] During patterning, an etching gas mixture or several gas mixtures with different etching species are sequentially supplied to the substrate surface to remove portions of the film stack 406 exposed by the patterned hard mask layer 414 from the substrate 402.

[0036] The endpoint of the patterning process in operation 308 can be controlled by time or other suitable methods. For example, the patterning process can be terminated after running for about 200 seconds to about 10 minutes until the underlying first insulating material 404 is exposed, as shown in FIG. 4D. The patterning process can be terminated, if desired, by a determination from an endpoint detector, such as an OES detector or other suitable detector.

[0037] It should be noted that although the profile of the magnetic tunnel junction (MTJ) structure 452 formed after patterning the film stack 406 has tapered sidewalls, the magnetic tunnel junction (MTJ) structure 452 may have a substantially vertical sidewall profile or any suitable sidewall profile with a desired slope as needed.

[0038] In operation 310, after the patterning process, a deposition process is performed to form a second insulating structure 418 (e.g., including the patterned hard mask layer 414 and the patterned film stack 406) on the magnetic tunnel junction (MTJ) structure 452, as shown in FIG. 4E. The second insulating structure 418 may be formed in one or more processing chambers incorporated into the cluster processing system 100 or 200 shown in FIGS. 1 and 2. The second insulating structure 418 is formed to have a thickness sufficient to cover the magnetic tunnel junction (MTJ) structure 452. The second insulating structure 418 may be a dielectric layer formed by a deposition process performed after the patterning process in operation 308. The second insulating structure 418 may be the same as or similar to the first insulating structure 404. In one example, the second insulating structure 418 includes a low-k material including SiOC.

[0039] In operation 312, a chemical-mechanical polishing process is performed to polish away excess second insulating structures 418 to expose top surfaces 435 of the magnetic tunnel junction (MTJ) structures 452 (e.g., top surfaces 435 of the patterned hard mask layer 414), as shown in FIG. 4F , such that the top surfaces 435 of the patterned hard mask layer 414 are substantially coplanar with the second insulating structures 418. The CMP process performed can remove excess second insulating structures 418 without adversely affecting or over-polishing nearby materials when the magnetic tunnel junction (MTJ) structures 452 are exposed. By using a relatively low polishing down force and a slow polishing rate, the second insulating structures 418 can be removed from the magnetic tunnel junction (MTJ) structures 452 without damaging or over-polishing the material.

[0040] The chemical mechanical polishing process can remove or polish the second insulating structure 418 by using a fluid supplied during the polishing process or by DI water. A relatively soft polishing pad, such as a pad with an elasticity of greater than 90%, can be used during the chemical mechanical polishing process. The selected polishing pad has a relatively soft surface during polishing and therefore may displace slurry or other chemical fluids, if desired. In one example, DI water can be utilized during the chemical mechanical polishing process. After the chemical mechanical polishing process, a cleaning process is optionally performed to enhance the cleanliness of the substrate surface.

[0041] In operation 314, as shown in FIG. 4G, a third insulating structure 420 is formed on the magnetic tunnel junction (MTJ) structure 452 and the second insulating structure 418. The third insulating structure 420 may be formed in one or more processing chambers incorporated into the cluster processing system 100 or 200 shown in FIGS. 1 and 2. Similarly, the third insulating structure 420 may be formed from any suitable deposition technique, such as CVD, ALD, PVD, spin coating, spray coating, or any suitable deposition process. The third insulating structure 420 may be the same as or similar to the first or second insulating structures 404, 418. In one example, the third insulating structure 420 includes a low-k material including SiOC.

[0042] In operation 316, another patterning process is performed to form openings 422 in the third insulating structure 420 to expose the top surfaces 435 of the magnetic tunnel junction (MTJ) structures 452, as shown in FIG. 4H. The patterning process can be performed in one or more processing chambers incorporated into the cluster processing systems 100 or 200 shown in FIGS. 1 and 2. One or more patterning masks (not shown) can be utilized to assist in the formation of the openings 422 in the third insulating structure 420. The patterning process is performed to pattern the third insulating structure 420 until the top surfaces 435 of the magnetic tunnel junction (MTJ) structures 452 are exposed.

[0043] In operation 318, a deposition process is performed to form a spin-orbit torque (SOT) layer 424 on the substrate and fill the openings 422 defined in and above the third insulating structure 420, as shown in FIG. 4I. The deposition process can be performed in one or more processing chambers incorporated into the cluster processing systems 100 or 200 shown in FIGS. 1 and 2. The material of the spin-orbit torque (SOT) layer 424 is selected to be similar or identical to that of the hard mask layer 414 to promote the electrical performance of the magnetic tunnel junction (MTJ) structure 452. Furthermore, because the materials of the spin-orbit torque (SOT) layer 424 and the hard mask layer 414 are similar or identical, adhesion control at the interface between the spin-orbit torque (SOT) layer 424 and the hard mask layer 414 is relatively easy and compatible, reducing manufacturing concerns or complexity. The hard mask layer 414 left in the magnetic tunnel junction (MTJ) structure 452 can also function as a capping layer to provide good electrical contact to the spin-orbit torque (SOT) layer 424. In one embodiment, the spin-orbit torque (SOT) layer 424 is fabricated from Ta, Ru, MgO, W, Pt, CuBi, Mo, or a combination thereof.

[0044] In operation 320, a chemical-mechanical polishing process is further performed to polish away excess spin-orbit torque (SOT) layer 424 such that a top surface 425 of the spin-orbit torque (SOT) layer 424 is substantially flush with a top surface 426 of the third insulating structure 420, as shown in FIG. 4J. The CMP process performed can remove excess spin-orbit torque (SOT) layer 424 without adversely affecting nearby material or over-polishing, such that the excess spin-orbit torque (SOT) layer 424 can fill the third insulating structure 420 with the desired dimensions to provide electrical connection to the underlying magnetic tunnel junction (MTJ) structure 452. By using a relatively low polishing down force and a slow polishing rate, the excess spin-orbit torque (SOT) layer 424 can be removed without damaging or over-polishing material from the magnetic tunnel junction (MTJ) structure 452 and the third insulating structure 420.

[0045] After the SOT layer 424 is formed in the third insulating structure 420, an additional interconnect structure 432 is formed on the spin-orbit torque (SOT) layer 424 to provide electrical connection and / or communication to the magnetic tunnel junction (MTJ) structure 452, as shown in FIG. 4K. The additional interconnect structure 432 is also formed in the fourth insulating structure 430 to form a back-end structure. The additional interconnect structure 432 formed in the fourth insulating structure 430 is a single damascene structure. It should be noted that the additional interconnect structure may be formed in other forms, such as a dual damascene structure or other suitable structure.

[0046] FIG. 5 illustrates another example of an interconnect structure 550 formed on a substrate 402. Similar to the interconnect structure 450 illustrated in FIG. 4K, the interconnect structure 550 includes a first interconnect structure 407 formed in a first insulating structure 404, a magnetic tunnel junction (MTJ) structure 452 formed on the first interconnect structure 407, and a SOT layer 424 formed on the magnetic tunnel junction (MTJ) structure 452. However, the SOT layer 424 in this example illustrated in FIG. 5 has a relatively long width that allows for the formation of two additional upper interconnect structures 504 a, 504 b thereon. The two upper interconnect structures 504 a, 504 b each have a first conductive line 506 a, 506 b connecting to the SOT layer 424 and a second conductive line 508 a, 508 b connecting to the two lower interconnect structures 502 a, 502 b, respectively. As used herein, the upper interconnect structures 504a, 504b are dual damascene structures. The two upper interconnect structures 504a, 504b are in direct contact with and electrically connect / communicate with the two lower interconnect structures 502a, 502b via second conductive lines 508a, 508b. The first interconnect structure 407 and the magnetic tunnel junction (MTJ) structure 452 may be vertically interposed between the two upper interconnect structures 504a, 504b and the two lower interconnect structures 502a, 502b, as shown in FIG. 5 .

[0047] 6 illustrates yet another example of an interconnect structure 650 formed on a substrate 402. The interconnect structure 650 includes multiple, e.g., three, magnetic tunnel junction (MTJ) structures 452a, 452b, and 452c, each formed on a lower interconnect structure 602a, 602b, and 602c. The SOT layer 424 has a relatively long width to allow two additional upper interconnect structures 640a, 640b to be formed on the SOT layer 424. In this example, the upper interconnect structures 640a, 640b are not in direct contact with the lower interconnect structures 602a, 602b, and 602c. Instead, the upper interconnect structures 640a, 640b are electrically connected / communicating with the lower interconnect structures 602a, 602b, and 602c via the SOT layer 424 and the three magnetic tunnel junction (MTJ) structures 452a, 452b, and 452c interposed therebetween. Utilizing multiple magnetic tunnel junction (MTJ) structures 452a, 452b, 452c and interconnect structures 602a, 602b, 602c, 640a, 640b can improve electrical performance and increase device density.

[0048] FIG. 7 shows another example of a magnetic tunnel junction (MTJ) 702. The magnetic tunnel junction (MTJ) 702 can also be utilized as the magnetic tunnel junction (MTJ) 452 shown in FIGS. 4K, 5, and 6. The magnetic tunnel junction (MTJ) 702 includes the film stack 406 shown above, with a first ferromagnetic layer 412 and a second ferromagnetic layer 408 sandwiching a tunnel barrier layer 410. In addition to the film stack 406, a seed layer 710 can be formed at the bottom of the magnetic tunnel junction (MTJ) 702. Materials can be used to form the seed layer 710, including NiCr, Pt, Cr, CoFeB, Ta, Ru, TaN, alloys, or combinations thereof. A pinning layer 708 can be formed on the seed layer 710. The pinning layer 708 can include one or more of several types of pinning layers, such as a simple pinned, antiparallel pinned, self-pinned, or antiferromagnetic pinned sensor. 7, the pinned layer 708 includes multiple layers, for example, four layers. It should be noted that the number of pinned layers 708 may be any number as desired. The pinned layer 708 may be composed of a number of magnetic materials, such as a metal alloy, including a dopant, such as a boron dopant, an oxygen dopant, or other suitable material. The metal alloy may be a nickel-containing material, a platinum-containing material, a Ru-containing material, a cobalt-containing material, a tantalum-containing material, and a palladium-containing material. Suitable examples of magnetic materials that may comprise the pinned layer 708 include Ru, Ta, Co, Pt, Ni, TaN, NiFeO x , NiFeB, CoFeO x B, CoFeB, CoFe, NiO x B. CoBO x ,FeBO x , CoFeNiB, CoPt, CoPd, TaO x These include:

[0049] A Ruderman-Kittel-Kasuya-Yoshida (RKKY) layer 706 (also called a coupling layer) may be disposed on the pinned layer 708 below the film stack 406. The RKKY layer 706 may be formed to control the spin direction in the magnetic tunnel junction (MTJ) 702. Materials utilized in fabricating the RKKY layer 706 include Ir, Ru, Ta, W, Mo, alloys thereof, or combinations thereof.

[0050] A capping layer 704 may be formed on the film stack 406. In the example shown above, the capping layer 704 may be the patterned hard mask layer 414 described above with reference to FIGS. 4I, 5, and 6. In some examples, additional capping layers may be formed on the film stack 406, the patterned hard mask layer 414, or other suitable locations within the magnetic tunnel junction (MTJ) 702, as needed. Suitable examples of the capping layer 704 (or patterned hard mask layer 414) include one or more layers of one or more of CoFeB, MgO, Ta, W, Pt, CuBi, Mo, Ru, alloys thereof, and combinations thereof. In one example, the film stack 710 includes multiple layers, including, in total, TaN, NiCr, Co, Ni, Ir, Co or Ni, Mo, CoFeB, MgO, CoFeB, Mo, CoFeB, MgO, CoFeB, Mo, and Ru layers.

[0051] In the example shown in Figure 7, all of these layers or film stacks 710, 708, 706, 406, 704 may be formed by any suitable technique, such as CVD, PVD, ALD, spin coating, spray coating, and any suitable method. Examples of systems that can be used to form these layers include the CENTURA®, PRECISION5000®, and PRODUCER® deposition systems, all of which are available from Applied Materials Inc., Santa Clara, California, USA, or other manufacturers. It is contemplated that other processing systems, including those available from other manufacturers, may be adapted to practice the present disclosure. It should be noted that all of these layers and film stacks 710, 708, 706, 406, 704 in the magnetic tunnel junction (MTJ) 702 may be formed in one or more processing chambers incorporated into the cluster processing systems 100, 200 shown in Figures 1 and 2.

[0052] Thus, a process and apparatus for forming an MTJ device structure for MRAM, particularly for hybrid (also called integrated) spin-orbit torque magnetic random access memory (SOT-STT MRAM) applications, are provided. In one embodiment, a hard mask can be utilized while patterning a film stack to form the MTJ structure. Such a hard mask layer can be the same material as a spin-orbit torque (SOT) layer disposed on the MTJ structure. In some examples, the hard mask layer can also function as the spin-orbit torque (SOT) layer when the MTJ structure is patterned and formed. After the MTJ structure and the SOT layer thereon are formed, a back-end (e.g., single damascene or dual damascene) interconnect structure can be formed on the SOT layer such that the back-end interconnect structure electrically communicates with the MTJ structure. Multiple back-end and MTJ structures can be utilized to improve the density and electrical performance of MRAM devices.

[0053] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. 1. A method of forming an interconnect structure, comprising: forming a film stack on a substrate, the film stack including a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunnel barrier layer; forming a patterned hard mask layer over the film stack; patterning the film stack using the patterned hard mask layer as an etch mask layer; forming a first insulating material to cover the patterned hard mask layer and the film stack on the substrate; polishing the first insulating material until a top surface of the patterned hard mask layer is exposed; forming a spin-orbit torque (SOT) layer on top of the patterned hard mask layer; and forming a first back-end interconnect structure on the SOT layer; Including, forming the SOT layer, forming a patterned insulating layer having openings exposing the patterned hard mask layer; and forming the SOT layer in the opening; Including, The method includes polishing the SOT layer and the patterned insulating layer so that a top surface of the SOT layer is substantially coplanar with the patterned insulating layer. The method further comprises:

2. The method of claim 1 , wherein the combination of the film stack and the patterned hard mask layer forms a magnetic tunnel junction structure.

3. 10. The method of claim 1, wherein the SOT layer is made of the same material as the patterned hard mask layer.

4. 10. The method of claim 1, wherein the SOT layer and the patterned hard mask layer are made of a material selected from the group consisting of CoFeB, MgO, Ta, W, Pt, CuBi, Mo, and Ru.

5. 10. The method of claim 1, wherein the first back-end interconnect structure is a dual damascene structure.

6. The method of claim 1, wherein patterning the film stack using the patterned hard mask layer as an etching mask layer forms at least three magnetic tunnel junction structures comprising the patterned hard mask layer and the film stack.

7. The method of claim 6, further comprising forming two or more back-end interconnection structures including the first back-end interconnection structure by forming at least one more back-end interconnection structure in addition to the first back-end interconnection structure on the SOT layer, wherein the number of the two or more back-end interconnection structures is less than the number of the at least three magnetic tunnel junction structures.

8. The method of claim 1 , wherein a lower interconnect structure is connected to the film stack.

9. The method of claim 8 , wherein the first back-end interconnect structure is connected to the lower interconnect structure.

10. The method of claim 1 , further comprising forming a second back-end interconnect structure on the SOT layer.

11. forming a film stack on a substrate, the film stack including a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunnel barrier layer; forming a patterned hard mask layer over the film stack; patterning the film stack using the patterned hard mask layer as an etch mask layer; forming a first insulating material to cover the patterned hard mask layer and the film stack on the substrate; polishing the first insulating material until a top surface of the patterned hard mask layer is exposed; forming a spin-orbit torque (SOT) layer on top of the patterned hard mask layer; and forming a first back-end interconnect structure on the SOT layer; one or more processing chambers configured to perform forming the SOT layer, forming a patterned insulating layer having openings exposing the patterned hard mask layer; and forming the SOT layer in the opening; Including, The one or more processing chambers include: a processing system further configured to polish the SOT layer and the patterned insulating layer so that a top surface of the SOT layer is substantially coplanar with the patterned insulating layer.

12. 12. The processing system of claim 11, wherein the combination of the film stack and the patterned hard mask layer forms a magnetic tunnel junction structure.

13. 12. The processing system of claim 11, wherein said SOT layer is fabricated from the same material as said patterned hard mask layer.

14. 12. The processing system of claim 11, wherein said SOT layer and said patterned hard mask layer are fabricated from a material selected from the group consisting of CoFeB, MgO, Ta, W, Pt, CuBi, Mo, and Ru.

15. 12. The processing system of claim 11, wherein said first back-end interconnect structure is a dual damascene structure.

16. The processing system of claim 11, wherein patterning the film stack using the patterned hard mask layer as an etching mask layer forms at least three magnetic tunnel junction structures comprising the patterned hard mask layer and the film stack.

17. The processing system of claim 16, further comprising forming two or more backend interconnection structures including the first backend interconnection structure by forming at least one more backend interconnection structure in addition to the first backend interconnection structure on the SOT layer, wherein the number of the two or more backend interconnection structures is less than the number of the at least three magnetic tunnel junction structures.

18. The processing system of claim 11 , wherein a lower interconnect structure is connected to the film stack.

19. 20. The processing system of claim 18, wherein the first back-end interconnect structure is connected to the lower interconnect structure.

20. 12. The processing system of claim 11, wherein the one or more processing chambers are further configured to form a second back-end interconnect structure on the SOT layer.

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