Display substrate and manufacturing method thereof, display device

Abstract

The display substrate includes a display area and a non-display area. A gate driving circuit is disposed in the non-display area, the gate driving circuit including a plurality of cascaded shift register units, the shift register units being connected to at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected to the first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on a side of the second output circuit away from the first group of clock signal lines.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as autonomous light emission, wide viewing angles, high contrast ratios, low power consumption, extremely fast response times, light weight, flexibility, and low cost. With the continuous development of display technology, flexible displays, which use OLEDs or QLEDs as light-emitting devices and thin film transistors (TFTs) for signal control, have become a major product in the current display field. Summary of the Invention [Means for solving the problem]

[0003] The following is a summary of the subject matter described in this specification, which does not limit the scope of protection of the claims.

[0004] The embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area. A gate driving circuit is installed in the non-display area. The gate driving circuit includes a plurality of cascaded shift register units, each connected to at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on a side of the second output circuit away from the first group of clock signal lines.

[0006] In some exemplary embodiments, the at least one power supply line includes a first power supply line and a second power supply line. The first power supply line is connected to a first output circuit, and the second power supply line is connected to a second output circuit. In the first direction, the first power supply line is located between the first output circuit and a first group of clock signal lines, and the second power supply line is located between the first group of clock signal lines and the second output circuit.

[0007] In some exemplary embodiments, a third power line and a fourth power line are further installed in the non-display area, the third power line being connected to a second output circuit, and the fourth power line being connected to a first output circuit, the fourth power line being located on a side of the first output circuit away from the first power line, and the third power line being located between the second power line and a second group of clock signal lines.

[0008] In some exemplary embodiments, an initial signal line is further disposed in the non-display area, and the initial signal line is located on a side of the fourth power line that is farther from the first output circuit in the first direction.

[0009] In some exemplary embodiments, the first output circuit includes a first node control subcircuit, a second node control subcircuit, and a first output subcircuit. The first node control subcircuit is connected to an input terminal, a first output terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, a first node, and a second node, and is configured to control the potentials of the first node and the second node under control of the first clock terminal, the third clock terminal, and the input terminal. The second node control subcircuit is connected to the first node, the second node, the second power supply terminal, and a first output terminal, and is configured to maintain the potentials of the first node and the second node. The first output subcircuit is connected to the first node, the second node, the second clock terminal, the second power supply terminal, and a first output terminal, and is configured to control output of a first output signal from the first output terminal under control of the first node and the second node. The second node control subcircuit, the first output subcircuit, and the first node control subcircuit are sequentially arranged along a first direction.

[0010] In some exemplary embodiments, the first node control subcircuit includes a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor. The first control transistor has a control pole connected to a first clock terminal, a first pole connected to an input terminal, and a second pole connected to a fourth node. The second control transistor has a control pole connected to the first clock terminal, a first pole connected to the fourth node, and a second pole connected to the first node. The third control transistor has a control pole connected to a third clock terminal, a first pole connected to a first power supply terminal, and a second pole connected to a second node. The fourth control transistor has a control pole connected to the second node, a first pole connected to a second power supply terminal, and a second pole connected to a third node. The fifth control transistor has a control pole connected to the second node, a first pole connected to the third node, and a second pole connected to the first node. The sixth control transistor has a control pole connected to the first node, a first pole connected to the first power supply terminal, and a second pole connected to the third node. The seventh control transistor has a control pole connected to the input terminal, a first pole connected to the second power supply terminal, and a second pole connected to the second node. The eighth control transistor has a control pole connected to the first output terminal, a first pole connected to the second clock terminal, and a second pole connected to the fourth node. The second node control subcircuit includes a first capacitor and a second capacitor. The first capacitor has a first electrode connected to the first node and a second electrode connected to the first output terminal. The second capacitor has a first electrode connected to the second node and a second electrode connected to the second power supply terminal. The first output subcircuit includes a first output transistor and a second output transistor. The first output transistor has a control pole connected to the first node, a first pole connected to the second clock terminal, and a second pole connected to the first output terminal. The second output transistor has a control electrode connected to the second node, a first electrode connected to the second power supply terminal, and a second electrode connected to the first output terminal.

[0011] In some exemplary embodiments, the first capacitor and the first output transistor are adjacent in the first direction, the second capacitor and the second output transistor are adjacent in the first direction, the first capacitor and the second capacitor are adjacent in the second direction, and the first output transistor and the second output transistor are adjacent in the second direction, and the second direction intersects with the first direction.

[0012] In some exemplary embodiments, the active layers of the first control transistor, the second control transistor, and the eighth control transistor are an integrated structure, the active layers of the fourth control transistor and the fifth control transistor are an integrated structure, and the active layers of the first output transistor and the second output transistor are an integrated structure.

[0013] In some exemplary embodiments, in the first direction, the active layer of the sixth control transistor is located between the active layer of the fifth control transistor and the active layer of the second control transistor, and the active layer of the seventh control transistor is located between the active layer of the fourth control transistor and the active layer of the third control transistor.

[0014] In some exemplary embodiments, the second output circuit includes a noise cancellation control subcircuit, a second output subcircuit, and a third output subcircuit. The noise cancellation control subcircuit is connected to the first output terminal, the first clock terminal, the third clock terminal, the first power terminal, the second power terminal, and the first noise cancellation control node, and is configured to, under control of the third clock signal terminal, rectify charge at the first power terminal to the first noise cancellation control node to maintain the first noise cancellation control node at a voltage that turns on the second output subcircuit, and to transmit a signal at the second power terminal to the first noise cancellation control node to maintain the first noise cancellation control node at a voltage that turns off the second output subcircuit. The second output subcircuit is connected to the first noise cancellation control node, the second output terminal, and the first power terminal, and is configured to transmit the signal at the first power terminal to the second output terminal under control of the first noise cancellation control node. The third output sub-circuit is connected to the first node, the fourth clock terminal, and the second output terminal, and is configured to transmit a signal from the fourth clock terminal to the second output terminal under the control of the first node. In the second direction, the second output sub-circuit and the third output sub-circuit are adjacent to each other. In the first direction, the noise removal control sub-circuit is located between the first group of clock signal lines and the second output sub-circuit. The second direction and the first direction intersect.

[0015] In some exemplary embodiments, the noise reduction control subcircuit includes a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor. The first noise reduction control transistor has a control pole connected to the first output terminal, a first pole connected to the second power supply terminal, and a second pole connected to the second noise reduction control node. The second noise reduction control transistor has a control pole connected to the third clock terminal, a first pole connected to the first power supply terminal, and a second pole connected to the second noise reduction control node. The third noise reduction control transistor has a control pole and a first pole connected to the second noise reduction control node, and a second pole connected to the first noise reduction control node. The fourth noise reduction control transistor has a control pole connected to the first output terminal, a first pole connected to the second power supply terminal, and a second pole connected to the first noise reduction control node. The third capacitor has a first electrode connected to the second noise reduction control node and a second electrode connected to the first clock terminal. The fourth capacitor has a first electrode connected to the first noise reduction control node and a second electrode connected to the first power supply terminal. The second output sub-circuit includes a third output transistor. The third output transistor has a control electrode connected to the first noise reduction control node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second output terminal. The third output sub-circuit includes a fourth output transistor. The fourth output transistor has a control electrode connected to the first node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal.

[0016] In some exemplary embodiments, the third output transistor and the fourth output transistor are adjacent to each other in the second direction, and the first noise reduction control transistor and the second noise reduction control transistor are adjacent to each other in the second direction. In the first direction, the third capacitor is located between the second noise reduction control transistor and the third noise reduction control transistor, and the fourth noise reduction control transistor is located between the first noise reduction control transistor and the fourth capacitor.

[0017] In some exemplary embodiments, the active layers of the first noise reduction control transistor and the second noise reduction control transistor are an integrated structure, and the active layers of the third output transistor and the fourth output transistor are an integrated structure.

[0018] In some exemplary embodiments, the first group of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line, and the second group of clock signal lines includes a fourth clock signal line and a fifth clock signal line. The first clock signal through the first clock signal line, the second clock signal through the second clock signal line, and the third clock signal through the third clock signal line have the same duty ratio, and the fourth clock signal through the fourth clock signal line and the fifth clock signal through the fifth clock signal line have the same duty ratio, and the duty ratio of the fourth clock signal is smaller than the duty ratio of the first clock signal. The second clock signal is delayed from the first clock signal by a set time length, and the third clock signal is delayed from the second clock signal by a set time length, so that the first clock signal, the second clock signal, and the third clock signal are not simultaneously at a first voltage, the fourth clock signal and the fifth clock signal are not simultaneously at a second voltage, and the first voltage is different from the second voltage.

[0019] In some exemplary embodiments, in the first direction, the first clock signal line, the second clock signal line, and the third clock signal line are sequentially arranged along a direction away from a first output circuit, and the fourth clock signal line and the fifth clock signal line are sequentially arranged along a direction away from a second output circuit.

[0020] In some exemplary embodiments, a shift register unit in any stage has a first output circuit connected to the first clock signal line, the second clock signal line, and the third clock signal line, and a second output circuit connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

[0021] In some exemplary embodiments, the 6n+1-th stage shift register unit has a first clock terminal connected to the first clock signal line, a second clock terminal connected to the second clock signal line, a third clock terminal connected to the third clock signal line, and a fourth clock terminal connected to the fourth clock signal line. The 6n+2-th stage shift register unit has a first clock terminal connected to the second clock signal line, a second clock terminal connected to the third clock signal line, a third clock terminal connected to the first clock signal line, and a fourth clock terminal connected to the fifth clock signal line. The 6n+3-th stage shift register unit has a first clock terminal connected to the third clock signal line, a second clock terminal connected to the first clock signal line, a third clock terminal connected to the second clock signal line, and a fourth clock terminal connected to the fourth clock signal line. In the 6n+4th stage shift register unit, the first clock terminal is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. In the 6n+5th stage shift register unit, the first clock terminal is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. In the 6n+6th stage shift register unit, the first clock terminal is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fifth clock signal line, where n is a natural number.

[0022] In some exemplary embodiments, a first output terminal of the 2k-1 stage shift register unit is connected to an input terminal of the 2k+1 stage shift register unit, and an input terminal of the first stage shift register unit is connected to a first initial signal line. A first output terminal of the 2k stage shift register unit is connected to an input terminal of the 2k+2 stage shift register unit, and an input terminal of the second stage shift register unit is connected to a second initial signal line, where k is a positive integer. The first group of clock signal lines includes a first subgroup clock signal line and a second subgroup clock signal line, and the second group of clock signal lines includes a third subgroup clock signal line and a fourth subgroup clock signal line. The 2k-1 stage shift register unit is connected to the first subgroup clock signal line and the third subgroup clock signal line, and the 2k stage shift register unit is connected to the second subgroup clock signal line and the fourth subgroup clock signal line.

[0023] In some exemplary embodiments, in the first direction, the first subgroup clock signal line and the second subgroup clock signal line are arranged at a distance from each other, and the third subgroup clock signal line and the fourth subgroup clock signal line are arranged at a distance from each other.

[0024] In some exemplary embodiments, in a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes a base substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the base substrate. The first semiconductor layer includes at least active layers of the transistors of the shift register unit. The first conductive layer includes at least control electrodes of the transistors of the shift register unit and first electrodes of the capacitors. The second conductive layer includes at least second electrodes of the capacitors of the shift register unit. The third conductive layer includes at least first and second electrodes of the transistors of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, and a plurality of power supply lines. The fourth conductive layer includes at least a connection electrode connecting a first node and a third output sub-circuit of a second output circuit.

[0025] In another aspect, an embodiment of the present disclosure provides a display device, comprising the display substrate described above.

[0026] In another aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate for manufacturing the above-mentioned display substrate, the method including: providing a base substrate; and forming a gate driving circuit in a non-display area. The gate driving circuit includes a plurality of cascaded shift register units. The shift register units are connected to at least one power supply line. The shift register units include a first output circuit and a second output circuit, the first output circuit being connected to a first group of clock signal lines, and the second output circuit being connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on a side of the second output circuit away from the first group of clock signal lines.

[0027] Other aspects will be understood after reading and understanding the drawings and detailed description.

[0028] The drawings are intended to provide a further understanding of the technical solution of the present disclosure, to be a part of the specification, and to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. The shape and size of one or more parts in the drawings do not reflect actual proportions and are intended to schematically explain the contents of the present disclosure. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a structural schematic diagram of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 2] FIG. 2 is an equivalent circuit diagram of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 3]FIG. 3 is an operation timing diagram of the shift register unit shown in FIG. [Figure 4] FIG. 4 is a schematic diagram of a cascade of shift register units in accordance with at least one embodiment of the present disclosure. [Figure 5] FIG. 5 is a top view of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic local cross-sectional view taken along the QQ direction in FIG. [Figure 7A] FIG. 7A is a top view of a shift register unit after forming a first semiconductor layer in accordance with at least one embodiment of the present disclosure. [Figure 7B] FIG. 7B is a top view of the shift register unit after forming the first conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 7C] FIG. 7C is a top view of the shift register unit after forming the second conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 7D] FIG. 7D is a top view of the shift register unit after forming a fourth insulating layer in accordance with at least one embodiment of the present disclosure. [Figure 7E] FIG. 7E is a top view of the shift register unit after forming a third conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 7F] FIG. 7F is a top view of the shift register unit after forming a fourth conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 8] FIG. 8 is another schematic diagram of a cascade connection of shift register units in accordance with at least one embodiment of the present disclosure. [Figure 9] FIG. 9 is a timing diagram of clock signals in accordance with at least one embodiment of the present disclosure. [Figure 10] FIG. 10 is another top view of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 11A] FIG. 11A is another top view of the shift register unit after forming the first semiconductor layer in accordance with at least one embodiment of the present disclosure. [Figure 11B]FIG. 11B is another top view of the shift register unit after forming the first conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 11C] FIG. 11C illustrates another top view of the shift register unit after forming the second conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 11D] FIG. 11D illustrates another top view of the shift register unit after forming the third conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 11E] FIG. 11E is another top view of the shift register unit after forming the fourth conductive layer in accordance with at least one embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, examples of the present disclosure will be described in detail with reference to the drawings. The embodiments can be implemented in many different forms. As those skilled in the art can easily understand, the method and content can be converted into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the description of the following embodiments. If there is no conflict, the examples and features of the examples of the present disclosure can be combined with each other.

[0031] In the drawings, the size, layer thickness, or area of ​​one or more components may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not limited to the size, and the shape and size of one or more parts in the drawings do not reflect actual proportions. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0032] In this disclosure, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to be limiting in terms of quantity. In this disclosure, the term "plurality" indicates a quantity of two or more.

[0033] In this disclosure, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is for the purpose of explaining and simplifying the present specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components are appropriately changed depending on the direction in which the components are described. Therefore, the terms are not limited to those described in the specification, and may be appropriately changed in some cases.

[0034] In this disclosure, unless otherwise clearly specified and limited, the terms "attach," "couple," and "connect" should be understood in a broad sense. For example, they may refer to a fixed connection, a detachable connection, or an integral connection. They may be a mechanical connection or an electrical connection. They may be a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will be able to understand the meaning of the above terms in this disclosure according to the specific situation. "Electrical connection" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit an electrical signal between the connected components. Examples of "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0035] In this disclosure, a transistor refers to an element that includes at least three terminals: a gate electrode (gate electrode), a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode. In this disclosure, a channel region refers to a region through which current mainly flows.

[0036] In this disclosure, to distinguish between the two poles of a transistor other than the gate electrode, one of the electrodes is referred to as a first pole and the other as a second pole, where the first pole may be a source electrode or a drain electrode, and the second pole may be a drain electrode or a source electrode, and the gate electrode of a transistor is referred to as a control pole. When using a transistor with opposite polarity or when the current direction during operation in a circuit changes, the functions of the "source electrode" and the "drain electrode" may be interchangeable. Therefore, in this disclosure, the terms "source electrode" and "drain electrode" may be interchangeable.

[0037] In this disclosure, "parallel" refers to a state in which the angle formed by two lines is between -10° and 10°, and may include a state in which the angle is between -5° and 5°. Additionally, "perpendicular" refers to a state in which the angle formed by two lines is between 80° and 100°, and may include a state in which the angle is between 85° and 95°.

[0038] In the present disclosure, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0039] In this disclosure, the terms "about" and "approximately" are used without strict boundaries, but rather allow for process and measurement error margins.

[0040] An embodiment of the present disclosure provides a display substrate, including a display area and a non-display area. A gate driving circuit is disposed in the non-display area. The gate driving circuit includes a plurality of cascaded shift register units, each connected to at least one power supply line. The shift register unit includes a first output circuit and a second output circuit, the first output circuit connected to a first group of clock signal lines, and the second output circuit connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on a side of the second output circuit away from the first group of clock signal lines.

[0041] In the display substrate according to this embodiment, the first output circuit and the second output circuit are configured to share the first group of clock signal lines, and the power supply lines and the shared first group of clock signal lines are arranged between the first output circuit and the second output circuit, thereby saving wiring space and contributing to the realization of a display substrate with a narrow frame design.

[0042] In some exemplary embodiments, the output signals of the first and second output circuits are of opposite phase.

[0043] In some exemplary embodiments, the at least one power supply line includes a first power supply line and a second power supply line, the first power supply line being connected to the first output circuit and the second power supply line being connected to the second output circuit. In the first direction, the first power supply line is located between the first output circuit and the first group of clock signal lines, and the second power supply line is located between the first group of clock signal lines and the second output circuit. In some examples, the first power supply line continues to provide a low-level signal, and the second power supply line continues to provide a high-level signal. However, this embodiment is not limited thereto.

[0044] In some exemplary embodiments, a third power line and a fourth power line are further installed in the non-display area. The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit. In the first direction, the fourth power line is located on the side away from the first power line of the first output circuit, and the third power line is located between the second power line and the second group of clock signal lines. In some examples, the third power line continues to provide a low-level signal, and the fourth power line continues to provide a high-level signal. However, this embodiment is not limited thereto.

[0045] In some exemplary embodiments, an initial signal line is further installed in the non-display area. In the first direction, the initial signal line is located on a side of the fourth power supply line away from the first output circuit. In some examples, the input end of the first-stage shift register unit is connected to the initial signal line. In some examples, the initial signal line includes a first initial signal line and a second initial signal line, the first initial signal line being connected to the input end of the first-stage shift register unit, and the second initial signal line being connected to the input end of the second-stage shift register unit. However, this embodiment is not limited thereto.

[0046] In some exemplary embodiments, the first output circuit includes a first node control subcircuit, a second node control subcircuit, and a first output subcircuit. The first node control subcircuit is connected to the input terminal, the first output terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, and is configured to control the potentials of the first node and the second node under control of the first clock terminal, the third clock terminal, and the input terminal. The second node control subcircuit is connected to the first node, the second node, the second power supply terminal, and the first output terminal, and is configured to maintain the potentials of the first node and the second node. The first output subcircuit is connected to the first node, the second node, the second clock terminal, the second power supply terminal, and the first output terminal, and is configured to control output of a first output signal by the first output terminal under control of the first node and the second node. The second node control subcircuit, the first output subcircuit, and the first node control subcircuit are sequentially arranged along a first direction. In some instances, the first power supply terminal continues to provide a low level signal, and the second power supply terminal continues to provide a high level signal. The circuit arrangement according to this embodiment can save wiring space.

[0047] In some exemplary embodiments, the first node control subcircuit includes a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor. The first control transistor has a control pole connected to the first clock terminal, a first pole connected to the input terminal, and a second pole connected to the fourth node. The second control transistor has a control pole connected to the first clock terminal, a first pole connected to the fourth node, and a second pole connected to the first node. The third control transistor has a control pole connected to the third clock terminal, a first pole connected to the first power supply terminal, and a second pole connected to the second node. The fourth control transistor has a control pole connected to the second node, a first pole connected to the second power supply terminal, and a second pole connected to the third node. The fifth control transistor has a control pole connected to the second node, a first pole connected to the third node, and a second pole connected to the first node. The sixth control transistor has a control pole connected to the first node, a first pole connected to the first power supply terminal, and a second pole connected to the third node. The seventh control transistor has a control pole connected to the input terminal, a first pole connected to the second power supply terminal, and a second pole connected to the second node. The eighth control transistor has a control pole connected to the first output terminal, a first pole connected to the second clock terminal, and a second pole connected to the fourth node. The second node control subcircuit includes a first capacitor and a second capacitor. The first capacitor has a first electrode connected to the first node and a second electrode connected to the first output terminal. The second capacitor has a first electrode connected to the second node and a second electrode connected to the second power supply terminal. The first output subcircuit includes a first output transistor and a second output transistor. The first output transistor has a control pole connected to the first node, a first pole connected to the second clock terminal, and a second pole connected to the first output terminal. The second output transistor has a control pole connected to the second node, a first pole connected to the second power supply terminal, and a second pole connected to the first output terminal.

[0048] In some exemplary embodiments, the first capacitor and the first output transistor are adjacent in a first direction, the second capacitor and the second output transistor are adjacent in the first direction, the first capacitor and the second capacitor are adjacent in a second direction, and the first output transistor and the second output transistor are adjacent in the second direction. The second direction and the first direction intersect. For example, the first direction and the second direction are located on the same plane and perpendicular to each other.

[0049] In some exemplary embodiments, the active layers of the first control transistor, the second control transistor, and the eighth control transistor are an integrated structure, the active layers of the fourth control transistor and the fifth control transistor are an integrated structure, and the active layers of the first output transistor and the second output transistor are an integrated structure, although this embodiment is not limited thereto.

[0050] In some exemplary embodiments, in the first direction, the active layer of the sixth control transistor is located between the active layer of the fifth control transistor and the active layer of the second control transistor, and the active layer of the seventh control transistor is located between the active layer of the fourth control transistor and the active layer of the third control transistor, although this embodiment is not limited thereto.

[0051] In some exemplary embodiments, the second output circuit includes a noise cancellation control subcircuit, a second output subcircuit, and a third output subcircuit. The noise cancellation control subcircuit is connected to the first output terminal, the first clock terminal, the third clock terminal, the first power terminal, the second power terminal, and the first noise cancellation control node, and is configured to, under control of the third clock signal terminal, rectify charge at the first power terminal to the first noise cancellation control node to maintain the first noise cancellation control node at a voltage that turns on the second output subcircuit, and to transmit a signal at the second power terminal to the first noise cancellation control node to maintain the first noise cancellation control node at a voltage that turns off the second output subcircuit. The second output subcircuit is connected to the first noise cancellation control node, the second output terminal, and the first power terminal, and is configured to transmit the signal at the first power terminal to the second output terminal under control of the first noise cancellation control node. The third output sub-circuit is connected to the first node, the fourth clock terminal, and the second output terminal, and is configured to transmit a signal from the fourth clock terminal to the second output terminal under the control of the first node. In the second direction, the second output sub-circuit and the third output sub-circuit are adjacent to each other, and in the first direction, the noise removal control sub-circuit is located between the first group of clock signal lines and the second output sub-circuit. The second direction and the first direction intersect.

[0052] In some exemplary embodiments, the noise reduction control subcircuit includes a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor. The first noise reduction control transistor has a control pole connected to the first output terminal, a first pole connected to the second power supply terminal, and a second pole connected to the second noise reduction control node. The second noise reduction control transistor has a control pole connected to the third clock terminal, a first pole connected to the first power supply terminal, and a second pole connected to the second noise reduction control node. The third noise reduction control transistor has a control pole and a first pole connected to the second noise reduction control node, and a second pole connected to the first noise reduction control node. The fourth noise reduction control transistor has a control pole connected to the first output terminal, a first pole connected to the second power supply terminal, and a second pole connected to the first noise reduction control node. The third capacitor has a first electrode connected to the second noise reduction control node and a second electrode connected to the first clock terminal. The fourth capacitor has a first electrode connected to the first noise reduction control node and a second electrode connected to the first power supply terminal. The second output sub-circuit includes a third output transistor. The third output transistor has a control electrode connected to the first noise reduction control node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second output terminal. The third output sub-circuit includes a fourth output transistor. The fourth output transistor has a control electrode connected to the first node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal.

[0053] In some exemplary embodiments, the third output transistor and the fourth output transistor are adjacent to each other in the second direction, and the first noise reduction control transistor and the second noise reduction control transistor are adjacent to each other in the second direction. In the first direction, the third capacitor is located between the second noise reduction control transistor and the third noise reduction control transistor, and the fourth noise reduction control transistor is located between the first noise reduction control transistor and the fourth capacitor. However, this embodiment is not limited thereto.

[0054] In some exemplary embodiments, the active layers of the first noise reduction control transistor and the second noise reduction control transistor are integrated, and the active layers of the third output transistor and the fourth output transistor are integrated, although this embodiment is not limited thereto.

[0055] In some exemplary embodiments, the first group of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line. The second group of clock signal lines includes a fourth clock signal line and a fifth clock signal line. The first clock signal through the first clock signal line, the second clock signal through the second clock signal line, and the third clock signal through the third clock signal line have the same duty ratio, and the fourth clock signal through the fourth clock signal line and the fifth clock signal through the fifth clock signal line have the same duty ratio, but the duty ratio of the fourth clock signal is smaller than the duty ratio of the first clock signal. The second clock signal is delayed from the first clock signal by a set time, and the third clock signal is delayed from the second clock signal by a set time, so that the first clock signal, the second clock signal, and the third clock signal are not simultaneously at the first voltage. The fourth clock signal and the fifth clock signal are not simultaneously at the second voltage. The first voltage is different from the second voltage. For example, the first voltage is smaller than the second voltage. For example, the first voltage may be a low level and the second voltage may be a high level, although this embodiment is not limited thereto.

[0056] In some exemplary embodiments, in the first direction, the first clock signal line, the second clock signal line, and the third clock signal line are sequentially arranged along the direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are sequentially arranged along the direction away from the second output circuit. However, in these embodiments, the arrangement order of the multiple clock signal lines of the first group is not limited, and the arrangement order of the multiple clock signal lines of the second group is not limited.

[0057] In some exemplary embodiments, the shift register unit of any stage has a first output circuit connected to the first clock signal line, the second clock signal line, and the third clock signal line, and a second output circuit connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

[0058] In some exemplary embodiments, the 6n+1-th stage shift register unit has a first clock terminal connected to the first clock signal line, a second clock terminal connected to the second clock signal line, a third clock terminal connected to the third clock signal line, and a fourth clock terminal connected to the fourth clock signal line. The 6n+2-th stage shift register unit has a first clock terminal connected to the second clock signal line, a second clock terminal connected to the third clock signal line, a third clock terminal connected to the first clock signal line, and a fourth clock terminal connected to the fifth clock signal line. The 6n+3-th stage shift register unit has a first clock terminal connected to the third clock signal line, a second clock terminal connected to the first clock signal line, a third clock terminal connected to the second clock signal line, and a fourth clock terminal connected to the fourth clock signal line. In the (6n+4)th shift register unit, the first clock terminal is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. In the (6n+5)th shift register unit, the first clock terminal is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. In the (6n+6)th shift register unit, the first clock terminal is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fifth clock signal line, where n is a natural number. In this example, six cascaded shift register units are considered to be one minimum period repeating unit, and can drive six rows of subpixels in the display area.

[0059] In some exemplary embodiments, a first output terminal of the 2k-1-stage shift register unit is connected to an input terminal of the 2k+1-stage shift register unit, and an input terminal of the first-stage shift register unit is connected to a first initial signal line. A first output terminal of the 2k-stage shift register unit is connected to an input terminal of the 2k+2-stage shift register unit, and an input terminal of the second-stage shift register unit is connected to a second initial signal line, where k is a positive integer. The first group of clock signal lines includes a first subgroup clock signal line and a second subgroup clock signal line, and the second group of clock signal lines includes a third subgroup clock signal line and a fourth subgroup clock signal line. The 2k-1-stage shift register unit is connected to the first subgroup clock signal line and the third subgroup clock signal line, and the 2k-stage shift register unit is connected to the second subgroup clock signal line and the fourth subgroup clock signal line. In some examples, 12 shift register units are considered as one minimum period repeating unit, and can drive 12 rows of subpixels in the display area.

[0060] In some exemplary embodiments, the first subgroup clock signal line and the second subgroup clock signal line are spaced apart in the first direction, and the third subgroup clock signal line and the fourth subgroup clock signal line are spaced apart in the first direction. However, this embodiment is not limited thereto. For example, the first subgroup clock signal line and the second subgroup clock signal line are sequentially arranged along the first direction, and the third subgroup clock signal line and the fourth subgroup clock signal line are sequentially arranged along the first direction.

[0061] In some exemplary embodiments, the first subgroup clock signal lines include a first clock signal line, a second clock signal line, and a third clock signal line, and the second subgroup clock signal lines include a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line. The third subgroup clock signal lines include a fourth clock signal line and a fifth clock signal line, and the fourth subgroup clock signal line includes a ninth clock signal line and a tenth clock signal line. The first clock signal from the first clock signal line, the second clock signal from the second clock signal line, the third clock signal from the third clock signal line, the sixth clock signal from the sixth clock signal line, the seventh clock signal from the seventh clock signal line, and the eighth clock signal from the eighth clock signal line have the same duty ratio. The second clock signal is delayed by a first set time length from the first clock signal, and the third clock signal is delayed by a first set time length from the second clock signal, so that the first, second, and third clock signals are not all at the first voltage simultaneously. The seventh clock signal is delayed by a first set time length from the sixth clock signal, and the eighth clock signal is delayed by a first set time length from the seventh clock signal, so that the sixth, seventh, and eighth clock signals are not all at the first voltage simultaneously. The sixth clock signal is delayed by a second set time length from the first clock signal, and the seventh clock signal is delayed by a second set time length from the second clock signal, and the eighth clock signal is delayed by a second set time length from the third clock signal. The fourth clock signal from the fourth clock signal line, the fifth clock signal from the fifth clock signal line, the ninth clock signal from the ninth clock signal line, and the tenth clock signal from the tenth clock signal line have the same duty ratio. The duty cycle of the fourth clock signal is smaller than that of the first clock signal, the fourth clock signal and the fifth clock signal are not simultaneously at the second voltage, the ninth clock signal and the tenth clock signal are not simultaneously at the second voltage, the second voltage is different from the first voltage, the ninth clock signal is delayed from the fourth clock signal by a second set time length, and the tenth clock signal is delayed from the fifth clock signal by a second set time length.

[0062] In some exemplary embodiments, in a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes a base substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the base substrate. The first semiconductor layer includes at least active layers of a plurality of transistors in the shift register unit. The first conductive layer includes at least control electrodes of a plurality of transistors in the shift register unit and first electrodes of a plurality of capacitors. The second conductive layer includes at least second electrodes of a plurality of capacitors in the shift register unit. The third conductive layer includes at least first and second electrodes of a plurality of transistors in the shift register unit, a first group of clock signal lines, a second group of clock signal lines, and a plurality of power supply lines. The fourth conductive layer includes at least a connection electrode connecting the first node and a third output sub-circuit of the second output circuit.

[0063] The solution of this embodiment will be described below by way of some examples.

[0064] In some exemplary embodiments, the display substrate may include a display area and a non-display area. For example, the non-display area may be located around the display area, but this embodiment is not limited thereto. The display area includes at least a plurality of regularly arranged pixel circuits, a plurality of gate lines (e.g., including scan lines, reset signal lines, and light-emitting control lines) extending along a first direction, and a plurality of data lines and power lines extending along a second direction. The first and second directions are located on the same plane and intersect with each other, for example, the first direction is perpendicular to the second direction.

[0065] In some exemplary embodiments, one pixel unit in the display area may include three subpixels, which may be red, green, and blue subpixels, respectively. However, this embodiment is not limited thereto. In some examples, one pixel unit may include four subpixels, which may be red, green, blue, and white subpixels, respectively.

[0066] In some exemplary embodiments, the shape of the subpixel may be rectangular, diamond, pentagonal, or hexagonal. When one pixel unit includes three subpixels, the three subpixels may be arranged in a horizontal parallel-array, vertical parallel-array, or square-shaped manner. When one pixel unit includes four subpixels, the four subpixels may be arranged in a horizontal parallel-array, vertical parallel-array, or square-shaped manner. However, this embodiment is not limited thereto.

[0067] In some exemplary embodiments, a timing controller, a data driving circuit, and a gate driving circuit may be installed in the non-display area. The gate driving circuits may be installed on opposite sides of the display area, for example, on the left and right sides of the display area. The timing controller and the data driving circuit may be installed on one side of the display area, for example, below the display area. However, this embodiment is not limited thereto.

[0068] In some exemplary embodiments, the data driving circuit can provide data signals to the sub-pixels via data lines. The gate driving circuit can provide scan signals to the sub-pixels via scan lines, reset signals to the sub-pixels via reset signal lines, or light-emitting control signals to the sub-pixels via light-emitting control lines. A timing controller can provide driving signals to the data driving circuit and the gate driving circuit. The operations of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide grayscale data specifying a grayscale to be displayed in the sub-pixels to the data driving circuit. The data driving circuit can provide data signals with potentials corresponding to the grayscale data of the sub-pixels to the sub-pixels in a row selected by the gate driving circuit via the data lines.

[0069] In some exemplary embodiments, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure, although this embodiment is not limited thereto. For example, the pixel driving circuit may include an N-type transistor and a P-type transistor. The N-type transistor may be, for example, an oxide film transistor, and the P-type transistor may be, for example, a low-temperature polysilicon film transistor. The active layer of the low-temperature polysilicon film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide film transistor is made of an oxide semiconductor (oxide). The low-temperature polysilicon film transistor has advantages such as high mobility and fast charging, while the oxide film transistor has advantages such as low leakage current. By integrating the low-temperature polysilicon film transistor and the oxide film transistor on a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0070] In some exemplary embodiments, the gate drive circuit includes a plurality of cascaded shift register units. For example, the input terminal of the first-stage shift register unit may be connected to an initial signal line, and the first output terminal of the i-th stage shift register unit may be connected to the input terminal of the i+1-th stage shift register unit to provide an input signal to the i+1-th stage shift register unit, where i is a positive integer. The second output terminal of the shift register unit may provide a scan signal to the subpixel via a scan line and a reset signal to the subpixel via a reset signal line. For example, the first output signal from the first output terminal of the shift register unit may be configured to control the turn-on of a P-type transistor (e.g., a low-temperature polysilicon film transistor) in the pixel circuit. The second output signal from the second output terminal of the shift register unit may be configured to control the turn-on of an N-type transistor (e.g., an oxide film transistor) in the pixel circuit. However, this embodiment is not limited thereto.

[0071] 1 is a structural schematic diagram of a shift register unit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG. 1, the shift register unit according to the exemplary embodiment includes a first output circuit 10 and a second output circuit 20. The first output circuit 10 outputs a first output signal through a first output terminal OUT1, and the second output circuit 20 outputs a second output signal through a second output terminal OUT2. The first output signal and the second output signal have opposite phases.

[0072] 1 , the first output circuit 10 includes a first node control subcircuit 11, a second node control subcircuit 12, and a first output subcircuit 13. The first node control subcircuit 11 is connected to the input terminal INPUT, the first output terminal OUT1, the first power supply terminal V1, the second power supply terminal V2, the first clock terminal CK1, the second clock terminal CK2, the third clock terminal CK3, the first node N1, and the second node N2, and is configured to control the potentials of the first node N1 and the second node N2 under the control of the first clock terminal CK1, the input terminal INPUT, and the third clock terminal CK3. The second node control subcircuit 12 is connected to the first node N1, the second node N2, the second power supply terminal V2, and the first output terminal OUT1, and is configured to maintain the potentials of the first node N1 and the second node N2. The first output sub-circuit 13 is connected to the second clock terminal CK2, the second power supply terminal V2, the first node N1, the second node N2 and the first output terminal OUT1, and is configured to control the output of the first output signal by the first output terminal OUT1 under the control of the first node N1 and the second node N2.

[0073] 1 , the second output circuit 20 includes a noise cancellation control subcircuit 21, a second output subcircuit 22, and a third output subcircuit 23. The noise cancellation control subcircuit 21 is connected to a first clock terminal CK1, a third clock terminal CK3, a first noise cancellation control node PD1, a first output terminal OUT1, a first power supply terminal V1, and a second power supply terminal V2. The noise cancellation control subcircuit 21 is configured to, under the control of the third clock terminal CK3, rectify the charge at the first power supply terminal V1 to the first noise cancellation control node PD1 to maintain the first noise cancellation control node PD1 at a voltage that turns on the second output subcircuit 22, and to transmit the signal at the second power supply terminal V2 to the first noise cancellation control node PD1 to maintain the first noise cancellation control node PD1 at a voltage that turns off the second output subcircuit 22. The second output sub-circuit 22 is connected to the first noise reduction control node PD1, the second output terminal OUT2, and the first power supply terminal V1, and is configured to transfer a signal from the first power supply terminal V1 to the second output terminal OUT2 under the control of the first noise reduction control node PD1. The third output sub-circuit 23 is connected to the first node N1, the fourth clock terminal CB, and the second output terminal OUT2, and is configured to transfer a signal from the fourth clock terminal CB to the second output terminal OUT2 under the control of the first node N1.

[0074] In some examples, the first power supply terminal V1 can continue to provide a low level signal, and the second power supply terminal V2 can continue to provide a high level signal, although this embodiment is not limited thereto.

[0075] In this exemplary embodiment, the first output signal output from the first output terminal OUT1 and the second output signal output from the second output terminal OUT2 have opposite phases. By providing a noise cancellation control sub-circuit in the second output circuit, continuous noise cancellation for the second output terminal OUT2 of the shift register unit can be realized, thereby improving display stability.

[0076] 2 is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure. As shown in FIG. 2, the first node control sub-circuit 11 includes a first control transistor M1, a second control transistor M2, a third control transistor M5, a fourth control transistor M6, a fifth control transistor M7, a sixth control transistor M8, a seventh control transistor M9, and an eighth control transistor M10.

[0077] The first control transistor M1 has a control pole connected to the first clock terminal CK1, a first pole connected to the input terminal INPUT, and a second pole connected to the fourth node N4. The second control transistor M2 has a control pole connected to the first clock terminal CK1, a first pole connected to the fourth node N4, and a second pole connected to the first node N1. The third control transistor M5 has a control pole connected to the third clock terminal CK3, a first pole connected to the first power supply terminal V1, and a second pole connected to the second node N2. The fourth control transistor M6 has a control pole connected to the second node N2, a first pole connected to the second power supply terminal V2, and a second pole connected to the third node N3. The fifth control transistor M7 has a control pole connected to the second node N2, a first pole connected to the third node N3, and a second pole connected to the first node N1. The sixth control transistor M8 has a control electrode connected to the first node N1, a first electrode connected to the first power supply terminal V1, and a second electrode connected to the third node N3. The seventh control transistor M9 has a control electrode connected to the input terminal INPUT, a first electrode connected to the second power supply terminal V2, and a second electrode connected to the second node N2. The eighth control transistor M10 has a control electrode connected to the first output terminal OUT1, a first electrode connected to the second clock terminal CK2, and a second electrode connected to the fourth node N4.

[0078] In this exemplary embodiment, the first control transistor M1 and the second control transistor M2 form a double-gate transistor having low leakage current, the eighth control transistor M10 is employed to control the potential of the fourth node N4 to reduce the drain-source voltages of the first control transistor M1 and the second control transistor M2 during the set time period, thereby reducing the leakage currents of the first control transistor M1 and the second control transistor M2, the fourth control transistor M6 and the fifth control transistor M7 form a double-gate transistor, and the sixth control transistor M8 is employed to control the potential of the third node N3 to reduce the drain-source voltages of the fourth control transistor M6 and the fifth control transistor M7 during the set time period, thereby reducing the leakage currents of the fourth control transistor M6 and the fifth control transistor M7.

[0079] The second node control subcircuit 12 includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 has a first electrode connected to the first node N1 and a second electrode connected to the first output terminal OUT1. The second capacitor C2 has a first electrode connected to the second node N2 and a second electrode connected to the second power supply terminal V2.

[0080] The first output sub-circuit 13 includes a first output transistor M3 and a second output transistor M4. The first output transistor M3 has a control pole connected to the first node N1, a first pole connected to the second clock terminal CK2, and a second pole connected to the first output terminal OUT1. The second output transistor M4 has a control pole connected to the second node N2, a first pole connected to the second power supply terminal V2, and a second pole connected to the first output terminal OUT1.

[0081] In some exemplary embodiments, as shown in FIG. 2, the noise cancellation control subcircuit 21 includes a first noise cancellation control transistor M11, a second noise cancellation control transistor M12, a third noise cancellation control transistor M13, a fourth noise cancellation control transistor M14, a third capacitor C3, and a fourth capacitor C4.

[0082] The first noise reduction control transistor M11 has a control pole connected to the first output terminal OUT1, a first pole connected to the second power supply terminal V2, and a second pole connected to the second noise reduction control node PD2. The second noise reduction control transistor M12 has a control pole connected to the third clock terminal CK3, a first pole connected to the first power supply terminal V1, and a second pole connected to the second noise reduction control node PD2. The third noise reduction control transistor M13 has a control pole and a first pole connected to the second noise reduction control node PD2, and a second pole connected to the first noise reduction control node PD1. The fourth noise reduction control transistor M14 has a control pole connected to the first output terminal OUT1, a first pole connected to the second power supply terminal V2, and a second pole connected to the first noise reduction control node PD1. The third capacitor C3 has a first electrode connected to the second noise reduction control node PD2, and a second electrode connected to the first clock terminal CK1. The fourth capacitor C4 has a first electrode connected to the first noise removal control node PD1 and a second electrode connected to the first power supply terminal V1.

[0083] In this exemplary embodiment, the second noise cancellation control transistor M12, the third noise cancellation control transistor M13, the third capacitor C3, and the fourth capacitor C4 form a charge pump structure, and the voltage adjusting effect of the charge pump structure is used to stabilize the potential of the first noise cancellation control node PD1 to a potential that can turn on the second output sub-circuit, thereby ensuring that the second output sub-circuit is continuously turned on during the sustain phase in the driving process of one row of gate lines, and continuously performing noise cancellation for the second output terminal.

[0084] In some exemplary embodiments, the second output sub-circuit includes a third output transistor M15. The third output transistor M15 has a control pole connected to the first noise removal control node PD1, a first pole connected to the first power supply terminal V1, and a second pole connected to the second output terminal OUT2. The third output sub-circuit includes a fourth output transistor M16. The fourth output transistor M16 has a control pole connected to the first node N1, a first pole connected to the fourth clock terminal CB, and a second pole connected to the second output terminal OUT2.

[0085] In this exemplary embodiment, the first noise reduction control node PD1, the second noise reduction control node PD2, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual components, but represent the junctions of related electrical connections in the circuit diagram, in other words, these nodes are equivalent nodes based on the junctions of related electrical connections in the circuit diagram.

[0086] In this exemplary embodiment, exemplary structures of the first node control sub-circuit, the second node control sub-circuit, the first output sub-circuit, the noise reduction control sub-circuit, the second output sub-circuit, and the third output sub-circuit are shown in Figure 2. As will be readily understood by those skilled in the art, the implementation of the first node control sub-circuit, the second node control sub-circuit, the first output sub-circuit, the noise reduction control sub-circuit, the second output sub-circuit, and the third output sub-circuit is not limited thereto as long as the functions thereof can be realized.

[0087] The technical solutions of the embodiments of the present disclosure will be further described below with reference to the operation process of the shift register unit. The operation process of the first-stage shift register unit will be described below as an example, and the input terminal INPUT of the first-stage shift register unit is connected to the initial signal line STV. Figure 3 is an operation timing diagram of the shift register unit shown in Figure 2.

[0088] In this exemplary embodiment, in the driving process of one row of gate lines within one frame period, after the shift register unit outputs the scanning signal through the second output terminal, the shift register unit outputs a non-operating voltage to the gate line connected thereto in the sustain phase to ensure that the sub-pixels connected to the gate line are turned off.

[0089] In the following description, the transistors in the shift register unit are all P-type transistors, the first power supply terminal V1 provides a low-level voltage, and the second power supply terminal V2 provides a high-level voltage. In this exemplary embodiment, the shift register unit is described as having a first clock terminal CK1 connected to the first clock signal line GCK1, a second clock terminal CK2 connected to the second clock signal line GCK2, a third clock terminal CK3 connected to the third clock signal line GCK3, and a fourth clock terminal CB connected to the fourth clock signal line GCB1.

[0090] As shown in FIG. 3, the driving process of one row of gate lines of the shift register unit according to this exemplary embodiment includes at least a precharge step S1, a bootstrap output step S2, a node pull-up step S3 and a sustain step S4.

[0091] During the precharge stage S1, the initial signal line STV provides a low-level signal, the first clock signal line GCK1 provides a low-level signal, the fourth clock signal line GCB1 provides a low-level signal, and the second clock signal line GCK2 and the third clock signal line GCK3 provide high-level signals. The first control transistor M1 and the second control transistor M2 turn on under the control of the low-level signal from the first clock signal line GCK1, the initial signal line STV provides a low-level signal to the first node N1, the potential of the first node N1 is pulled down to the low potential VGL+Vth, the first output transistor M3 turns on under the control of the low potential of the first node N1, and the second clock signal line GCK2 provides a high-level signal to the first output terminal OUT1. The voltage stored across the first capacitor C1 is VGL+Vth-VGH, where Vth is the threshold voltage of the first control transistor M1 and VGL is the low voltage.

[0092] In the precharge stage S1, the seventh control transistor M9 is turned on under control of a low-level signal from the input terminal INPUT, and the second power supply terminal V2 provides a high-level signal to the second node N2. The second output transistor M4, the fourth control transistor M6, and the fifth control transistor M7 are turned off under control of a high potential at the second node N2. The third control transistor M5 is turned off under control of a high-level signal from the third clock signal line GCK3. The sixth control transistor M8 is turned on under control of a low potential at the first node N1, and the first power supply terminal V1 provides a low-level signal to the third node N3. The eighth control transistor M10 is turned off under control of a high-level signal from the first output terminal OUT1.

[0093] In the precharge stage S1, the first noise cancellation control transistor M11 and the fourth noise cancellation control transistor M14 are both turned off under control of a high-level signal from the first output terminal OUT1, the second noise cancellation control transistor M12 is turned off under control of a high-level signal from the third clock signal line GCK3, the fourth output transistor M16 is turned on under control of a low potential at the first node N1, and the fourth clock signal line GCB1 provides a low-level signal to the second output terminal OUT2.

[0094] During the bootstrap output stage S2, the initial signal line STV provides a high-level signal, the first clock signal line GCK1, the third clock signal line GCK3, and the fourth clock signal line GCB1 provide high-level signals, and the second clock signal line GCK2 provides a low-level signal. The first control transistor M1 and the second control transistor M2 turn off under the control of the high-level signal from the first clock signal line GCK1. The first node N1 remains at a low potential, and the first output transistor M3 turns on. The second clock signal line GCK2 provides a low-level signal to the first output terminal OUT1. Because the voltage across the first capacitor C1 cannot change suddenly, the voltage at the first node N1 is pulled down to 2VGL+Vth-2VGH under the action of the first capacitor C1, ensuring that the first output transistor M3 turns on. VGH is a high voltage.

[0095] In the bootstrap output stage S2, the seventh control transistor M9 is turned off under control of a high-level signal from the initial signal line STV. Under the action of the second capacitor C2, the second node N2 is maintained at a high potential, and the second output transistor M4, the fourth control transistor M6, and the fifth control transistor M7 are turned off. The sixth control transistor M8 is turned on under control of a low potential at the first node N1, and the first power supply terminal V1 provides a low-level signal to the third node N3.

[0096] In the bootstrap output stage S2, the first noise cancellation control transistor M11 and the fourth noise cancellation control transistor M14 are both turned on under the control of a low-level signal at the first output terminal OUT1, and the second power supply terminal V2 provides a high-level signal to the first noise cancellation control node PD1 and the second noise cancellation control node PD2. Second noise removal control node PD2 is turned off under control of a high-level signal from the third clock signal line GCK3. The third noise cancellation control transistor M13 is turned off under control of a high potential from the second noise cancellation control node PD2, and the third output transistor M15 is turned off under control of a high potential from the first noise cancellation control node PD1. The fourth output transistor M16 is turned on under control of a low potential from the first node N1, and the fourth clock signal line GCB1 provides a high-level signal to the second output terminal OUT2.

[0097] During the latter period included in the bootstrap output stage S2, the second clock signal through the second clock signal line GCK2 jumps from a low level to a high level, and the potential of the first node N1 is still lower than the potential of the second clock signal, so the first output transistor M3 turns on, and the first output terminal OUT1 outputs the second clock signal, thereby realizing a low pulse output from the first output terminal OUT1.

[0098] In the bootstrap output stage S2, the low potential at the first node N1 controls the turn-on of the fourth output transistor M16, and the second output terminal OUT2 outputs the fourth clock signal through the fourth clock signal line GCB1. Because the pulse width of the high pulse of the fourth clock signal is smaller than the pulse width of the low pulse of the second clock signal through the second clock signal line GCK2, the entire pulse of the fourth clock signal, including its rising and falling portions, can be transmitted to the second output terminal OUT2. The low potential at the first output terminal OUT1 controls the turn-on of the first noise cancellation control transistor M11 and the fourth noise cancellation control transistor M14, stabilizing the potentials of the first noise cancellation control node PD1 and the second noise cancellation control node PD2 at high potentials and turning off the third output transistor M15, thereby avoiding logic conflict output from the second output terminal OUT2.

[0099] In the node pull-up stage S3, the initial signal line STV provides a high-level signal, the first clock signal line GCK1 and the second clock signal line GCK2 provide high-level signals, and the third clock signal line GCK3 and the fourth clock signal line GCB1 provide low-level signals. The third control transistor M5 is turned on under control of the low-level signal from the third clock signal line GCK3, and the first power supply terminal V1 provides a low-level signal to the second node N2. The second output transistor M4, the fourth control transistor M6, and the fifth control transistor M5 are turned on under control of the low potential of the second node N2, and the second power supply terminal V2 provides a high-level signal to the first output terminal OUT1 and the first node N1. The first output transistor M3 and the sixth control transistor M8 are turned off under control of the high potential of the first node N1.

[0100] In the node pull-up stage S3, the first noise cancellation control transistor M11 and the fourth noise cancellation control transistor M14 are both turned off under control of a high-level signal from the first output terminal OUT1. The second noise cancellation control transistor M12 is turned on under control of a low-level signal from the third clock signal line GCK3, and the first power supply terminal V1 provides a low-level signal to the second noise cancellation control node PD2. Because the first clock signal line GCK1 provides a high-level signal, the potential stored in the third capacitor C3 is VGL+Vth12-VGH, where Vth12 is the threshold voltage of the second noise cancellation control transistor M12. The third noise cancellation control transistor M13 is turned on under control of a low potential from the second noise cancellation control node PD2, and the first noise cancellation control node PD1 is pulled down to a low potential. The third output transistor M15 is turned on under control of a low potential from the first noise cancellation control node PD1, and the first power supply terminal V1 provides a low-level signal to the second output terminal OUT2. The fourth output transistor M16 is turned off under the control of the high potential of the first node N1.

[0101] In the sustaining stage S4, the third clock signal via the third clock signal line GCK3 periodically reduces the potential of the second node N2 to a low potential, ensuring that the second output transistor M4 is turned on and stabilizing the high potential output from the first output terminal OUT1. The third clock signal periodically pulls down the potentials of the second noise reduction control node PD2 and the first noise reduction control node PD1, storing VGL+Vth12-VGH in the third capacitor C3. At the same time, the first clock signal via the first clock signal line GCK1 periodically jumps to a low voltage, reducing the potentials of the second noise reduction control node PD2 and the first noise reduction control node PD1 to lower potentials via the third capacitor C3, ensuring that the third output transistor M15 is turned on sufficiently and allowing a low-level signal via the first power supply terminal V1 to be output to the second output terminal OUT2.

[0102] In this exemplary embodiment, noise removal is continuously performed on the second output terminal OUT2 in the maintaining step S4, so that the stability of the display screen can be maintained and the display effect can be improved.

[0103] In some exemplary embodiments, as shown in FIG. 3 , the first clock signal via the first clock signal line GCK1, the second clock signal via the second clock signal line GCK2, the third clock signal via the third clock signal line GCK3, the fourth clock signal via the fourth clock signal line GCB1, and the fifth clock signal via the fifth clock signal line GCB2 are all pulse signals. The first, second, and third clock signals may have the same duty cycle. The second clock signal is delayed from the first clock signal by a set time, and the third clock signal is delayed from the second clock signal by a set time, so that the first, second, and third clock signals are not simultaneously at a low voltage. For example, the second clock signal is delayed by 1H from the first clock signal, and the third clock signal is delayed by 1H from the second clock signal, where H is the time required to update one row of pixels with the data signal. The fourth and fifth clock signals may have the same duty cycle. The duty cycle of the fourth clock signal may be smaller than the duty cycle of the first clock signal. The duty ratio refers to the ratio of the high level time length to the entire pulse period (including the high level time length and the low level time length). The fourth clock signal and the fifth clock signal are not simultaneously at high voltage, although this embodiment is not limited to this.

[0104] In some exemplary embodiments, the first clock signal, the second clock signal, and the third clock signal may have a duty ratio slightly less than 1 / 3, or the first clock signal, the second clock signal, and the third clock signal may have a duty ratio approximately equal to 1 / 3, although this embodiment is not limited thereto.

[0105] 4 is a schematic diagram of a gate drive circuit in accordance with at least one embodiment of the present disclosure. In some exemplary embodiments, the gate drive circuit includes multiple cascaded shift register units, as shown in FIG.

[0106] The 6n+1-th stage shift register unit has a first clock end connected to the first clock signal line GCK1, a second clock end connected to the second clock signal line GCK2, a third clock end connected to the third clock signal line GCK3, and a fourth clock end connected to the fourth clock signal line GCB1.

[0107] The 6n+2-th stage shift register unit has a first clock end connected to the second clock signal line GCK2, a second clock end connected to the third clock signal line GCK3, a third clock end connected to the first clock signal line GCK1, and a fourth clock end connected to the fifth clock signal line GCB2.

[0108] The (6n+3)-th stage shift register unit has a first clock end connected to the third clock signal line GCK3, a second clock end connected to the first clock signal line GCK1, a third clock end connected to the second clock signal line GCK2, and a fourth clock end connected to the fourth clock signal line GCB1.

[0109] The 6n+4th stage shift register unit has a first clock end connected to the first clock signal line GCK1, a second clock end connected to the second clock signal line GCK2, a third clock end connected to the third clock signal line GCK3, and a fourth clock end connected to the fifth clock signal line GCB2.

[0110] The 6n+5th stage shift register unit has a first clock end connected to the second clock signal line GCK2, a second clock end connected to the third clock signal line GCK3, a third clock end connected to the first clock signal line GCK1, and a fourth clock end connected to the fourth clock signal line GCB1.

[0111] The 6n+6th stage shift register unit has a first clock end connected to the third clock signal line GCK3, a second clock end connected to the first clock signal line GCK1, a third clock end connected to the second clock signal line GCK2, and a fourth clock end connected to the fifth clock signal line GCB2, where n is a natural number.

[0112] In this exemplary embodiment, the first group of clock signal lines includes a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3, and the second group of clock signal lines includes a fourth clock signal line GCB1 and a fifth clock signal line GCB2. The shift register unit of any stage is connected to three clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines. The six cascaded shift register units of the gate driving circuit according to this embodiment are considered as one minimum-period repeating unit, and can drive six rows of sub-pixels in the display area.

[0113] The clock signals transmitted through the first clock signal line GCK1 to the fifth clock signal line GCB2 have been described above, and will not be described again here.

[0114] FIG. 5 is a top view of a shift register unit according to at least one embodiment of the present disclosure. FIG. 5 illustrates an example of cascaded 6n+1-stage and 6n+2-stage shift register units (e.g., n=1). The following description mainly focuses on the structure of the 6n+1-stage shift register unit. FIG. 6 is a schematic local cross-sectional view taken along the QQ direction in FIG. 5. An equivalent circuit diagram of the shift register unit according to this exemplary embodiment is shown in FIG. 2. In this exemplary embodiment, the transistors in the shift register unit are P-type transistors and low-temperature polysilicon film transistors. However, this embodiment is not limited thereto.

[0115] 5, in a plane parallel to the display substrate, the first output circuit, the first group of clock signal lines, the second output circuit, and the second group of clock signal lines are sequentially arranged along a first direction X. In this example, the first output circuit and the second output circuit share the first group of clock signal lines, and the first group of clock signal lines is arranged between the first output circuit and the second output circuit, thereby saving wiring space.

[0116] 5, the first group of clock signal lines includes a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3. The second group of clock signal lines includes a fourth clock signal line GCB1 and a fifth clock signal line GCB2. The first clock signal line GCK1, the second clock signal line GCK2, and the third clock signal line GCK3 are arranged sequentially in the first direction X, away from the first output circuit. The fourth clock signal line GCB1 and the fifth clock signal line GCB2 are arranged sequentially in the first direction X, away from the second output circuit.

[0117] In some exemplary embodiments, as shown in FIG. 5 , in a first direction X, a first group of clock signal lines is located between a first node control subcircuit of a first output circuit and a noise cancellation control subcircuit of a second output circuit. A second group of clock signal lines is located away from the second output subcircuit and the noise cancellation control subcircuit of a third output subcircuit. A first node control subcircuit is located between the first output subcircuit and the first group of clock signal lines. A first output subcircuit is located between the second node control subcircuit and the first node control subcircuit. A noise cancellation control subcircuit is located between the first group of clock signal lines and a second output subcircuit. A second output subcircuit and a third output subcircuit are sequentially arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0118] In some exemplary embodiments, as shown in FIG. 5, a low-level signal is continuously provided via the first power supply line PL1a and the third power supply line PL1b. The first power supply line PL1a is connected to the first output circuit of the shift register unit and configured to provide a low-level signal to the first output circuit. The third power supply line PL1b is connected to the second output circuit of the shift register unit and configured to provide a low-level signal to the second output circuit. In the first direction X, the first power supply line PL1a is located between the first node control subcircuit and the first group of clock signal lines, and the third power supply line PL1b is located closer to the second output subcircuit and the first group of clock signal lines of the third output subcircuit. However, this embodiment is not limited thereto.

[0119] In some exemplary embodiments, as shown in FIG. 5, a high-level signal is continuously provided via the second power supply line PL2b and the fourth power supply line PL2a. The second power supply line PL2b is connected to the second output circuit and configured to provide a high-level signal to the second output circuit. The fourth power supply line PL2a is connected to the first output circuit and configured to provide a high-level signal to the first output circuit. In the first direction X, the fourth power supply line PL2a is located on a side of the first output subcircuit that is farther from the first node control subcircuit, and the second power supply line PL2b is located on a side closer to the first group of clock signal lines of the noise cancellation control subcircuit. However, this embodiment is not limited thereto.

[0120] 5, in the first direction X, the initial signal line STV is located on the side of the fourth power line PL2a that is farther away from the first output sub-circuit. However, this embodiment is not limited thereto.

[0121] 5 , the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCB1, the fifth clock signal line GCB2, the first power supply line PL1a, the fourth power supply line PL2a, the third power supply line PL1b, the second power supply line PL2b, and the initial signal line STV all extend along the second direction Y. The first output terminal OUT1 and the second output terminal OUT2 all extend along the first direction X.

[0122] 5, in a plane parallel to the display substrate, the first output transistor M3 and the second output transistor M4 of the first output sub-circuit are adjacent in the second direction Y. The first capacitor C1 and the second capacitor C2 of the second node control sub-circuit are adjacent in the second direction Y. The first capacitor C1 and the first output transistor M3 are adjacent in the first direction X, and the first capacitor C1 is located on the side of the first output transistor M3 that is remote from the first node control sub-circuit. The second capacitor C2 and the second output transistor M4 are adjacent in the first direction X, and the second capacitor C2 is located on the side of the second output transistor M4 that is remote from the first node control sub-circuit.

[0123] In some exemplary embodiments, as shown in FIG. 5 , in a plane parallel to the display substrate, the fourth control transistor M6 and the fifth control transistor M7 are adjacent to each other in the second direction Y. The seventh control transistor M9 and the fourth control transistor M6 are adjacent to each other in the first direction X, and the seventh control transistor M9 is located on the side of the fourth control transistor M6 that is farther from the second output transistor M4. The sixth control transistor M8 and the fifth control transistor M7 are adjacent to each other in the first direction X, and the sixth control transistor M8 is located on the side of the fifth control transistor M7 that is farther from the first output transistor M3. The second control transistor M2 and the sixth control transistor M8 are adjacent to each other in the first direction X, and the second control transistor M2 is located on the side of the sixth control transistor M8 that is farther from the fifth control transistor M7. The eighth control transistor M10 and the second control transistor M2 are adjacent to each other in the first direction X, and the eighth control transistor M10 is located on the side of the second control transistor M2 that is farther from the sixth control transistor M8. In the first direction X, the first control transistor M1 is located between the second control transistor M2 and the eighth control transistor M10. The third control transistor M5 and the first control transistor M1 are adjacent to each other in the first direction X, and the third control transistor M5 is located on the side of the first control transistor M1 that is farther from the second control transistor M2.

[0124] 5, in a plane parallel to the display substrate, the first noise cancellation control transistor M11 and the second noise cancellation control transistor M12 are adjacent to each other in the second direction Y. The first noise cancellation control transistor M11 and the second noise cancellation control transistor M12 are adjacent to each other in the first direction X with the second power line PL2b. The first noise cancellation control transistor M11 and the fourth noise cancellation control transistor M14 are adjacent to each other in the first direction X, with the fourth noise cancellation control transistor M14 located on the side of the first noise cancellation control transistor M11 that is farther from the second power line PL2b. The third capacitor C3 and the second noise cancellation control transistor M12 are adjacent to each other in the first direction X, with the third capacitor C3 located on the side of the second noise cancellation control transistor M12 that is farther from the second power line PL2b. The third noise cancellation control transistor M13 and the third capacitor C3 are adjacent to each other in the first direction X, with the third noise cancellation control transistor M13 located on the side of the third capacitor C3 that is farther from the second noise cancellation control transistor M12. The fourth capacitor C4 and the fourth noise removal control transistor M14 are adjacent to each other in the first direction X, and the fourth capacitor C4 is located on the side of the fourth noise removal control transistor M14 that is farther away from the first noise removal control transistor M11. The third noise removal control transistor M13 and the fourth capacitor C4 are adjacent to each other in the second direction Y.

[0125] 5, in a plane parallel to the display substrate, the third output transistor M15 and the fourth output transistor M16 are adjacent to each other in the second direction Y. The third output transistor M15 and the fourth capacitor C4 are adjacent to each other in the first direction X, and the third output transistor M15 is located on the side of the fourth capacitor C4 that is away from the fourth noise cancellation control transistor M14. The fourth output transistor M16 and the third noise cancellation control transistor M13 are adjacent to each other in the first direction X, and the fourth output transistor M16 is located on the side of the third noise cancellation control transistor M13 that is away from the third capacitor C3.

[0126] 5, in a plane parallel to the display substrate, in a first direction X, the first output transistor M3 and the second output transistor M4 of the first output sub-circuit and the first control transistor M1 to the eighth control transistor M10 of the first node control sub-circuit are located between the first power line PL1a and the fourth power line PL2a. In the first direction X, the first noise cancellation control transistor M11, the second noise cancellation control transistor M12, and the fourth noise cancellation control transistor M14 of the noise cancellation control sub-circuit are located between the third power line PL1b and the second power line PL2b. In the first direction X, the third noise cancellation control transistor M13 of the noise cancellation control sub-circuit and the third output transistor M15 of the second output sub-circuit and the fourth output transistor M16 of the third output sub-circuit are located between the third power line PL1b and the second group of clock signal lines. The first clock signal line GCK1, the second clock signal line GCK2, and the third clock signal line GCK3 are located in the first direction X between the first power supply line PL1a and the second power supply line PL2b.

[0127] In some exemplary embodiments, as shown in FIG. 6 , in a plane perpendicular to the display substrate, the non-display region of the display substrate may include a base substrate 60, a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base substrate 60. The first insulating layer 61 is disposed between the base substrate 60 and the first semiconductor layer, the second insulating layer 62 is disposed between the first conductive layer and the first semiconductor layer, the third insulating layer 63 is disposed between the first conductive layer and the second conductive layer, and the fourth insulating layer 64 is disposed between the second conductive layer and the third conductive layer. The fifth insulating layer 65 and the sixth insulating layer 66 are disposed between the third conductive layer and the fourth conductive layer. The fifth insulating layer 65 is located closer to the base substrate 60 than the sixth insulating layer 66. In some examples, the first insulating layer 61 to the fifth insulating layer 65 are inorganic insulating layers, and the sixth insulating layer 66 is an organic insulating layer. However, this embodiment is not limited thereto.

[0128] 7A is a top view of a shift register unit after forming a first semiconductor layer according to at least one embodiment of the present disclosure. As shown in FIGS. 5 to 7A, the first semiconductor layer in the non-display area includes at least active layers of a plurality of transistors in the shift register unit. For example, the first semiconductor layer includes at least an active layer 110 of a first control transistor M1, an active layer 120 of a second control transistor M2, an active layer 150 of a third control transistor M5, an active layer 160 of a fourth control transistor M6, an active layer 170 of a fifth control transistor M7, an active layer 180 of a sixth control transistor M8, an active layer 190 of a seventh control transistor M9, an active layer 200 of an eighth control transistor M10, an active layer 130-1 of a first output transistor M3, and an active layer 140-2 of a second output transistor M4. 130-2, active layers 140-1 and 140-2 of the second output transistor M4, active layer 210 of the first noise reduction control transistor M11, active layer 220 of the second noise reduction control transistor M12, active layer 230 of the third noise reduction control transistor M13, active layer 240 of the fourth noise reduction control transistor M14, active layers 250-1 and 250-2 of the third output transistor M15, and active layers 260-1 and 260-2 of the fourth output transistor M16.

[0129] In some exemplary embodiments, in the first direction X, the active layer 160 of the fourth control transistor M6 is located between the active layer 140-2 of the second output transistor M4 and the active layer 190 of the seventh control transistor M9, the active layer 170 of the fifth control transistor M7 is located between the active layer 130-2 of the first output transistor M3 and the active layer 180 of the sixth control transistor M8, and the active layer 110 of the first control transistor M1 and the active layer 120 of the second control transistor M2 are located between the active layer 140-2 of the second output transistor M4 and the active layer 190 of the seventh control transistor M9. The active layer 230 of the third noise reduction control transistor M13 is located between the active layer 220 of the second noise reduction control transistor M12 and the active layer 260-1 of the fourth output transistor M16, and the active layer 240 of the fourth noise reduction control transistor M14 is located between the active layer 210 of the first noise reduction control transistor M11 and the active layer 250-1 of the third output transistor M15.

[0130] In some exemplary embodiments, the active layer 130-1 of the first output transistor M3 and the active layer 140-1 of the second output transistor M4 have an integrated structure, e.g., a rectangular shape with a cutout. The active layer 130-2 of the first output transistor M3 and the active layer 140-2 of the second output transistor M4 have an integrated structure, e.g., a rectangular shape with a cutout. The active layer 160 of the fourth control transistor M6 and the active layer 170 of the fifth control transistor M7 have an integrated structure, e.g., a rectangular shape. The active layer 110 of the first control transistor M1, the active layer 120 of the second control transistor M2, and the active layer 200 of the eighth control transistor M10 have an integrated structure. The active layer 210 of the first noise cancellation control transistor M11 and the active layer 220 of the second noise cancellation control transistor M12 have an integrated structure. The active layer 250-1 of the third output transistor M15 and the active layer 260-1 of the fourth output transistor M16 are integrated into a single structure, e.g., a rectangular shape. The active layer 250-2 of the third output transistor M15 and the active layer 260-2 of the fourth output transistor M16 are integrated into a single structure, e.g., a rectangular shape, although this embodiment is not limited thereto.

[0131] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and multiple doped regions. The channel region may be undoped or have semiconducting properties. The multiple doped regions may be located on either side of the channel region and may be doped with impurities to be conductive. The impurities may vary depending on the type of transistor.

[0132] In some exemplary embodiments, the doped regions of the active layer may be interpreted as source or drain electrodes of a transistor. For example, the source electrode of the first control transistor M1 may correspond to the first doped region 110b doped with impurities around the channel region 110a of the active layer 110. The drain electrode of the first control transistor M1 may correspond to the second doped region 110c doped with impurities around the channel region 110a of the active layer 110. Furthermore, the portions of the active layer between the transistors may be interpreted as wiring doped with impurities and may be used for electrical connection of the transistors.

[0133] 7B is a top view of the shift register unit after forming a first conductive layer according to at least one embodiment of the present disclosure. As shown in FIGS. 5 to 7B, the first conductive layer in the non-display area includes at least the control poles of the plurality of transistors and the first electrodes of the plurality of capacitors of the shift register unit. For example, the first conductive layer may include the control pole 113 of the first control transistor M1, the control pole 123 of the second control transistor M2, the control poles 153a and 153b of the third control transistor M5, the control pole 163 of the fourth control transistor M6, the control pole 173 of the fifth control transistor M7, the control pole 183 of the sixth control transistor M8, the control pole 193 of the seventh control transistor M9, the control poles 203a and 203b of the eighth control transistor M10, the control poles 133a, 133b, and 133c of the first output transistor M3, the control pole 143 of the second output transistor M4, the control pole 153a, 153b, and 153c of the first noise reduction control transistor M5, and the control poles 163a, 163b, and 163c of the second output transistor M6. The control electrodes 213a and 213b of the fourth noise reduction control transistor M11, the control electrode 223 of the second noise reduction control transistor M12, the control electrode 233 of the third noise reduction control transistor M13, the control electrodes 243a and 243b of the fourth noise reduction control transistor M14, the control electrode 253 of the third output transistor M15, the control electrodes 263a, 263b, and 263c of the fourth output transistor M16, the first electrode 301 of the first capacitor C1, the first electrode 302 of the second capacitor C2, the first electrode 303 of the third capacitor C3, the first electrode 304 of the fourth capacitor C4, the first connecting electrode 501, and the second connecting electrode 502.

[0134] In some exemplary embodiments, the first electrode 301 of the first capacitor C1, the control poles 133a, 133b, and 133c of the first output transistor M3, and the control pole 183 of the sixth control transistor M8 may be integrated. The first electrode 302 of the second capacitor C2, the control pole 143 of the second output transistor M4, the control pole 163 of the fourth control transistor M6, and the control pole 173 of the fifth control transistor M7 may be integrated. The control pole 113 of the first control transistor M1 and the control pole 123 of the second control transistor M2 may be integrated. The control poles 153a and 153b of the third control transistor M5 and the control pole 223 of the second noise reduction control transistor M12 may be integrated. The control poles 213a and 213b of the first noise reduction control transistor M11 and the control poles 243a and 243b of the fourth noise reduction control transistor M14 may be integrated. The first electrode 303 of the third capacitor C3 and the control electrode 233 of the third noise reduction control transistor M13 may be integrated. The first electrode 304 of the fourth capacitor C4 and the control electrode 253 of the third output transistor M15 may be integrated. The control electrodes 263a, 263b, and 263c of the fourth output transistor M16 may be integrated. The control electrode 193 of the seventh control transistor M9 of a given stage shift register unit, the control electrodes 203a and 203b of the eighth control transistor M10 of the previous stage shift register unit, and the first connection electrode 501 of the previous stage shift register unit may be integrated. However, this embodiment is not limited to this.

[0135] In this exemplary embodiment, the third control transistor M5, the eighth control transistor M10, the first noise reduction control transistor M11, and the fourth noise reduction control transistor M14 may be double-gate transistors, and the first output transistor M3 and the fourth output transistor M16 may be triple-gate transistors, which can prevent and reduce leakage current, but this embodiment is not limited thereto.

[0136] 7C is a top view of the shift register unit after forming a second conductive layer according to at least one embodiment of the present disclosure. As shown in FIGS. 5 to 7C, the second conductive layer in the non-display area includes at least second electrodes, first output terminals, and second output terminals of the plurality of capacitors in the shift register unit. For example, the second conductive layer may include the second electrode 401 of the first capacitor C1, the second electrode 402 of the second capacitor C2, the second electrode 403 of the third capacitor C3, the second electrode 404 of the fourth capacitor C4, the first output terminal OUT1, the second output terminal OUT2, the third connecting electrode 503, and the first connecting line 701.

[0137] In some demonstrative embodiments, there is an overlap between the orthogonal projection of the second electrode 401 of the first capacitor C1 on the base substrate 60 and the orthogonal projection of the first electrode 301 of the first capacitor C1 on the base substrate 60. There is an overlap between the orthogonal projection of the second electrode 402 of the second capacitor C2 on the base substrate 60 and the orthogonal projection of the first electrode 302 of the second capacitor C2 on the base substrate 60. There is an overlap between the orthogonal projection of the second electrode 403 of the third capacitor C3 on the base substrate 60 and the orthogonal projection of the first electrode 303 of the third capacitor C3 on the base substrate 60. There is an overlap between the orthogonal projection of the second electrode 404 of the fourth capacitor C4 on the base substrate 60 and the orthogonal projection of the first electrode 304 of the fourth capacitor C4 on the base substrate 60.

[0138] In some exemplary embodiments, the first output terminal OUT1 and the second output terminal OUT2 extend along a first direction X. The first output terminal OUT1 is located on a side of the third output transistor M15 away from the fourth output transistor M16 in the second direction Y, and the second output terminal OUT2 is located on a side of the third output transistor M15 away from the fourth capacitor C4 in the first direction X. The first connection line 701 extends along the first direction X, and is located between two adjacent stages of shift register units in the second direction Y.

[0139] FIG. 7D is a top view of a shift register unit after forming a fourth insulating layer according to at least one embodiment of the present disclosure. As shown in FIGS. 5 to 7D, a plurality of vias are formed in the fourth insulating layer 64 in the non-display area. For example, the plurality of vias may include a plurality of first vias K1 to K30, a plurality of second vias H1 to H17, and a plurality of third vias D1 to D10. The fourth insulating layer 64, the third insulating layer 63, and the second insulating layer 62 in the plurality of first vias K1 to K30 are etched to expose the surface of the first semiconductor layer. The fourth insulating layer 64 and the third insulating layer 63 in the plurality of second vias H1 to H17 are etched to expose the surface of the first conductive layer. The fourth insulating layer 64 in the plurality of third vias D1 to D10 is etched to expose the surface of the second conductive layer.

[0140] 7E is a top view of a shift register unit after forming a third conductive layer according to at least one embodiment of the present disclosure. As shown in FIGS. 5 to 7E, the third conductive layer in the non-display area includes at least first and second poles of the plurality of transistors of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, and a plurality of power lines. For example, the third conductive layer may be connected to the first pole 111 and the second pole 112 of the first control transistor M1, the first pole 121 and the second pole 122 of the second control transistor M2, the first pole 151 and the second pole 152 of the third control transistor M5, the first pole 161 and the second pole 162 of the fourth control transistor M6, the first pole 171 and the second pole 172 of the fifth control transistor M7, the first pole 181 and the second pole 182 of the sixth control transistor M8, the first pole 191 and the second pole 192 of the seventh control transistor M9, the first pole 201 and the second pole 202 of the eighth control transistor M10, the first pole 131 and the second pole 132 of the first output transistor M3, the first pole 141 and the second pole 142 of the second output transistor M4, the first pole 211 and the second pole 212 of the first noise elimination control transistor M11, It may include a first pole 221 and a second pole 222 of the noise elimination control transistor M12, a first pole 231 and a second pole 232 of the third noise elimination control transistor M13, a first pole 241 and a second pole 242 of the fourth noise elimination control transistor M14, a first pole 251 and a second pole 252 of the third output transistor M15, a first pole 261 and a second pole 262 of the fourth output transistor M16, an initial signal line STV, a first power supply line PL1a, a third power supply line PL1b, a fourth power supply line PL2a, a second power supply line PL2b, a first clock signal line GCK1, a second clock signal line GCK2, a third clock signal line GCK3, a fourth clock signal line GCB1, a fifth clock signal line GCB2, a fourth connecting electrode 504, a fifth connecting electrode 505, a sixth connecting electrode 506, and a second connecting line 702.

[0141] In some exemplary embodiments, the fourth power supply line PL2a, the first pole 141 of the second output transistor M4, the first pole 161 of the fourth control transistor M6, and the first pole 191 of the seventh control transistor M9 may be integrated. The second pole 132 of the first output transistor M3 and the second pole 142 of the second output transistor M4 may be integrated. The second pole 162 of the fourth control transistor M6, the first pole 171 of the fifth control transistor M7, and the second pole 182 of the sixth control transistor M8 may be integrated. The second pole 112 of the first control transistor M1, the first pole 121 of the second control transistor M2, and the second pole 202 of the eighth control transistor M10 may be integrated. The second pole 192 of the seventh control transistor M9 and the second pole 152 of the third control transistor M5 may be integrated. The first power supply line PL1a, the first pole 151 of the third control transistor M5, and the first pole 181 of the sixth control transistor M8 may be integrated. The second power supply line PL2b, the first pole 211 of the first noise reduction control transistor M11, and the first pole 241 of the fourth noise reduction control transistor M14 may be integrated. The third power supply line PL1b, the first pole 221 of the second noise reduction control transistor M12, and the first pole 251 of the third output transistor M15 may be integrated. The second pole 212 of the first noise reduction control transistor M11 and the second pole 222 of the second noise reduction control transistor M12 may be integrated. The second pole 252 of the third output transistor M15 and the second pole 262 of the fourth output transistor M16 may be integrated.

[0142] 7F is a top view of a shift register unit after forming a fourth conductive layer according to at least one embodiment of the present disclosure. As shown in FIGS. 5 to 7F, a plurality of vias are formed in the sixth insulating layer 66 in the non-display area. For example, the plurality of vias may include a plurality of fourth vias F1 to F3. The fifth insulating layer 65 and the sixth insulating layer 66 in the plurality of fourth vias F1 to F3 are etched to expose the surface of the third conductive layer.

[0143] In some exemplary embodiments, the fourth conductive layer in the non-display area includes at least a connecting electrode. For example, the fourth conductive layer may include a seventh connecting electrode 507 and a third connecting line 703. The seventh connecting electrode 507 and the third connecting line 703 both extend along the first direction X. The seventh connecting electrode 507 may be connected to the second pole 172 of the fifth control transistor M7 through a fourth via F1 and further connected to the fifth connecting electrode 505 through a fourth via F2. The fifth connecting electrode 505 may be connected to the control pole 263c of the fourth output transistor M16 through two vertically arranged second vias H17. The third connecting line 703 may be connected to the second connecting line 702 through a fourth via F3. The second connecting line 702 may be connected to the first connecting line 701 through a third via D3.

[0144] In some examples, the gate driving circuit according to this embodiment may be configured to provide scan signals and reset signals to the sub-pixels of the display area. A light emitting driving circuit configured to provide light emitting control signals to the sub-pixels of the display area may be provided on the side of the gate driving circuit according to this embodiment away from the display area. The light emitting driving circuit may include a plurality of cascaded shift register units. The output terminals of the shift register units of any stage of the light emitting driving circuit are connected to a first connection line 701, and are sequentially connected via a second connection line 702 and a third connection line 703 to transmit the light emitting control signals to the display area. However, this embodiment is not limited thereto.

[0145] In some exemplary embodiments, the first control transistor M1 includes an active layer 110, a control pole 113, a first pole 111, and a second pole 112. The active layer 110 includes a channel region 110a, a first doped region 110b, and a second doped region 110c. The control pole 113 of the first control transistor M1 and the control pole 123 of the second control transistor M2 are integrated into one structure. The control pole 113 of the first control transistor M1 is connected to the first clock signal line GCK1 through two vertically arranged second vias H6. The first pole 111 of the first control transistor M1 is connected to the first doped region 110b of the active layer 110 through three parallel-arranged first vias K14 and further connected to the control pole 193 of the seventh control transistor M9 through a second via H4. The second pole 112 of the first control transistor M1 is connected to the second doped region 110c of the active layer 110 through six first vias K15 arranged in a 2*3 array. First control transistor M1 2nd pole 112 The first pole 121 of the second control transistor M2 and the second pole 202 of the eighth control transistor M10 are integrated into one structure.

[0146] In the embodiments of the present disclosure, "parallel placement" may refer to sequential placement along the first direction X, and "vertical placement" may refer to sequential placement along the second direction Y.

[0147] In some exemplary embodiments, the second control transistor M2 includes an active layer 120, a control pole 123, a first pole 121, and a second pole 122. The active layer 120 includes a channel region 120a, a first doped region 120b, and a second doped region 120c. The active layer 120 of the second control transistor M2 and the active layer 110 of the first control transistor M1 are integrated into one structure, and the first doped region 120b of the active layer 120 is connected to the second doped region 110c of the active layer 110. The second pole 122 of the second control transistor M2 is connected to the second doped region 120c of the active layer 120 through two vertically arranged first vias K13 and is further connected to the control pole 183 of the sixth control transistor M8 through two vertically arranged second vias H3.

[0148] In some exemplary embodiments, the third control transistor M5 includes an active layer 150, control poles 153a and 153b, a first pole 151, and a second pole 152. The active layer 150 includes channel regions 150a1, 150a2, and 150a3, a first doped region 150b, and a second doped region 150c. The control poles 153a and 153b of the third control transistor M5 and the control pole 223 of the second noise reduction control transistor M12 are integrated into one structure. The control poles 153a and 153b of the third control transistor M5 are connected to the third clock signal line GCK3 through two vertically installed second vias H5. The first pole 151 of the third control transistor M5 is connected to the first doped region 150b of the active layer 150 through a first via K17. The first pole 151 of the third control transistor M5 and the first power line PL1a are integrated into one structure. The second pole 152 of the third control transistor M5 is connected through a first via K16 to the second doped region 150c of the active layer 150. The second pole 152 of the third control transistor M5 and the second pole 192 of the seventh control transistor M9 are integrated into one structure.

[0149] In some exemplary embodiments, the fourth control transistor M6 includes an active layer 160, a control pole 163, a first pole 161, and a second pole 162. The active layer 160 includes a channel region 160a, a first doped region 160b, and a second doped region 160c. The active layer 160 of the fourth control transistor M6 and the active layer 170 of the fifth control transistor M7 are integrated, and the second doped region 160c of the active layer 160 is connected to the first doped region 170b of the active layer 170. The control pole 163 of the fourth control transistor M6 is connected to the second pole 192 of the seventh control transistor M9 through a second via H1. The control pole 163 of the fourth control transistor M6, the control pole 173 of the fifth control transistor M7, the control pole 143 of the second output transistor M4, and the first electrode 302 of the second capacitor C2 may be integrated. The first pole 161 of the fourth control transistor M6 is connected to the first doped region 160b of the active layer 160 through a first via K6. The first pole 161 of the fourth control transistor M6, the first pole 191 of the seventh control transistor M9, the first pole 141 of the second output transistor M4, and the fourth power supply line PL2a have an integrated structure. The second pole 162 of the fourth control transistor M6 is connected to the second doped region 160c of the active layer 160 through a first via K7. The second pole 162 of the fourth control transistor M6, the first pole 171 of the fifth control transistor M7, and the second pole 182 of the sixth control transistor M8 have an integrated structure.

[0150] In some exemplary embodiments, the fifth control transistor M7 includes an active layer 170, a control pole 173, a first pole 171, and a second pole 172. The active layer 170 includes a channel region 170a, a first doped region 170b, and a second doped region 170c. The second pole 172 of the fifth control transistor M7 is connected to the second doped region 170c of the active layer 170 through a first via K8 and further connected to the second doped region 170c through a second via H2. Sixth control transistor M8 is connected to the control pole 183 of the

[0151] In some exemplary embodiments, the sixth control transistor M8 includes an active layer 180, a control pole 183, a first pole 181, and a second pole 182. The active layer 180 includes a channel region 180a, a first doped region 180b, and a second doped region 180c. The control pole 183 of the sixth control transistor M8, the control poles 133a, 133b, and 133c of the first output transistor M3, and the first electrode 301 of the first capacitor C1 may be integrated into one structure. The first pole 181 of the sixth control transistor M8 is connected to the first doped region 180b of the active layer 180 through a first via K12. The first pole 181 of the sixth control transistor M8 and the first power line PL1a are integrated into one structure. The second pole 182 of the sixth control transistor M8 is connected to the second doped region 180c of the active layer 180 through a first via K11.

[0152] In some exemplary embodiments, the seventh control transistor M9 includes an active layer 190, a control electrode 193, a first electrode 191, and a second electrode 192. The active layer 190 includes a channel region 190a, a first doped region 190b, and a second doped region 190c. The first electrode 191 of the seventh control transistor M9 is connected to the first doped region 190b of the active layer 190 through a first via K9, and the second electrode 192 is connected to the second doped region 190c of the active layer 190 through a first via K10. The control electrode 193 of the seventh control transistor M9 of a given stage of shift register unit, the control electrodes 203a and 203b of the eighth control transistor M10 of the previous stage of shift register unit, and the first connecting electrode 501 of the previous stage of shift register unit are integrated. In this way, the first output signal output from the shift register unit of that stage is transmitted to the input terminal of the shift register unit of the next stage. The first connection electrode 501 is connected to the second pole 132 of the first output transistor M3 through two second vias H10 arranged in parallel.

[0153] In some exemplary embodiments, the eighth control transistor M10 includes an active layer 200, control electrodes 203a and 203b, a first electrode 201, and a second electrode 202. The active layer 200 includes channel regions 200a1, 200a2, and 200a3, a first doped region 200b, and a second doped region 200c. The active layer 200 of the eighth control transistor M10 and the active layer 110 of the first control transistor M1 have an integrated structure, and the second doped region 200c of the active layer 200 is connected to the second doped region 110c of the active layer 110. The control electrodes 203a and 203b of the eighth control transistor M10 have an integrated structure and may be connected to a sixth connecting electrode 506 through a second via H11. The sixth connecting electrode 506 may be connected to the first output terminal OUT1 through a third via D4. The first electrode 201 of the eighth control transistor M10 is connected to the first doped region 200b of the active layer 200 through a first via K18, and further connected to a second connection electrode 502 through a second via H7. The second connection electrode 502 is connected to the first electrode 131 of the first output transistor M3 through a second via H8, and further connected to a second clock signal line GCK2 through two second vias H9 that are vertically disposed.

[0154] In some exemplary embodiments, first output transistor M3 includes active layers 130-1 and 130-2, control poles 133a, 133b, and 133c, first pole 131, and second pole 132. Active layer 130-1 includes channel regions 130-1a1, 130-1a2, and 130-1a3, first doped region 130-1b, second doped region 130-1c, third doped region 130-1d, and fourth doped region 130-1e. Active layer 130-2 includes channel regions 130-2a1, 130-2a2, and 130-2a3, first doped region 130-2b, second doped region 130-2c, third doped region 130-2d, and fourth doped region 130-2e. The active layer 130-1 of the first output transistor M3 and the active layer 140-1 of the second output transistor M4 are integrated, and the fourth doped region 130-1e of the active layer 130-1 is connected to the second doped region 140-1c of the active layer 140-1. The active layer 130-2 of the first output transistor M3 and the active layer 140-2 of the second output transistor M4 are integrated, and the fourth doped region 130-2e of the active layer 130-2 is connected to the second doped region 140-2c of the active layer 140-1.

[0155] The first electrode 131 of the first output transistor M3 is connected to the first doped region 130-1b of the active layer 130-1 via a plurality of first vias K5 (e.g., seven first vias K5) arranged in parallel, connected to the first doped region 130-2b of the active layer 130-2 via a plurality of first vias K5 (e.g., seven first vias K5) arranged in parallel, further connected to the third doped region 130-1d of the active layer 130-1 via a plurality of first vias K3 (e.g., seven first vias K3) arranged in parallel, connected to the third doped region 130-2d of the active layer 130-2 via a plurality of first vias K3 (e.g., seven first vias K3) arranged in parallel, and further connected to the second connection electrode 502 via the second via H8.

[0156] The second pole 132 of the first output transistor M3 is connected to the second doped region 130-1c of the active layer 130-1 through a plurality of first vias K4 (e.g., seven first vias K4) arranged in parallel, to the second doped region 130-2c of the active layer 130-2 through a plurality of first vias K4 (e.g., seven first vias K4) arranged in parallel, to the fourth doped region 130-1e of the active layer 130-1 through a plurality of first vias K2 (e.g., seven first vias K2) arranged in parallel, and to the fourth doped region 130-2e of the active layer 130-2 through a plurality of first vias K2 (e.g., seven first vias K2) arranged in parallel. The second pole 132 of the first output transistor M3 is further connected to the second electrode 402 of the second capacitor C2 through three vertically arranged third vias D2, and to the first connecting electrode 501 through two parallelly arranged second vias H10. The second pole 132 of the first output transistor M3 and the second pole 142 of the second output transistor M4 have an integrated structure.

[0157] In some exemplary embodiments, the second output transistor M4 includes active layers 140-1 and 140-2, a control pole 143, a first pole 141, and a second pole 142. The active layer 140-1 includes a channel region 140-1a, a first doped region 140-1b, and a second doped region 140-1c. The active layer 140-2 includes a channel region 140-2a, a first doped region 140-2b, and a second doped region 140-2c. The first pole 141 of the second output transistor M4 is connected to the first doped region 140-1b of the active layer 140-1 through a plurality of first vias K1 (e.g., six first vias K1) arranged in parallel and is connected to the first doped region 140-2b of the active layer 140-2 through a plurality of first vias K1 (e.g., six first vias K1) arranged in parallel.

[0158] In some exemplary embodiments, the first capacitor C1 includes a first electrode 301 and a second electrode 401. The first electrode 301 and the control poles 133a1, 133a2, and 133a3 of the first output transistor M3 are integrated, and the second electrode 401 is connected to the second pole 132 of the first output transistor M3 through three vertically arranged third vias D2. The second capacitor C2 includes a first electrode 302 and a second electrode 402. The first electrode 302 and the control pole 143 of the second output transistor M4 are integrated, and the second electrode 402 is connected to the fourth power line PL2a through the third via D1.

[0159] In some exemplary embodiments, the first noise cancellation control transistor M11 includes an active layer 210, control electrodes 213a and 213b, a first electrode 211, and a second electrode 212. The active layer 210 includes channel regions 210a1, 210a2, and 210a3, a first doped region 210b, and a second doped region 210c. The active layer 210 of the first noise cancellation control transistor M11 and the active layer 220 of the second noise cancellation control transistor M12 are integrated into one structure, and the second doped region 210c of the active layer 210 is connected to the second doped region 220c of the active layer 220. The control electrodes 213a and 213b of the first noise cancellation control transistor M11 and the control electrodes 243a and 243b of the fourth noise cancellation control transistor M14 are integrated into one structure and are connected to the fourth connecting electrode 504 through a second via H16. The fourth connection electrode 504 may be connected to the first output terminal OUT1 through a third via D5. The first electrode 211 of the first noise removal control transistor M11 is connected to the first doped region 210b of the active layer 210 through a first via K21. First noise elimination control transistor M11 The second pole 212 of the first noise cancellation control transistor M11 is connected to the second doped region 210c of the active layer 210 through four first vias K20 arranged in a 2*2 array, and is further connected to the first electrode 303 of the third capacitor C3 through a second via H12. The first pole 211 of the first noise cancellation control transistor M11 and the first pole 241 of the fourth noise cancellation control transistor M14 are integrated into one structure. The second pole 212 of the first noise cancellation control transistor M11 and the second pole 222 of the second noise cancellation control transistor M12 are integrated into one structure.

[0160] In some exemplary embodiments, the second noise reduction control transistor M12 includes an active layer 220, a control pole 223, a first pole 221, and a second pole 222. The active layer 220 includes a channel region 220a, a first doped region 220b, and a second doped region 220c. The first pole 221 of the second noise reduction control transistor M12 is connected to the first doped region 220b of the active layer 220 through two first vias K19 arranged in parallel.

[0161] In some exemplary embodiments, the third noise reduction control transistor M13 includes an active layer 230, a control pole 233, a first pole 231, and a second pole 232. The active layer 230 includes a channel region 230a, a first doped region 230b, and a second doped region 230c. The control pole of the third noise reduction control transistor M13 and the first electrode 303 of the third capacitor C3 have an integrated structure. The first pole 231 of the third noise reduction control transistor M13 is connected to the first doped region 230b of the active layer 230 through two first vias K24 arranged in parallel, and is further connected to the first electrode 303 of the third capacitor C3 through two second vias H13 arranged in parallel. The second pole 232 of the third noise elimination control transistor M13 is connected to the second doped region 230c of the active layer 230 through two first vias K25 arranged in parallel, and is further connected to the first electrode 304 of the fourth capacitor C4 through two second vias H14 arranged in parallel.

[0162] In some exemplary embodiments, the fourth noise cancellation control transistor M14 includes an active layer 240, control poles 243a and 243b, a first pole 241, and a second pole 242. The active layer 240 includes channel regions 240a1, 240a2, and 240a3, a first doped region 240b, and a second doped region 240c. The first pole 241 of the fourth noise cancellation control transistor M14 is connected to the first doped region 240b of the active layer 240 through a first via K22. The second pole 242 of the fourth noise cancellation control transistor M14 is connected to the second doped region 240c of the active layer 240 through a first via K23 and is further connected to the first electrode 304 of the fourth capacitor C4 through a second via H15.

[0163] In some exemplary embodiments, the third output transistor M15 includes active layers 250-1 and 250-2, a control electrode 253, a first electrode 251, and a second electrode 252. The active layer 250-1 includes a channel region 250-1a, a first doped region 250-1b, and a second doped region 250-1c. The active layer 250-2 includes a channel region 250-2a, a first doped region 250-2b, and a second doped region 250-2c. The active layer 250-1 of the third output transistor M15 and the active layer 260-1 of the fourth output transistor M16 are integrated into one structure, and the second doped region 250-1c of the active layer 250-1 is connected to the fourth doped region 260-1e of the active layer 260-1. The active layer 250-2 of the third output transistor M15 and the active layer 260-2 of the fourth output transistor M16 are integrated, and the second doped region 250-2c of the active layer 250-2 is connected to the fourth doped region 260-2e of the active layer 260-2. First electrode 304 is an integrated structure.

[0164] The first electrode 251 of the third output transistor M15 is connected to the first doped region 250-1b of the active layer 250-1 through a plurality of first vias K30 (e.g., four first vias K30) arranged in parallel, and is further connected to the first doped region 250-2b of the active layer 250-2 through a plurality of first vias K30 (e.g., four first vias K30) arranged in parallel. The first electrode 251 of the third output transistor M15 and the third power line PL1b have an integrated structure.

[0165] The second pole 252 of the third output transistor M15 is connected to the second doped region 250-1c of the active layer 250-1 through a plurality of first vias K29 (e.g., four first vias K29) arranged in parallel, and is further connected to the second doped region 250-2c of the active layer 250-2 through a plurality of first vias K29 (e.g., four first vias K29) arranged in parallel. The second pole 252 of the third output transistor M15 and the second pole 262 of the fourth output transistor M16 have an integrated structure.

[0166] In some exemplary embodiments, fourth output transistor M16 includes active layers 260-1 and 260-2, control poles 263a, 263b, and 263c, first pole 261, and second pole 262. Active layer 260-1 includes channel regions 260-1a1, 260-1a2, and 260-1a3, first doped region 260-1b, second doped region 260-1c, third doped region 260-1d, and fourth doped region 260-1e. Active layer 260-2 includes channel regions 260-2a1, 260-2a2, and 260-2a3, first doped region 260-2b, second doped region 260-2c, third doped region 260-2d, and fourth doped region 260-2e.

[0167] The control electrodes 263a, 263b, and 263c of the fourth output transistor M16 have an integrated structure and are connected to a fifth connection electrode 505 through two vertically disposed second vias H17. The fifth connection electrode 505 is connected to a sixth connection electrode 506 through a fourth via F2. The sixth connection electrode 506 is connected to the second electrode 172 of the fifth control transistor M7 through a fourth via F1.

[0168] The first electrode 261 of the fourth output transistor M16 is connected to the first doped region 260-1b of the active layer 260-1 through a plurality of first vias K26 (e.g., four first vias K26) arranged in parallel, to the first doped region 260-2b of the active layer 260-2 through a plurality of first vias K26 (e.g., four first vias K26) arranged in parallel, to the third doped region 260-1d of the active layer 260-1 through a plurality of first vias K28 (e.g., four first vias K28) arranged in parallel, and to the third doped region 260-2d of the active layer 260-2 through a plurality of first vias K28 (e.g., four first vias K28) arranged in parallel. The first electrode 261 of the fourth output transistor M16 is further connected to the third connection electrode 503 through two third vias D8 arranged in parallel. The third connection electrode 503 is connected to the fourth clock signal line GCB1 through two third vias D9 that are vertically disposed.

[0169] The second electrode 262 of the fourth output transistor M16 is connected to the second doped region 260-1c of the active layer 260-1 through a plurality of first vias K27 (e.g., four first vias K27) arranged in parallel, and is connected to the second doped region 260-2c of the active layer 260-2 through a plurality of first vias K27 (e.g., four first vias K27) arranged in parallel. The second electrode 262 of the fourth output transistor M16 is connected to the second output terminal OUT2 through two third vias D10 arranged vertically.

[0170] In some exemplary embodiments, the third capacitor C3 includes a first electrode 303 and a second electrode 403, the first electrode 303 of which is connected to the first pole 231 of the third noise cancellation control transistor M13 and the second pole 222 of the second noise cancellation control transistor M12, and the second electrode 403 of which is connected to the first clock signal line GCK1 through two vertically arranged third vias D6. The fourth capacitor C4 includes a first electrode 304 and a second electrode 404, the first electrode 304 of which is connected to the second pole 232 of the third noise cancellation control transistor M13 and the second pole 242 of the fourth noise cancellation control transistor M14, and the second electrode 404 of which is connected to the third power line PL1b through two vertically arranged third vias D7.

[0171] In some exemplary embodiments, as shown in FIGS. 5 to 7F , the control electrode 113 of the first control transistor M1 of the 6n+1-th stage shift register unit may be connected to the first clock signal line GCK1 through a second via, and the second electrode 403 of the third capacitor C3 may be connected to the first clock signal line GCK1 through a third via. The control electrode of the third control transistor M5 and the control electrode of the second noise reduction control transistor M12 are integrated and may be connected to the third clock signal line GCK3 through a second via. The second connecting electrode 502 is connected to the second clock signal line GCK2, and the second connecting electrode 502 is connected to the first pole 201 of the eighth control transistor M10 and the first pole 131 of the first output transistor M3. The first pole 261 of the fourth output transistor M16 is connected to the fourth clock signal line GCB1 through a third connecting electrode 503.

[0172] In some exemplary embodiments, as shown in FIGS. 5 to 7F, the control electrode 113 of the first control transistor M1 of the (6n+2)-th stage shift register unit may be connected to the second clock signal line GCK2 through a second via, and the third capacitor C3 Second electrode 403 The control electrode of the third control transistor M5 and the control electrode of the second noise removal control transistor M12 are integrated and can be connected to the first clock signal line GCK1 through a second via. The second connecting electrode 502 can be connected to the third clock signal line GCK3, and the second connecting electrode 502 is connected to the first pole 201 of the eighth control transistor M10 and the first pole 131 of the first output transistor M3. The first pole 261 of the fourth output transistor M16 is connected to the fifth clock signal line GCB2 through a third connecting electrode 503.

[0173] In this exemplary embodiment, the connection method between the shift register units at each stage and the clock signal lines of the first group and the clock signal lines of the second group can be determined by referring to the cascade connection relationship of the shift register units shown in FIG. 4 and the structure of the shift register units shown in FIGS. 5 to 7F, so it will not be described again here.

[0174] The structure of a display substrate will be described below using an example of a manufacturing process for a display substrate. The "patterning process" described in this disclosure includes the processes of depositing a film layer, applying photoresist, mask exposure, development, etching, and photoresist stripping. The deposition may be performed by one or more of sputtering, evaporation, and chemical vapor deposition. The application may be performed by one or more of spray coating and spin coating. The etching may be performed by one or more of dry etching and wet etching. A "thin film" refers to a thin film layer fabricated by a deposition or application process based on a certain material. If the "thin film" does not require a patterning process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern."

[0175] In the present disclosure, "A and B are disposed on the same layer" means that A and B are formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B is within the boundary range of the projection of A, or the boundary of the projection of A overlaps the boundary of the projection of B.

[0176] The manufacturing process of the display substrate according to this exemplary embodiment includes the following steps.

[0177] (1) Provide a base substrate. In some exemplary embodiments, the base substrate 60 may be a rigid base or a flexible base. A rigid base may include one or more of glass, a metal foil sheet, and a flexible base may include one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0178] (2) Forming a first semiconductor layer pattern. In some exemplary embodiments, as shown in FIG. 7A , a first insulating thin film and a first semiconductor thin film are sequentially deposited on a base substrate 60, and the first semiconductor thin film is patterned by a patterning process to form a first insulating layer 61 covering the entire base substrate 60 and a first semiconductor layer pattern disposed on the first insulating layer 61. The first semiconductor layer pattern includes at least active layers of multiple transistors (e.g., transistors M1 to M16) in the shift register unit. The active layers may include at least one channel region and multiple doped regions. The doped regions may be undoped with impurities or may have semiconductor properties. The doped regions are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor thin film may be polysilicon.

[0179] (3) Forming a first conductive layer pattern. 7B , a second insulating thin film and a first conductive thin film are sequentially deposited on the patterned base substrate 60, and the first conductive thin film is patterned by a patterning process to form a second insulating layer 62 covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer 62. In some examples, the first conductive layer pattern may include control electrodes of multiple transistors (e.g., transistors M1 to M16) of the shift register unit, first electrodes of multiple capacitors (e.g., first capacitor C1 to fourth capacitor C4) of the shift register unit, and multiple connecting electrodes (e.g., first connecting electrode 501 and second connecting electrode 502).

[0180] (4) forming a second conductive layer pattern; 7C , a third insulating thin film and a second conductive thin film are sequentially deposited on the patterned base substrate 60, and the second conductive thin film is patterned by a patterning process to form a third insulating layer 63 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 63. In some examples, the second conductive layer pattern may include second electrodes of a plurality of capacitors (e.g., the first capacitor C1 to the fourth capacitor C4) of the shift register unit, a first output terminal OUT1, a second output terminal OUT2, and a connecting electrode (e.g., the third connecting electrode 503).

[0181] (5) Forming a fourth insulating layer pattern. In some exemplary embodiments, as shown in FIG. 7D , a fourth insulating thin film is deposited on the patterned base substrate 60, and the fourth insulating thin film is patterned by a patterning process to form a fourth insulating layer 64 pattern covering the second conductive layer. In some examples, a plurality of vias are opened in the fourth insulating layer 64. The plurality of vias includes at least a plurality of first vias K1-K30, a plurality of second vias H1-H17, and a plurality of third vias D1-D10. The fourth insulating layer 64, the third insulating layer 63, and the second insulating layer 62 in the plurality of first vias K1-K30 are etched to expose the surface of the first semiconductor layer. The fourth insulating layer 64 and the third insulating layer 63 in the plurality of second vias H1-H17 are etched to expose the surface of the first conductive layer. The fourth insulating layer 64 in the plurality of third vias D1-D10 is etched to expose the surface of the second conductive layer.

[0182] (6) Forming a third conductive layer pattern. 7E, a third conductive thin film is deposited on the base substrate 60 on which the above-described pattern is formed, and the third conductive thin film is patterned by a patterning process to form a third conductive layer pattern on the fourth insulating layer 64. In some examples, the third conductive layer pattern may include first and second poles of a plurality of transistors (e.g., transistors M1 to M16) of the shift register unit, a first group of clock signal lines (e.g., including a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3), a second group of clock signal lines (e.g., including a fourth clock signal line GCB1 and a fifth clock signal line GCB2), a plurality of power supply lines (e.g., a first power supply line PL1a, a fourth power supply line PL2a, a third power supply line PL1b, and a second power supply line PL2b), and connecting electrodes (e.g., a fourth connecting electrode 504, a fifth connecting electrode 505, and a sixth connecting electrode 506).

[0183] (7) Forming patterns of the fifth insulating layer and the sixth insulating layer. In some exemplary embodiments, a fifth insulating thin film 65 is deposited on the base substrate 60 on which the above pattern has been formed, then a sixth insulating thin film is applied, and a sixth insulating layer 66 pattern is formed by masking, exposing, and developing the sixth insulating thin film. Then, a patterning process is performed on the fifth insulating thin film to form the fifth insulating layer 65 pattern. In some examples, a plurality of vias are formed in the sixth insulating layer 66. For example, the plurality of vias may include a plurality of fourth vias F1-F3. The fifth insulating layer 65 and the sixth insulating layer 66 in the plurality of fourth vias F1-F3 are etched to expose the surface of the third conductive layer.

[0184] (8) Form a fourth conductive layer pattern. 7F , a fourth conductive thin film is deposited on the base substrate 60 on which the above-described pattern has been formed, and the fourth conductive thin film is patterned by a patterning process to form a fourth conductive layer pattern in the sixth insulating layer 66. In some examples, the fourth conductive layer pattern includes at least a connecting electrode, and may include, for example, the seventh connecting electrode 507 and the third connecting line 703.

[0185] In some exemplary embodiments, a shift register unit may be formed in the non-display area, while a pixel circuit may be formed in the display area. For example, the first semiconductor layer in the display area may include an active layer of a transistor in the pixel driving circuit. The first conductive layer in the display area may include a control electrode of a transistor in the pixel driving circuit and a first electrode of a storage capacitor. The second conductive layer in the display area may include at least a second electrode of a storage capacitor in the pixel driving circuit. The third conductive layer in the display area may include at least a first electrode and a second electrode of a transistor in the pixel driving circuit. The fourth conductive layer in the display area may include at least a connection electrode between the pixel driving circuit and an anode of the light-emitting element. After forming the first conductive layer, a second semiconductor layer may be formed in the display area, with an insulating layer disposed between the second semiconductor layer and the first conductive layer. The material of the second semiconductor thin film may be a metal oxide, such as IGZO. However, this embodiment does not limit the location of the second semiconductor layer.

[0186] In some exemplary embodiments, after forming the fourth conductive layer, a pattern of a seventh insulating layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer may be sequentially formed in the display area. In some examples, a seventh insulating thin film is applied to the patterned base substrate, and a seventh insulating layer pattern is formed by masking, exposing, and developing the seventh insulating thin film. Then, an anode thin film is deposited on the patterned base substrate in the display area, and the anode thin film is patterned by a patterning process to form an anode pattern in the seventh insulating layer. Then, a pixel definition thin film is applied to the patterned base substrate, and a pixel definition layer (PDL) pattern is formed by masking, exposing, and developing. The pixel definition layer is formed in each subpixel of the display area, and a pixel opening exposing the anode is formed in the pixel definition layer in each subpixel. Then, an organic light-emitting layer is formed in the formed pixel opening, and the organic light-emitting layer is connected to the anode. Then, a cathode thin film is deposited and patterned by a patterning process to form a cathode pattern, and the cathodes are respectively connected to the organic light-emitting layer and the second power line. Then, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material. In some possible implementations, the cathodes can be connected to the second power line by multiple methods, such as laser drilling.

[0187] In some exemplary embodiments, the first, second, third, and fourth conductive layers may be made of metal materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers 61, 62, 63, 64, and 65 may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be made of a single layer, multi-layer, or composite. The sixth and seventh insulating layers 66 and 67 may be made of organic materials, such as polyimide, acrylic, or polyethylene terephthalate. The first insulating layer 61 may be referred to as a buffer layer, and is configured to improve the water and oxygen resistance of the base substrate 60. The second insulating layer 62 and the third insulating layer 63 are referred to as gate insulating (GI) layers, the fourth insulating layer 64 is referred to as an interlayer insulating (ILD) layer, the fifth insulating layer is referred to as a PVX layer, and the sixth insulating layer 66 and the seventh insulating layer are referred to as planarization layers. The pixel defining layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode may be made of one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy composed of one or more of the above metals. However, this embodiment is not limited thereto. For example, the anode may be made of a reflective material such as a metal, and the cathode may be made of a transparent conductive material.

[0188] The structures and manufacturing processes shown in the exemplary embodiments are merely illustrative. In some exemplary embodiments, the corresponding structures may be modified or the patterning process may be increased or decreased according to actual needs. For example, the fourth conductive layer may not be provided. Also, for example, the order of the clock signal lines in the first group of clock signal lines may be changed, and the order of the clock signal lines in the second group of clock signal lines may be changed. However, this embodiment is not limited thereto.

[0189] The manufacturing process according to the exemplary embodiment can be realized using currently mature manufacturing equipment, is highly compatible with conventional manufacturing processes, is simple to realize and easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0190] In the display substrate according to this exemplary embodiment, the first output circuit and the second output circuit are configured to share a clock signal line, and a first group of clock signal lines, a first power supply line and a second power supply line are arranged between the first output circuit and the second output circuit, thereby improving the layout density of the shift register unit, contributing to the realization of a narrow frame, and reducing the load on the clock signal line, contributing to the improvement of the performance of the shift register unit.

[0191] In some exemplary embodiments, the gate drive circuit includes a plurality of cascaded shift register units. A first output terminal of a (2k-1)-stage shift register unit is connected to an input terminal of a (2k+1)-stage shift register unit, and an input terminal of the first-stage shift register unit is connected to a first initial signal line STVO. A first output terminal of a (2k)-stage shift register unit is connected to an input terminal of a (2k+2)-stage shift register unit, and an input terminal of the second-stage shift register unit is connected to a second initial signal line STVE, where k is a positive integer.

[0192] In some exemplary embodiments, the first group of clock signal lines includes a first subgroup clock signal line and a second subgroup clock signal line, the second group of clock signal lines includes a third subgroup clock signal line and a fourth subgroup clock signal line, the (2k-1)-stage shift register unit is connected to the first subgroup clock signal line and the third subgroup clock signal line, and the (2k-1)-stage shift register unit is connected to the second subgroup clock signal line and the fourth subgroup clock signal line.

[0193] In some example embodiments, the first subgroup clock signal lines include a first clock signal line GCKO1, a second clock signal line GCKO2, and a third clock signal line GCKO3. The second subgroup clock signal lines include a sixth clock signal line GCKE1, a seventh clock signal line GCKE2, and an eighth clock signal line GCKE3. The third subgroup clock signal lines include a fourth clock signal line GCBO1 and a fifth clock signal line GCBO2. The fourth subgroup clock signal lines include a ninth clock signal line GCBE1 and a tenth clock signal line GCBE2.

[0194] In this exemplary embodiment, the odd-numbered shift register units are cascaded in sequence and connected to the first sub-group clock signal line and the third sub-group clock signal line, and the even-numbered shift register units are cascaded in sequence and connected to the second sub-group clock signal line and the fourth sub-group clock signal line. The gate driving circuit of this exemplary embodiment increases the number of clock signals and adopts odd-numbered and even-numbered row driving, thereby increasing the charging time length and ensuring pixel charging effect, and is applicable to high-frequency driving mode.

[0195] 8 is another schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG. 8, the 12n+1-th stage shift register unit has a first clock end connected to the first clock signal line GCKO1, a second clock end connected to the second clock signal line GCKO2, a third clock end connected to the third clock signal line GCKO3, and a fourth clock end connected to the fourth clock signal line GCBO1.

[0196] The 12n+3-stage shift register unit has a first clock end connected to the second clock signal line GCKO2, a second clock end connected to the third clock signal line GCKO3, a third clock end connected to the first clock signal line GCKO1, and a fourth clock end connected to the fifth clock signal line GCBO2.

[0197] The 12n+5th stage shift register unit has a first clock end connected to the third clock signal line GCKO3, a second clock end connected to the first clock signal line GCKO1, a third clock end connected to the second clock signal line GCKO2, and a fourth clock end connected to the fourth clock signal line GCBO1.

[0198] The 12n+7-stage shift register unit has a first clock end connected to the first clock signal line GCKO1, a second clock end connected to the second clock signal line GCKO2, a third clock end connected to the third clock signal line GCKO3, and a fourth clock end connected to the fifth clock signal line GCBO2.

[0199] The 12n+9th stage shift register unit has a first clock end connected to the second clock signal line GCKO2, a second clock end connected to the third clock signal line GCKO3, a third clock end connected to the first clock signal line GCKO1, and a fourth clock end connected to the fourth clock signal line GCBO1.

[0200] The 12n+11th stage shift register unit has a first clock end connected to the third clock signal line GCKO3, a second clock end connected to the first clock signal line GCKO1, a third clock end connected to the second clock signal line GCKO2, and a fourth clock end connected to the fifth clock signal line GCBO2.

[0201] The 12n+2-th stage shift register unit has a first clock end connected to the sixth clock signal line GCKE1, a second clock end connected to the seventh clock signal line GCKE2, a third clock end connected to the eighth clock signal line GCKE3, and a fourth clock end connected to the ninth clock signal line GCBE1.

[0202] The 12n+4th stage shift register unit has a first clock end connected to the seventh clock signal line GCKE2, a second clock end connected to the eighth clock signal line GCKE3, a third clock end connected to the sixth clock signal line GCKE1, and a fourth clock end connected to the tenth clock signal line GCBE2.

[0203] The 12n+6th stage shift register unit has a first clock end connected to the eighth clock signal line GCKE3, a second clock end connected to the sixth clock signal line GCKE1, a third clock end connected to the seventh clock signal line GCKE2, and a fourth clock end connected to the ninth clock signal line GCBE1.

[0204] The 12n+8th stage shift register unit has a first clock end connected to the sixth clock signal line GCKE1, a second clock end connected to the seventh clock signal line GCKE2, a third clock end connected to the eighth clock signal line GCKE3, and a fourth clock end connected to the tenth clock signal line GCBE2.

[0205] The 12n+10th stage shift register unit has a first clock end connected to the seventh clock signal line GCKE2, a second clock end connected to the eighth clock signal line GCKE3, a third clock end connected to the sixth clock signal line GCKE1, and a fourth clock end connected to the ninth clock signal line GCBE1.

[0206] The 12n+12th stage shift register unit has a first clock end connected to the eighth clock signal line GCKE3, a second clock end connected to the sixth clock signal line GCKE1, a third clock end connected to the seventh clock signal line GCKE2, and a fourth clock end connected to the tenth clock signal line GCBE2, where n is a natural number.

[0207] The 12 shift register units of the gate driving circuit according to this embodiment are used as one minimum period repeating unit, and can drive 12 rows of sub-pixels.

[0208] 9 is a timing diagram of clock signals according to at least one embodiment of the present disclosure. As shown in FIG. 9, the first clock signal from the first clock signal line GCKO1, the second clock signal from the second clock signal line GCKO2, the third clock signal from the third clock signal line GCKO3, the fourth clock signal from the fourth clock signal line GCBO1, the fifth clock signal from the fifth clock signal line GCBO2, the sixth clock signal from the sixth clock signal line GCKE1, the seventh clock signal from the seventh clock signal line GCKE2, the eighth clock signal from the eighth clock signal line GCKE3, the ninth clock signal from the ninth clock signal line GCBE1, and the tenth clock signal from the tenth clock signal line GCBE2 ​​are all pulse signals.

[0209] 9, the first, second, third, sixth, seventh, and eighth clock signals may have the same duty cycle. The second clock signal is delayed from the first clock signal by a first set length of time (e.g., 2H), and the third clock signal is delayed from the second clock signal line by a first set length of time (e.g., 2H), so that the first, second, and third clock signals are not simultaneously at a low voltage. The seventh clock signal is delayed from the sixth clock signal by a first set length of time (e.g., 2H), and the eighth clock signal is delayed from the seventh clock signal line by a first set length of time (e.g., 2H), so that the sixth, seventh, and eighth clock signals are not simultaneously at a low voltage. The sixth clock signal is delayed by a second set time length (e.g., 1H) from the first clock signal, the seventh clock signal is delayed by a second set time length (e.g., 1H) from the second clock signal, and the eighth clock signal is delayed by a second set time length (e.g., 1H) from the third clock signal.

[0210] In some exemplary embodiments, as shown in FIG. 9, the second initial signal via the second initial signal line STVE is delayed by 1H from the first initial signal via the first initial signal line STVO.

[0211] In some exemplary embodiments, as shown in FIG. 9 , the fourth clock signal, the fifth clock signal, the ninth clock signal, and the tenth clock signal may have the same duty cycle. The duty cycle of the fourth clock signal may be smaller than the duty cycle of the first clock signal. The fourth clock signal and the fifth clock signal are not simultaneously at a high voltage, and the ninth clock signal and the tenth clock signal are not simultaneously at a high voltage. The ninth clock signal is delayed by a second set time length (e.g., 1H) from the fourth clock signal, and the tenth clock signal is delayed by a second set time length (e.g., 1H) from the fifth clock signal.

[0212] 8 may include a first stage OS1, a second stage OS2, a third stage OS3, and a fourth stage OS4. The operation process of the second stage shift register unit may include a first stage ES1, a second stage ES2, a third stage ES3, and a fourth stage ES4. The operation processes of the four stages can be referred to the description of the operation process of the shift register unit according to the above embodiment, and will not be described again here.

[0213] 10 is another top view of a shift register unit according to at least one embodiment of the present disclosure. In FIG. 10, 12n+1-stage and 12n+2-stage shift register units (e.g., n=1) are shown as examples. The following description mainly focuses on the structure of the 12n+1-stage shift register unit.

[0214] 11A is a top view of a shift register unit after forming a first semiconductor layer according to at least one embodiment of the present disclosure. FIG. 11B is another top view of a shift register unit after forming a first conductive layer according to at least one embodiment of the present disclosure. FIG. 11C is another top view of a shift register unit after forming a second conductive layer according to at least one embodiment of the present disclosure. FIG. 11D is another top view of a shift register unit after forming a third conductive layer according to at least one embodiment of the present disclosure. FIG. 11E is another top view of a shift register unit after forming a fourth conductive layer according to at least one embodiment of the present disclosure.

[0215] 10, in a plane parallel to the display substrate, in the first direction X, the second initial signal line STVE is located between the first initial signal line STVO and the fourth power supply line PL2a, the first group of clock signal lines is located between the first power supply line PL1a and the second power supply line PL2b, and the third power supply line PL1b is located between the second power supply line PL2b and the second group of clock signal lines. The first group of clock signal lines is called the first sub-group of clock signal lines. Second subgroup clock signal lineThe first subgroup clock signal lines and the second subgroup clock signal lines are arranged at intervals in the first direction X. In this example, the first subgroup clock signal lines include the first clock signal line GCKO1, the second clock signal line GCKO2, and the third clock signal line GCKO3, and the second subgroup clock signal lines include the sixth clock signal line GCKE1, the seventh clock signal line GCKE2, and the eighth clock signal line GCKE3. In the first direction D1 from the first power supply line PL1a to the second power supply line PL2b, the first clock signal line GCKO1, the sixth clock signal line GCKE1, the second clock signal line GCKO2, the seventh clock signal line GCKE2, the third clock signal line GCKO3, and the eighth clock signal line GCKE3 are arranged in sequence. The second group clock signal lines include the third subgroup clock signal line and the fourth subgroup clock signal line. The third subgroup clock signal lines include the fourth clock signal line GCBO1 and the fifth clock signal line GCBO2, and the fourth subgroup clock signal lines include the ninth clock signal line GCBE1 and the tenth clock signal line GCBE2. In the first direction D1 away from the second output circuit, the fourth clock signal line GCBO1, the ninth clock signal line GCBE1, the fifth clock signal line GCBO2, and the tenth clock signal line GCBE2 ​​are arranged sequentially. However, this embodiment is not limited thereto. In some examples, the first subgroup clock signal lines and the second subgroup clock signal lines may be arranged sequentially along the first direction. The third subgroup clock signal lines and the fourth subgroup clock signal lines may be arranged sequentially along the first direction.

[0216] 11B, the first conductive layer in the non-display area includes at least the control electrodes of the transistors (e.g., transistors M1 to M16) of the shift register unit and the first electrodes of the capacitors (e.g., the first capacitor C1 to the fourth capacitor C4). The control electrodes 203a and 203b of the eighth control transistor M10 of the shift register unit of any stage and the first connecting electrode 501 may be integrated and not connected to the control electrode 193 of the seventh control transistor M9 of the shift register unit of the next stage.

[0217] 11D , the third conductive layer in the non-display area may include first and second poles of a plurality of transistors (e.g., transistors M1 to M16) of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, a plurality of power lines, and connecting electrodes (e.g., the eighth connecting electrode 508 and the ninth connecting electrode 509). For example, the control electrode 193 of the seventh control transistor M9 of the 12n+1-th shift register unit may be connected to the eighth connecting electrode 508 through two vertically installed second vias H18 and connected to the first output terminal OUT1 of the 12n-1-th shift register unit through the eighth connecting electrode 508. The first output terminal OUT1 of the 12n+1th shift register unit is connected to another eighth connection electrode 508 through a third via D11, and is connected to the control electrode 193 of the seventh control transistor M9 of the 12n+3th shift register unit through the eighth connection electrode 508, thereby providing an input signal to the 12n+3th shift register unit. The control electrode 193 of the seventh control transistor M9 of the 12n+2th shift register unit is connected to the ninth connection electrode 509 through two vertically arranged second vias H19, and is connected to the first output terminal OUT1 of the 12nth shift register unit through the ninth connection electrode 509.

[0218] In some exemplary embodiments, as shown in FIGS. 10 to 11E , the control electrode of the third control transistor M5 and the control electrode of the second noise cancellation control transistor M12 in the 12n+1-stage shift register unit may be integrated and connected to the third clock signal line GCKO3 via a second via. The second electrode of the third capacitor C3 is connected to the first clock signal line GCKO1 via a third via. The control electrode of the first control transistor M1 is connected to the first clock signal line GCKO1 via a second via. The second connecting electrode connected to the first electrode of the eighth control transistor M10 may be connected to the second clock signal line GCKO2 via a second via, and the second connecting electrode is further connected to the first electrode of the first output transistor M3 via a second via. The first electrode of the fourth output transistor M16 is connected to the fourth clock signal line GCBO1 via a third connecting electrode.

[0219] In some exemplary embodiments, as shown in FIGS. 10 to 11E , the control electrode of the third control transistor M5 and the control electrode of the second noise cancellation control transistor M12 in the 12n+2-stage shift register unit may be integrated and connected to the eighth clock signal line GCKE3 through a second via. The second electrode of the third capacitor C3 is connected to the sixth clock signal line GCKE1 through a third via. The control electrode of the first control transistor M1 is connected to the sixth clock signal line GCKE1 through a second via. The second connecting electrode connected to the first electrode of the eighth control transistor M10 may be connected to the seventh clock signal line GCKE2 through a second via, and the second connecting electrode is further connected to the first electrode of the first output transistor M3 through a second via. The first electrode of the fourth output transistor M16 is connected to the ninth clock signal line GCBE1 through a third connecting electrode.

[0220] The cascade connection relationship of the shift register units according to this embodiment can be seen in FIG. 8, and the remaining structure of the display substrate according to this embodiment can be seen in the description of the above embodiment, so it will not be described again here.

[0221] An embodiment of the present disclosure further provides a method for manufacturing the display substrate described above. The manufacturing method according to the embodiment includes providing a base substrate and forming a gate driving circuit in a non-display area. The gate driving circuit includes a plurality of cascaded shift register units, each connected to at least one power supply line. The shift register unit includes a first output circuit and a second output circuit, the first output circuit connected to a first group of clock signal lines, and the second output circuit connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on a side of the second output circuit away from the first group of clock signal lines.

[0222] Regarding the manufacturing method of the display substrate according to this embodiment, the description of the above embodiment can be referred to, and therefore, the description will not be repeated here.

[0223] FIG. 12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 12, this embodiment provides a display device 91, which includes a display substrate 910. The display substrate 910 is a display substrate according to the above-described embodiments. The display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be a product or component with a display function, such as an OLED display device, a watch, a mobile phone, a tablet, a television, a monitor, a laptop, a digital frame, a navigation system, etc. However, this embodiment is not limited thereto.

[0224] The drawings in this disclosure only relate to the structures disclosed herein, and other structures may refer to conventional designs. Where there is no conflict, the embodiments and features of the embodiments in this disclosure may be combined with each other to obtain new embodiments. As will be understood by those skilled in the art, modifications or equivalent substitutions may be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure. Any such modifications or equivalent substitutions should be included within the scope of the claims of this disclosure. [Explanation of symbols]

[0225] 10 First output circuit 20 Second output circuit V1 1st power supply terminal V2 2nd power terminal N1~N4 1st to 4th nodes CK1~3 1st to 3rd clock terminals CB 4th clock terminal INPUT Input terminal OUT1 First output terminal OUT2 Second output terminal PD1 Noise reduction control node No. 1 PD2 Second noise reduction control node C1~C4 1st to 4th capacitors M1 First control transistor M2 Second control transistor M3 First output transistor M4 Second output transistor M5 to M10 3rd to 8th control transistors M11 to M14: 1st to 4th noise elimination control transistors M15 Third output transistor M16 4th output transistor S1 Precharge stage S2 Bootstrap output stage S3 node pull-up phase S4 Maintenance Phase STV initial signal line GCK1~3 1st to 3rd clock signal lines GCB1 4th clock signal line GCB2 5th clock signal line PL1a 1st power line PL2b 2nd power line PL1b 3rd power line PL2a 4th power line 60 Base board 61~66 1st to 6th insulating layers 230 Active layer 231 1st pole 232 2nd pole 233 Control pole 263a~263c Control pole 301~304 1st electrode 401~404 2nd electrode 501 to 509 1st to 9th connection electrodes 701~703 1st~3rd connecting lines

Claims

1. a display substrate, comprising a display area and a non-display area, a gate driving circuit installed in the non-display area, the gate driving circuit including a plurality of cascaded shift register units, the shift register units being connected to at least one power line; the shift register unit includes a first output circuit and a second output circuit, the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines; In a first direction, the clock signal lines of the first group and at least one power supply line are located between the first output circuit and the second output circuit, and the clock signal lines of the second group are located on a side of the second output circuit that is away from the clock signal lines of the first group; the first output circuit includes a first node control subcircuit, a second node control subcircuit, and a first output subcircuit; the first node control subcircuit is connected to the input terminal, the first output terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power supply terminal, the second power supply terminal, the first node and the second node, and is configured to control the potentials of the first node and the second node under the control of the first clock terminal, the third clock terminal and the input terminal; the second node control subcircuit is connected to the first node, the second node, the second power supply terminal, and the first output terminal, and is configured to maintain the potentials of the first node and the second node; the first output sub-circuit is connected to a first node, a second node, a second clock terminal, a second power supply terminal and a first output terminal, and is configured to control output of a first output signal by the first output terminal under control of the first node and the second node; The second node control sub-circuit, the first output sub-circuit and the first node control sub-circuit are sequentially arranged along a first direction.

2. the at least one power supply line includes a first power supply line and a second power supply line, the first power supply line is connected to a first output circuit, and the second power supply line is connected to a second output circuit; 2. The display substrate of claim 1, wherein, in the first direction, the first power supply line is located between the first output circuit and a first group of clock signal lines, and the second power supply line is located between the first group of clock signal lines and a second output circuit.

3. a third power line and a fourth power line are further installed in the non-display area; the third power supply line is connected to a second output circuit, and the fourth power supply line is connected to a first output circuit; 3. The display substrate of claim 2, wherein, in the first direction, the fourth power supply line is located on a side away from the first power supply line of the first output circuit, and the third power supply line is located between the second power supply line and a second group of clock signal lines.

4. the first node control subcircuit includes a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor; the first control transistor has a control pole connected to a first clock terminal, a first pole connected to an input terminal, and a second pole connected to a fourth node; the second control transistor has a control pole connected to the first clock terminal, a first pole connected to the fourth node, and a second pole connected to the first node; the third control transistor has a control pole connected to a third clock terminal, a first pole connected to a first power supply terminal, and a second pole connected to a second node; the fourth control transistor has a control electrode connected to a second node, a first electrode connected to a second power supply terminal, and a second electrode connected to a third node; the fifth control transistor has a control pole connected to the second node, a first pole connected to the third node, and a second pole connected to the first node; the sixth control transistor has a control pole connected to a first node, a first pole connected to a first power supply terminal, and a second pole connected to a third node; the seventh control transistor has a control pole connected to the input terminal, a first pole connected to the second power supply terminal, and a second pole connected to the second node; the eighth control transistor has a control pole connected to the first output terminal, a first pole connected to the second clock terminal, and a second pole connected to a fourth node; the second node control subcircuit includes a first capacitor and a second capacitor, the first capacitor having a first electrode connected to a first node and a second electrode connected to a first output terminal, the second capacitor having a first electrode connected to a second node and a second electrode connected to a second power supply terminal; 2. The display substrate of claim 1, wherein the first output sub-circuit includes a first output transistor and a second output transistor, the first output transistor having a control pole connected to a first node, a first pole connected to a second clock terminal, and a second pole connected to a first output terminal, and the second output transistor having a control pole connected to a second node, a first pole connected to a second power supply terminal, and a second pole connected to the first output terminal.

5. 5. The display substrate of claim 4, wherein the first capacitor and the first output transistor are adjacent to each other in the first direction, the second capacitor and the second output transistor are adjacent to each other in the first direction, the first capacitor and the second capacitor are adjacent to each other in the second direction, the first output transistor and the second output transistor are adjacent to each other in the second direction, and the second direction intersects with the first direction.

6. 5. The display substrate of claim 4, wherein active layers of the first control transistor, the second control transistor, and the eighth control transistor have an integrated structure, active layers of the fourth control transistor and the fifth control transistor have an integrated structure, and active layers of the first output transistor and the second output transistor have an integrated structure.

7. 7. The display substrate of claim 6, wherein, in the first direction, the active layer of the sixth control transistor is located between the active layer of the fifth control transistor and the active layer of the second control transistor, and the active layer of the seventh control transistor is located between the active layer of the fourth control transistor and the active layer of the third control transistor.

8. the second output circuit includes a noise cancellation control subcircuit, a second output subcircuit, and a third output subcircuit; the noise reduction control sub-circuit is connected to a first output terminal, a first clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal and a first noise reduction control node, and is configured to, under the control of the third clock signal terminal, rectify the charge of the first power supply terminal to the first noise reduction control node to maintain the first noise reduction control node at a voltage that turns on the second output sub-circuit, and transmit the signal of the second power supply terminal to the first noise reduction control node to maintain the first noise reduction control node at a voltage that turns off the second output sub-circuit, under the control of the first output terminal; the second output sub-circuit is connected to the first noise reduction control node, the second output terminal, and the first power supply terminal, and is configured to transmit a signal from the first power supply terminal to the second output terminal under control of the first noise reduction control node; the third output sub-circuit is connected to the first node, the fourth clock terminal and the second output terminal, and is configured to transmit a signal of the fourth clock terminal to the second output terminal under the control of the first node; the second output sub-circuit and the third output sub-circuit are adjacent in the second direction; The display substrate of any one of claims 1 to 7, wherein in the first direction, the noise removal control sub-circuit is located between the first group of clock signal lines and the second output sub-circuit, and the second direction and the first direction intersect.

9. the noise reduction control subcircuit includes a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor; the first noise reduction control transistor has a control electrode connected to a first output terminal, a first electrode connected to a second power supply terminal, and a second electrode connected to a second noise reduction control node; the second noise reduction control transistor has a control electrode connected to a third clock terminal, a first electrode connected to a first power supply terminal, and a second electrode connected to a second noise reduction control node; the third noise reduction control transistor has a control electrode and a first electrode connected to a second noise reduction control node and a second electrode connected to a first noise reduction control node; the fourth noise reduction control transistor has a control electrode connected to the first output terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the first noise reduction control node; the third capacitor has a first electrode connected to the second noise removal control node and a second electrode connected to the first clock terminal; the fourth capacitor has a first electrode connected to the first noise removal control node and a second electrode connected to the first power supply terminal; the second output subcircuit includes a third output transistor; the third output transistor has a control electrode connected to the first noise removal control node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second output terminal; the third output sub-circuit includes a fourth output transistor; 9. The display substrate of claim 8, wherein the fourth output transistor has a control terminal connected to the first node, a first terminal connected to the fourth clock terminal, and a second terminal connected to the second output terminal.

10. the third output transistor and the fourth output transistor are adjacent to each other in the second direction, and the first noise removal control transistor and the second noise removal control transistor are adjacent to each other in the second direction; In the first direction, the third capacitor is located between the second noise removal control transistor and the third noise removal control transistor, and the fourth noise removal control transistor is located between the first noise removal control transistor and the fourth capacitor; 10. The display substrate of claim 9, wherein active layers of the first noise reduction control transistor and the second noise reduction control transistor are integrated, and active layers of the third output transistor and the fourth output transistor are integrated.

11. the first group of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line; the second group of clock signal lines includes a fourth clock signal line and a fifth clock signal line; the first clock signal from the first clock signal line, the second clock signal from the second clock signal line, and the third clock signal from the third clock signal line have the same duty ratio, the fourth clock signal from the fourth clock signal line and the fifth clock signal from the fifth clock signal line have the same duty ratio, and the duty ratio of the fourth clock signal is smaller than the duty ratio of the first clock signal; The display substrate of any one of claims 1 to 10, wherein the second clock signal is delayed from the first clock signal by a set time length, and the third clock signal is delayed from the second clock signal by a set time length, so that the first clock signal, the second clock signal, and the third clock signal are not simultaneously at a first voltage, the fourth clock signal and the fifth clock signal are not simultaneously at a second voltage, and the first voltage is different from the second voltage.

12. 12. The display substrate of claim 11, wherein in each stage of the shift register unit, a first output circuit is connected to the first clock signal line, the second clock signal line, and the third clock signal line, and a second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

13. the first group of clock signal lines includes a first subgroup clock signal line and a second subgroup clock signal line, and the second group of clock signal lines includes a third subgroup clock signal line and a fourth subgroup clock signal line; 13. The display substrate of claim 12, wherein the first subgroup clock signal lines and the second subgroup clock signal lines are spaced apart in the first direction, and the third subgroup clock signal lines and the fourth subgroup clock signal lines are spaced apart in the first direction.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

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