Indication device

Abstract

To provide a stretchable display device.SOLUTION: A display device includes: a stretchable lower substrate including a display area and a non-display area; a plurality of pixels provided on the display area of the lower substrate; a power supply provided on the non-display area of the lower substrate; a plurality of lower connection lines provided on the lower substrate and connected to the plurality of pixels, respectively; a stretchable upper substrate separated from the lower substrate; a plurality of conductive patterns provided between the upper substrate and the lower substrate and connected to the pixels, respectively; and a plurality of upper connection lines provided between the upper substrate and the lower substrate and connected to the conductive patterns, respectively. The power supply is electrically connected to the plurality of pixels through at least one of the upper connection lines and at least one of the upper connection lines, to stably supply a voltage to the plurality of pixels.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] The present specification relates to a stretchable display device. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, display devices that are manufactured by forming a display unit, wiring, etc. on a flexible substrate such as a flexible material such as plastic, and that can be stretched and contracted in a specific direction and can be changed into a variety of shapes, have been attracting attention as next-generation display devices. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved in this specification is to provide a stretchable display device including vertical light emitting devices (Vertical LEDs).

[0006] Another problem to be solved in this specification is to provide a display device capable of reducing or minimizing the drop in driving voltage.

[0007] Another object of the present invention is to provide a display device capable of reducing the number of connection wires on a lower substrate.

[0008] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A display device according to one embodiment of the present specification includes a lower substrate having a display area and a non-display area and is extendable, a plurality of pixels arranged on the display area of ​​the lower substrate, a power supply arranged on the non-display area of ​​the lower substrate, a plurality of lower connection wirings arranged on the lower substrate and connected to each of the plurality of pixels, an upper substrate spaced apart from the lower substrate and extendable, a plurality of conductive patterns arranged between the upper substrate and the lower substrate and connected to each of the plurality of pixels, and a plurality of upper connection wirings arranged between the upper substrate and the lower substrate and connected to the plurality of conductive patterns, wherein the power supply is electrically connected to the plurality of pixels via at least one of the plurality of upper connection wirings and at least one of the plurality of upper connection wirings, and can stably supply voltage to each of the plurality of pixels.

[0010] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0011] In the display device of the present specification, a stable low potential voltage can be supplied to the light-emitting element, the light-emitting efficiency and stability of the light-emitting element can be ensured, and low-power driving can be achieved.

[0012] By reducing the number of connection wires on the lower substrate of the display device of the present invention, the display device may have an improved elongation ratio.

[0013] The display device of the present disclosure can reduce or minimize the resistance of the conductive pattern that transmits the gate voltage, thereby preventing delay in the gate voltage.

[0014] Advantageously, as the number of pixels in the display device of this specification increases, the resolution can also be improved.

[0015] There is an advantage that the production yield of the light-emitting element of the display device of this specification can be improved.

[0016] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0017] [Figure 1a] 1 is a plan view showing a display device according to an embodiment of the present specification; [Figure 1b] 1 is a plan view showing a display device according to an embodiment of the present specification; [Figure 2] 1 is an enlarged plan view of a lower substrate disposed in a display area of ​​a display device according to an embodiment of the present specification; [Figure 3] 2 is an enlarged plan view of an upper substrate disposed in a display area of ​​a display device according to an embodiment of the present specification; [Figure 4] FIG. 4 is a cross-sectional view taken along the line IV-IV′ shown in FIGS. 2 and 3. [Figure 5] 1 is an enlarged plan view of a lower substrate disposed in a non-display area of ​​a display device according to an embodiment of the present disclosure; [Figure 6] 1 is an enlarged plan view of an upper substrate disposed in a non-display area of ​​a display device according to an embodiment of the present disclosure; [Figure 7] FIG. 7 is a cross-sectional view taken along the line VII-VII′ shown in FIGS. 5 and 6. [Figure 8] 10 is an enlarged plan view of a lower substrate disposed in a non-display area of ​​a display device according to another embodiment of the present disclosure; [Figure 9] 10 is an enlarged plan view of an upper substrate disposed in a non-display area of ​​a display device according to another embodiment of the present disclosure; [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX′ shown in FIGS. 8 and 9. DETAILED DESCRIPTION OF THE INVENTION

[0018] The advantages and features of the present specification, and methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms. These embodiments are provided solely so that this disclosure will be complete and will fully convey the scope of the invention to those skilled in the art to which the present specification pertains. The present specification is defined only by the scope of the claims.

[0019] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0020] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0021] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used. When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0022] Furthermore, when referring to "connected" or "connected," unless "immediately" or "directly" is used, it can also include being "connected" or "connected" through one or more other components located between the two components.

[0023] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0024] Like reference numbers refer to like elements throughout the specification.

[0025] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0026] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0027] Various embodiments of the present specification will now be described in detail with reference to the accompanying drawings.

[0028] A display device according to an embodiment of the present specification is a display device that can display an image even when warped or stretched, and may also be referred to as a stretchable display device, a flexible display device, or a display device that can be stretched. The display device has not only high flexibility compared to conventional general display devices but also stretchability. Thus, a user can warp or stretch the display device, and the shape of the display device can be freely changed by the user's operation. For example, when a user pulls the end of the display device, the display device can stretch in the direction of the user's pulling. Alternatively, when a user places the display device on an uneven surface, the display device can be arranged to warp along the shape of the outer surface of the wall. Furthermore, when the force applied by the user is removed, the display device can return to its original shape.

[0029] <Stretchable substrate and pattern layer> 1a and 1b are plan views showing a display device according to an embodiment of the present specification.

[0030] FIG. 2 is an enlarged plan view of a lower substrate disposed in a display area of ​​a display device according to an embodiment of the present specification.

[0031] FIG. 3 is an enlarged plan view of an upper substrate disposed in a display area of ​​a display device according to an embodiment of the present specification.

[0032] FIG. 4 is a cross-sectional view taken along the line IV-IV' shown in FIGS.

[0033] For convenience of explanation, Figures 1a and 1b show components other than the upper substrate 112. Figure 2 shows the lower substrate 111 and components disposed on the lower substrate 111 for region A shown in Figures 1a and 1b. Figure 3 shows the upper substrate 112 and components disposed on the upper substrate 112 for region A shown in Figures 1a and 1b.

[0034] 1a and 1b, a display device 100 according to an embodiment of the present disclosure may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gate driver GD, a data driver DD, and a power supply PS. Further referring to FIG. 4, in an embodiment, the display device 100 may further include a filler layer 190 and an upper substrate 112.

[0035] The lower substrate 111 is a substrate for supporting and protecting various components of the display device 100. The upper substrate 112 is a substrate for covering and protecting various components of the display device 100. That is, the lower substrate 111 is a substrate for supporting the pattern layer 120 on which the pixels PX, gate drivers GD, and power supplies PS are formed. The upper substrate 112 is a substrate for covering the pixels PX, gate drivers GD, and power supplies PS.

[0036] The lower substrate 111 and the upper substrate 112 may each be made of a flexible insulating material that can bend and stretch. For example, the lower substrate 111 and the upper substrate 112 may each include an elastomer such as silicone rubber (e.g., polydimethylsiloxane (PDMS)), polyurethane (PU), or polytetrafluoroethylene (PTFE). This allows the lower substrate 111 and the upper substrate 112 to have flexible properties. According to an embodiment, the lower substrate 111 and the upper substrate 112 may be made of the same material, but the material is not limited thereto and may be variously modified.

[0037] The lower substrate 111 and the upper substrate 112 may each be a ductile substrate capable of reversibly expanding and contracting. Accordingly, the lower substrate 111 may also be referred to as a lower stretchable substrate, lower elastic substrate, lower stretchable substrate, lower ductile substrate, lower flexible substrate, first stretchable substrate, first elastic substrate, first stretchable substrate, first ductile substrate, or first flexible substrate, and the upper substrate 112 may also be referred to as an upper stretchable substrate, upper elastic substrate, upper stretchable substrate, upper ductile substrate, upper flexible substrate, second stretchable substrate, second elastic substrate, second stretchable substrate, second ductile substrate, or second flexible substrate. The modulus of elasticity of each of the lower substrate 111 and the upper substrate 112 may range from several MPa to several hundred MPa. The ductile breaking rate of each of the lower substrate 111 and the upper substrate 112 may be 100% or more. Here, the ductile fracture rate refers to the elongation rate at which the object being stretched breaks or cracks. The thickness of the lower substrate 111 may be 10 μm to 1 mm, but is not limited thereto.

[0038] The lower substrate 111 may include a display area (active area) AA and a non-active area (non-active area) NA surrounding the display area AA. However, the display area AA and the non-active area NA are not limited to the lower substrate 111, but may refer to the entire display device 100.

[0039] The display area AA may be an area where an image is displayed on the display device 100. A plurality of pixels PX may be arranged on the display area AA. Each pixel PX may include a display element and various driving elements for driving the display element. The various driving elements may include, but are not limited to, at least one thin film transistor (TFT) and a capacitor. Each of the plurality of pixels PX may be connected to various wirings. For example, each of the plurality of pixels PX may be connected to various wirings such as a gate wiring, a data wiring, a high potential voltage wiring, a low potential voltage wiring, a reference voltage wiring, and an initialization voltage wiring.

[0040] The non-display area NA may be an area where no image is displayed. The non-display area NA may be disposed adjacent to the display area AA. For example, the non-display area NA may be an area surrounding the display area AA. However, the non-display area NA is not limited thereto, and may correspond to an area of ​​the lower substrate 111 excluding the display area AA, and may be deformed and separated into various shapes. Components for driving the pixels PX disposed in the display area AA may be disposed on the non-display area NA. A gate driver GD and a power supply PS may be disposed on the non-display area NA. In addition, a plurality of pads connected to the gate driver GD and the data driver DD may be disposed on the non-display area NA, and each pad may be connected to each of the pixels PX in the display area AA.

[0041] A pattern layer 120 may be disposed between the lower substrate 111 and the upper substrate 112. Specifically, as shown in Fig. 4, the pattern layer 120 may include lower pattern layers 121a and 122a and upper pattern layers 121b and 122b. The lower pattern layers 121a and 122a are pattern layers disposed on the lower substrate 111 and in contact with the lower substrate 111. The upper pattern layers 121b and 122b are pattern layers disposed on the upper substrate 112 and in contact with the upper substrate 112.

[0042] 1a and 1b, the pattern layer 120 may include a plurality of plate patterns 121 (including plates 121a and 121b) arranged in the form of islands spaced apart from each other, and a plurality of wiring patterns 122 (122a and 122b) connecting the plurality of plate patterns.

[0043] 2, the lower pattern layers 121a and 122a may include a plurality of lower plate patterns 121a arranged in an island shape spaced apart from each other and a plurality of lower wiring patterns 122a connecting the plurality of lower plate patterns 121a. And, as shown in FIG. 3, the upper pattern layers 121b and 122b may include a plurality of upper plate patterns 121b arranged in an island shape spaced apart from each other and a plurality of upper wiring patterns 122b connecting the plurality of upper plate patterns 121b.

[0044] 1a, 1b, 2, and 4, a plurality of pixels PX may be formed on the plurality of lower plate patterns 121a arranged in the display area AA, and a gate driver GD and a power supply PS may be formed on the plurality of lower plate patterns 121a arranged in the non-display area NA.

[0045] In other words, a plurality of pixels PX may be formed below the plurality of upper plate patterns 121b arranged in the display area AA, and a gate driver GD and a power supply PS may be formed below the upper pattern layers 121b and 122b arranged in the non-display area NA.

[0046] The upper plate patterns 121b and the lower plate patterns 121a may be individually separated from one another. Thus, the upper plate patterns 121b may also be referred to as upper island patterns or upper individual patterns. The lower plate patterns 121a may also be referred to as bottom island patterns or bottom individual patterns.

[0047] In one embodiment, a gate driver GD may be mounted on the plurality of lower plate patterns 121a arranged in the non-display area NA. Various circuit components constituting the gate driver GD, such as various transistors, capacitors, wiring, etc., may be disposed on the plurality of lower plate patterns 121a arranged in the non-display area NA. However, this is merely an example, and the embodiments of the present specification are not limited thereto. The gate driver GD may be mounted on the plurality of lower plate patterns 121a arranged in the non-display area NA using a COF (Chip on Film) method.

[0048] In one embodiment, a power supply PS may be mounted on the plurality of lower plate patterns 121a arranged in the non-display area NA, and power blocks arranged in different layers may be arranged on the plurality of lower plate patterns 121a arranged in the non-display area NA.

[0049] 1a and 1b, the size of the plurality of bottom plate patterns 121a arranged in the non-display area NA may be larger than the size of the plurality of bottom plate patterns 121a arranged in the display area AA. More specifically, since the area occupied by various circuit components constituting one stage of the gate driver GD is relatively larger than the area occupied by the pixel PX, the size of the plurality of bottom plate patterns 121a arranged in the non-display area NA may be larger than the size of the plurality of bottom plate patterns 121a arranged in the display area AA.

[0050] 1a, the plurality of bottom plate patterns 121a disposed in the plurality of non-display areas NA are shown to be disposed on both sides of the display area AA in the second direction Y, but this is merely an example and the embodiments of the present specification are not limited thereto. For example, as shown in FIG. 1b, the plurality of bottom plate patterns 121a disposed in the non-display area NA may be disposed on one side of the display area AA in the first direction X as well as on both sides of the display area AA in the second direction Y. Also, in FIGS. 1a, 1b, and 2, the plurality of bottom plate patterns 121a are shown to have a rectangular shape, but this is merely an example and the embodiments of the present specification are not limited thereto, and the plurality of bottom plate patterns 121a may have various shapes.

[0051] Meanwhile, the plurality of lower wiring patterns 122a are patterns that connect adjacent lower plate patterns 121a and may be referred to as lower connection patterns. That is, the plurality of lower wiring patterns 122a may be arranged between the plurality of lower plate patterns 121a.

[0052] The upper wiring patterns 122b are patterns that connect the adjacent upper plate patterns 121b and may be referred to as upper connection patterns. That is, the upper wiring patterns 122b may be arranged between the upper plate patterns 121b.

[0053] 1a and 1b, in one embodiment, each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a may have a curved shape. For example, each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a may have a sinusoidal wave shape. However, this is merely an example, and the shapes of each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a are not limited thereto. For example, each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a may have a zigzag shape. As another example, each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a may have various shapes, such as a plurality of diamond-shaped substrates connected at their vertices. As such, the number and shape of each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a shown in FIGS. 1a and 1b are merely exemplary, and the number and shape of each of the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a may be variously changed according to design.

[0054] In one embodiment, each of the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a may be a rigid pattern. For example, each of the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a may be more rigid than the lower substrate 111 and the upper substrate 112. Therefore, the modulus of elasticity of each of the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a may be higher than the modulus of elasticity of the lower substrate 111 and the upper substrate 112. The modulus of elasticity is a parameter indicating the ratio of deformation to stress applied to a substrate, and a relatively high modulus of elasticity may result in a relatively high hardness. The elastic modulus of each of the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b and the plurality of lower wiring patterns 122a may be more than 1000 times higher than the elastic modulus of the lower substrate 111 and the upper substrate 112, but this is merely an example and the embodiments of this specification are not limited thereto.

[0055] In one embodiment, the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a may each include a plastic material having lower flexibility than the lower substrate 111 and the upper substrate 112. For example, the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a may each include at least one material selected from the group consisting of polyimide (PI), polyacrylate, and polyacetate. According to an embodiment, the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a may each be made of the same material, but are not limited thereto and may each be made of different materials. When the plurality of upper plate patterns 121b, the plurality of lower plate patterns 121a, the plurality of upper wiring patterns 122b, and the plurality of lower wiring patterns 122a are made of the same material, the plurality of upper plate patterns 121b and the plurality of upper wiring patterns 122b may be formed integrally, and the plurality of lower plate patterns 121a and the plurality of lower wiring patterns 122a may be formed integrally.

[0056] In some embodiments, the lower substrate 111 may include a plurality of first lower patterns and a plurality of second lower patterns. The plurality of first lower patterns may be regions of the lower substrate 111 that overlap with the plurality of upper plate patterns 121b and the plurality of lower plate patterns 121a, and the second lower pattern may be a region that does not overlap with the plurality of upper plate patterns 121b and the plurality of lower plate patterns 121a.

[0057] The upper substrate 112 may also include a plurality of first upper patterns and a plurality of second upper patterns. The plurality of first upper patterns may be regions of the upper substrate 112 that overlap with the plurality of upper plate patterns 121b and the plurality of lower plate patterns 121a, and the second upper pattern may be a region that does not overlap with the plurality of upper plate patterns 121b and the plurality of lower plate patterns 121a.

[0058] In this case, the elastic modulus of the first lower patterns and the first upper patterns may be greater than the elastic modulus of the second lower pattern and the second upper pattern. For example, the first lower patterns and the first upper patterns may be made of the same material as the upper plate patterns 121b and the lower plate patterns 121a, and the second lower pattern and the second upper pattern may be made of a material having a lower elastic modulus than the upper plate patterns 121b and the lower plate patterns 121a.

[0059] For example, the first lower pattern and the first upper pattern may be made of polyimide (PI), polyacrylate, polyacetate, etc., and the second lower pattern and the second upper pattern may be made of elastomers such as silicone rubber (e.g., polydimethylsiloxane (PDMS)), polyurethane (PU), and PTFE (polytetrafluoroethylene).

[0060] <Non-display area driving element> The gate driver GD supplies gate voltages to the pixels PX arranged in the display area AA. The gate driver GD includes multiple stages formed on the lower plate patterns 121a arranged in the non-display area NA, and the stages included in the gate driver GD are electrically connected to each other through multiple gate connection lines. Therefore, the gate voltage output from any one stage can be transmitted to the other stages. Each stage can then sequentially supply gate voltages to the pixels PX connected to that stage.

[0061] The power supply PS is connected to the gate driver GD and can supply a gate driving voltage and a gate clock voltage to the gate driver GD. The power supply PS is connected to the pixels PX and can supply a pixel driving voltage to each of the pixels PX. The power supply PS can also be formed on the lower plate patterns 121a arranged in the non-display area NA. That is, the power supply PS can be formed adjacent to the gate driver GD on the lower plate patterns 121a arranged in the non-display area NA. Each of the power supplies PS formed on the lower plate patterns 121a arranged in the non-display area NA can be electrically connected to the gate driver GD and each of the pixels PX. That is, the power supplies PS formed on the lower plate patterns 121a arranged in the non-display area NA can be connected to the gate driver GD and each of the pixels PX via gate power supply connecting wiring and pixel power supply connecting wiring. Each of the power supplies PS can supply a gate driving voltage, a gate clock voltage, and a pixel driving voltage.

[0062] The printed circuit board PCB can transmit signals and voltages for driving the display elements from a controller to the display elements. Therefore, the printed circuit board PCB may also be referred to as a driver board. A controller such as an IC chip, a circuit unit, etc. may be attached to the printed circuit board PCB. A memory, a processor, etc. may also be attached to the printed circuit board PCB. The printed circuit board PCB included in the display device 100 may include a stretched region and a non-stretched region to ensure stretchability. The IC chip, the circuit unit, the memory, the processor, etc. may also be attached to the non-stretched region, and wiring electrically connected to the IC chip, the circuit unit, the memory, and the processor may be arranged in the stretched region.

[0063] The data driver DD can supply data voltages to a plurality of pixels PX arranged in the display area AA. The data driver DD can be configured in the form of an IC chip and can also be called a data integrated circuit (D-IC). The data driver DD can be mounted in a non-extending area of ​​a printed circuit board PCB. That is, the data driver DD can be mounted on the printed circuit board PCB in the form of a COB (Chip On Board). Although FIGS. 1a and 1b show the data driver DD mounted in a COF (Chip on Film) manner, the present invention is not limited thereto, and the data driver DD can also be mounted in other manners such as COB (Chip on Board), COG (Chip on Glass), and TCP (Tape Carrier Package).

[0064] 1A and 1B, one data driver DD is disposed corresponding to one row of the lower plate patterns 121a disposed in the display area AA, but this is not limiting. For example, one data driver DD may be disposed corresponding to multiple rows of the lower plate patterns 121a.

[0065] Hereinafter, reference will be made to both FIGS. 4 and 5 for a more detailed description of the display area AA of the display device 100 according to an embodiment of the present specification.

[0066] <Planar and cross-sectional structure of the display area> 2 and 4, a pixel PX including a plurality of sub-pixels SPX may be disposed on a lower plate pattern 121a disposed on a lower substrate 111. Each of the plurality of sub-pixels SPX may include a light-emitting element 170 as a display element, and a driving transistor 160 and a switching transistor 150 for driving the light-emitting element 170. However, the display element in the sub-pixel SPX is not limited to an LED and may be changed to an organic light-emitting diode (OLED). The plurality of sub-pixels SPX may include, but are not limited to, red sub-pixels, green sub-pixels, and blue sub-pixels, and the colors of the plurality of sub-pixels SPX may be variously changed as needed.

[0067] The subpixels SPX may be connected to the lower connecting wirings 181a, 182a. For example, the subpixels SPX may be electrically connected to the first lower connecting wiring 181a extending in the first direction X, and the subpixels SPX may be electrically connected to the second lower connecting wiring 182a extending in the second direction Y.

[0068] 3 and 4, first conductive patterns CPA may be disposed on the upper plate pattern 121b disposed on the upper substrate 112 in the display area AA. The first conductive patterns CPA may be connected to the upper connection wirings 181b. The upper connection wirings 181b may extend in the first direction X and be electrically connected to the first conductive patterns CPA.

[0069] 3, a plurality of light emitting elements 170 corresponding to the plurality of sub-pixels SPX may be disposed on the first conductive pattern CPA based on the upper substrate 112. The upper substrate 112 on which the plurality of light emitting elements 170 are disposed may be bonded to the lower substrate 111. Then, the light emitting elements 170 may be bonded to each of the plurality of sub-pixels SPX.

[0070] The cross-sectional structure of the display area AA will be described in more detail below with reference to FIG.

[0071] 4, a plurality of inorganic insulating layers may be disposed on the plurality of lower plate patterns 121a disposed in the display area AA. For example, the plurality of inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, the embodiments of the present specification are not limited thereto, and various inorganic insulating layers may be further disposed on the plurality of lower plate patterns 121a, or at least one of the inorganic insulating layers, the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145, may be omitted.

[0072] More specifically, a buffer layer 141 may be disposed on the plurality of lower plate patterns 121a disposed in the display area AA. The buffer layer 141 may be formed on the plurality of lower plate patterns 121a to protect various components of the display device 100 from the penetration of moisture (H2O), oxygen (O2), etc. from the outside of the lower substrate 111 and the plurality of lower plate patterns 121a. The buffer layer 141 may be made of an insulating material. For example, the buffer layer 141 may be made of a single layer or multiple layers made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). However, the buffer layer 141 may be omitted depending on the structure and characteristics of the display device 100.

[0073] Here, the buffer layer 141 may be formed only in the region where the lower substrate 111 overlaps with the plurality of lower plate patterns 121a. As described above, the buffer layer 141 may be made of an inorganic material and therefore may be easily damaged, such as cracked, during the process of stretching the display device 100. Therefore, the buffer layer 141 may not be formed in the region between the plurality of lower plate patterns 121a, but may be patterned into the shape of the plurality of lower plate patterns 121a and formed only on the plurality of lower plate patterns 121a. Therefore, in the display device 100 according to an embodiment of the present specification, the buffer layer 141 is formed only in the region where the lower substrate 111 overlaps with the plurality of lower plate patterns 121a, which are rigid patterns, thereby reducing damage to various components of the display device 100 even when the display device 100 is deformed, such as warped or stretched.

[0074] On the buffer layer 141, a switching transistor 150 including a gate electrode 151, an active layer 152, a source electrode 153, and a drain electrode 154, and a driving transistor 160 including a gate electrode 161, an active layer 162, a source electrode, and a drain electrode 164 may be formed.

[0075] First, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be disposed on the buffer layer 141. For example, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may each be formed of an oxide semiconductor. Alternatively, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, or the like.

[0076] A gate insulating layer 142 may be disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 may electrically insulate the gate electrode 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150, and may electrically insulate the gate electrode 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. The gate insulating layer 142 may include an insulating material. For example, the gate insulating layer 142 may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0077] A gate electrode 151 of the switching transistor 150 and a gate electrode 161 of the driving transistor 160 may be disposed on the gate insulating layer 142. The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may be disposed to be spaced apart from each other on the gate insulating layer 142. Furthermore, the gate electrode 151 of the switching transistor 150 may overlap with the active layer 152 of the switching transistor 150, and the gate electrode 161 of the driving transistor 160 may overlap with the active layer 162 of the driving transistor 160.

[0078] The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may each be made of various metal materials, such as, but not limited to, any one or an alloy of two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a multilayer thereof.

[0079] A first interlayer insulating layer 143 may be disposed on the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160. The first interlayer insulating layer 143 may insulate the gate electrode 161 of the driving transistor 160 from the intermediate metal layer IM. The first interlayer insulating layer 143 may be made of an inorganic material, similar to the buffer layer 141. For example, the first interlayer insulating layer 143 may be made of a single layer of inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0080] An intermediate metal layer IM may be disposed on the first interlayer insulating layer 143. The intermediate metal layer IM may overlap the gate electrode 161 of the driving transistor 160. As a result, a capacitor (e.g., a storage capacitor) may be formed in an overlapping region of the intermediate metal layer IM and the gate electrode 161 of the driving transistor 160. Specifically, the storage capacitor may be formed by the gate electrode 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM. However, the arrangement region of the intermediate metal layer IM is not limited thereto, and the intermediate metal layer IM may overlap with other electrodes to form various storage capacitors.

[0081] The intermediate metal layer IM may be made of any one of various metal materials, such as, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of these, or a multilayer thereof.

[0082] A second interlayer insulating layer 144 may be disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 may insulate the gate electrode 151 of the switching transistor 150 from the source electrode 153 and drain electrode 154 of the switching transistor 150. The second interlayer insulating layer 144 may also insulate the intermediate metal layer IM from the source electrode and drain electrode 164 of the driving transistor 160. The second interlayer insulating layer 144 may be made of an inorganic material, similar to the buffer layer 141. For example, the first interlayer insulating layer 143 may be made of a single layer of inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0083] A source electrode 153 and a drain electrode 154 of the switching transistor 150 may be disposed on the second interlayer insulating layer 144. A source electrode and a drain electrode 164 of the driving transistor 160 may be disposed on the second interlayer insulating layer 144. The source electrode 153 and the drain electrode 154 of the switching transistor 150 may be disposed spaced apart from each other on the same layer. Although the source electrode of the driving transistor 160 is omitted in FIG. 4 , the source electrode of the driving transistor 160 may also be disposed spaced apart from each other on the same layer as the drain electrode 164. In the switching transistor 150, the source electrode 153 and the drain electrode 154 may be electrically connected to the active layer 152 in a manner that they contact the active layer 152. In the driving transistor 160, the source electrode and the drain electrode 164 may be electrically connected to the active layer 162 in a manner that they contact the active layer 162. In addition, the drain electrode 154 of the switching transistor 150 may be electrically connected to the gate electrode 161 of the driving transistor 160 through a contact hole.

[0084] The source electrode 153 and the drain electrodes 154, 164 may include, but are not limited to, any one or more alloys of various metal materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or multiple layers thereof.

[0085] Although the driving transistor 160 has been described herein as having a coplanar structure, various transistors such as a staggered structure may also be used. Also, the transistor may be formed in a bottom gate structure as well as a top gate structure.

[0086] A gate pad and a data pad DP may be disposed on the second interlayer insulating layer 144 .

[0087] Specifically, the gate pad may be a pad for transmitting a gate voltage to the sub-pixels SPX. The gate pad may be connected to the first lower connection wiring 181a through a contact hole. The gate voltage supplied from the first lower connection wiring 181a may be transmitted from the gate pad to the gate electrode 151 of the switching transistor 150 through a wiring formed on the lower plate pattern 121a.

[0088] The data pad DP may be a pad for transmitting a data voltage to the plurality of sub-pixels SPX. The data pad DP may be connected to the second lower connection wiring 182a through a contact hole. The data voltage supplied from the second lower connection wiring 182a may be transmitted from the data pad DP to the source electrode 153 of the switching transistor 150 through a wiring formed on the lower plate pattern 121a.

[0089] The voltage pad VP may be a pad for transmitting a high potential voltage to the plurality of sub-pixels SPX. The voltage pad VP may be connected to the first lower connection wiring 181a through a contact hole. In addition, the high potential voltage supplied from the first lower connection wiring 181a may be transmitted from the voltage pad VP to the driving transistor 160 through a wiring formed on the lower plate pattern 121a. The above-mentioned high potential voltage may be referred to as a second driving voltage, and the below-mentioned low potential voltage may be referred to as a first driving voltage.

[0090] The gate pad, the data pad DP, and the voltage pad VP may be made of the same material as the source electrode 153 and the drain electrodes 154 and 164, but are not limited thereto.

[0091] A passivation layer 145 may be formed on the switching transistor 150 and the driving transistor 160. That is, the passivation layer 145 may be disposed to cover the switching transistor 150 and the driving transistor 160 to protect them from the penetration of moisture, oxygen, etc. The passivation layer 145 may be made of an inorganic material and may be formed as a single layer or multiple layers, but is not limited thereto.

[0092] In addition, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may be patterned and formed only in regions overlapping the plurality of lower plate patterns 121a. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may be made of an inorganic material, similar to the buffer layer 141, and may be easily damaged, such as cracked, during the process of extending the display device 100. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may not be formed in regions between the plurality of lower plate patterns 121a, but may be patterned into the shape of the plurality of lower plate patterns 121a and formed only on the plurality of lower plate patterns 121a.

[0093] A planarization layer 146 may be formed on the passivation layer 145. The planarization layer 146 may planarize the tops of the switching transistor 150 and the driving transistor 160. The planarization layer 146 may be configured as a single layer or multiple layers and may be made of an organic material. Therefore, the planarization layer 146 may also be referred to as an organic insulating layer. For example, the planarization layer 146 may be made of an acrylic organic material, but is not limited thereto.

[0094] 4, the planarization layer 146 may be disposed on the plurality of lower plate patterns 121a to cover the upper and side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. The planarization layer 146 may also surround the plurality of lower plate patterns 121a as well as the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. More specifically, the planarization layer 146 may be disposed to cover the upper and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the side surfaces of the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the upper surfaces of the plurality of lower plate patterns 121a. As a result, the planarization layer 146 can compensate for steps on the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Furthermore, the planarization layer 146 can increase the adhesive strength with the lower connection wirings 181a and 182a disposed on the side surfaces of the planarization layer 146.

[0095] 4, the inclination angle of the side surface of the planarization layer 146 may be smaller than the inclination angles of the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 may have a gentler inclination than the inclinations of the side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the side surfaces of the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, and the side surfaces of the buffer layer 141. As a result, the lower connection wirings 181a and 182a arranged to contact the side surfaces of the planarization layer 146 are arranged with a gentle inclination, and stress generated in the lower connection wirings 181a and 182a when the display device 100 is stretched may be reduced. Furthermore, since the side surfaces of the planarization layer 146 have a relatively gentle slope, the phenomenon in which the lower connection wirings 181a and 182a are cracked or peeled off at the side surfaces of the planarization layer 146 can be reduced.

[0096] 2 to 4, the lower connection wirings 181a and 182a refer to wirings that electrically connect pads on the lower plate patterns 121a. The lower connection wirings 181a and 182a may be disposed on the lower wiring patterns 122a. Furthermore, in the regions between the lower plate patterns 121a, the lower wiring patterns 122a are not disposed in the regions where the lower connection wirings 181a and 182a are not disposed.

[0097] The lower connection wirings 181a, 182a may include a first lower connection wiring 181a and a second lower connection wiring 182a. The first lower connection wiring 181a and the second lower connection wiring 182a may be disposed between the plurality of lower plate patterns 121a. Specifically, the first lower connection wiring 181a may refer to a wiring of the lower connection wirings 181a, 182a that extends in the first direction X between the plurality of lower plate patterns 121a, and the second lower connection wiring 182a may refer to a wiring of the lower connection wirings 181a, 182a that extends in the second direction Y between the plurality of lower plate patterns 121a.

[0098] The lower connection wirings 181a and 182a may be made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or a laminated structure of metal materials such as copper / molybdenum-titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), etc., but are not limited thereto.

[0099] In a display panel of a general display device, various wirings such as a plurality of gate wirings, a plurality of data wirings, etc. are arranged to extend linearly between a plurality of sub-pixels, and a plurality of sub-pixels are connected to one signal wiring. Therefore, in a display panel of a general display device, various wirings such as a plurality of gate wirings, a plurality of data wirings, a plurality of high potential voltage wirings, a plurality of reference voltage wirings, etc. can extend from one side to the other side of a display panel of an organic light emitting display device without being cut on a substrate.

[0100] In contrast, in the display device 100 according to an embodiment of the present disclosure, various wirings such as linear gate wirings, data wirings, high potential voltage wirings, reference voltage wirings, initialization voltage wirings, etc., which are likely to be used in the display panel of a general display device, may be disposed only on the plurality of lower plate patterns 121 a. That is, in the display device 100 according to an embodiment of the present disclosure, linear wirings may be disposed only on the plurality of lower plate patterns 121 a.

[0101] In the display device 100 according to an embodiment of the present disclosure, pads on two adjacent lower plate patterns 121a may be connected by lower connection wirings 181a and 182a. Therefore, the lower connection wirings 181a and 182a may electrically connect gate pads, data pads DP, or voltage pads VP on the two adjacent lower plate patterns 121a. Therefore, the display device 100 according to an embodiment of the present disclosure may include a plurality of lower connection wirings 181a and 182a to electrically connect various wirings, such as gate wirings, data wirings, high potential voltage wirings, and reference voltage wirings, between the plurality of lower plate patterns 121a. For example, gate wirings may be disposed on the plurality of lower plate patterns 121a adjacent to each other in the first direction X, and gate pads may be disposed at both ends of the gate wirings. In this case, the plurality of gate pads on the plurality of lower plate patterns 121a adjacent to each other in the first direction X may be connected to each other by the first lower connection wirings 181a functioning as gate wirings. As a result, the gate lines arranged on the plurality of lower plate patterns 121a and the first lower connection lines 181a arranged on the lower wiring patterns 122a can function as a single gate line. The gate lines may be called scan signal lines. In addition, among all the various lines that may be included in the display device 100, lines extending in the first direction X, such as light-emitting signal lines and high-potential voltage lines, may also be electrically connected by the first lower connection lines 181a as described above.

[0102] 2 and 4, the first lower connection wiring 181a may connect the voltage pads VP on two adjacent lower plate patterns 121a among the voltage pads VP on the plurality of lower plate patterns 121a arranged adjacent to each other in the first direction X. The first lower connection wiring 181a may function as a scan signal wiring, which is a gate wiring, and an emission signal wiring, but is not limited thereto. The voltage pads VP on the plurality of lower plate patterns 121a arranged in the first direction X may be connected by the first lower connection wiring 181a functioning as a high-potential voltage wiring, and one high-potential voltage may be transmitted.

[0103] The second lower connection wiring 182a may connect data pads DP on two adjacent lower plate patterns 121a among the data pads DP on the lower plate patterns 121a arranged adjacent to each other in the second direction Y. The second lower connection wiring 182a may function as, but is not limited to, a data wiring or a reference voltage wiring. Internal wirings on the lower plate patterns 121a arranged in the second direction Y may be connected by the second lower connection wirings 182a functioning as data wirings, and one data voltage may be transmitted.

[0104] 4, the first lower connection wiring 181a may be disposed to contact the upper and side surfaces of the planarization layer 146 disposed on the lower plate pattern 121a. The first lower connection wiring 181a may be formed to extend onto the upper surface of the lower wiring pattern 122a. The second lower connection wiring 182a may be disposed to contact the upper and side surfaces of the planarization layer 146 disposed on the lower plate pattern 121a. The second lower connection wiring 182a may be formed to extend onto the upper surface of the lower wiring pattern 122a.

[0105] However, since there is no need to place a rigid pattern in the area where the first lower connection wiring 181a and the second lower connection wiring 182a are not placed, the lower wiring pattern 122a, which is a rigid pattern, is not placed below the first lower connection wiring 181a and the second lower connection wiring 182a.

[0106] 4, banks 147 may be formed on the connection pads CNT, the lower connection lines 181a and 182a, and the planarization layer 146. The banks 147 may separate adjacent subpixels SPX. The banks 147 may be disposed to cover at least a portion of the connection pads CNT, the lower connection lines 181a and 182a, and the planarization layer 146. The banks 147 may be made of an insulating material. The banks 147 may also include a black material. The black material in the banks 147 serves to block lines visible through the display area AA. For example, the banks 147 may be made of a carbon-based compound, such as carbon black. However, the bank 147 is not limited thereto and may be made of a transparent insulating material. Although the height of the banks 147 is shown to be shorter than the height of the light emitting elements 170 in FIGS. 1a and 1b, the height of the banks 147 is not limited thereto and may be the same as the height of the light emitting elements 170.

[0107] 4, a light emitting element 170 may be disposed on the connection pad CNT and the first lower connection wiring 181a. The light emitting element 170 includes a first electrode 171, a first semiconductor layer 172, a light emitting layer 173, a second semiconductor layer 174, and a second electrode 175. The first semiconductor layer 172, the light emitting layer 173, the second semiconductor layer 174, and the second electrode 175 may be sequentially disposed on the first electrode 171. Therefore, the light emitting element 170 is a vertical light emitting element in which the second electrode 175 is disposed on the first electrode 171.

[0108] In one embodiment, the bank layer has an opening 197, and the entire LED may be disposed within the bank opening 197. That is, the bank layer 147 is completely formed on the planarization layer 146. The opening 197 is then formed, such as by patterning and etching, resulting in sidewalls of the bank layer 147 on either side of the opening 197. The anode, photoelectron and hole transport layers, light-emitting layer, and corner are all formed within the opening 197 after fabrication and spaced apart from the bank layer. The LED is vertically elongated, with no part of the bank layer overlapping it or overlapping it. All layers, i.e., the anode, light-generating layer, and cathode, that make up the LED are spaced apart from the walls of the bank layer 147. In a preferred embodiment, the bank layer 147 is completely formed, then the opening 197 is formed, followed by the anode, the light-emitting layer, and the cathode. The upper substrate 112 is then overlaid on the LED, as shown in FIG. 4.

[0109] A first semiconductor layer 172 is disposed on the first adhesive layer AD1, and a second semiconductor layer 174 is disposed on the first semiconductor layer 172. The first semiconductor layer 172 and the second semiconductor layer 174 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 172 and the second semiconductor layer 174 may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with p-type or n-type impurities. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0110] The light emitting layer 173 is disposed between the first semiconductor layer 172 and the second semiconductor layer 174. The light emitting layer 173 can emit light by receiving holes and electrons from the first semiconductor layer 172 and the second semiconductor layer 174. The light emitting layer 173 may have a single layer or a multi-quantum well (MQW) structure and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0111] The first electrode 171 is disposed under the first semiconductor layer 172. The first electrode 171 may be disposed on the lower surface of the first semiconductor layer 172. The first electrode 171 is an electrode for electrically connecting the driving transistor 160 and the first semiconductor layer 172. The first electrode 171 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0112] A second electrode 175 is disposed on the second semiconductor layer 174. The second electrode 175 may be disposed on an upper surface of the second semiconductor layer 174. The second electrode 175 is an electrode for electrically connecting the first conductive pattern CPA and the second semiconductor layer 174. The second electrode 175 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0113] The first adhesive layer AD1 is disposed between the connection pad CNT and the first electrode 171, and the light emitting element 170 can be adhered onto the connection pad CNT. The second adhesive layer AD2 is disposed between the first conductive pattern CPA and the second electrode 175, and the light emitting element 170 can be adhered below the first conductive pattern CPA.

[0114] Each of the first adhesive layer AD1 and the second adhesive layer AD2 may be a conductive adhesive layer in which conductive balls are dispersed on an insulating base member, and when heat or pressure is applied to the adhesive layer AD, the conductive balls may be electrically connected at the portions to which heat or pressure is applied, thereby providing conductive properties.

[0115] The connection pad CNT is electrically connected to the drain electrode 164 of the driving transistor 160 and can receive a driving voltage from the driving transistor 160 to drive the light-emitting element 170. The electrical connection from the drain electrode 164 to the connection pad CNT exists in various layers, including one or more of layers 141 to 146. Note that this connection is on a different plane and is not shown in FIG. 4 . While FIG. 4 shows the connection pad CNT and the drain electrode 164 of the driving transistor 160 as being indirectly connected rather than in direct contact, they are electrically connected using other conductors, not visible in this figure, that extend through contacts present on layers 145 and 146 and may extend through other layers if necessary. The embodiments of this specification are not limited thereto; the connection pad CNT and the drain electrode 164 of the driving transistor 160 may also be in direct contact. A low potential voltage for driving the light-emitting element 170 can be applied to the first lower connection wiring 181a.

[0116] 3, when the upper substrate 112 is used as a reference, a plurality of upper plate patterns 121b and a plurality of upper wiring patterns 122b connecting the plurality of upper plate patterns 121b may be arranged on the upper substrate 112. Referring to Fig. 4, when the lower substrate 111 is used as a reference, a plurality of upper plate patterns 121b and a plurality of upper wiring patterns 122b connecting the plurality of upper plate patterns 121b may be arranged below the upper substrate 112. That is, the plurality of upper plate patterns 121b and the plurality of upper wiring patterns 122b may be arranged in contact with the upper substrate 112.

[0117] In particular, the upper wiring patterns 122b arranged in the display area AA connect the upper plate patterns 121b arranged adjacently in the first direction X. Therefore, the upper wiring patterns 122b may extend in the first direction X. However, this is not limited thereto, and the extension direction of the upper wiring patterns 122b may extend in the first direction X or in both the first direction X and the second direction Y.

[0118] When the upper substrate 112 is used as a reference, the first conductive pattern CPA may be disposed on the upper plate pattern 121b disposed in the display area AA, and the upper connection wiring 181b may be disposed on the upper wiring pattern 122b disposed in the display area AA. When the lower substrate 111 is used as a reference, the first conductive pattern CPA may be disposed below the upper plate pattern 121b disposed in the display area AA, and the upper connection wiring 181b may be disposed below the upper wiring pattern 122b disposed in the display area AA.

[0119] The first conductive patterns CPA disposed in the display area AA may have the same shape as the upper plate patterns 121b. For example, since the upper plate patterns 121b have an island shape spaced apart from each other, the first conductive patterns CPA may also have an island shape spaced apart from each other. However, the shape of the first conductive patterns CPA is not limited thereto and may be modified into various shapes that overlap the shape of the upper plate patterns 121b.

[0120] The upper connection wiring 181b may also have the same shape as the upper wiring pattern 122b. For example, the upper connection wiring 181b may also have a sine wave shape. However, this is merely an example, and the shape of the plurality of upper connection wirings 181b is not limited thereto. For example, the plurality of upper wiring patterns 122b and the plurality of upper connection wirings 181b may have a zigzag shape. As another example, the plurality of upper connection wirings 181b may have various shapes, such as a plurality of diamond-shaped substrates connected at their vertices and extending.

[0121] The plurality of first conductive patterns CPA and the plurality of upper connection wirings 181b may be formed of, but are not limited to, a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or a laminated structure of metal materials such as copper / molybdenum-titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), etc. The plurality of first conductive patterns CPA and the plurality of upper connection wirings 181b may be integrally formed.

[0122] A low potential voltage for driving the light emitting element 170 may be applied to the first conductive patterns CPA and the upper connection wirings 181b. That is, the first conductive patterns CPA and the upper connection wirings 181b may form a conductive surface to which one low potential voltage is applied.

[0123] Therefore, when the display device 100 is turned on, a driving voltage is applied to the first electrode 171 through the connection pad CNT, and a low potential voltage is applied to the second electrode 175 through the first conductive pattern CPA. Thus, different voltage levels are respectively transmitted to the first electrode 171 and the second electrode 175, causing the light emitting element 170 to emit light.

[0124] In addition, a filler layer 190 may be disposed on the front surface of the lower substrate 111 to fill a gap between the components disposed on the upper substrate 112 and the lower substrate 111. The filler layer 190 may be made of a curable adhesive. Specifically, a material constituting the filler layer 190 may be coated on the front surface of the lower substrate 111 and then cured to form the filler layer 190 between the components disposed on the upper substrate 112 and the lower substrate 111. For example, the filler layer 190 may be an optically clear adhesive (OCA), and may be made of an acrylic adhesive, a silicone adhesive, a urethane adhesive, or the like.

[0125] As described above, the display device according to an embodiment of the present disclosure can supply a low potential voltage to the light emitting element through the upper connection wiring 181b and the first conductive pattern CPA attached to the upper substrate 112.

[0126] In addition, since the total area of ​​the upper connection wiring 181b and the first conductive pattern CPA is larger than the total area of ​​the lower connection wirings 181a and 182a, the total resistance of the upper connection wiring 181b and the first conductive pattern CPA may be relatively low.

[0127] Therefore, the voltage drop of the low potential voltage supplied through the upper connection wiring 181b and the first conductive pattern CPA can be reduced, and therefore the light emitting element 170 can be supplied with a stable low potential voltage.

[0128] As a result, the display device according to an embodiment of the present disclosure can ensure the luminous efficiency and stability of the light emitting element 170, thereby improving image quality.

[0129] <Planar and cross-sectional structure of non-display area> FIG. 5 is an enlarged plan view of a lower substrate disposed in a non-display area of ​​a display device according to an embodiment of the present specification.

[0130] FIG. 6 is an enlarged plan view of an upper substrate disposed in a non-display area of ​​a display device according to an embodiment of the present specification.

[0131] FIG. 7 is a cross-sectional view taken along the line VII-VII′ shown in FIGS.

[0132] 5 shows the lower substrate 111 and components disposed on the lower substrate 111 for region B shown in Figures 1a and 1b, and Fig. 6 shows the upper substrate 112 and components disposed on the upper substrate 112 for region B shown in Figures 1a and 1b.

[0133] As shown in FIG. 5, a gate driver GD and a power supply PS may be disposed on the lower plate pattern 121a disposed in the non-display area NA.

[0134] Still referring to FIG. 7, the power supply PS may include a first power block PB1, a second power block PB2, and a third power block PB3.

[0135] The first power block PB1 and the second power block PB2 may be arranged on the same layer, and the third power block PB3 may be arranged on a different layer from the first power block PB1 and the second power block PB2.

[0136] For example, the third power block PB3 may be disposed on the lower plate pattern 121a disposed in the non-display area NA, and an insulating layer INS may be disposed on the third power block PB3.

[0137] A first power block PB1 and a second power block PB2 may be disposed on the insulating layer INS. The gate driver GD may also be disposed on the insulating layer INS, but the arrangement of the gate driver GD is merely exemplary, and the gate driver GD may be disposed on the lower plate pattern 121a disposed in the non-display area NA.

[0138] 5, the first power block PB1 may be disposed inside the first power block PB1. The first power block PB1 and the second power block PB2 may be connected to each other through the second lower connection wiring 182a disposed in the non-display area NA. Thus, adjacent first power blocks PB1 may be electrically connected through the second lower connection wiring 182a. Thus, adjacent first power blocks PB1 may be electrically connected through the second lower connection wiring 182a.

[0139] 7, the second power block PB2 and the third power block PB3, which are arranged on different layers, may be connected through contact holes. The third power block PB3 may be connected to the first lower connection wiring 181a arranged in the non-display area NA. Thus, the second power block PB2 and the third power block PB3 may be electrically connected to the voltage pad VP through the first lower connection wiring 181a.

[0140] Meanwhile, as shown in FIG. 6, a second conductive pattern CPB may be disposed on the upper plate pattern 121b disposed in the non-display area NA based on the upper substrate 112.

[0141] In other words, as shown in FIG. 7, the second conductive pattern CPB may be disposed below the upper plate pattern 121b disposed in the non-display area NA based on the lower substrate 111.

[0142] The second conductive pattern CPB may be connected to the first upper connecting wiring 181b arranged in the non-display area NA. The second conductive pattern CPB may be connected to the first power block PB1 through a contact hole. As described above, the first upper connecting wiring 181b is connected to the first conductive pattern CPA, so that the first power block PB1 and the second conductive pattern CPB may be electrically connected to the first conductive pattern CPA through the first upper connecting wiring 181b.

[0143] Meanwhile, each of the first power block PB1, the second power block PB2, the third power block PB3, the first conductive pattern CPA, and the second conductive pattern CPB may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0144] Since the first conductive pattern CPA and the second conductive pattern CPB may be made of metal, they may reflect external light from the display device, thereby reducing visibility.

[0145] Therefore, a low-reflection material may be added to each of the upper pattern layers, the upper plate pattern 121b and the upper wiring pattern 122b, to improve visibility. For example, the low-reflection material may include, but is not limited to, polarized iodine particles or dyes.

[0146] In summary, in a display device according to an embodiment of the present specification, the second power block PB2 and the third power block PB3 may be electrically connected to the voltage pad VP through the first lower connection wiring 181a, and the first power block PB1 and the second conductive pattern CPB may be electrically connected to the first conductive pattern CPA through the first upper connection wiring 181b.

[0147] A low potential voltage can be applied to the first power block PB1, and a high potential voltage can be applied to the second power block PB2.

[0148] Therefore, a low potential voltage is applied to the first power block PB1 and the second conductive pattern CPB. The low potential voltage is also applied to the first conductive pattern CPA through the first upper connection wiring 181b, and the low potential voltage can be applied to the second electrode through the first conductive pattern CPA.

[0149] A high potential voltage is applied to the second power block PB2 and the third power block PB3, and a high potential voltage can be applied to the voltage pad VP through the first lower connection wiring 181a.

[0150] Therefore, a high potential voltage is applied to the drive transistor through the voltage pad VP, and a drive voltage can be supplied to each light-emitting element.

[0151] As described above, in one embodiment of this specification, a display device can be manufactured by forming a plurality of conductive patterns and vertical light-emitting elements on the upper substrate 112, and forming transistors and power supplies PS for driving the light-emitting elements on the lower substrate 111 and bonding them together.

[0152] That is, the light emitting device of the display device according to the embodiment of the present disclosure is not bonded in a separate process, but the display device can be manufactured in a single bonding process.

[0153] This has the advantage of improving the manufacturing yield of light-emitting elements for display devices.

[0154] Furthermore, the display device according to an embodiment of the present disclosure can supply a low potential voltage through the plurality of conductive patterns and the upper connection wiring.

[0155] Therefore, since there is no need to supply a low potential voltage through the lower connection wiring, the number of lower connection wirings can be relatively reduced.

[0156] As a result, the number of connection wires on the lower substrate 111 is reduced, and the extension ratio of the display device can be improved.

[0157] Furthermore, by applying a vertical light emitting device in one embodiment of the present disclosure, the number of pixels that can be arranged per unit area can be increased compared to when a horizontal light emitting device is applied.

[0158] Therefore, in the display device according to an embodiment of the present specification, there is an advantage that the resolution can be improved as the number of pixels increases.

[0159] <Another embodiment of the present invention> Hereinafter, a display device according to another embodiment of the present specification will be described. The display device according to one embodiment of the present specification and the display device according to the other embodiment of the present specification differ in terms of the power supply and its connection relationship, and this will be mainly described. Furthermore, the same components in the display device according to one embodiment of the present specification and the display device according to the other embodiment of the present specification will be designated by the same reference numerals, and redundant description will be omitted.

[0160] FIG. 8 is an enlarged plan view of a lower substrate disposed in a non-display area of ​​a display device according to another embodiment of the present specification.

[0161] FIG. 9 is an enlarged plan view of an upper substrate disposed in a non-display area of ​​a display device according to another embodiment of the present specification.

[0162] FIG. 10 is a cross-sectional view taken along the line XX' shown in FIGS.

[0163] Figure 8 shows the lower substrate 111 and components disposed on the lower substrate 111 for region B shown in Figures 1a and 1b, and Figure 9 shows the upper substrate 112 and components disposed on the upper substrate 112 for region B shown in Figures 1a and 1b.

[0164] As shown in FIG. 8, a gate driver GD and a power supply PS may be disposed on the lower plate pattern 121a disposed in the non-display area NA.

[0165] Still referring to FIG. 10, the power supply PS may include a first power block PB1', a second power block PB2', and a third power block PB3'.

[0166] The first power block PB1' and the second power block PB2' may be arranged on the same layer, and the third power block PB3' may be arranged on a different layer from the first power block PB1' and the second power block PB2'.

[0167] For example, a third power block PB3' may be disposed on the lower plate pattern 121a disposed in the non-display area NA, and an insulating layer INS may be disposed on the third power block PB3'.

[0168] A first power block PB1' and a second power block PB2' may be disposed on the insulating layer INS. The gate driver GD may also be disposed on the insulating layer INS, but the arrangement of the gate driver GD is merely exemplary, and the gate driver GD may be disposed on the lower plate pattern 121a disposed in the non-display area NA.

[0169] 8, the first power block PB1' may be disposed inside the first power block PB1'. The first power block PB1' and the second power block PB2' may be connected to each other through the second lower connection wiring 182a disposed in the non-display area NA. Thus, adjacent first power blocks PB1' may be electrically connected to each other through the second lower connection wiring 182a. Thus, adjacent first power blocks PB1' may be electrically connected to each other through the second lower connection wiring 182a.

[0170] 10, the first power block PB1′ and the third power block PB3′ disposed on different layers may be connected through contact holes. The third power block PB3′ may be connected to the first lower connection wiring 181a disposed in the non-display area NA. Thus, the first power block PB1′ and the third power block PB3′ may be electrically connected to the voltage pad VP through the first lower connection wiring 181a.

[0171] Meanwhile, as shown in FIG. 9, a second conductive pattern CPB' may be disposed on the upper plate pattern 121b disposed in the non-display area NA based on the upper substrate 112.

[0172] In other words, as shown in FIG. 10, the second conductive pattern CPB' may be disposed below the upper plate pattern 121b disposed in the non-display area NA based on the lower substrate 111.

[0173] The second conductive pattern CPB' may be connected to the first upper connecting wiring 181b arranged in the non-display area NA. The second conductive pattern CPB' may be connected to the second power block PB2' through a contact hole. As described above, since the first upper connecting wiring 181b is connected to the first conductive pattern CPA, the second power block PB2' and the second conductive pattern CPB' may be electrically connected to the first conductive pattern CPA through the first upper connecting wiring 181b.

[0174] Meanwhile, each of the first power block PB1', the second power block PB2', the third power block PB3', the first conductive pattern CPA, and the second conductive pattern CPB' may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0175] Since the first conductive pattern CPA and the second conductive pattern CPB' may be made of metal, they may reflect external light from the display device, thereby reducing visibility.

[0176] Therefore, a low-reflection material may be added to each of the upper pattern layers, the upper plate pattern 121b and the upper wiring pattern 122b, to improve visibility. For example, the low-reflection material may include, but is not limited to, polarized iodine particles or dyes.

[0177] In summary, in a display device according to another embodiment of this specification, the first power block PB1′ and the third power block PB3′ may be electrically connected to the voltage pad VP through the first lower connection wiring 181a, and the second power block PB2′ and the second conductive pattern CPB may be electrically connected to the first conductive pattern CPA through the first upper connection wiring 181b.

[0178] A high potential voltage can be applied to the first power block PB1', and a low potential voltage can be applied to the second power block PB2'.

[0179] Therefore, a low potential voltage is applied to the second power block PB2' and the second conductive pattern CPB'. Then, a low potential voltage is also applied to the first conductive pattern CPA through the first upper connection wiring 181b, and the low potential voltage can be applied to the second electrode through the first conductive pattern CPA.

[0180] A high potential voltage is applied to the first power block PB1' and the third power block PB3'. A high potential voltage can be applied to the voltage pad VP through the first lower connection wiring 181a.

[0181] Therefore, a high potential voltage is applied to the drive transistor through the voltage pad VP, and a drive voltage can be supplied to each light-emitting element.

[0182] As described above, in another embodiment of this specification, a display device can be fabricated by forming a plurality of conductive patterns and vertical light-emitting elements on the upper substrate 112, and forming transistors and power supplies PS for driving the light-emitting elements on the lower substrate 111 and bonding them together.

[0183] That is, the light emitting device bonding of the display device 200 according to another embodiment of the present specification is not performed in a separate process, but the display device can be manufactured in a single bonding process.

[0184] This has the advantage that the manufacturing yield of the light emitting elements of the display device 200 can be improved.

[0185] In addition, a display device according to another embodiment of the present specification can supply a low potential voltage through a plurality of conductive patterns and upper connection wirings.

[0186] Therefore, since there is no need to supply a low potential voltage through the lower connection wiring, the number of lower connection wirings can be relatively reduced.

[0187] As a result, the number of connection wires on the lower substrate 111 is reduced, and the extension ratio of the display device can be improved.

[0188] Furthermore, by applying a vertical light emitting device in other embodiments of the present specification, the number of pixels that can be arranged per unit area can be increased compared to when a horizontal light emitting device is applied.

[0189] Therefore, in the display device according to the other embodiments of this specification, there is an advantage that the resolution can be improved as the number of pixels increases.

[0190] Display devices according to various embodiments of the present disclosure can be described as follows.

[0191] An embodiment of the present invention can also be described as follows.

[0192] According to an aspect of the present invention, in order to solve the above-mentioned problems, a display device according to one embodiment of the present specification includes a lower substrate divided into a display area and a non-display area and capable of being stretched, a plurality of pixels arranged on the display area of ​​the lower substrate, a power supply arranged on the non-display area of ​​the lower substrate, a plurality of lower connection wirings arranged on the lower substrate and connected to each of the plurality of pixels, an upper substrate facing the lower substrate and capable of being stretched, a plurality of conductive patterns arranged below the upper substrate and connected to each of the plurality of pixels, and a plurality of upper connection wirings arranged below the upper substrate and connected to the plurality of conductive patterns, and the power supply is electrically connected to the plurality of pixels through some of the plurality of upper connection wirings and some of the plurality of upper connection wirings, thereby being able to stably supply voltage to the plurality of pixels. According to another feature of the present disclosure, the power supply may include a plurality of first power blocks and a plurality of second power blocks arranged on the same layer, and a plurality of third power blocks arranged on a different layer from the plurality of first power blocks and the plurality of second power blocks.

[0193] According to still another feature herein, the plurality of first power blocks may be disposed inside the plurality of second power blocks.

[0194] According to another feature of the present specification, the plurality of third power blocks may be connected to the plurality of lower connecting wires.

[0195] According to another feature of the present specification, each of the plurality of conductive patterns may include a plurality of first conductive patterns arranged in the display area and a plurality of second conductive patterns arranged in the non-display area.

[0196] According to another feature of the present specification, each of the plurality of first power blocks may be connected to each of the plurality of second conductive patterns through a contact hole, and each of the plurality of second power blocks may be connected to each of the plurality of third power blocks through a contact hole.

[0197] According to another feature of the present specification, a low potential voltage may be applied to the plurality of first power blocks and the plurality of second conductive patterns, and a high potential voltage may be applied to the plurality of second power blocks and the plurality of third power blocks.

[0198] According to another feature of the present specification, each of the plurality of first power blocks may be connected to each of the plurality of third power blocks through a contact hole, and each of the plurality of second power blocks may be connected to each of the plurality of second conductive patterns through a contact hole.

[0199] According to another feature of the present specification, a low potential voltage may be applied to the plurality of second power blocks and the plurality of second conductive patterns, and a high potential voltage may be applied to the plurality of first power blocks and the plurality of third power blocks.

[0200] According to another feature of the present disclosure, each of the plurality of pixels may include a vertical light emitting element electrically connected to one of the plurality of first conductive patterns.

[0201] According to yet another feature of the present disclosure, only a low potential voltage may be applied to the plurality of conductive patterns.

[0202] According to another feature of the present specification, a plurality of lower plate patterns may be formed between the lower substrate and the plurality of pixels, and a plurality of lower wiring patterns may be formed between the lower substrate and the plurality of lower connection wirings, and the elastic modulus of each of the plurality of lower plate patterns and the plurality of lower wiring patterns may be higher than the elastic modulus of the lower substrate.

[0203] According to another feature of the present specification, a plurality of upper plate patterns are formed between the upper substrate and the plurality of conductive patterns, and a plurality of upper wiring patterns are formed between the upper substrate and the plurality of upper connection wirings, and the elastic modulus of each of the plurality of upper plate patterns and the plurality of upper wiring patterns may be higher than the elastic modulus of the upper substrate.

[0204] Although the embodiments of the present specification have been described in more detail, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to illustrate, not limit, the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood to be illustrative in all respects and not limiting. The scope of protection of the present specification should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present specification. [Explanation of symbols]

[0205] 100:Display device 111: Lower board 112: Upper board

Claims

1. a stretchable bottom substrate including a display area and a non-display area; a plurality of pixels disposed on the display area of ​​the lower substrate; a power supply disposed on the non-display area of ​​the lower substrate; a plurality of lower connection wirings disposed on the lower substrate and connected to the plurality of pixels, respectively; an upper substrate spaced apart from the lower substrate and extensible; a plurality of conductive patterns disposed between the upper substrate and the lower substrate and connected to the plurality of pixels, respectively; a plurality of upper connection wirings disposed between the upper substrate and the lower substrate and connected to the plurality of conductive patterns, respectively; The power supply is electrically connected to each of the plurality of pixels via at least one of the plurality of upper connection wirings and at least one of the plurality of lower connection wirings.

2. The power supply a plurality of first power blocks and a plurality of second power blocks arranged in the same layer; 2. The display device according to claim 1, further comprising a plurality of third power blocks arranged in a layer different from the plurality of first power blocks and the plurality of second power blocks.

3. The display device according to claim 2 , wherein the plurality of first power blocks are arranged inside the plurality of second power blocks.

4. The display device according to claim 2 , wherein the third power blocks are connected to the lower connection wirings.

5. Each of the plurality of conductive patterns is a plurality of first conductive patterns arranged in the display area; The display device according to claim 1 , further comprising: a plurality of second conductive patterns arranged in the non-display area.

6. Each of the plurality of first power blocks of the power supply is connected to each of the plurality of second conductive patterns through a contact hole; 6. The display device according to claim 5, wherein each of the second power blocks of the power supply is connected to each of the third power blocks of the power supply through a contact hole.

7. a low potential voltage is applied to the plurality of first power blocks and the plurality of second conductive patterns; The display device according to claim 6 , wherein a high potential voltage is applied to the plurality of second power blocks and the plurality of third power blocks.

8. Each of the plurality of first power blocks of the power supply is connected to each of the plurality of third power blocks of the power supply through a contact hole; The display device according to claim 5 , wherein each of the second power blocks of the power supply is connected to each of the second conductive patterns through a contact hole.

9. a low potential voltage is applied to the second power blocks and the second conductive patterns; The display device according to claim 8 , wherein a high potential voltage is applied to the plurality of first power blocks and the plurality of third power blocks.

10. The display device of claim 5 , wherein each of the plurality of pixels includes a vertical light emitting element electrically connected to one of the plurality of first conductive patterns.

11. The display device according to claim 1 , wherein only a low potential voltage is applied to the plurality of conductive patterns.

12. a plurality of lower plate patterns are formed between the lower substrate and the plurality of pixels; a plurality of lower wiring patterns are formed between the lower substrate and the plurality of lower connection wirings; The display device of claim 1 , wherein the elastic modulus of each of the lower plate patterns and the lower wiring patterns is higher than the elastic modulus of the lower substrate.

13. a plurality of upper plate patterns are formed between the upper substrate and the plurality of conductive patterns; a plurality of upper wiring patterns are formed between the upper substrate and the plurality of upper connection wirings; The display device of claim 1 , wherein the upper plate patterns and the upper wiring patterns each have a higher elastic modulus than the upper substrate.

14. a stretchable bottom substrate including a display area and a non-display area; a plurality of driving transistors disposed in the display region of the lower substrate; a plurality of switching transistors disposed in the display region of the lower substrate, each of which is connected to each of the plurality of driving transistors; a power supply disposed in the non-display area of ​​the lower substrate; a plurality of lower connection wirings disposed on the lower substrate and connected to the plurality of switching transistors, respectively; an upper substrate spaced apart from the lower substrate and extensible; a plurality of conductive patterns disposed adjacent to the upper substrate; a plurality of light emitting diodes (LEDs) electrically connected to the plurality of conductive patterns, respectively; a plurality of upper connection wirings disposed between the upper substrate and the plurality of LEDs, the upper connection wirings electrically connecting each of the plurality of LEDs to the plurality of conductive patterns, The power supply is electrically connected to each of the plurality of LEDs via the plurality of drive transistors based on a plurality of signals from the plurality of switching transistors.

15. The display device of claim 14 , wherein the plurality of conductive patterns are between the upper substrate and the lower substrate.

16. 15. The display device of claim 14, wherein one of the LEDs, one of the drive transistors, and a first of the plurality of switching transistors are electrically connected to each other to form one subpixel.

17. 15. The display device of claim 14, further comprising: a plurality of lower plate patterns disposed on the lower substrate; and three sub-pixels on each of the plurality of lower plate patterns to form one pixel on the lower plate pattern.

18. The display device of claim 17 , further comprising: a plurality of inorganic insulating layers on the lower plate pattern; a bank layer on the plurality of inorganic insulating layers; and an opening in the bank layer.

19. The display device of claim 18 , wherein the LED is entirely disposed in the opening in the bank layer.

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