Indication device

Abstract

To detect a crack which is generated in a non-display area or an optical area.SOLUTION: A display device comprises: a substrate which includes a display area, an optical area disposed in the display area and including a through hole, and a non-display area enclosing the display area; a first detection line which is disposed in the non-display area and encloses an outer periphery of the display area; a second detection line which is disposed inside more than the first detection line and encloses an outer periphery of the display area and the through hole; and a plurality of metal patterns which is disposed along an outer periphery of the through hole below the second detection line. At least one of the plurality of metal patterns is electrically connected to the second detection line. Accordingly, when a crack is generated in the non-display area or the optical area, a location where the crack is generated may be identified.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display device, and more particularly to a display device capable of detecting cracks occurring in an optical area where a camera or sensor is arranged. [Background technology]

[0002] With the advent of the information age, the field of display devices that visually display electrical information signals has been developing rapidly, and research is ongoing to develop various display devices with improved performance, such as thinner, lighter, and lower power consumption.

[0003] Representative display devices include liquid crystal displays (LCDs), field emission displays (FEDs), electro-wetting displays (EWDs), and organic Examples include organic light emitting displays (OLEDs).

[0004] Electroluminescent displays (ELDs), typified by organic light-emitting displays (OLEDs), are self-emitting displays that, unlike LCDs, do not require a separate light source and can be manufactured in a lightweight and thin form. Furthermore, ELDs are advantageous in terms of power consumption due to their low voltage operation, and also have excellent color reproduction, response speed, viewing angle, and contrast ratio (CR), making them expected to be used in a variety of fields. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of detecting cracks occurring in the non-display area or the optical area.

[0006] Another problem to be solved in another embodiment of the present specification is to provide a display device that can identify the location of a crack when the crack occurs in the non-display area or the optical area.

[0007] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment of the present specification includes a substrate including a display area, an optical area disposed within the display area and including a through hole, and a non-display area surrounding the display area, a first detection wiring disposed in the non-display area and surrounding the outer periphery of the display area, a second detection wiring disposed inside the first detection wiring and surrounding the outer periphery of the display area and the through hole, and a plurality of metal patterns disposed along the outer periphery of the through hole below the second detection wiring, wherein at least one of the plurality of metal patterns is electrically connected to the second detection wiring.

[0009] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] A display device according to an embodiment of the present disclosure can detect cracks occurring in the non-display area or the optical area.

[0011] A display device according to an embodiment of the present specification can identify the location of a crack when the crack occurs in the non-display area or the optical area.

[0012] A display device according to one embodiment of the present specification can detect whether a crack occurs on the top of a sealing portion in an optical region including a through hole or whether a crack occurs in an insulating film disposed under a plurality of thin film transistors.

[0013] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view of a display device according to an embodiment of the present specification; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 3] FIG. 2 is an enlarged plan view of region A in FIG. [Figure 4] FIG. 4 is an enlarged plan view of region B in FIG. 3. [Figure 5] FIG. 5 is a cross-sectional view taken along the line VV′ in FIG. [Figure 6] 1 is a plan view of a display device according to an embodiment of the present specification; [Figure 7] FIG. 10 is a plan view of a display device according to another embodiment of the present specification. [Figure 8] FIG. 10 is a plan view of a display device according to still another embodiment of the present specification. DETAILED DESCRIPTION OF THE INVENTION

[0015] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the embodiments of the present invention to those skilled in the art.

[0016] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are merely illustrative and should not be construed as limiting the scope of the embodiments of this specification. The same reference symbols refer to the same elements throughout the specification. Furthermore, when describing an embodiment of this specification, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of the embodiment of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0017] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0018] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0019] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0020] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0021] Like reference numbers refer to like elements throughout the specification.

[0022] The area and thickness of each structure shown in the drawings are shown for convenience of explanation, and an embodiment of this specification is not necessarily limited to the area and thickness of the structure shown.

[0023] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0024] An embodiment of the present specification will be described below with reference to the drawings.

[0025] FIG. 1 is a plan view of a display device according to an embodiment of the present specification.

[0026] Referring to FIG. 1, a display device 100 according to an embodiment of the present specification may include a circuit unit in which a display panel DP and a detection pad PAD are arranged.

[0027] According to one embodiment of the present specification, the display panel DP may include a display area DA, an optical area OA disposed within the display area DA and including through-holes TH, and a non-display area NDA surrounding the display area DA.

[0028] The display area DA is an area where an image is displayed on the display panel DP.

[0029] A number of pixels P and circuits for driving the pixels P may be arranged in the display area DA. The pixels P are the smallest units constituting the display area DA, and a display element may be arranged in each of the pixels P. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode may be arranged in each of the pixels P, but this is not limited thereto. In addition, the circuit for driving the pixels P may include driving elements and wiring, etc. For example, the circuit may include, but is not limited to, a thin film transistor, a storage capacitor, a gate wiring, a data wiring, etc.

[0030] The optical area OA is located within the display area DA. The optical area OA may be an area where through-holes TH formed by punching the display panel DP are located. The optical area OA may be an area for arranging optical electronic devices such as a camera, flash, speaker, or optical sensor within the display area DA. The through-holes TH are located within the display area DA of the display panel DP, reducing the bezel area, which is the non-display area (NDA), and maximizing the display area DA. Products designed to maximize the display area DA may maximize a user's immersion in the screen and be more aesthetically pleasing.

[0031] 1, the number of through-holes TH may be two, but is not limited thereto and may be variously arranged. For example, one or two holes may be arranged within the display area DA, with a camera arranged in the first hole and a distance detection sensor or a face recognition sensor and a wide-angle camera arranged in the second hole.

[0032] The non-display area NDA is an area where no video is displayed.

[0033] The non-display area NDA may be bent so that it cannot be seen from the front or may be hidden by a case (not shown), and is also called a bezel area.

[0034] 1, the non-display area NDA is shown surrounding the rectangular display area DA, but the shapes and arrangements of the display area DA and the non-display area NDA are not limited to the example shown in Fig. 1. That is, the display area DA and the non-display area NDA may have shapes suitable for the design of an electronic device incorporating the display device 100. For example, exemplary shapes of the display area DA may be pentagonal, hexagonal, circular, elliptical, etc.

[0035] Various wirings and circuits for driving the organic light emitting elements in the display area DA may be arranged in the non-display area NDA, such as link wirings for transmitting signals to a number of sub-pixels and circuits in the display area DA, GIP (Gate-In-Panel) wirings, or driving ICs such as gate drivers and data drivers, but are not limited thereto.

[0036] Detection wiring 130 for detecting cracks occurring in the display panel DP may be arranged in the non-display area NDA. For example, the detection wiring 130 may include a first detection wiring 131 surrounding the periphery of the display area DA and a second detection wiring 132 arranged inside the first detection wiring 131 and surrounding the periphery of the display area DA and the through-hole TH. The first detection wiring 131 can detect cracks occurring in the periphery of the display panel DP, and the second detection wiring 132 can detect cracks occurring in the optical area OA.

[0037] One end and the other end of each of the first detection wiring 131 and the second detection wiring 132 may be connected to a detection pad PAD arranged in the non-display area NDA, and the detection pad PAD may receive a detection signal output via the detection wiring 130.

[0038] The detection pad PAD may be located on a printed circuit film PCB connected to the non-display area NDA of the display panel DP, but is not limited thereto, and may be directly mounted on the non-display area NDA of the display panel DP. The printed circuit film PCB may further include, but is not limited to, a data driver that generates data signals for driving the pixels P, a timing controller, etc. When the detection pad PAD is located on the printed circuit film PCB, the first detection wiring 131 and the second detection wiring 132 may extend to the printed circuit film PCB.

[0039] The detection pad PAD applies a detection signal to the first detection wire 131 and receives the first detection signal therethrough to check whether the first detection wire 131 is normal. The detection pad PAD applies a detection signal to the second detection wire 132 and receives the second detection signal therethrough to check whether the second detection wire 132 is normal. The detection pad PAD can detect cracks around the non-display area NDA and the optical area OA depending on whether the first detection wire 131 and the second detection wire 132 are normal.

[0040] For example, when the display panel DP undergoes a lighting test (auto probe) for final testing, a certain level of power can be applied to the detection pad PAD using either a separate device or a separate device, and the input and output values ​​can be compared. The degree of resistance can be determined from the difference between the input and output values, and based on this, it can be determined whether or not the detection wiring is broken. For example, if a crack occurs in the non-display area NDA of the display panel DP, some or all of the detection wiring 130 may be broken. For example, if part of the detection wiring 130 is broken, the resistance may gradually increase, and the output power may weaken. In this way, it can be determined whether or not a crack has occurred in the display panel DP based on resistance-related characteristics, but the method of determining whether or not a crack has occurred is not limited to this.

[0041] The display device 100 may further include various additional elements for generating various signals or driving the pixels P in the display area DA. The additional elements for driving the pixels P may include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, etc. The display device 100 may also include additional elements associated with functions other than driving the pixels P. For example, the display device 100 may further include additional elements providing a touch detection function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure detection function, a tactile feedback function, etc. The aforementioned additional elements may be located in the non-display area NDA and / or an external circuit connected to the connection interface.

[0042] In the following, reference will be made to FIG. 2 for a more detailed description of the cross-sectional structure of the display area DA of the display device 100.

[0043] FIG. 2 is a cross-sectional view showing the cross-sectional structure of one pixel arranged in a display region according to an embodiment of the present specification.

[0044] The display device 100 according to one embodiment of the present specification may include a substrate 110, a first buffer layer 111, a first thin film transistor TR1, a second thin film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a connecting electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 145, a bank 116a, a spacer 116b, an anode 121, a light-emitting layer 122, a cathode 123, an encapsulating portion 117, and a touch detection portion.

[0045] The substrate 110 serves to support and protect the components of the flexible display device disposed thereon.

[0046] The substrate 110 is configured to support various components included in the display device 100 and may be made of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. By configuring the substrate 110 with the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c in this manner, moisture penetration can be prevented. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the interlayer insulating film 110c may be a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

[0047] A light blocking layer 125 may be disposed on the substrate 110 .

[0048] A first buffer layer 111 may be disposed on the substrate 110, covering the light-shielding layer 125. Specifically, a multi-buffer layer 111a may be disposed on the substrate 110, covering the light-shielding layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0049] The multi-buffer layer 111a can delay the diffusion of moisture or oxygen that has penetrated into the substrate 110, and can include at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0050] The active buffer layer 111b can protect the first active layer A1 and block various types of defects from entering from the substrate 110. For example, the active buffer layer 111b can include at least one of a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0051] The first thin film transistor TR1 may be disposed on the first buffer layer 111. The first thin film transistor TR1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Here, according to the design of the pixel circuit, the first source electrode S1 may be the first drain electrode, and the first drain electrode D1 may be the first source electrode.

[0052] The first active layer A1 may be disposed on the first buffer layer 111 so as to overlap the light-shielding layer 125. The first active layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first active layer A1 may include low-temperature polysilicon (LTPS). For example, polysilicon materials have high mobility (100 cm 2 / Vs or more), low energy consumption, and excellent reliability, the thin film transistor (TR1) may be applied to a gate driver and / or a multiplexer (MUX) for a driving element that drives a thin film transistor for a display element, and may be applied to the first active layer A1 of the driving thin film transistor in the display device 100 according to an embodiment of the present disclosure, but is not limited thereto. For example, the thin film transistor (TR1) may also be applied to the second active layer A2 of the switching thin film transistor depending on the characteristics of the display device 100. The first active layer A1 may be formed by depositing an amorphous silicon (a-Si) material on the first buffer layer 111 and performing a dehydrogenation process and a crystallization process to form polysilicon, and then patterning the polysilicon. Here, the first active layer A1 may include a first channel region in which a channel is formed when the first thin film transistor TR1 is operated, and first source and drain regions on both sides of the first channel region. The first source region refers to a portion of the first active layer A1 connected to the first source electrode S1, and the first drain region refers to a portion of the first active layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region may be formed by ion doping (impurity doping) the first active layer A1. The first source region and the first drain region may be formed by ion doping a polysilicon material, and the first channel region may refer to the remaining portion of the polysilicon material that is not ion doped.

[0053] A first gate insulating layer 112a may be disposed on the first active layer A1. The first gate insulating layer 112a may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. Contact holes may be formed in the first gate insulating layer 112a to connect the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 to the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1, respectively.

[0054] A first gate electrode G1 of the first thin film transistor TR1 and a first capacitor electrode C1 of the storage capacitor Cst may be disposed on the first gate insulating layer 112a.

[0055] In this case, the first gate electrode G1 and the first capacitor electrode C1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode G1 may be formed on the first gate insulating layer 112a to overlap with the first channel region of the first active layer A1 of the first thin film transistor TR1.

[0056] The first capacitor electrode C1 may be omitted depending on the driving characteristics of the display device 100 and the structure and type of the thin film transistor. The first gate electrode G1 and the first capacitor electrode C1 may be formed by the same process. In addition, the first gate electrode G1 and the first capacitor electrode C1 may be formed of the same material and on the same layer.

[0057] A first interlayer insulating layer 113a may be disposed on the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the first interlayer insulating layer 113a to expose a first source region and a first drain region of the first active layer A1 of the first thin film transistor TR1.

[0058] A second capacitor electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second capacitor electrode C2 may be formed on the first interlayer insulating layer 113a to overlap the first capacitor electrode C1. The second capacitor electrode C2 may be formed of the same material as the first capacitor electrode C1. The second capacitor electrode C2 may be omitted depending on the driving characteristics of the display device 100 and the structure and type of the thin film transistor.

[0059] A second buffer layer 114 may be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. Contact holes may be formed in the second buffer layer 114 to expose the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1. In addition, a contact hole may be formed in the second buffer layer 114 to expose the second capacitor electrode C2 of the storage capacitor Cst.

[0060] The second buffer layer 114 may be formed as a multi-layer structure, but is not limited thereto.

[0061] A second active layer A2 of a second thin film transistor TR2 may be disposed on the second buffer layer 114. Here, the second thin film transistor TR2 may include the second active layer A2, a second gate insulating layer 112b, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The first thin film transistor TR1 and the second thin film transistor TR2 may be disposed on different layers. The second thin film transistor TR2 may be disposed on the first thin film transistor TR1, but is not limited thereto. Here, depending on the design of the pixel circuit, the second source electrode S2 may serve as the drain electrode, and the second drain electrode D2 may serve as the source electrode.

[0062] The second active layer A2 may include a second channel region where a channel is formed when the second thin film transistor TR2 is driven, and a second source region and a second drain region on both sides of the second channel region. The second source region may refer to a portion of the second active layer A2 connected to the second source electrode S2, and the second drain region may refer to a portion of the second active layer A2 connected to the second drain electrode D2.

[0063] The second active layer A2 may be made of an oxide semiconductor. Oxide semiconductor materials have a larger bandgap than silicon materials, preventing electrons from crossing the bandgap in the off state, resulting in a low off-current. Therefore, a thin film transistor including an active layer made of an oxide semiconductor may be suitable for, but not limited to, a switching thin film transistor, which maintains a short on-time and a long off-time. Depending on the characteristics of the display device 100, it may also be used as a driving thin film transistor. Furthermore, since the off-current is small, the storage capacitance can be reduced, making it suitable for high-resolution display devices. For example, the second active layer A2 may be made of a metal oxide, such as indium-gallium-zinc-oxide (IGZO). Here, the second active layer A2 of the second thin film transistor TR2 has been described assuming that it is made of IGZO among various metal oxides, but is not limited thereto and may be made of other metal oxides such as IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), or IGO (indium-gallium-oxide).

[0064] The second active layer A2 may be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0065] The second gate insulating layer 112b may be disposed over the entire substrate 110, including the second active layer A2. For example, the second gate insulating layer 112b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof.

[0066] A second gate electrode G2 may be disposed on the second gate insulating layer 112b.

[0067] The second gate electrode G2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0068] For example, a metal material may be formed on the second gate insulating layer 112b, a photoresist pattern may be formed on the metal material, and the metal material may be wet-etched using the photoresist pattern as a mask to form the second gate electrode G2. A wet etchant for etching the metal material may be one that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or alloys thereof, but does not etch insulating materials.

[0069] A second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate electrode G2. Contact holes may be formed in the second interlayer insulating layer 113b to expose the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2. For example, contact holes may be formed in the second interlayer insulating layer 113b to expose the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1. Contact holes may be formed in the second interlayer insulating layer 113b to expose the second source region and the second drain region of the second active layer A2 of the second thin film transistor TR2.

[0070] The second interlayer insulating layer 113b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of these.

[0071] A connecting electrode CE, a first source electrode S1 and a first drain electrode D1 of the first thin film transistor TR1, and a second source electrode S2 and a second drain electrode D2 of the second thin film transistor TR2 may be disposed on the second interlayer insulating layer 113b.

[0072] The connecting electrode CE may be electrically connected to the second drain electrode D2 of the second thin film transistor TR2. The connecting electrode CE may also be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through contact holes formed in the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b. That is, the connecting electrode CE may serve to electrically connect the second capacitor electrode C2 of the storage capacitor Cst to the second drain electrode D2 of the second thin film transistor TR2.

[0073] Here, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 can be connected to the first active layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, and the second interlayer insulating layer 113b.

[0074] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be connected to the second active layer A2 through contact holes formed in the second interlayer insulating layer 113b.

[0075] The connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be formed of the same material using the same process.

[0076] For example, the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin film transistor TR2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. For example, the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin film transistor TR2 may be formed as a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited thereto.

[0077] The connecting electrode CE may be integrally formed with the second drain electrode D2 of the second thin film transistor TR2, but is not limited thereto.

[0078] A first planarization layer 115a may be disposed on the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0079] The first planarization layer 115a may be an organic layer for planarizing and protecting the tops of the first thin film transistor TR1 and the second thin film transistor TR2, and may be formed of, for example, an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0080] An auxiliary electrode 145 may be disposed on the first planarization layer 115a. The auxiliary electrode 145 may be connected to the second drain electrode D2 of the second thin film transistor TR2 through a contact hole in the first planarization layer 115a. The auxiliary electrode 145 may serve to electrically connect the second thin film transistor TR2 to the anode 121. The auxiliary electrode 145 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The auxiliary electrode 145 may be formed of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2.

[0081] A second planarization layer 115b may be disposed on the auxiliary electrode 145 and the first planarization layer 115a. Although not shown in the drawings, a third planarization layer may be disposed on the second planarization layer 115b. For example, the second planarization layer 115b and the third planarization layer may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0082] The light emitting element 120 may be disposed on the second planarization layer 115b.

[0083] The anode 121 may be disposed on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the auxiliary electrode 145 through a contact hole provided in the second planarization layer 115b or the third planarization layer. The anode 121 may be formed of a metallic material.

[0084] When the display device 100 is a top emission type in which light emitted from the light emitting element 120 is emitted above the substrate 110, the anode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be made of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0085] The bank 116a may be disposed to cover the anode 121. The bank 116a may be a pixel defining layer that exposes the light-emitting region of each subpixel. The bank 116a may be open in a portion corresponding to the light-emitting region of the subpixel. A portion of the anode 121 may be exposed in the open portion of the bank 116a (hereinafter referred to as the open region). The bank 116a may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), an organic insulating material such as a benzocyclobutene-based resin, an acrylic resin, or an imide-based resin, or an opaque material (e.g., a black material) to prevent optical interference between adjacent subpixels. In this case, the bank 116a may include a light-shielding material made of at least one of a color pigment, organic black, and carbon, but is not limited thereto. A spacer 116b may be further disposed on the bank 116a.

[0086] The light-emitting layer 122 can be disposed in the open areas of the bank 116a, whereby the light-emitting layer 122 can be disposed on the anode 121 exposed through the open areas of the bank 116a.

[0087] A cathode 123 may be disposed to cover the light-emitting layer 122 and the bank 116a.

[0088] The anode 121, the light-emitting layer 122, and the cathode 123 may form a light-emitting element 120. The light-emitting layer 122 may include multiple organic films.

[0089] An encapsulant 117 may be located on the light emitting element 120 described above.

[0090] The sealing portion 117 may have a single-layer structure or a multi-layer structure, for example, the sealing portion 117 may include a first sealing layer 117a, a second sealing layer 117b, and a third sealing layer 117c.

[0091] In this case, the first encapsulating layer 117a and the third encapsulating layer 117c may be made of an inorganic film, and the second encapsulating layer 117b may be made of an organic film. Among the first encapsulating layer 117a, the second encapsulating layer 117b, and the third encapsulating layer 117c, the second encapsulating layer 117b is the thickest and can serve as a planarizing layer.

[0092] The first encapsulating layer 117a may be disposed on the cathode 123 and may be disposed closest to the light emitting element 120. The first encapsulating layer 117a may be formed of an inorganic insulating material that can be deposited at low temperatures. For example, the first encapsulating layer 117a may be made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Because the first encapsulating layer 117a is deposited in a low-temperature atmosphere, it is possible to prevent damage to the light emitting layer 122, which includes organic materials that are vulnerable to high-temperature atmospheres, during the deposition process.

[0093] The second encapsulation layer 117b may be formed to have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may serve as a buffer to relieve stress between layers due to warping of the flexible display device and to enhance planarization performance.

[0094] For example, the second sealing layer 117b may be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbonate (SiOC), etc. For example, the second sealing layer 117b may be formed using an inkjet method, but is not limited thereto.

[0095] The third encapsulation layer 117c may be formed on the substrate on which the second encapsulation layer 117b is formed to cover the top and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. In this case, the third encapsulation layer 117c may minimize or block external moisture or oxygen from penetrating into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0096] A touch-sensitive layer may be disposed on the encapsulant 117 .

[0097] For example, the touch buffer layer 118a may be disposed on the third sealing layer 117c, and the touch electrode TE may be disposed on the touch buffer layer 118a.

[0098] The touch electrode TE may include a touch sensor electrode TS and a touch bridge electrode BM located in different layers. An inter-touch layer insulating layer 118b may be disposed between the touch sensor electrode TS and the touch bridge electrode BM.

[0099] The touch buffer layer 118a and the touch interlayer insulating layer 118b may be disposed to eliminate steps at the locations where the touch electrodes TE are disposed and to ensure good electrical insulation.

[0100] Meanwhile, although not shown, a polarizing layer may be disposed on the touch detection layer.

[0101] The polarizing layer suppresses reflection of external light on the display area DA of the substrate 110. When the display device 100 is used outdoors, external natural light enters and may be reflected by the reflective layer included in the anode 121 of the light emitting element 120 or by the electrode made of metal disposed under the light emitting element 120. Such reflected light may make it difficult to view images on the display device 100. The polarizing layer polarizes the external light in a specific direction and prevents the reflected light from being emitted outside the display device 100.

[0102] Although not shown, a cover glass may be attached to the polarizing layer by an adhesive layer. The adhesive layer may serve to bond the components of the display device 100 together, and may be formed using an optically transparent adhesive for displays, such as, but not limited to, a pressure-sensitive adhesive, an optically clear adhesive (OCR), or an optically clear resin (OCR).

[0103] The cover glass protects the components of the display device 100 from external impacts and can prevent damage such as scratches.

[0104] Fig. 3 is an enlarged plan view of region A, which corresponds to the optical region in Fig. 1. Fig. 4 is an enlarged plan view of region B in Fig. 3. Fig. 5 is a cross-sectional view taken along VV' of the optical region in Fig. 4.

[0105] Referring to FIG. 3 , the optical region OA has a through-hole TH in its center for disposing an optical electronic device, where a camera module or a sensor may be disposed. The optical region OA may include a circular or elliptical through-hole TH and an area where a nearby dam 150, a connection prevention portion 140, etc. are disposed. The through-hole TH may be removed by a laser during the panel completion process. The non-display region NDA may be located between the through-hole TH and the display region DA, and high-voltage power wiring PL, gate wiring SL, etc. may be disposed therein. Although the light emitting elements 120 and pixel circuits in the corresponding region are removed due to the disposition of the optical region OA, the light emitting elements 120 and pixel circuits disposed above, below, left, and right of the optical region OA must be electrically connected. To this end, the high-voltage power wiring PL and gate wiring SL may be disposed in the non-display region NDA near the optical region OA so as to bypass the through-hole TH and be connected above, below, left, and right.

[0106] 3, the connection prevention unit 140 may be composed of a first prevention unit 141 and a second prevention unit 142, and a dam 150 may be disposed between the first prevention unit 141 and the second prevention unit 142. Although one dam 150 is illustrated in one embodiment of the present specification, the present invention is not limited to this, and more dams may be disposed depending on the spatial arrangement. Referring to FIG. 3, the first prevention unit 141, the dam 150, the second detection wiring 132, the metal wiring 162, and the second prevention unit 142 may be sequentially disposed around the through hole TH.

[0107] Generally, the dam 150 may be intended to prevent the second sealing layer 117b, which is part of the sealing portion 117, from sliding down to the end of the outer periphery of the display panel DP, thereby maintaining the adhesive strength between the upper and lower substrates that constitute the display panel DP.

[0108] A dam 150 in the optical area OA may also be formed to prevent the second sealing layer 117b of the sealing part 117 for protecting the light emitting element 120 from penetrating or leaking into the optical area OA.

[0109] The first and second barriers 141 and 142 may be disposed to protect the light emitting elements 120 in the display area from moisture or oxygen that may enter through the through holes TH. The cathode 123 of the light emitting elements 120 may be deposited on the front surface of the display panel DP, but may also be uniformly deposited in the optical area OA. Moisture and oxygen may be transferred to the light emitting elements 120 in the display area DA through the cathode 123. To prevent this, the first and second barriers 141 and 142 may partially disconnect the cathode 123. Although two barriers are illustrated in this specification, the present invention is not limited to this.

[0110] The first prevention portion 141 includes a first structure 141-1 and a second structure 141-2, and the second prevention portion 142 includes a third structure 142-1 and a fourth structure 142-2. Referring to FIGS. 3 and 4, the first prevention portion 141, the dam 150, and the second prevention portion 142 are arranged in a closed loop shape centered on the through-hole TH. The reason for arranging the first prevention portion 141, the dam 150, and the second prevention portion 142 in a closed loop shape is that if there is even one opening, moisture and oxygen may penetrate from the outside into the display area DA, or conversely, the second encapsulation layer 117b may flood from the inside into the optical area OA and even the through-hole TH. Referring to FIG. 4, the first prevention portion 141 and the second prevention portion 142 may each be composed of two structures, but this is not intended to be limiting. For example, the first prevention portion 141 and the second prevention portion 142 may each be composed of one structure or three or more structures, but this is not intended to be limiting.

[0111] 3, 4, and 5, the second detection wiring 132 may be disposed between the first prevention portion 141 and the dam 150. That is, the second detection wiring 132 may include a first branch portion 132a, a first outer portion 132b, an inner portion 132c, a second outer portion 132d, and a second branch portion 132e, where the inner portion 132c is disposed between the through-hole TH and the first outer portion 132b or the second outer portion 132d. In addition, the first branch portion 132a and the second branch portion 132e are disposed to overlap the dam 150.

[0112] A through-hole TH may be formed in the optical area OA of the display panel DP to allow a camera or optical sensor to be disposed therein. To form the through-hole TH, a precision cutting process using a laser may be performed on the substrate 110 of the optical area OA of the display panel DP.

[0113] The laser may be irradiated in a circular or elliptical shape according to the shape of the optical region OA, and the entire region above the substrate 110, including the substrate 110, may be removed through the laser irradiation. There may be a difference between the actual optical region OA and the laser irradiation region. For example, the laser irradiation region of the optical region OA may be a region about 100 μm inward. Only by having such a difference between the laser irradiation region and the optical region OA can the insulating layer of the optical region OA be damaged during laser irradiation.

[0114] The laser may be, but is not limited to, a picosecond laser or a femtosecond laser. Lasers utilize stimulated emission by amplifying the light generated by applying energy to a specific material. They have radio wave-like properties and are monochromatic, directional, and are used in communications, medical care, and industrial applications. Lasers can easily form patterns or remove specific areas. Lasers use energy to form or remove patterns. When a laser irradiates a target object, the thermal energy melts the target object, forming a pattern. The longer the laser is irradiated, the more likely a thermal effect will occur, which is transferred to the area surrounding the patterned area. This thermal effect occurs when heat accumulates around the laser-irradiated area of ​​the target object, potentially burning or deforming surrounding areas larger than the intended pattern. Due to these laser characteristics, if the laser-irradiated area overlaps or is adjacent to an insulating film, the laser's thermal energy can also deform the insulating film. Deformation of the insulating film may cause cracks, which may propagate through the insulating film, resulting in peeling or the penetration of moisture and oxygen. For example, to prevent deformation or peeling of the insulating films, such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, the insulating films may be removed at a distance of about 100 μm from the laser irradiation position.

[0115] Cracks that occur when cutting the substrate 110 with a laser can propagate through the rigid inorganic insulating layer. Alternatively, cracks can occur in the through-holes TH formed by the laser due to interference during assembly of a camera or sensor. The cracks that occur at this time can also propagate through the inorganic insulating layer. If a crack that occurs in the through-holes TH propagates through the inorganic insulating layer, a line defect or a growing dark spot (GDS) defect can occur.

[0116] To prevent this, according to one embodiment of the present specification, a second detection wiring 132 can be disposed that can detect a crack when it occurs near the through-hole TH.

[0117] According to an embodiment of the present specification, the second detection wiring 132 may be formed to check the expansion of a crack that occurs at the cut surface of the through hole TH.

[0118] 2, 4, and 5, the second detection wiring 132 according to an embodiment of the present specification may be disposed in the same layer as the plurality of touch sensor electrodes TS or the plurality of touch bridge electrodes BM disposed on the encapsulation portion 117. Therefore, the second detection wiring 132 may facilitate detection of cracks occurring on the encapsulation portion 117, but may make it difficult to detect cracks occurring in or transmitted through the inorganic insulating layer below the encapsulation portion 117.

[0119] Therefore, according to one embodiment of the present specification, a plurality of metal patterns 161 may be further disposed below the second detection wiring 132, overlapping with the second detection wiring 132, and along the outer periphery of the through hole TH, and at least one of the plurality of metal patterns 161 may be electrically connected to the second detection wiring 132. The plurality of metal patterns 161 may be formed in a polygonal shape such as a triangle, a rectangle, a pentagon, etc., but the shape of the plurality of metal patterns 161 is not limited thereto.

[0120] For example, if a crack occurs or propagates in an inorganic insulating layer such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, a portion of the second detection wiring 132 connected to the plurality of metal patterns 161 may be disconnected, increasing resistance. This allows for precise detection of cracks that occur or propagate in the inorganic insulating layers of the optical region OA.

[0121] According to an embodiment of the present disclosure, the semiconductor device may further include a metal wiring 162 connecting the plurality of metal patterns 161. For example, the metal wiring 162 may be disposed in the same layer and made of the same material as the gate wiring or the second gate electrode G2. Since the metal wiring 162 connects the plurality of metal patterns 161, even if a crack occurs in a region between the plurality of metal patterns 161, the metal wiring 162 can accurately detect the crack.

[0122] 4 and 5, the first prevention portion 141 may include a first structure 141-1 and a second structure 141-2, as described with reference to FIG. 4. The first structure 141-1 and the second structure 141-2 may be formed as a two-tiered structure, with an upper and lower structure, to separate the cathode 123, which may serve as a moisture transmission path from the area where the through-holes TH are disposed, and an undercut structure may be formed on the side of the upper structure. Specifically, the upper portions of the first structure 141-1 and the second structure 141-2 may be arranged to have a trapezoidal cross section with a positive taper, and the lower portions may be arranged to have a rectangular cross section with a positive taper or a constant height close to vertical, so that a difference in width may occur between the lower surface of the upper portion and the upper surface of the lower portion, where the upper and lower portions meet. Because the upper surface of the lower portion may be narrower than the lower surface of the upper portion, an undercut structure may be formed in which a portion of the lower surface of the upper portion is exposed. Therefore, the cathode 123 deposited on the front surface of the display panel DP may be interrupted by the undercut structure of the upper side surfaces of the first structure 141-1 and the second structure 141-2 described above.

[0123] The first structure 141-1 and the second structure 141-2 constituting the first prevention unit 141 may be made of an organic material or an inorganic material. For example, the upper portions of the first structure 141-1 and the second structure 141-2 may be made of the same material as the first planarization layer 115a and the second planarization layer 115b, but are not limited to this. Also, the lower portions of the first structure 141-1 and the second structure 141-2 may be made of the same material as the second interlayer insulating layer 113b, but are not limited to this.

[0124] The second stopper 142 may include a third structure 142-1 and a fourth structure 142-2. The third structure 142-1 and the fourth structure 142-2 constituting the second stopper 142 may be formed in a two-tiered structure, with an upper and a lower layer, like the first structure 141-1 and the second structure 141-2. The second sealing layer 117b disposed on the second stopper 142 makes it difficult for moisture or oxygen to permeate the upper portion, and an undercut structure may be formed on the side of the upper portion, similar to the first stopper 141, to block the permeation path, mainly through the through-hole TH and the side where the first stopper 141 is disposed. The arrangement of the first stopper 141 and the second stopper 142 may prevent moisture or oxygen from permeating through the cathode 123 to the light emitting element 120 in the display area DA in the optical area OA.

[0125] The third structure 142-1 and the fourth structure 142-2 constituting the second prevention unit 142 may also be made of an organic material or an inorganic material. For example, the upper portions of the third structure 142-1 and the fourth structure 142-2 may be made of the same material as the first planarization layer 115a and the second planarization layer 115b, but are not limited to this. The lower portions of the third structure 142-1 and the fourth structure 142-2 may be made of the same material as the second interlayer insulating layer 113b, but are not limited to this.

[0126] As shown in FIG. 5, the dam 150 may be formed by stacking a second planarization layer 115b, a bank 116a, and a spacer 116b, but is not limited thereto and may further include a first planarization layer 115a or other layers.

[0127] The second detection wiring 132 disposed between the second structure 141-2 of the first prevention part 141 and the dam 150 may be disposed in the same layer as the plurality of touch sensor electrodes TS or the plurality of touch bridge electrodes BM.

[0128] The second detection wiring 132 can be electrically connected to a plurality of metal patterns 161 arranged in the same layer as the second gate electrode G2 of the display panel DP through a contact hole on the plurality of metal patterns 161 that exposes a portion of the plurality of metal patterns 161.

[0129] The line width of the second detection wiring 132 is not limited, but may be selected taking into consideration the size of the structure of the first prevention unit 141 and the crack detection sensitivity. The designed width of the second detection wiring 132 may be smaller than the structure of the first prevention unit 141, which is intended to prevent the penetration of moisture and oxygen. The second detection wiring 132 may be disposed adjacent to the second prevention unit 142, but it may be preferable to dispose the second detection wiring 132 between the first prevention unit 141 and the dam 150 to detect whether a crack has occurred at an early stage.

[0130] 6 is a plan view of an optical region according to one embodiment of the present specification. The plan view of FIG. 6 is intended to illustrate contacts between the second detection wiring and the multiple metal patterns in the optical region, and for the sake of convenience, redundant explanations other than those for the multiple metal patterns and the contacts between the second detection wiring will be omitted.

[0131] According to another feature of the present disclosure, the plurality of metal patterns 161 may be connected to the second detection wiring 132 through contact holes on the plurality of metal patterns 161 that expose portions of the plurality of metal patterns 161 .

[0132] According to one embodiment of the present disclosure, even if only one of the plurality of metal patterns 161 connected to each other by the plurality of metal wires 162 is connected to the second detection wire 132, if a crack occurs or the generated crack propagates in an inorganic insulating layer such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, a portion of the second detection wire 132 connected to the plurality of metal patterns 161 may be disconnected, increasing resistance. This allows for precise detection of cracks that occur or propagate in the inorganic insulating layers of the optical region OA.

[0133] In the following, reference will be made to FIG. 7 for a more detailed description of the optical area OA of a display device according to another embodiment of the present specification.

[0134] 7 is a cross-sectional view of a display device according to another embodiment of the present specification. The plan view of FIG. 7 shows substantially the same configuration except for the metal wiring connecting the plurality of metal patterns in the optical region. Therefore, for the sake of convenience, redundant description will be omitted, excluding the plurality of metal patterns and the metal wiring such as the second detection wiring.

[0135] According to another embodiment of the display device 200 of the present specification, the metal wiring 262 connecting the plurality of metal patterns 261 is composed of a first portion P1, a second portion P2 opposite to the first portion, a third portion P3 connected to one end of the first portion P1 and one end of the second portion P2, and a fourth portion P4 opposite to the third portion P3 and connected to the other end of the first portion P1 and the other end of the second portion P2, and at least one of the first portion P1, the second portion P2, the third portion P3 and the fourth portion P4 of the metal wiring 262 may be composed of a plurality of metal wirings.

[0136] Specifically, the first portion P1 may be composed of one metal wire, the second portion P2 may be composed of two metal wires, the third portion P3 may be composed of three metal wires, and the fourth portion P4 may be composed of five metal wires. For example, the plurality of metal wires may be metal wires 262 connected in parallel, or metal wires made of the same material as the metal wire 262 may be arranged in parallel in the same layer.

[0137] According to another embodiment of the present specification, the number of metal wirings 262 may vary depending on the position, so that the first portion P1, the second portion P2, the third portion P3, and the fourth portion P4 of the metal wiring 262 may have different resistance values. Therefore, when the metal wiring 262 connecting the plurality of metal patterns 261 is disconnected due to a crack, the degree of increase in resistance varies depending on the number of disconnected cracks. Therefore, when the number of metal wirings 262 varies depending on the position, the position where the crack occurred can be accurately detected.

[0138] Hereinafter, reference will be made to FIG. 8 for a more detailed description of the optical area OA of a display device according to another embodiment of the present specification.

[0139] 8 is a plan view of a display device according to another embodiment of the present specification. The plan view of FIG. 8 is substantially the same as the other embodiments except for the plurality of metal patterns and the contacts of the second detection lines in the optical region. Therefore, for the sake of convenience, redundant description will be omitted except for the plurality of metal patterns and the contacts of the second detection lines.

[0140] In a display device 300 according to another embodiment of the present disclosure, the plurality of metal patterns 361 may be connected to the second detection wiring 332 through contact holes that expose portions of the plurality of metal patterns 361 on the plurality of metal patterns 361. For example, contact holes may be disposed in at least two of the plurality of metal patterns 361, and the second detection wiring 332 may be electrically connected to at least two of the plurality of metal patterns 361 through the contact holes.

[0141] According to another embodiment of the present disclosure, when at least two of the plurality of metal patterns 361, more preferably all of the plurality of metal patterns 361, connected to each other by the plurality of metal wires 362, are connected to the second detection wire 332, when a crack occurs or propagates in an inorganic insulating layer, such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, a portion of the second detection wire 332 connected to the plurality of metal patterns 361 may be disconnected, increasing resistance. This allows for precise detection of cracks that occur or propagate in the inorganic insulating layer of the optical region OA.

[0142] An embodiment of the present invention can also be described as follows.

[0143] A display device according to one embodiment of the present specification includes a substrate including a display area, an optical area disposed within the display area and including a through hole, and a non-display area surrounding the display area, a first detection wiring disposed in the non-display area and surrounding the outer periphery of the display area, a second detection wiring disposed inside the first detection wiring and surrounding the outer periphery of the display area and the through hole, and a plurality of metal patterns disposed along the outer periphery of the through hole below the second detection wiring, wherein at least one of the plurality of metal patterns is electrically connected to the second detection wiring.

[0144] According to another feature of the present disclosure, the semiconductor device may further include metal wiring connecting the plurality of metal patterns.

[0145] According to another feature of the present specification, a metal wiring connecting a plurality of metal patterns includes a first portion, a second portion opposite the first portion, a third portion connected to one end of the first portion and one end of the second portion, and a fourth portion opposite the third portion and connected to the other end of the first portion and the other end of the second portion, and at least one of the first portion, the second portion, the third portion, and the fourth portion of the metal wiring may be composed of a plurality of metal wirings.

[0146] According to another feature of the present specification, the second portion may consist of two metal traces, the third portion may consist of three metal traces, and the fourth portion may consist of four metal traces.

[0147] According to another feature of the present disclosure, the first, second, third, and fourth portions of the metal wiring may have different resistance values.

[0148] According to another feature of the present specification, the display area further includes a plurality of thin film transistors arranged on the substrate, a plurality of light-emitting elements arranged on the plurality of thin film transistors, a sealing portion covering the plurality of light-emitting elements, and a plurality of touch sensor electrodes and a plurality of touch bridge electrodes arranged on the sealing portion, and the second detection wiring may be arranged in the same layer as the plurality of touch sensor electrodes or the plurality of touch bridge electrodes.

[0149] According to another feature of the present specification, the first detection wiring may be disposed in the same layer as the second detection wiring.

[0150] According to another feature of the present specification, the plurality of thin film transistors may be disposed on a substrate in the display region, further comprising: a first thin film transistor having a first active layer including silicon, a first gate electrode, a first source electrode, and a first drain electrode; and a second thin film transistor disposed on the first thin film transistor, having a second active layer including an oxide, a second gate electrode, a second source electrode, and a second drain electrode, wherein the plurality of metal patterns may be disposed on the same layer as the first gate electrode.

[0151] According to another feature of the present disclosure, the plurality of metal patterns may be connected to the second detection wiring through a contact hole on the plurality of metal patterns that exposes a portion of the plurality of metal patterns.

[0152] According to another feature of the present specification, contact holes may be disposed in at least two of the plurality of metal patterns, and the second detection wiring may be electrically connected to at least two of the plurality of metal patterns through the contact holes.

[0153] According to another feature of the present specification, the semiconductor device may further include at least one dam disposed on the substrate and surrounding the through hole, and at least one connection prevention portion disposed on the substrate and closer to the through hole than the at least one dam, and the second detection wiring may be disposed between the at least one dam and the at least one connection prevention portion.

[0154] According to another feature of the present disclosure, the optical device may further include an optical-electronic device disposed so as to overlap with the optical region.

[0155] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. All technical concepts within the scope of the claims of the present specification should be construed as being within the scope of the present specification.

Claims

1. a substrate including a display area, an optical area disposed within the display area and including a through-hole, and a non-display area surrounding the display area; a first detection wiring that is disposed in the non-display area and surrounds the outer periphery of the display area; a second detection wiring disposed inside the first detection wiring and surrounding the outer periphery of the display area and the through-hole; a plurality of metal patterns disposed in the optical region and arranged along an outer periphery of the through hole under the second detection wiring; At least one of the plurality of metal patterns is electrically connected to the second detection wiring.

2. The display device of claim 1 , further comprising a metal wiring connecting the plurality of metal patterns.

3. a metal wiring connecting the plurality of metal patterns includes a first portion, a second portion opposite to the first portion, a third portion connected to one end of the first portion and one end of the second portion, and a fourth portion opposite to the third portion and connected to the other end of the first portion and the other end of the second portion; The display device of claim 1 , wherein at least one of the first portion, the second portion, the third portion, and the fourth portion of the metal wiring is formed of a plurality of the metal wirings.

4. the second portion is made up of two of the metal wirings, the third portion is made up of three of the metal wirings, The display device according to claim 3 , wherein the fourth portion is made up of four of the metal wirings.

5. The display device according to claim 4 , wherein the first portion, the second portion, the third portion, and the fourth portion of the metal wiring have resistance values ​​different from one another.

6. The display area includes a plurality of thin film transistors disposed on the substrate; a plurality of light-emitting elements disposed on the plurality of thin film transistors; a sealing portion that covers the plurality of light-emitting elements; Further comprising a plurality of touch sensor electrodes and a plurality of touch bridge electrodes disposed on the sealing portion; The display device according to claim 1 , wherein the second detection wiring is arranged in the same layer as the plurality of touch sensor electrodes or the plurality of touch bridge electrodes.

7. The display device according to claim 6 , wherein the first detection wiring is disposed in the same layer as the second detection wiring.

8. The plurality of thin film transistors are arranged on the substrate in the display area, and include a first thin film transistor including a first active layer including silicon, a first gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the first thin film transistor, the second thin film transistor including a second active layer including an oxide, a second gate electrode, a second source electrode, and a second drain electrode; The display device according to claim 6 , wherein the plurality of metal patterns are disposed in the same layer as the first gate electrode.

9. The display device of claim 8 , wherein the plurality of metal patterns are connected to the second detection wiring through contact holes that expose portions of the plurality of metal patterns.

10. the contact holes are arranged in at least two of the plurality of metal patterns; The display device of claim 9 , wherein the second detection wiring is electrically connected to at least two of the plurality of metal patterns through the contact hole.

11. at least one dam disposed on the substrate and surrounding the through-hole; and at least one connection prevention portion disposed on the substrate and closer to the through-hole than the at least one dam. The display device of claim 1 , wherein the second detection wiring is disposed between at least one of the dams and at least one of the coupling prevention portions.

12. The display device of claim 1 , further comprising an optoelectronic device disposed overlapping the optical region.

13. a substrate including a display area, an optical area disposed within the display area and including a through-hole, and a non-display area surrounding the display area; a second detection wiring surrounding the outer periphery of the display area and the through-hole; the display area includes a plurality of thin film transistors disposed on the substrate; The plurality of thin film transistors are a first thin film transistor disposed on the substrate in the display area, the first thin film transistor including a first active layer including polysilicon; a second thin film transistor including a second active layer including an oxide; the optical region includes a plurality of metal patterns disposed along an outer periphery of the through hole under the second detection wiring, At least one of the plurality of metal patterns is electrically connected to the second detection wiring; The display device, wherein the plurality of metal patterns are formed in the same layer as the first gate electrode of the first thin film transistor.

14. The display device of claim 13 , wherein the first thin film transistor and the second thin film transistor are disposed in different layers.

15. The display device of claim 14 , wherein the second thin film transistor is disposed on the first thin film transistor.

16. The display device of claim 13 , wherein a first planarization layer is disposed on the first thin film transistor and the second thin film transistor, and a second planarization layer is disposed on the first planarization layer.

17. The display device of claim 16 , wherein a third planarization layer is disposed on the second planarization layer.

18. The display device of claim 17, wherein at least one of the second planarization layer and the third planarization layer comprises an auxiliary electrode electrically connecting the second thin film transistor to a light emitting diode.

19. 20. The display device of claim 18, wherein the display area includes a bank, and a light-emitting layer of the light-emitting diode is exposed through an open area of ​​the bank.

20. 20. The display device according to claim 19, wherein the bank is made of an opaque material.

21. 20. The display device of claim 19, wherein the bank includes a light-shielding material made of at least one of a colored pigment, organic black, and carbon.

22. The display device according to claim 18 , wherein an encapsulation portion is disposed on the light-emitting diode.

23. The display device according to claim 22 , wherein the display area includes a plurality of touch sensor electrodes and a plurality of touch bridge electrodes arranged on the sealing portion.

24. The display device according to claim 23 , wherein the second detection wiring is arranged in the same layer as the plurality of touch sensor electrodes or the plurality of touch bridge electrodes.

25. 14. The display device of claim 13, wherein the second detection wiring includes a first branch portion, a first outer portion, an inner portion, a second outer portion, and a second branch portion, and the inner portion is disposed between the through hole and the first outer portion or the second outer portion.

26. further comprising at least one dam disposed on the substrate and surrounding the through-hole; The display device of claim 25 , wherein the first branch portion and the second branch portion are arranged to overlap the at least one dam.

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