Semiconductor Devices

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and a calculation circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer containing metal oxide in a channel formation region. The calculation circuit includes a third transistor. The third transistor includes a semiconductor layer containing silicon in the channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided on a layer including the third transistor. The layer including the second transistor is provided on the layer including the first transistor. The first memory circuit has a data holding characteristic different from that of the second memory circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are becoming widespread. To process large amounts of data at high speed, such electronic devices are subject to active technological development aimed at improving the performance of semiconductor devices. One example of a technology that achieves high performance is the so-called SoC (System on Chip) technology, which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with a CPU. With semiconductor devices that achieve high performance through SoC technology, increased heat generation and power consumption become problems.

[0004] Artificial intelligence (AI) technology requires enormous amounts of calculations and parameters, resulting in a significant increase in the amount of computation. Because an increase in the amount of calculations leads to increased heat generation and power consumption, architectures to reduce the amount of calculations have been actively proposed. Representative architectures include binary neural networks (BNNs) and ternary neural networks (TNNs), which are particularly effective for reducing circuit size and power consumption (see, for example, Patent Document 1). For example, BNNs can significantly reduce the amount of calculations and the number of parameters by compressing data originally expressed with 32-bit or 16-bit precision into two values: "+1" or "-1." Because BNNs are effective for reducing circuit size and power consumption, they are considered to be well suited to applications requiring low power consumption with limited hardware resources, such as embedded chips. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0006] When using an accelerator for AI technology calculations, the weight data used in the calculations is transmitted at high speed to the accelerator from chips such as DRAM or SRAM, which are manufactured using a process separate from the accelerator. To reduce the frequency of data transfers, the accelerator requires a large amount of memory capacity to hold the weight data or intermediate data. If the accelerator's memory capacity is small, high-speed data transmission is required. Furthermore, if the accelerator is far from the chip storing the weight data, the parasitic capacitance or resistance of the wiring increases, which may result in higher power consumption.

[0007] An object of one embodiment of the present invention is to reduce power consumption in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to suppress heat generation in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to reduce the size of a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to reduce the number of data transfers between a CPU and a semiconductor device functioning as a memory in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to improve the data transfer rate between a storage memory and a semiconductor device functioning as a cache memory in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a CPU and an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. The first transistor and the second transistor each include a semiconductor layer having a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer having silicon in a channel formation region. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a fourth transistor. The fourth transistor includes a semiconductor layer having a metal oxide in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor and the layer including the second transistor are provided over the layer including the third transistor.

[0010] In one embodiment of the present invention, the backup circuit preferably has a function of retaining data retained in the flip-flop in a state where the supply of power supply voltage is stopped when the CPU is power-gating.

[0011] In one aspect of the present invention, the first memory circuit and the second memory circuit preferably have a function of holding data input to the arithmetic circuit.

[0012] In one aspect of the present invention, the second memory circuit preferably has a different circuit configuration from that of the first memory circuit.

[0013] One embodiment of the present invention is a semiconductor device including a CPU and an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. The first transistor and the second transistor each include a semiconductor layer having a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer having silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer having the first transistor is provided over the layer having the third transistor. The layer having the second transistor is provided over the layer having the first transistor. The first memory circuit has data retention characteristics different from those of the second memory circuit.

[0014] In one embodiment of the present invention, the first memory circuit is preferably a semiconductor device having a function of holding data input to an arithmetic circuit or data output from the arithmetic circuit.

[0015] In one aspect of the present invention, the amplitude voltage for driving the first transistor is preferably smaller than the amplitude voltage for driving the second transistor.

[0016] In one aspect of the present invention, the thickness of the gate insulating film of the first transistor is preferably smaller than the thickness of the gate insulating film of the second transistor.

[0017] In one aspect of the present invention, the second memory circuit preferably has a different circuit configuration from that of the first memory circuit.

[0018] In one aspect of the present invention, the arithmetic circuit is preferably a circuit that performs a product-sum operation.

[0019] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0020] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0021] One embodiment of the present invention can reduce power consumption in a semiconductor device including an accelerator. Another embodiment of the present invention can suppress heat generation in a semiconductor device including an accelerator. Another embodiment of the present invention can reduce the size of a semiconductor device including an accelerator. Another embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device functioning as a memory in a semiconductor device including an accelerator. Another embodiment of the present invention can improve the data transfer rate between a storage memory and a semiconductor device functioning as a cache memory in a semiconductor device including an accelerator. Another embodiment of the present invention can provide a semiconductor device with a novel structure.

[0022] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 5] 5A to 5E are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6]6A and 6B are diagrams illustrating a configuration example of a semiconductor device. [Figure 7] 7A and 7B are diagrams showing various types of memories by hierarchy. [Figure 8] 8A to 8C are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 9] 9A to 9C are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 12] 12A and 12B are diagrams illustrating a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 14] 14A and 14B are diagrams illustrating a configuration example of a semiconductor device. [Figure 15] 15A and 15B are diagrams illustrating a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a diagram illustrating a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a diagram illustrating an example of the configuration of a CPU. [Figure 18] 18A and 18B are diagrams illustrating an example of the configuration of a CPU. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of a CPU. [Figure 20] 20A and 20B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 21] 21A and 21B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 22] FIG. 22 is a top view of a memory device according to one embodiment of the present invention. [Figure 23] FIG. 23 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 24]FIG. 24 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 26] Fig. 26A is a diagram explaining the classification of IGZO crystal structures, Fig. 26B is a diagram explaining the XRD spectrum of silica glass, and Fig. 26C is a diagram explaining the XRD spectrum of crystalline IGZO. [Figure 27] FIG. 27 is a diagram illustrating an example of the configuration of an integrated circuit. [Figure 28] 28A and 28B are diagrams illustrating an example of the configuration of an integrated circuit. [Figure 29] 29A and 29B are diagrams illustrating an application example of an integrated circuit. [Figure 30] 30A and 30B are diagrams illustrating an application example of an integrated circuit. [Figure 31] 31A to 31C are diagrams illustrating an application example of an integrated circuit. [Figure 32] FIG. 32 is a diagram illustrating an application example of an integrated circuit. DETAILED DESCRIPTION OF THE INVENTION

[0024] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0025] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0026] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0027] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0028] Furthermore, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, the symbol may be accompanied by an identifying symbol such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0029] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0030] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0031] 1A and 1B are diagrams illustrating a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a CPU 10, an accelerator 20, and a bus 30. The accelerator 20 includes an arithmetic processing unit 21 and a memory unit 22. The arithmetic processing unit 21 includes an arithmetic circuit 23. The memory unit 22 includes a memory circuit 24. The memory unit 22 may also be referred to as a device memory or a shared memory. The memory circuit 24 includes a transistor 25 including a semiconductor layer 29 having a channel formation region. The arithmetic circuit 23 and the memory circuit 24 are electrically connected to each other via wiring 31.

[0032] The CPU 10 has the function of performing general-purpose processing such as running an operating system, controlling data, and executing various calculations and programs. The CPU 10 has one or more CPU cores. The CPU 10 has, for example, transistors (Si transistors) that have silicon in their channel formation regions. The Si transistors can be made into complementary transistors to form a CMOS circuit (SiCMOS). The CPU 10 is connected to the accelerator 20 via a bus 30.

[0033] Each CPU core is preferably configured to have a data retention circuit that can retain data even when the supply of power supply voltage is stopped. With this configuration, the supply of power supply voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. The power supply voltage is sometimes called a drive voltage. As the data retention circuit, for example, a memory having a transistor (OS transistor) having an oxide semiconductor in its channel formation region is suitable. The configuration of a CPU core including a data retention circuit having an OS transistor will be described in embodiment 3.

[0034] The accelerator 20 has a function of executing a program (also called a kernel or kernel program) called from a host program. The accelerator 20 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0035] The memory unit 22 has a function of storing data to be processed by the accelerator 20. Specifically, it can store data to be input to or output from the arithmetic processing unit 21, such as weight data used in parallel processing of product-sum operations of a neural network.

[0036] The memory portion 22 is provided across multiple memory circuit layers 22_1 to 22_N (N is a natural number equal to or greater than 2). Each of the multiple memory circuit layers 22_1 to 22_N has a memory circuit 24. The memory circuit 24 in each of the multiple memory circuit layers 22_1 to 22_N is electrically connected to the arithmetic circuit 23 of the arithmetic processing unit 21 via wiring 31 and has a function of holding a binary or ternary digital value. In the memory circuit 24, the semiconductor layer 29 of the transistor 25 is an oxide semiconductor. That is, the transistor 25 is an OS transistor. The memory circuit 24 is preferably a memory having an OS transistor (hereinafter also referred to as an OS memory).

[0037] Because the band gap of metal oxides is 2.5 eV or more, OS transistors have extremely small off-state currents. For example, when the voltage between the source and drain is 3.5 V and at room temperature (25°C), the off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24The drain current on / off current ratio can be set to less than A. In other words, the drain current on / off current ratio can be set to 20 to 150 digits. Therefore, the amount of charge leaked from the retention node via the OS transistor in the OS memory is extremely small. Therefore, the OS memory can function as a nonvolatile memory circuit. Also, power gating of the accelerator becomes possible.

[0038] High-density integrated semiconductor devices may generate heat due to circuit operation. This heat increases the temperature of transistors, which can change the transistor's characteristics, resulting in changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, making them less susceptible to temperature-induced changes in field-effect mobility and a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, OS transistors enable stable operation in high-temperature environments.

[0039] Metal oxides suitable for OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for OS transistors because they can provide transistors with excellent electrical properties, such as field-effect mobility, by adjusting the ratio of elements. Furthermore, the oxide containing indium and zinc may contain one or more elements selected from the group consisting of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0040] To improve the reliability and electrical characteristics of OS transistors, the metal oxide used in the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0041] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0042] CAC-OS has the function of both allowing electrons (or holes) to flow and preventing electrons from flowing. By separating the electron flow function from the electron blocking function, both functions can be maximized. In other words, using CAC-OS in the channel formation region of an OS transistor can achieve both a high on-state current and an extremely low off-state current.

[0043] Metal oxides have a wide band gap, which makes it difficult for electrons to be excited, and they have a large effective mass for holes. This means that OS transistors are less susceptible to avalanche breakdown and other problems than typical Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0044] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), a short-channel effect, compared to inversion-type transistors (typically, Si transistors) with pn junctions. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0045] Because OS transistors have high resistance to short-channel effects, their channel length can be reduced without degrading their reliability, allowing for increased circuit integration. As the channel length decreases, the drain electric field becomes stronger, but as mentioned above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0046] Furthermore, because OS transistors have high resistance to short-channel effects, their gate insulating films can be thicker than those of Si transistors. For example, even for miniaturized transistors with channel lengths and widths of 50 nm or less, it may be possible to provide a gate insulating film as thick as about 10 nm. By increasing the gate insulating film thickness, parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by increasing the gate insulating film thickness, leakage current through the gate insulating film can be reduced, leading to a reduction in static current consumption.

[0047] As described above, the accelerator 20 can retain data even when the supply of power supply voltage is stopped by having the memory circuit 24, which is an OS memory. This enables power gating of the accelerator 20, thereby enabling a significant reduction in power consumption.

[0048] The memory circuit 24, which is composed of OS transistors, can be stacked with the arithmetic circuit 23, which can be composed of Si CMOS. That is, the multiple memory circuit layers 22_1 to 22_N are provided on a substrate on which the arithmetic processing unit 21 is provided. The multiple memory circuit layers 22_1 to 22_N can be stacked. This allows for layout without increasing the circuit area, thereby increasing the memory capacity required for arithmetic processing in the accelerator 20. The number of data transfers required for arithmetic processing can be reduced, thereby achieving low power consumption. The memory circuit layers 22_1 to 22_N, each having the multiple memory circuits 24, are electrically connected to the arithmetic circuit 23 via wiring 31 extending in a direction approximately perpendicular to the surface of the substrate on which the arithmetic circuit 23 is provided (the z direction perpendicular to the xy plane in FIG. 1B). Note that "approximately perpendicular" refers to a state in which the wiring 31 is arranged at an angle of 85 degrees to 95 degrees.

[0049] Although the description will be given using an OS transistor as a transistor included in the memory circuit 24, any transistor that can be stacked with a Si transistor included in the underlying arithmetic circuit 23 may be used. For example, a Si transistor stacked on a substrate including a Si transistor by using a bonding technique or the like may be used as the upper-layer transistor. In this case, the Si transistor provided in the upper layer preferably has a longer channel length than the Si transistor in the lower layer so that the transistor has a small off-state current.

[0050] The memory circuit 24 of the accelerator 20 may be a single-layer structure or may be a stack of multiple memory circuit layers 22_1 to 22_N. The single-layer memory circuit layer 22_1 having OS transistors may be stacked with the arithmetic circuit 23, which may be configured with Si CMOS. Therefore, by shortening the physical distance between the arithmetic circuit 23 and the memory circuit 24, the wiring distance can be shortened, reducing parasitic capacitance generated in signal lines and enabling lower power consumption.

[0051] In the accelerator 20, by using a stacked transistor configuration, it is possible to suppress an increase in the circuit area, and therefore it is possible to increase the number of arithmetic circuits 23. Since it is possible to increase the number of circuits (number of cores) that perform calculations in the arithmetic circuits 23, it is possible to lower the frequency of the signals that drive the arithmetic circuits 23. In addition, it is possible to reduce the power supply voltage that drives the arithmetic circuits 23. As a result, it is possible to reduce the power consumption required for calculations by a ratio of several tens of times.

[0052] The memory circuit 24 can be configured as a non-oscillating random-access memory (NOSRAM). "NOSRAM" (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory in which memory cells are two-transistor (2T) or three-transistor (3T) gain cells and access transistors are OS transistors. The memory circuit 24 can be configured by stacking memory circuit layers 22_1 to 22_N using OS transistors. Furthermore, OS transistors have extremely low leakage current, i.e., the current that flows between the source and drain in the off state. NOSRAM can be used as a non-volatile memory by utilizing its extremely low leakage current to retain charge corresponding to data within the memory circuit. In particular, NOSRAM can read stored data without destroying it (non-destructive read), making it suitable for parallel processing of product-sum operations in neural networks, which require repeated large amounts of data read operations.

[0053] The arithmetic processing unit 21 has the function of performing arithmetic processing using digital values. Digital values ​​are less susceptible to noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires highly accurate calculation results. The arithmetic processing unit 21 is preferably configured using Si CMOS, i.e., transistors having silicon in the channel formation region (Si transistors). This configuration allows it to be stacked with OS transistors.

[0054] The arithmetic circuit 23 has a function of performing one of processes such as integer arithmetic, single-precision floating-point arithmetic, and double-precision floating-point arithmetic using digital value data held in each of the memory circuits 24 of the multiple memory circuit layers 22_1 to 22_N. The arithmetic circuit 23 has a function of repeatedly executing the same process such as a multiply-accumulate operation.

[0055] The arithmetic circuits 23 are configured so that one arithmetic circuit 23 is provided for each read bit line of the memory circuit 24, i.e., for each column (column). This configuration allows parallel arithmetic processing of data for one row of the memory circuit 24 (up to all bit lines). Compared to multiply-and-accumulate operations using the CPU 10, column-parallel calculation is not limited by the data bus size (e.g., 32 bits) between the CPU and memory. This significantly increases the parallelism of calculations, thereby improving the efficiency of massive arithmetic processing, such as deep neural network learning (AI technology) and scientific and engineering calculations using floating-point arithmetic. Furthermore, because data output from the memory circuit 24 can be read after completion of calculations, the power consumed by memory access (data transfer between the CPU and memory and calculations by the CPU) can be reduced, suppressing heat generation and power consumption. Furthermore, shortening the physical distance between the arithmetic circuits 23 and the memory circuit 24, for example, by stacking the wiring distance, reduces the parasitic capacitance generated in the signal lines, thereby enabling lower power consumption.

[0056] The sum-of-products operation in inference processing requires a large amount of data, which requires a huge bandwidth (data transfer rate). By arranging multiple memory circuit layers 22_1 to 22_N on the arithmetic circuit 23, as shown in the configuration of Figure 1B, a wide bandwidth can be secured. Furthermore, the distance between circuits can be reduced, which increases the transfer speed of multiple data. Therefore, the power consumption required for the sum-of-products operation in inference processing can be reduced by several tenths.

[0057] Inference processing based on deep neural networks is optimized for data with a bit depth of preferably 32 bits or less, more preferably 16 bits or less, and even more preferably 8 bits or less, rather than calculations using data with a large bit depth such as 64 bits, thereby enabling low power consumption without reducing calculation accuracy.

[0058] The bus 30 electrically connects the CPU 10 and the accelerator 20. That is, the CPU 10 and the accelerator 20 can transmit data via the bus 30.

[0059] FIG. 2A is a schematic diagram illustrating data read from the memory circuits 24 of the stacked memory circuit layers 22_1 to 22_N to the arithmetic circuit 23 in the accelerator 20 illustrated in FIG. 1B. In FIG. 2A, arrows indicate the movement of data. As illustrated in FIG. 2A, the semiconductor device of one embodiment of the present invention can read data from the memory circuits 24 included in the stacked memory circuit layers 22_1 to 22_N via wirings 31. The physical distance between the arithmetic circuit 23 and the memory circuit 24, which are stacked, is very short, and therefore the wiring distance is short. Therefore, parasitic capacitance generated in the wiring 31 can be reduced, thereby enabling low power consumption.

[0060] Note that as the number of stacked memory circuit layers 22_1 to 22_N increases, the parasitic capacitance generated in the wiring 31 increases. Therefore, it is preferable to provide switches SW_1 to SW_N in each of the memory circuit layers 22_1 to 22_N between the wiring 31 and the wiring to which the memory circuit 24 is connected, such as a read bit line. The switches SW_1 to SW_N are configured to be controlled so as to be turned off in the memory circuit layers 22_1 to 22_N from which data is not read and turned on in the memory circuit layers 22_1 to 22_N from which data is read. This configuration can reduce the parasitic capacitance of the wiring 31 that accompanies an increase in the number of memory circuit layers 22_1 to 22_N, thereby achieving low power consumption.

[0061] Furthermore, the number of memory circuits 24 may be varied by varying the circuit layout, transistor channel length, channel width, or transistor density in each of the stacked memory circuit layers 22_1 to 22_N. For example, as shown in FIG. 3A, the memory circuits 24 in the lower layers (e.g., memory circuit layer 22_1) of the memory circuit layers 22_1 to 22_N may have a circuit layout in which the transistor density is high, and the transistor density decreases toward the upper layers (z direction in the figure). This configuration allows the number of memory circuits that are physically close to the arithmetic circuit 23 to be increased, thereby improving the data retention characteristics of the memory circuits 24 in the upper layers.

[0062] 3B, the memory circuits 24 in the upper layers (e.g., memory circuit layer 22_N) of the memory circuit layers 22_1 to 22_N may have a circuit layout in which the transistor density is high, and the transistor density decreases toward the lower layers (the memory circuit layer 22_1 side in the figure). By adopting such a configuration, it is possible to improve the data retention characteristics of the memory circuits that are physically close to the arithmetic circuit 23, and also to increase the data density.

[0063] One embodiment of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can reduce the size of a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. Another embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device that functions as a memory in a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters. In other words, a semiconductor device that functions as an accelerator for AI technology or the like, which requires a huge amount of calculation and a large number of parameters, has a non-von Neumann architecture, and can perform parallel processing with significantly less power consumption than a von Neumann architecture, which consumes more power as the processing speed increases.

[0064] 4A is a diagram illustrating an example of a circuit configuration applicable to each of memory circuit layers 22_1 to 22_N included in the semiconductor device 100 of the present invention. FIG. 4A illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and read bit lines RBL_1 to RBL_N, which are arranged in an M-row, N-column matrix (M and N are natural numbers of 2 or greater). Also illustrated is a memory circuit 24 connected to each word line and bit line.

[0065] 4B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 24. The memory circuit 24 includes a transistor 25, a transistor 26, a transistor 27, and a capacitor 28 (also referred to as a capacitor).

[0066] One of the source or drain of the transistor 25 is connected to the write bit line WBL. The gate of the transistor 25 is connected to the write word line WWL. The other of the source or drain of the transistor 25 is connected to one electrode of the capacitance element 28 and the gate of the transistor 26. One of the source or drain of the transistor 26 and the other electrode of the capacitance element 28 are connected to a wiring that applies a fixed potential, such as a ground potential. The other of the source or drain of the transistor 26 is connected to one of the source or drain of the transistor 27. The gate of the transistor 27 is connected to the read word line RWL. The other of the source or drain of the transistor 27 is connected to the read bit line RBL. As described above, the read bit line RBL is connected to the arithmetic circuit 23 via the wiring 31 or the like that extends in a direction substantially perpendicular to the surface of the substrate on which the arithmetic circuit 23 is provided.

[0067] The circuit configuration of memory circuit 24 shown in FIG. 4B corresponds to a three-transistor (3T) gain cell NOSRAM. Transistors 25 to 27 are OS transistors. OS transistors have an extremely small leakage current, i.e., a current that flows between the source and drain when they are off. NOSRAM can be used as a nonvolatile memory by utilizing its extremely small leakage current characteristic to retain charge corresponding to data within the memory circuit.

[0068] The circuit configuration applicable to the memory circuit 24 in FIG. 4A is not limited to the 3T-type NOSRAM in FIG. 4B. For example, a circuit equivalent to the DOSRAM shown in FIG. 5A may also be used. DOSRAM is a RAM having 1T1C-type memory cells and is an abbreviation for Dynamic Oxide Semiconductor RAM. FIG. 5A illustrates a memory circuit 24A having a transistor 25A and a capacitive element 28A. The transistor 25A is an OS transistor. The memory circuit 24A is illustrated as being connected to a bit line BL, a word line WL, and a back gate line BGL.

[0069] A circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a circuit equivalent to a 2T-type NOSRAM illustrated in FIG. 5B. FIG. 5B illustrates a memory circuit 24B including a transistor 25B, a transistor 26B, and a capacitor 28B. The transistors 25B and 26B are OS transistors. The transistors 25B and 26B may be OS transistors whose semiconductor layers are arranged in different layers or may be OS transistors whose semiconductor layers are arranged in the same layer. The memory circuit 24B is illustrated as being connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL.

[0070] A circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a circuit combining 3T-type NOSRAMs as shown in FIG. 5C. FIG. 5B illustrates a memory circuit 24C including a memory circuit 24_P and a memory circuit 24_N, each capable of holding data of different logic levels. FIG. 5B illustrates a memory circuit 24_P including a transistor 25_P, a transistor 26_P, a transistor 27_P, and a capacitor 28_P, and a memory circuit 24_N including a transistor 25_N, a transistor 26_N, a transistor 27_N, and a capacitor 28_N. Each transistor included in the memory circuit 24_P and the memory circuit 24_N is an OS transistor. Each transistor included in the memory circuit 24_P and the memory circuit 24_N may be an OS transistor having semiconductor layers arranged in different layers or an OS transistor having semiconductor layers arranged in the same layer. The memory circuit 24C is shown as being connected to a write bit line WBL_P, a read bit line RBL_P, a write bit line WBL_N, a read bit line RBL_N, a write word line WWL, and a read word line RWL. The memory circuit 24C holds data of different logics, reads the data of different logics to the read bit line RBL_P and the write bit line WBL_N, and amplifies the data with a sense amplifier or the like, thereby enabling high-speed data reading.

[0071] 5C, an exclusive OR circuit (XOR circuit) may be provided so that data equivalent to the multiplication of the data held in the memory circuit 24_P and the memory circuit 24_N is output to the read bit line RBL. This configuration makes it possible to omit the operation equivalent to the multiplication in the arithmetic circuit 23, thereby achieving low power consumption.

[0072] A circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a NAND memory circuit having a charge storage layer, such as a MONOS type, as shown in FIG. 5D. FIG. 5D illustrates a memory circuit 24D including transistors 32[1] to 32[n] and transistors SW1 and SW2. The transistors 32[1] to 32[n] and the transistors SW1 and SW2 are OS transistors. The transistors 32[1] to 32[n] and the transistors SW1 and SW2 may be OS transistors having semiconductor layers provided in the same layer or different layers. The transistors 32[1] to 32[n] each include a control gate electrode and a charge storage layer or a floating gate electrode.

[0073] 5D may be a string-type (also called a macaroni-type) NAND memory in which an opening is provided in a stack of alternately stacked conductive layers and insulating layers, and conductors, insulators, semiconductors, etc. are concentrically stacked on the inner wall of the opening. The memory circuit 24D illustrates an example in which the transistors 32[1] to 32[n] are connected to word lines WL[1] to WL[n] and back gate lines BGL[1] to BGL[n], and the transistors SW1 and SW2 are connected to control lines SEL1 and SEL2, a read bit line, and a source line SL.

[0074] A circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a NAND memory circuit combining NOSRAM as shown in FIG. 5E. FIG. 5E illustrates a memory circuit 24E including transistors 25[1] to 25[n], transistors 26[1] to 26[n], and transistors SW1 and SW2. The transistors 25[1] to 25[n], transistors 26[1] to 26[n], and transistors SW1 and SW2 are OS transistors. The transistors 25[1] to 25[n], transistors 26[1] to 26[n], and transistors SW1 and SW2 may be OS transistors having semiconductor layers provided in the same layer or different semiconductor layers. The circuit including the transistors 25[1] to 25[n] and transistors 26[1] to 26[n] includes nodes ND[1] to ND[n] where charges corresponding to data are held by turning off the transistors 25[1] to 25[n].

[0075] In FIG. 5E, transistors 25[1] to 25[n] and transistors 26[1] to 26[n] may be vertical channel (also called macaroni) NAND memory devices, in which an opening is formed in a stack of alternating conductive and insulating layers, and conductors, insulators, semiconductors, etc. are concentrically stacked on the inner walls of the opening. NAND memory devices composed of OS transistors, which can be fabricated on a layer containing Si transistors, function not only as storage memory but also as main memory, and can be called universal memory. Universal memory devices can also function as main memory devices, such as DRAM (Dynamic Random Access Memory) chips, potentially enabling the construction of computer systems that do not require DRAM. The memory circuit 24E illustrates an example in which transistors 25[1] to 25[n] are connected to word lines WL[1] to WL[n], respectively, and transistors 26[1] to 26[n] are connected to nodes ND[1] to ND[n], which are data storage nodes of NOSRAM. The memory circuit 24E also illustrates an example in which the transistors SW1 and SW2 are connected to the control lines SEL1 and SEL2, the read bit line RBL, and the source line SL.

[0076] Furthermore, the circuit configuration of the memory circuit applicable to each of the memory circuit layers 22_1 to 22_N included in the semiconductor device 100 of the present invention may differ for each layer. For example, as shown in Fig. 6A, the memory circuit in the lower layer (e.g., memory circuit layer 22_1) of the memory circuit layers 22_1 to 22_N is referred to as memory circuit 24A, and the memory circuits in the upper layers (e.g., memory circuit layer 22_2, memory circuit layer 22_N) are referred to as memory circuit 24B. The memory circuit 24A, which is physically close to the arithmetic circuit 23, may have a NOSRAM circuit configuration, while the memory circuit 24B may have other circuit configurations such as DOSRAM or NAND memory.

[0077] In the configuration shown in FIG. 6B , which differs from that shown in FIG. 6A , the memory circuit in the upper layer (e.g., memory circuit layers 22_2 to 22_N) is a vertical channel type universal memory memory circuit 24N. The memory circuit 24A, which is physically close to the arithmetic circuit 23, can be configured as a NOSRAM. By using a vertical channel type universal memory with high storage density as the memory circuit 24N, external memory such as DRAM can be omitted. Furthermore, by storing data required for arithmetic processing in NOSRAM, which has faster write and read speeds than universal memory, arithmetic processing can be performed at high speed. This configuration allows data stored in the universal memory (memory circuit 24N) to be processed via the NOSRAM (memory circuit 24A), significantly increasing the storage capacity of data used for arithmetic processing in the semiconductor device 100. Additionally, the gap in delay time required for data read and write can be reduced.

[0078] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 7A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. Figure 7A shows, from the top layer, memories embedded as registers in a processing unit (PU), memories that can be used as caches such as NOSRAM, and memories that can be used as storage memories such as OS memory or main memory.

[0079] 7A and 7B, a three-dimensional NAND-type universal memory using OS transistors is referred to as "OS Memory." Note that "OS Memory" is preferably an OS transistor with a larger storage capacity than NOSRAM.

[0080] Universal memory is randomly accessible and has an extremely small off-state current of the OS transistor, so it can retain written information for more than one year, or even more than ten years, even if power is cut off. Therefore, universal memory can also be considered nonvolatile memory.

[0081] Furthermore, since the amount of charge written into universal memory is unlikely to change over a long period of time, universal memory can hold not only binary (1 bit) information but also multi-value (multi-bit) information.

[0082] Furthermore, because universal memory writes charge to nodes via OS transistors, it does not require the high voltages required by conventional NAND flash memory, enabling high-speed write operations. Universal memory also eliminates the erase operation required by NAND flash memory before rewriting data. Furthermore, because charge injection and extraction into the floating gate or charge trapping layer are not performed, universal memory allows for virtually unlimited data write and read operations. Universal memory exhibits less degradation and higher reliability than conventional NAND flash memory.

[0083] A semiconductor device according to one embodiment of the present invention can significantly increase the storage capacity of data used in arithmetic processing. In addition, it can reduce the gap in delay time required for reading and writing data. Furthermore, as shown in FIG. 7B , memory circuits with different data retention characteristics or storage capacities are stacked in the z direction (the direction perpendicular to the substrate on which the arithmetic processing unit 21 is provided), allowing data to be input and output through each layer. Data input and output can be performed using wiring between each layer, which reduces the parasitic capacitance or resistance of the wiring and suppresses an increase in power consumption due to data input and output.

[0084] In one embodiment of the present invention, some of the memory circuit layers 22_1 to 22_N may be circuits having different functions. For example, as illustrated in FIG. 8A , a circuit 24F having a function different from that of a memory circuit may be provided in the memory circuit layer 22_N in the top layer of the accelerator 20.

[0085] The circuit 24F can be a circuit that can be provided using OS transistors. For example, as shown in FIG. 8B, it can be an amplifier circuit that can amplify the potential of the input IN at the output OUT. The transistor 33B can be configured using an OS transistor. In addition to the configuration of FIG. 8B, the circuit 24F may also have an antenna 34, for example, as shown in FIG. 8C. The antenna 34 can be formed by arranging a conductive layer used in the circuit 24F so that it functions as an antenna. For example, in the case of an antenna for a fifth-generation mobile communication system (5G), the antenna 34 uses communication frequencies in the 3.7 GHz band, the 4.5 GHz band, and the 28 GHz band in Japan.

[0086] In another embodiment of the present invention, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N are differentiated. The data retention characteristics correspond to the time for which written data can be retained (data retention time). In the schematic diagram shown in FIG. 9A, the data retention characteristics of the memory circuit 24A and the memory circuit 24B are differentiated. When the memory circuit 24A is used as a cache memory, the data retention time of the memory circuit 24A may be several milliseconds. When the memory circuit 24B is used as a main memory or a storage memory, the data retention time of the memory circuit 24B is preferably longer than that of the cache memory.

[0087] To achieve different retention times, as shown in FIG. 9A, the drive voltages V1 and V2 output by the drive circuit 35 for driving each memory circuit are made different. For example, as shown in FIG. 9B, the amplitude voltages for driving the transistors in the memory circuits are made different by the drive voltages V1 and V2. In FIG. 9B, the potential for turning off the transistors in the memory circuits 24A and 24B is designated as Voff. In FIG. 9B, the potential Von1 for turning on the transistor in the memory circuit 24A is set lower than the potential Von2 for turning on the transistor in the memory circuit 24B. By setting the drive voltages V1 and V2 in this manner, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different. By using different drive voltages V1 and V2 for driving each memory circuit, the S value (subthreshold swing value) and field-effect mobility of the transistors in each memory circuit can be made different.

[0088] As another example, as shown in Fig. 9C, a potential for turning on the transistors in the memory circuits 24A and 24B is set to be a potential Von. In Fig. 9C, a potential Voff1 for turning off the transistors in the memory circuit 24A is set to be higher than a potential Voff2 for turning on the transistors in the memory circuit 24B. By setting the drive voltages V1 and V2 in this manner, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different.

[0089] To achieve different retention times, the thickness of an insulator functioning as a gate insulating film of a transistor included in a memory circuit may be varied for each layer. For example, as shown in FIG. 10, the thickness of an insulator 36A functioning as a gate insulating film of a transistor 25A included in a memory circuit 24A in the memory circuit layer 22_1 is made smaller than the thickness of an insulator 36B functioning as a gate insulating film of a transistor 25B included in a memory circuit 24B in the memory circuit layers 22_2 to 22_N. By varying the thickness of the insulator functioning as a gate insulating film of a transistor included in a memory circuit for each layer in this manner, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different.

[0090] Another configuration for differentiating the retention times may be to vary the channel lengths of the transistors in the memory circuits for each layer. For example, as shown in FIG. 11, the channel length L1 of the transistor 25A in the memory circuit 24A in the memory circuit layer 22_1 is set to be shorter than the channel length L2 of the transistor 25B in the memory circuits 24B in the memory circuit layers 22_2 to 2_N. By varying the channel lengths of the transistors in the memory circuits for each layer in this manner, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be varied. Note that while FIG. 11 illustrates a configuration in which the channel lengths are varied for each layer, a combination of different transistor channel widths or channel length-to-channel width ratios (W / L), or different drive frequencies may also be used.

[0091] 12A is a diagram illustrating an example of a circuit configuration applicable to the arithmetic processing unit 21 included in the semiconductor device 100 of the present invention. The arithmetic processing unit 21 has N arithmetic circuits 23_1 to 23_N. Each of the N arithmetic circuits 23_1 to 23_N receives a signal from one of N read bit lines RBL_1 to RBL_N and outputs output signals Q_1 to Q_N. The signals from the read bit lines RBL_1 to RBL_N may be amplified by a sense amplifier or the like and read out. The output signals Q_1 to Q_N correspond to data obtained by performing a product-sum operation using data held in a memory circuit 24.

[0092] Fig. 12B is a diagram illustrating an example of the circuit configuration of the arithmetic circuit 23 applicable to the arithmetic circuits 23_1 to 23_N. Fig. 13 shows a circuit for executing arithmetic processing based on the architecture of a binary neural network (BNN). The arithmetic circuit 23 includes a read circuit 41 to which a signal from a read bit line RBL is supplied, a bit product-sum calculator 42, an accumulator 43, a latch circuit 44, and an encoding circuit 45 that outputs an output signal Q.

[0093] FIG. 13 shows a more detailed configuration example of the arithmetic circuit 23 shown in FIG. 12B. FIG. 13 shows an example of a configuration in which a multiply-and-accumulate operation is performed on 8-bit signals (W[0] to W[7], A[0] to A[7]) to output a 1-bit output signal Q and an 11-bit output signal (accout[10:0]). In FIG. 12B, memory access selects one row per clock, so M (=1 bit × M rows) products and their sums are executed in M ​​clocks. The arithmetic circuit of FIG. 13 requires M / 8 clocks to execute the same M products and their sums in 8 parallel × 1 bit × M / 8 rows. Therefore, the configuration of FIG. 13 can shorten the calculation time by executing the multiply-and-accumulate operation in parallel, thereby improving calculation efficiency.

[0094] 12A and 12B, the arithmetic circuit 23 can reduce the circuit area by using a circuit configuration that performs product-sum operations specialized for inference processing. As a result, the power consumption required for transmitting and receiving data using multiple accelerators 20 can be reduced by a factor of several tens.

[0095] In addition to reducing power consumption in the above-mentioned calculations, reducing power consumption through calculations specialized for product-sum calculations during inference processing, and reducing power consumption through miniaturization of circuit area, optimizing computer architecture, software, and driving methods will make it possible to reduce the power consumption of existing data centers or supercomputers by as much as one thousandth.

[0096] 13, the bit-wise sum-of-products calculator 42 has an accumulator to which 8-bit signals (W[0] to W[7], A[0] to A[7]) are input, and an adder to which the value obtained by the accumulator is input. As shown in FIG. 13, the products of 1-bit signals calculated in eight parallel operations are shown as WA0 to WA7, their sums as WA10, WA32, WA54, and WA76, and their further sums as WA3210 and WA7654.

[0097] 13, an accumulator 43 functioning as an adder outputs the sum of the signal of the bit sum-of-products calculator 42 and the output signal of the latch circuit 44 to the latch circuit 44. The accumulator 43 switches the signal to be input to the adder according to a control signal TxD_EN. When the control signal TxD_EN is 0 (TxD_EN=0), the accumulator 43 outputs the sum of the signal of the bit sum-of-products calculator 42 and the output signal of the latch circuit 44 to the latch circuit 44. When the control signal TxD_EN is 1 (TxD_EN=1), the accumulator 43 outputs the sum of the signal of the logic circuit 47 (11-bit selector) and the output signal of the latch circuit 44 to the latch circuit 44.

[0098] In FIG. 13, after completing the multiplication and accumulation of signals A[0] to A[7] and signals W[0] to W[7], logic circuit 47, which is composed of AND circuits, adds data for batch normalization, specifically signal W[7], while switching using a switching signal (th select[10:0]). Note that data for batch normalization may also be simultaneously read and selected from signals W[0] to W[6] in addition to signal W[7]. Batch normalization is an operation for adjusting the distribution of output data from each layer in a neural network to a consistent distribution. For example, image data often used in neural network calculations tends to have a variable distribution of data used for training, which may differ from the distribution of predicted data (input data). Batch normalization improves the accuracy of neural network training by normalizing the distribution of input data to the intermediate layer of the neural network to a Gaussian distribution with a mean of 0 and a variance of 1. In a Binary Neural Network (BNN), the output results of each layer are binarized by activation, so by suppressing the bias in data distribution relative to the threshold, it becomes possible to properly activate, that is, to separate information.

[0099] The latch circuit 44 holds the output signal (accout[10:0]) of the accumulator 43. The binary data passed to the next layer (NN layer) in the neural network by batch normalization becomes the most significant bit of the product-sum operation result held by the latch circuit 44. In the output signal (accout[10:0]), the most significant bit signal (accout10) represents the sign of the latched data calculated in two's complement, and is inverted by the inverter circuit 46, which functions as a coding circuit, and output as the output signal Q to pass the positive data as 1 and the negative data as 0 to the next NN layer. Since Q is the output of the intermediate layer, it is temporarily stored in the buffer memory (also called the input buffer) in the accelerator 20 before being used for the calculation of the next layer.

[0100] Figure 14A illustrates a hierarchical neural network based on a binary neural network (BNN) architecture. Figure 14A illustrates a fully connected neural network consisting of neurons 50, one input layer (I1), three hidden layers (M1 to M3), and one output layer (O1). If the number of neurons in the input layer I1 is 786, the number of neurons in the hidden layers M1 to M3 is 256, and the number of neurons in the output layer O1 is 10, then the number of connections in each layer (layer 51, layer 52, layer 53, and layer 54) is (786 x 256) + (256 x 256) + (256 x 256) + (256 x 10), or a total of 334,336. In other words, the weight parameters required for neural network calculations are approximately 330 Kbits in total, providing sufficient memory capacity for implementation even in a small-scale system.

[0101] Next, FIG. 14B shows a detailed block diagram of a semiconductor device 100 capable of performing the neural network calculations shown in FIG. 14A.

[0102] Figure 14B illustrates an example configuration of the peripheral circuits for driving each component illustrated in Figures 1A and 1B, in addition to the arithmetic processing unit 21, the arithmetic circuit 23, the memory circuit layer 22_1 of the memory unit 22, the memory circuit 24, and the wiring 31, which are described in Figures 1A and 1B.

[0103] 14B shows a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, a selector 68, an input buffer 71, and an arithmetic control circuit 72.

[0104] 15A is a diagram illustrating blocks that control the memory circuit layers 22_1 to 22_N of the memory unit 22 in each configuration illustrated in FIG. 14B. In FIG. 15A, a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, and a selector 68 are illustrated.

[0105] The controller 61 processes externally input signals and generates control signals for the row decoder 62 and the column decoder 64. The externally input signals are control signals, such as a write enable signal and a read enable signal, for controlling the memory circuit layers 22_1 to 22_N of the memory unit 22. The controller 61 also inputs and outputs data to be written to the memory circuit layers 22_1 to 22_N of the memory unit 22 or data read from the memory circuit layers 22_1 to 22_N of the memory unit 22, via a bus, to and from the CPU 10.

[0106] The row decoder 62 generates signals for driving the word line driver 63. The word line driver 63 generates signals to be applied to the write word lines WWL and the read word lines RWL. The column decoder 64 generates signals for driving the sense amplifier 67 and the write driver 65. The sense amplifier 67 amplifies the potential of the read bit lines RBL. The write driver generates signals for controlling the read bit lines RBL and the write bit lines WBL. The precharge circuit 66 has the function of precharging the read bit lines RBL and the like. Signals read from the memory circuits 24 of the memory circuit layers 22_1 to 22_N of the memory unit 22 are input to the arithmetic circuit 23 and can also be output via the selector 68. The selector 68 sequentially reads data corresponding to the bus width and can output the required data to the CPU 10 or the like via the controller 61.

[0107] FIG. 15B is a diagram illustrating the blocks that control the arithmetic processing unit 21 extracted from each configuration shown in FIG. 14B.

[0108] The controller 61 processes an external input signal and generates a control signal for the arithmetic control circuit 72. The controller 61 also generates various signals for controlling the arithmetic circuit 23 of the arithmetic processing unit 21. The controller 61 also inputs and outputs data related to the arithmetic results via an input buffer 71. By using this buffer memory, parallel calculations with a number of bits greater than the data bus width of the CPU become possible. Furthermore, the number of times a huge number of weight parameters are transferred between the CPU 10 can be reduced, thereby achieving low power consumption.

[0109] One embodiment of the present invention enables miniaturization of a semiconductor device that functions as an accelerator for AI technology or the like requiring a huge amount of calculation and a large number of parameters. Another embodiment of the present invention enables low power consumption of a semiconductor device that functions as an accelerator for AI technology or the like requiring a huge amount of calculation and a large number of parameters. Another embodiment of the present invention enables suppression of heat generation in a semiconductor device that functions as an accelerator for AI technology or the like requiring a huge amount of calculation and a large number of parameters. Another embodiment of the present invention enables reduction of the number of data transfers between a CPU and a semiconductor device that functions as a memory in a semiconductor device that functions as an accelerator for AI technology or the like requiring a huge amount of calculation and a large number of parameters. In other words, a semiconductor device that functions as an accelerator for AI technology or the like requiring a huge amount of calculation and a large number of parameters has a non-von Neumann architecture, and can perform parallel processing with significantly less power consumption than a von Neumann architecture, which consumes more power as the processing speed increases.

[0110] (Embodiment 2) In this embodiment, an example of operation will be described in which part of the calculations of the program executed by the CPU 10 described in the above embodiment is executed by the accelerator 20.

[0111] FIG. 16 is a diagram illustrating an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0112] The host program is executed by the CPU (step S1).

[0113] When the CPU confirms an instruction to reserve a data area required for performing an operation using the accelerator in the memory unit (step S2), the CPU reserves the data area in the memory unit (step S3). For example, in the first embodiment, the data required for the accelerator 20 to perform an operation in the arithmetic processing unit 21 is reserved in the memory unit 22.

[0114] Next, the CPU transmits input data from the main memory to the memory unit (step S4). The memory unit receives the input data and stores the input data in the area secured in step S2 (step S5).

[0115] When the CPU confirms the instruction to start the kernel program (step S6), the accelerator starts executing the kernel program (step S7).

[0116] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (step S8). In this case, the CPU is switched from the PG state to a state performing calculations immediately before the accelerator finishes executing the kernel program (step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, power consumption and heat generation of the entire semiconductor device can be suppressed.

[0117] When the accelerator finishes executing the kernel program, the output data is stored in the memory unit (step S10).

[0118] After the execution of the kernel program is completed, if the CPU requests an instruction to send the output data stored in the memory unit to the main memory (step S11), the accelerator sends the output data to the main memory, and the output data is stored in the main memory (step S12).

[0119] When the CPU issues a command to release the data area secured on the memory unit (step S13), the data area secured on the memory unit is released (step S14).

[0120] By repeating the above operations from step S1 to step S14, it is possible to suppress the power consumption and heat generation of the CPU and accelerator, while allowing the accelerator to execute part of the calculations of the program executed by the CPU.

[0121] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0122] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0123] 17 shows an example of the configuration of the CPU 10. The CPU 10 has a CPU core 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0124] The CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203 are interconnected by a bus interface unit 205.

[0125] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to externally input interrupt signals (Interrupts) and signals such as the SLEEP1 signal issued by the CPU 10. The clock signal GCLK1 and the PG control signals are input to the CPU 10. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0126] Power switches 210 and 211 respectively control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line). A power switch 212 controls the supply of voltage VDDH to a virtual power line V_VDH (hereinafter referred to as a V_VDH line). A voltage VSSS is input to the CPU 10 and PMU 193 without passing through a power switch. A voltage VDDD is input to the PMU 193 without passing through a power switch.

[0127] The voltages VDDD and VDD1 are drive voltages for the CMOS circuit. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is the drive voltage for the OS transistors and is higher than the voltage VDDD.

[0128] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. Each power domain that can be power-gated has one or more power switches. These power switches are controlled by a PG control signal.

[0129] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0130] 18A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 has a scan flip-flop 221 and a backup circuit 222.

[0131] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0132] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0133] A signal SCE is a scan enable signal and is generated by the PMU 193. The PMU 193 generates signals BK and RC. A level shifter 214 level-shifts the signals BK and RC to generate signals BKH and RCH. The signals BK and RC are a backup signal and a recovery signal.

[0134] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 18A, and any flip-flop available in a standard circuit library can be applied.

[0135] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitor C11.

[0136] The node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0137] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0138] The transistors M11 to M13 are OS transistors, similar to the transistors 25 to 27 included in the memory circuit 24. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0139] At least the transistors M11 and M12 are preferably OS transistors. The OS transistors have an extremely small off-state current, which prevents a voltage drop at the node SN11. Furthermore, the backup circuit 222 consumes almost no power to retain data, making it nonvolatile. Because data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and with low energy consumption.

[0140] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Fig. 18B, the backup circuit 222 can be stacked on a scan flip-flop 221 made up of a silicon CMOS circuit.

[0141] Since the backup circuit 222 has an extremely small number of elements compared to the scan flip-flop 221, stacking the backup circuit 222 does not require changing the circuit configuration and layout of the scan flip-flop 221. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be provided so as to overlap the area where the scan flip-flop 221 is formed, even if the backup circuit 222 is incorporated, the area overhead of the flip-flop 220 can be reduced to zero. Therefore, providing the backup circuit 222 in the flip-flop 220 enables power gating of the CPU core 200. Because little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0142] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0143] For example, a clock gating state, a power gating state, or a sleep state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operating state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0144] For example, when transitioning from a normal operating state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0145] When the CPU core 200 is transitioned from the normal operation state to the power gating state, an operation is performed to back up the data of the scan flip-flop 221 to the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, a recovery operation is performed to write the data of the backup circuit 222 back to the scan flip-flop 221.

[0146] 19 shows an example of a power gating sequence for the CPU core 200. In FIG. 19, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.

[0147] Before time t1, the state is normal operation. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, the level shifter 214 does not need to operate, so the power switch 212 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 221 stores the data of the node D1. In the example of FIG. 19, at time t1, the node SN11 of the backup circuit 222 is "L".

[0148] At operation time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 214 becomes active and outputs the signal BKH at "H" to the backup circuit 222.

[0149] The transistor M11 of the backup circuit 222 turns on, and the data at the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0150] The PMU 193 sets the signals PSE2 and BK to "L" at time t2, and sets the signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 200 transitions to the power gating state. Note that the signal PSE0 may also fall at the same timing as the signal BK falls.

[0151] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at node Q1 is lost. Node SN11 continues to hold the data at node Q1 at time t3.

[0152] The operation during recovery will be explained below. At time t4, the PMU 193 sets the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage on the V_VDD line reaches VDDD (time t5), the PMU 193 sets the signals PSE2, RC, and SCE to "H".

[0153] Transistor M12 turns on, and the charge of capacitive element C11 is distributed between node SN11 and node SD. If node SN11 is "H," the voltage of node SD rises. Since node SE is "H," the data of node SD is written to the input latch circuit of scan flip-flop 221. When clock signal GCLK1 is input to node CK at time t6, the data of the input latch circuit is written to node Q1. In other words, the data of node SN11 has been written to node Q1.

[0154] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0155] The backup circuit 222 using OS transistors is very suitable for normally-off computing because it consumes low power both dynamically and statically. Even if the flip-flop 220 is installed, it can be ensured that there is almost no decrease in performance of the CPU core 200 or an increase in dynamic power consumption.

[0156] The CPU core 200 may have multiple power domains that can be power-gated. Each of the multiple power domains is provided with one or more power switches for controlling voltage input. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power domain in which power gating is not performed may be provided with a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212.

[0157] The application of the flip-flop 220 is not limited to the CPU 10. In a computing device, the flip-flop 220 can be applied to a register provided in a power domain that is capable of power gating.

[0158] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0159] (Fourth embodiment) An example of the semiconductor device according to the above embodiment will be described below with reference to Figures 20 to 25. First, a configuration example of a memory circuit (memory cell) constituting the semiconductor device will be described.

[0160] <Memory circuit configuration example> 20A and 20B show the structure of a memory circuit 860 constituting a semiconductor device according to one embodiment of the present invention. FIG. 20A is a top view of the memory circuit 860 and its periphery. FIG. 20B is a cross-sectional view of the memory circuit 860, corresponding to the portion indicated by the dashed line A1-A2 in FIG. 20A. FIG. 20B shows a cross section of the transistor 600 in the channel length direction and a cross section of the transistor 700 in the channel width direction. Note that some elements are omitted from the top view of FIG. 20A for clarity. Note that the X, Y, and Z directions shown in FIG. 20A are orthogonal or intersect with each other. Here, it is preferable that the X and Y directions are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0161] The memory circuit 860 described in this embodiment includes a transistor 600, a transistor 700, and a capacitor 655. The memory circuit 860 corresponds to the memory circuit 24 described in the above embodiment, and the transistor 600, the transistor 700, and the capacitor 655 correspond to the transistor 25, the transistor 26, and the capacitor 28 described in the above embodiment 1, respectively, and correspond to a 2T NOSRAM in which the transistor 27 is omitted. One of the source and the drain of the transistor 600, the gate of the transistor 700, and one electrode of the capacitor 655 are electrically connected to each other.

[0162] 20A and 20B , in memory circuit 860, transistors 600 and 700 are arranged on insulator 614, insulator 680 is arranged on parts of transistors 600 and 700, insulator 682 is arranged on transistor 600, transistor 700, and insulator 680, insulator 685 is arranged on insulator 682, capacitor 655 is arranged on insulator 685, and insulator 688 is arranged on capacitor 655. Insulator 614, insulator 680, insulator 682, insulator 685, and insulator 688 function as interlayer films.

[0163] Here, transistor 600 includes an insulator 616 on an insulator 614, a conductor 605 (conductor 605a and conductor 605b) disposed so as to be embedded in insulator 616, an insulator 622 on insulator 616 and on conductor 605, an insulator 624 on insulator 622, an oxide 630a on insulator 624, an oxide 630b on oxide 630a, an oxide 643a and an oxide 643b on oxide 630b, a conductor 642a on oxide 643a, and a conductor 642b on oxide 643b. The semiconductor device includes an insulator 672 in contact with a portion of the insulator 624, a side surface of the oxide 630a, a side surface of the oxide 630b, a side surface of the oxide 643a, a side surface of the conductor 642a, a top surface of the conductor 642a, a side surface of the oxide 643b, a side surface of the conductor 642b, and a top surface of the conductor 642b, an insulator 673 on the insulator 672, an oxide 630c on the oxide 630b, an insulator 650 on the oxide 630c, and a conductor 660 (conductor 660a and conductor 660b) located on the insulator 650 and overlapping with the oxide 630c. The oxide 630c also contacts the side surface of the oxide 643a, the side surface of the oxide 643b, the side surface of the conductor 642a, and the side surface of the conductor 642b. 20B, the top surface of the conductor 660 is disposed so as to substantially coincide with the top surfaces of the insulator 650, the oxide 630c, and the insulator 680. The insulator 682 contacts the top surfaces of the conductor 660, the insulator 650, the oxide 630c, and the insulator 680.

[0164] In the following, the oxide 630a, the oxide 630b, and the oxide 630c may be collectively referred to as the oxide 630. The oxide 643a and the oxide 643b may be collectively referred to as the oxide 643. The conductor 642a and the conductor 642b may be collectively referred to as the conductor 642.

[0165] In the transistor 600, the conductor 660 functions as a gate, and the conductors 642a and 642b function as a source and a drain, respectively. The conductor 605 functions as a back gate. The transistor 600 is formed in a self-aligned manner so that the conductor 660 functioning as the gate fills an opening formed by the insulator 680 or the like. As described above, in the semiconductor device according to this embodiment, the conductor 660 can be reliably disposed in the region between the conductors 642a and 642b without alignment.

[0166] The transistor 700 also includes an insulator 616 on an insulator 614, a conductor 705 (conductor 705a and conductor 705b) disposed so as to be embedded in the insulator 616, an insulator 622 on the insulator 616 and on the conductor 705, an insulator 624 on the insulator 622, an oxide 730a on the insulator 624, an oxide 730b on the oxide 730a, an oxide 743a and an oxide 743b on the oxide 730b, a conductor 742a on the oxide 743a, and a conductor 742b on the oxide 743b. The semiconductor device includes an insulator 672 in contact with a portion of the edge 624, a side surface of the oxide 730a, a side surface of the oxide 730b, a side surface of the oxide 743a, a side surface of the conductor 742a, a top surface of the conductor 742a, a side surface of the oxide 743b, a side surface of the conductor 742b, and a top surface of the conductor 742b, an insulator 673 on the insulator 672, an oxide 730c on the oxide 730b, an insulator 750 on the oxide 730c, and a conductor 760 (conductor 760a and conductor 760b) located on the insulator 750 and overlapping with the oxide 730c. The oxide 730c also contacts the side surface of the oxide 743a, the side surface of the oxide 743b, the side surface of the conductor 742a, and the side surface of the conductor 742b. 20B, the top surface of the conductor 760 is positioned so as to be substantially flush with the top surfaces of the insulator 750, the oxide 730c, and the insulator 680. The insulator 682 is in contact with the top surfaces of the conductor 760, the insulator 750, the oxide 730c, and the insulator 680.

[0167] In the following, the oxide 730a, the oxide 730b, and the oxide 730c may be collectively referred to as the oxide 730. The oxide 743a and the oxide 743b may be collectively referred to as the oxide 743. The conductor 742a and the conductor 742b may be collectively referred to as the conductor 742.

[0168] In the transistor 700, the conductor 760 functions as a gate, and the conductors 742a and 742b function as a source and a drain, respectively. The conductor 705 functions as a backgate. The transistor 700 is formed in a self-aligned manner so that the conductor 760 functioning as the gate fills an opening formed by the insulator 680 or the like. As described above, in the semiconductor device of this embodiment, the conductor 760 can be reliably disposed in the region between the conductor 742a and the conductor 742b without alignment.

[0169] Here, the transistor 700 is formed in the same layer as the transistor 600 and has the same structure. Therefore, although a cross section of the transistor 700 in the channel length direction is not shown, the transistor 700 has a structure similar to that of the transistor 600 in the channel length direction shown in FIG. 20B. That is, the oxide 743 and the conductor 742, which are not shown in the cross section, also have structures similar to those of the oxide 643 and the conductor 642 shown in FIG. 20B. Although a cross section of the transistor 600 in the channel width direction is not shown, the transistor 700 has a structure similar to that of the transistor 700 in the channel width direction shown in FIG. 20B.

[0170] Therefore, the oxide 730 has a structure similar to that of the oxide 630, and the description of the oxide 630 can be referred to. The conductor 705 has a structure similar to that of the conductor 605, and the description of the conductor 605 can be referred to. The oxide 743 has a structure similar to that of the oxide 643, and the description of the oxide 643 can be referred to. The conductor 742 has a structure similar to that of the conductor 642, and the description of the conductor 642 can be referred to. The insulator 750 has a structure similar to that of the insulator 650, and the description of the insulator 650 can be referred to. The conductor 760 has a structure similar to that of the conductor 660, and the description of the conductor 660 can be referred to. Hereinafter, unless otherwise specified, the description of the transistor 600 can be referred to for the structure of the transistor 700 as described above.

[0171] Here, in the transistors 600 and 700, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxides 630 and 730, which include regions where channels are formed (hereinafter also referred to as channel formation regions).

[0172] For example, a metal oxide functioning as an oxide semiconductor preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide energy gap, the leakage current (off-state current) of the transistor 600 in an off state can be significantly reduced.

[0173] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) can be used. In particular, element M can be aluminum, gallium, yttrium, or tin. Alternatively, In-M oxide, In-Zn oxide, or M-Zn oxide can be used as the oxide semiconductor.

[0174] The transistors 600 and 700, each of which uses an oxide semiconductor for a channel formation region, have extremely low off-state current, making it possible to provide a semiconductor device with low power consumption. Furthermore, the off-state current of the transistors 600 and 700 hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200° C. Therefore, a semiconductor device with stable operation and high reliability even in a high-temperature environment can be provided.

[0175] Since the off-state current of the transistor 600 is extremely small, the capacitance of the capacitor 655 can be set small. As a result, the area occupied by the memory circuit 860 can be reduced, enabling the integration of semiconductor devices.

[0176] 20A, the conductor 742a, the conductor 660, the conductor 605, and the conductor 705 preferably extend in the Y direction. The conductor 660 functions as the write word line WWL shown in the previous embodiment.

[0177] The capacitor 655 includes a conductor 646a over an insulator 685, an insulator 686 covering the conductor 646a, and a conductor 656 arranged over the insulator 685 to overlap with at least a portion of the conductor 646a. The conductor 646a functions as one electrode of the capacitor 655, and the conductor 646b functions as the other electrode of the capacitor 655. The insulator 686 functions as a dielectric of the capacitor 655.

[0178] Openings are formed in the insulators 622, 624, 672, 673, 680, 682, and 685, and the conductors 640 (conductors 640a, 640b, 640c, and 640d) functioning as plugs are provided so as to be embedded in the openings. The conductors 640 are provided so as to be exposed on the upper surface of the insulator 685.

[0179] The bottom surface of the conductor 640a is in contact with the conductor 642a and the top surface is in contact with the conductor 646a. The bottom surface of the conductor 640c is in contact with the conductor 760 and the top surface is in contact with the conductor 646a. In this manner, one of the source and drain of the transistor 600, the gate of the transistor 700, and one electrode of the capacitor 655 are electrically connected to each other.

[0180] Conductor 640b is provided in contact with the side surface of conductor 642b. Conductor 615 and conductor 607 are provided below conductor 640b, and conductor 646b and conductor 657 are provided above conductor 640b. Conductor 607 is provided in an opening formed in insulator 614. Here, conductor 615 is formed in the same layer as conductor 605 and has the same structure. Conductor 646b is formed in the same layer as conductor 646a and has the same structure. Conductor 657 is provided in an opening formed in insulators 686 and 688.

[0181] The conductor 640b is electrically connected to the conductor 640b of the lower memory circuit 860 by the conductor 607 and the conductor 615. The conductor 640b is also electrically connected to the conductor 640b of the upper memory circuit 860 by the conductor 646b and the conductor 657. In this way, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 extend in the Z direction and function as the write bit line WBL described in the previous embodiment.

[0182] Although not shown in the cross-sectional view, conductor 640d is provided in contact with the side surface of conductor 742b. Conductor 715 is provided below conductor 640d. Conductors having structures similar to conductors 607, 646b, and 657 are provided, and conductor 640d is electrically connected to conductors 640d in the upper and lower layers. Thus, conductor 715, conductor 640d, and the like extend in the Z direction and function as the read bit line RBL described in the previous embodiment.

[0183] 20B, by forming the transistors 600 and 700 in the same layer, the transistors 600 and 700 can be formed in the same process, thereby shortening the process for manufacturing the semiconductor device and improving productivity.

[0184] Note that in the memory circuit 860, the transistor 600, the transistor 700, and the capacitor 655 are provided so that the channel length direction of the transistor 600 and the channel length direction of the transistor 700 are parallel to each other; however, the semiconductor device described in this embodiment is not limited to this. The memory circuit 860 illustrated in FIG. 20 and the like is an example of the configuration of a semiconductor device, and transistors or capacitors having appropriate structures may be arranged as appropriate depending on the circuit configuration and driving method.

[0185] [Detailed memory circuit configuration] The detailed structure of the memory circuit 860 according to one embodiment of the present invention will be described below. In the following description, the description of the components of the transistor 600 can be referred to for the components of the transistor 700.

[0186] 20B , oxide 630 preferably includes oxide 630a on insulator 624, oxide 630b on oxide 630a, and oxide 630c disposed on oxide 630b and at least a portion of which is in contact with the top surface of oxide 630b. Here, the side surfaces of oxide 630c are preferably in contact with oxide 643a, oxide 643b, conductor 642a, conductor 642b, insulator 672, insulator 673, and insulator 680.

[0187] That is, the oxide 630 includes an oxide 630a, an oxide 630b on the oxide 630a, and an oxide 630c on the oxide 630b. By providing the oxide 630a below the oxide 630b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 630a to the oxide 630b. Furthermore, by providing the oxide 630c on the oxide 630b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 630c to the oxide 630b.

[0188] Although the transistor 600 has a three-layer structure of oxide 630a, oxide 630b, and oxide 630c in the channel formation region and its vicinity, the present invention is not limited to this structure. For example, the present invention may have a single layer of oxide 630b, a two-layer structure of oxide 630b and oxide 630a, a two-layer structure of oxide 630b and oxide 630c, or a stacked structure of four or more layers. For example, the oxide 630c may have a two-layer structure, and a four-layer stacked structure may be formed.

[0189] The oxide 630 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M among the constituent elements of the metal oxide used for the oxide 630a is preferably greater than the atomic ratio of the element M among the constituent elements of the metal oxide used for the oxide 630b. The atomic ratio of the element M to In among the constituent elements of the metal oxide used for the oxide 630a is preferably greater than the atomic ratio of the element M to In among the constituent elements of the metal oxide used for the oxide 630b. The atomic ratio of In among the element M to In among the metal oxide used for the oxide 630b is preferably greater than the atomic ratio of In among the element M to In among the metal oxide used for the oxide 630a. The oxide 630c can be the same metal oxide as that used for the oxide 630a or the oxide 630b. The atomic ratio of In among the element M to In among the constituent elements of the metal oxide used for the oxide 630c may be greater than the atomic ratio of In among the element M to In among the metal oxide used for the oxide 630b.

[0190] Specifically, the oxide 630a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto, or an atomic ratio of 1:1:0.5 or a composition close thereto.

[0191] Alternatively, the oxide 630b may be a metal oxide having an In:Ga:Zn=4:2:3 atomic ratio or a similar composition, or an In:Ga:Zn=1:1:1 atomic ratio or a similar composition. Alternatively, the oxide 630b may be a metal oxide having an In:Ga:Zn=5:1:3 atomic ratio or a similar composition, or an In:Ga:Zn=10:1:3 atomic ratio or a similar composition. Alternatively, the oxide 630b may be an In-Zn oxide (e.g., an In:Zn=2:1 atomic ratio or a similar composition, an In:Zn=5:1 atomic ratio or a similar composition, or an In:Zn=10:1 atomic ratio or a similar composition). Alternatively, the oxide 630b may be an In oxide.

[0192] The oxide 630c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto, an atomic ratio of Ga:Zn=2:1 or a composition close thereto, or an atomic ratio of Ga:Zn=2:5 or a composition close thereto. The oxide 630c may be formed as a single layer or a multilayer using a material that can be used for the oxide 630b. For example, specific examples of the oxide 630c having a layered structure include a layered structure of an In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto and an In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, a layered structure of a Ga:Zn=2:1 [atomic ratio] or a composition close thereto and an In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, a layered structure of a Ga:Zn=2:5 [atomic ratio] or a composition close thereto and an In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and a layered structure of gallium oxide and an In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto.

[0193] In addition, increasing the ratio of indium in the oxides 630b and 630c is preferable because it can increase the on-state current, field-effect mobility, etc. of the transistor. The aforementioned "nearby" composition includes a range of ±30% of the desired atomic ratio.

[0194] The composition of elements contained in the metal oxide may be changed depending on the operating frequency required for the transistor. For example, in a transistor included in a memory circuit, the metal oxide may have a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a similar ratio, while in other transistors, the metal oxide may have a composition of In:Ga:Zn=5:1:3 [atomic ratio] or a similar ratio. Note that in other transistors, the metal oxide may have a composition of In:Ga:Zn=10:1:3 [atomic ratio] or a similar ratio, or In:Zn=2:1 [atomic ratio] or a similar ratio.

[0195] The oxide 630b may be crystalline. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), have high crystallinity, and have a dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 630b. Furthermore, even when heat treatment is performed, the transistor 600 is stable against high temperatures (so-called thermal budget) in the manufacturing process because extraction of oxygen from the oxide 630b can be reduced.

[0196] The oxide 630c is preferably provided in an opening in an interlayer film including the insulator 680. Therefore, the insulator 650 and the conductor 660 have a region overlapping with the stacked structure of the oxide 630b and the oxide 630a via the oxide 630c. This structure enables the oxide 630c and the insulator 650 to be formed by successive film formation, thereby keeping the interface between the oxide 630 and the insulator 650 clean. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 600 can achieve high on-state current and high frequency characteristics.

[0197] An oxide semiconductor with a low carrier concentration is preferably used for the oxide 630 (for example, the oxide 630b). The carrier concentration of an oxide semiconductor can be reduced by reducing the impurity concentration in the oxide semiconductor and reducing the density of defect states. In this specification and the like, a semiconductor with a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0198] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water, which creates oxygen vacancies (V O Furthermore, defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) functions as a donor and can generate electrons as carriers. In addition, some hydrogen atoms can bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stresses such as heat and an electric field, and therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0199] V OH can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as the "donor concentration."

[0200] From the above, when an oxide semiconductor is used for the oxide 630, V in the oxide 630 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygen addition treatment). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0201] For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) of oxide 630b is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using the oxide 630 in which impurities such as hydrogen are sufficiently reduced for the channel formation region of the transistor 600, the transistor 600 can have normally-off characteristics, stable electrical characteristics, and improved reliability.

[0202] When an oxide semiconductor is used for the oxide 630, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited. -9 cm -3 It can be said that:

[0203] Therefore, it is preferable to use a material that suppresses impurity diffusion (hereinafter also referred to as a barrier material for impurities) as the insulators 614, 622, 672, 673, and 682 to reduce the diffusion of impurities such as hydrogen into the oxide 630. Note that in this specification and the like, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability). Alternatively, it refers to a function of capturing and fixing (also referred to as gettering) a corresponding substance. Note that in this specification and the like, an insulating film having barrier properties may be referred to as a "barrier insulating film."

[0204] For example, materials that have the function of suppressing the diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. In particular, silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, and is therefore preferably used as a sealing material.

[0205] Furthermore, for example, materials having the function of capturing and fixing hydrogen include metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

[0206] For example, aluminum oxide, hafnium oxide, or the like is preferably used for the insulator 614. This can prevent impurities such as water or hydrogen from diffusing from the substrate to the transistor 600. Alternatively, it can prevent oxygen contained in the insulator 624 or the like from diffusing to the substrate.

[0207] The conductor 605 is disposed so as to overlap the oxide 630 and the conductor 660. The conductor 605 is preferably embedded in the insulator 616.

[0208] When the conductor 605 functions as a gate electrode, the threshold voltage (Vth) of the transistor 600 can be controlled by changing the potential applied to the conductor 605 independently of the potential applied to the conductor 660. In particular, applying a negative potential to the conductor 605 can increase the Vth of the transistor 600 and reduce the off-state current. Therefore, applying a negative potential to the conductor 605 can reduce the drain current when the potential applied to the conductor 660 is 0 V compared to not applying a negative potential to the conductor 605.

[0209] Note that the conductor 605 is preferably larger than a region of the oxide 630 that does not overlap with the conductors 642a and 642b, as shown in FIG. 20A . In particular, as shown in FIG. 20B , the conductor 605 preferably extends to a region outside the end of the oxide 630 that intersects with the channel width direction. That is, outside the side surface of the oxide 630 in the channel width direction, the conductor 605 and the conductor 660 preferably overlap with each other through an insulator. Alternatively, providing a large conductor 605 may reduce local charging (referred to as charge-up) in plasma treatment in manufacturing steps after the formation of the conductor 605. However, one embodiment of the present invention is not limited thereto. The conductor 605 may overlap at least the oxide 630 located between the conductors 642a and 642b.

[0210] Furthermore, it is preferable that, with respect to the bottom surface of insulator 624, the height of the bottom surface of conductor 660 in the region where oxide 630a and oxide 630b do not overlap with conductor 660 is positioned at a lower position than the height of the bottom surface of oxide 630b.

[0211] 20B, the conductor 660 functioning as a gate covers the side and top surfaces of the oxide 630b in the channel formation region via the oxide 630c and the insulator 650. This allows the electric field generated by the conductor 660 to be applied to the entire channel formation region in the oxide 630b. This increases the on-state current of the transistor 600 and improves its frequency characteristics. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the gate (first gate) and the back gate (second gate) is referred to as a surrounded channel (S-channel) structure.

[0212] The conductor 605a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. The conductor 605b is preferably a conductive material containing tungsten, copper, or aluminum as a main component. While the conductor 605 is illustrated as having two layers, it may also have a multi-layer structure of three or more layers.

[0213] The insulators 616, 680, 685, and 688 preferably have a lower dielectric constant than the insulator 614. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 616, 680, 685, and 688 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like as appropriate.

[0214] Furthermore, the insulators 616, 680, 685, and 688 may be formed by a CVD method or an ALD method using a compound gas that does not contain hydrogen atoms or that contains a small amount of hydrogen atoms. The CVD method may be either a thermal CVD method or a PECVD (Plasma Enhanced CVD). The ALD method may be either a thermal ALD method or a PEALD (Plasma Enhanced ALD). However, film formation methods that use plasma, such as PECVD and PEALD, are preferred because they are more suitable for mass production.

[0215] In the formation of the insulating film, a gas having molecules containing silicon atoms is mainly used as the film formation gas. In order to reduce the hydrogen contained in the insulating film, it is preferable that the molecules containing silicon atoms contain fewer hydrogen atoms, and it is more preferable that the molecules containing silicon atoms do not contain hydrogen atoms. Of course, it is also preferable that film formation gases other than the gas having molecules containing silicon atoms contain fewer hydrogen atoms, and it is more preferable that they do not contain hydrogen atoms.

[0216] The molecules containing silicon atoms as shown above are called Si x -R y In this example, the functional group R can be at least one of an isocyanate group (-N=C=O), a cyanate group (-OC≡N), a cyano group (-C≡N), a diazo group (=N2), an azide group (-N3), a nitroso group (-NO), and a nitro group (-NO2). For example, 1≦x≦3 and 1≦y≦8 may be satisfied. Examples of such molecules containing silicon atoms include tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, and octaisocyanate silane. While molecules in which the same type of functional group is bonded to the silicon atom have been exemplified here, the present embodiment is not limited to this. Different types of functional groups may also be bonded to the silicon atom.

[0217] Furthermore, for example, a halogen (Cl, Br, I, or F) may be used as the functional group R. For example, 1≦x≦2 and 1≦y≦6 may be satisfied. Examples of molecules containing silicon atoms include tetrachlorosilane (SiCl4) and hexachlorodisilane (Si2Cl6). Although an example in which chlorine is used as the functional group has been shown, halogens other than chlorine, such as bromine, iodine, and fluorine, may also be used as the functional group. Also, a different type of halogen may be bonded to the silicon atom.

[0218] The insulator 622 and the insulator 624 function as gate insulators.

[0219] Here, the insulator 624 in contact with the oxide 630 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 624 can be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced, and the reliability of the transistor 600 can be improved.

[0220] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 624. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0221] The insulator 622 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 600 from the substrate side. For example, the insulator 622 preferably has lower hydrogen permeability than the insulator 624. By surrounding the insulator 624 and the oxide 630 with the insulator 622 and the insulator 683, impurities such as water or hydrogen can be prevented from entering the transistor 600 from the outside.

[0222] Furthermore, the insulator 622 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate). For example, the insulator 622 preferably has lower oxygen permeability than the insulator 624. The insulator 622 is preferable because it has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the oxide 630 below the insulator 622. Furthermore, the conductor 605 can be prevented from reacting with oxygen contained in the insulator 624 or the oxide 630.

[0223] The insulator 622 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 622 is formed using such a material, the insulator 622 functions as a layer that prevents oxygen from being released from the oxide 630 and prevents impurities, such as hydrogen, from entering the oxide 630 from the periphery of the transistor 600.

[0224] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0225] The insulator 622 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0226] The insulator 622 and the insulator 624 may have a stacked structure of two or more layers. In this case, the insulators are not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0227] Alternatively, the oxide 643 (oxide 643a and oxide 643b) may be disposed between the oxide 630b and the conductor 642 (conductor 642a and conductor 642b) functioning as a source electrode or a drain electrode. This prevents the conductor 642 from contacting the oxide 630, thereby preventing the conductor 642 from absorbing oxygen from the oxide 630. In other words, preventing the conductor 642 from being oxidized can suppress a decrease in the conductivity of the conductor 642. Therefore, the oxide 643 preferably has a function of suppressing the oxidation of the conductor 642.

[0228] Therefore, the oxide 643 preferably has a function of suppressing oxygen permeation. By disposing the oxide 643, which has a function of suppressing oxygen permeation, between the conductor 642 functioning as a source electrode or a drain electrode and the oxide 630b, the electrical resistance between the conductor 642 and the oxide 630b can be reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 600 can be improved.

[0229] A metal oxide containing element M may be used as oxide 643. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 643 has a higher concentration of element M than oxide 630b. Alternatively, oxide 643 may be gallium oxide. Alternatively, oxide 643 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 643 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 630b. Furthermore, the film thickness of oxide 643 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm. Furthermore, oxide 643 preferably has crystallinity. When oxide 643 has crystallinity, oxygen release from oxide 630 can be effectively suppressed. For example, oxide 643 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 630.

[0230] Note that the oxide 643 is not necessarily provided. In this case, when the conductor 642 (conductor 642a and conductor 642b) comes into contact with the oxide 630, oxygen in the oxide 630 may diffuse into the conductor 642, causing the conductor 642 to be oxidized. The oxidation of the conductor 642 is likely to result in a decrease in the conductivity of the conductor 642. Note that the diffusion of oxygen in the oxide 630 into the conductor 642 can be rephrased as the conductor 642 absorbing the oxygen in the oxide 630.

[0231] Furthermore, oxygen in the oxide 630 diffuses into the conductor 642 (conductor 642a and conductor 642b), which may form a heterogeneous layer between the conductor 642a and the oxide 630b and between the conductor 642b and the oxide 630b. Since the heterogeneous layer contains more oxygen than the conductor 642, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 642, the heterogeneous layer, and the oxide 630b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0232] It should be noted that the above-mentioned different layer is not limited to being formed between the conductor 642 and the oxide 630b, but may be formed, for example, between the conductor 642 and the oxide 630c, between the conductor 642 and the oxide 630b, and between the conductor 642 and the oxide 630c.

[0233] A conductor 642 (a conductor 642a and a conductor 642b) functioning as a source electrode and a drain electrode is provided over the oxide 643. The thickness of the conductor 642 is, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.

[0234] The conductor 642 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing the above metal elements or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferred. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are also preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0235] The insulator 672 is preferably provided in contact with the top surface of the conductor 642 and functions as a barrier insulating film. Furthermore, an insulator 673 functioning as a barrier insulating film is preferably provided over the insulator 672. This structure can prevent the conductor 642 from absorbing excess oxygen contained in the insulator 680. Furthermore, suppressing oxidation of the conductor 642 can prevent an increase in contact resistance between the transistor 600 and a wiring. Therefore, the transistor 600 can have good electrical characteristics and reliability.

[0236] Therefore, the insulators 672 and 673 preferably have a function of suppressing oxygen diffusion. For example, the insulator 672 preferably has a function of suppressing oxygen diffusion more than the insulator 680. The insulator 672 may be formed using, for example, an insulator containing an oxide of one or both of aluminum and hafnium. The insulator 673 may be formed using, for example, silicon nitride or silicon nitride oxide.

[0237] Furthermore, it is possible to prevent impurities such as water or hydrogen from diffusing from the insulator 680 or the like disposed between the insulators 672 and 673 toward the transistor 600. In this manner, it is preferable to have a structure in which the transistor 600 is surrounded by the insulators 672 and 673, which have the function of preventing diffusion of impurities such as water or hydrogen and oxygen.

[0238] The insulator 650 functions as a gate insulator. The insulator 650 is preferably disposed in contact with the upper surface of the oxide 630c. The insulator 650 can be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable.

[0239] Like the insulator 624, the insulator 650 is preferably formed using an insulator that releases oxygen when heated. By providing the insulator 650 in contact with the top surface of the oxide 630c, oxygen can be effectively supplied to the channel formation region of the oxide 630b. Similarly to the insulator 624, the concentration of impurities such as water or hydrogen in the insulator 650 is preferably reduced. The thickness of the insulator 650 is preferably 1 nm or more and 20 nm or less.

[0240] Furthermore, a metal oxide may be provided between the insulator 650 and the conductor 660. The metal oxide preferably suppresses oxygen diffusion from the insulator 650 to the conductor 660. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 650 to the conductor 660 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 630 can be suppressed. Furthermore, oxidation of the conductor 660 by oxygen from the insulator 650 can be suppressed.

[0241] Furthermore, the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 650, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator with a stacked structure of the insulator 650 and the metal oxide, it is possible to achieve a stacked structure that is thermally stable and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0242] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0243] Alternatively, the metal oxide may function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0244] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as a gate. Alternatively, the conductive material containing the metal element and nitrogen described above may be used. Also, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0245] The conductor 660 is disposed so that its bottom and side surfaces are in contact with the insulator 650. Although the conductor 660 is shown as having a two-layer structure in Fig. 20B, it may have a single-layer structure or a laminated structure of three or more layers.

[0246] The conductor 660a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0247] Furthermore, since the conductor 660a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 660b caused by oxygen contained in the insulator 650. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0248] The conductor 660b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 660 also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 660b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0249] The insulator 680 is preferably made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. The insulator 680 may also have a stacked structure of the above materials, such as a stacked structure of silicon oxide formed by sputtering and a silicon oxynitride film formed by CVD. Silicon nitride may also be stacked on top of this.

[0250] Here, the insulator 680 preferably contains excess oxygen. For example, the insulator 680 can be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing the insulator 680 containing excess oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced, thereby improving the reliability of the transistor 600. To make the insulator 680 contain excess oxygen, for example, the insulator 682 can be deposited by sputtering in an oxygen-containing atmosphere. By depositing the insulator 682 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulator 680 during deposition.

[0251] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 680. The top surface of the insulator 680 may be planarized.

[0252] The insulator 682 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 680 from above. The insulator 682 also preferably functions as a barrier insulating film that prevents oxygen from passing through. The insulator 682 can be, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 682 can be made of aluminum oxide, which has a high barrier property against oxygen.

[0253] 20B, the insulator 682 is in direct contact with the oxide 630c. This structure can suppress diffusion of oxygen contained in the insulator 680 to the conductor 660. Therefore, oxygen contained in the insulator 680 can be efficiently supplied to the oxides 630a and 630b through the oxide 630c, thereby reducing oxygen vacancies in the oxides 630a and 630b and improving the electrical characteristics and reliability of the transistor 600.

[0254] An insulator 685 functioning as an interlayer film is preferably provided over the insulator 682. Like the insulator 624, the insulator 685 preferably has a reduced concentration of impurities such as water or hydrogen.

[0255] The conductor 640 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 640 may also have a layered structure. Note that, although the conductor 640 in FIG. 20A has a circular shape when viewed from above, this is not limiting. For example, the conductor 640 may have a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above.

[0256] Furthermore, when the conductor 640 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen, may be used in a single layer or a layered structure. By using such a conductive material, it is possible to further reduce the intrusion of impurities such as water or hydrogen that diffuse from the insulator 680 into the oxide 630 through the conductor 640. It is also possible to prevent oxygen added to the insulator 680 from being absorbed by the conductor 640.

[0257] Conductor 646a is disposed in contact with the upper surface of conductor 640a and the upper surface of conductor 640c, and conductor 646b is disposed in contact with the upper surface of conductor 640b. Conductor 646a and conductor 646b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Conductor 646a and conductor 646b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0258] An insulator 686 is provided to cover the insulator 685, the conductor 646a, and the conductor 646b. The insulator 686 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or zirconium oxide, and can be formed as a stacked layer or a single layer.

[0259] For example, a stacked structure of a high dielectric strength material such as silicon oxynitride and a high dielectric constant (high-k) material may be used for the insulator 686. With this structure, the capacitor 655 can ensure sufficient capacitance by having an insulator with a high dielectric constant (high-k), and the insulator with a high dielectric strength improves the dielectric strength, thereby preventing electrostatic breakdown of the capacitor 655.

[0260] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0261] Alternatively, the insulator 686 may be a single layer or a stack of insulators containing high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). For example, when the insulator 686 is a stack, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially formed may be used, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are sequentially formed may be used. Furthermore, the insulator 686 may be a compound containing hafnium and zirconium. As semiconductor devices become more miniaturized and highly integrated, thinning of the dielectrics used in gate insulators and capacitors may cause problems such as leakage current in transistors and capacitors. By using high-k materials for the gate insulator and the insulator that functions as the dielectric used in the capacitor element, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor element while maintaining the physical film thickness.

[0262] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0263] The conductor 656 is arranged to overlap with at least part of the conductor 646a with the insulator 686 interposed therebetween. The conductor 656 may be any conductor that can be used for the conductor 646.

[0264] It is also preferable to provide an insulator 688 functioning as an interlayer film over the insulator 686 and the conductor 646b. Like the insulator 624, the insulator 688 preferably has a reduced concentration of impurities such as water or hydrogen.

[0265] <<Modification of memory circuit>> Below, a modified example of a memory circuit will be described using Figures 21A and 21B. Figure 21A is a top view of the periphery of a memory circuit 860. Figure 21B is a cross-sectional view of the memory circuit 860, and Figure 21B corresponds to the portion indicated by the dashed line A1-A2 in Figure 21A. Figure 21B shows a cross-section of a transistor 600 in the channel length direction and a cross-section of a transistor 700 in the channel width direction. Note that some elements are omitted from the top view of Figure 21A for clarity. Note that the X direction, Y direction, and Z direction shown in Figure 21A are directions that are orthogonal to or intersect each other. Here, it is preferable that the X direction and Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0266] 21A and 21B differs from the memory circuit 860 shown in FIGS. 20A and 20B in that transistors 690 and 790 are used instead of transistors 600 and 700. Here, transistor 790 is formed in the same layer as transistor 690 and has a similar configuration. Hereinafter, the components of transistor 790 can be determined by referring to the description of the components of transistor 690.

[0267] Transistor 690 differs from transistor 600 in that oxide 630c is formed in a U-shape to fit along openings formed in insulator 680, insulator 672, insulator 673, conductor 642 (conductor 642a, conductor 642b), and oxide 630b.

[0268] For example, when the channel length of the transistor is miniaturized (typically, 5 nm or more and less than 60 nm, preferably 10 nm or more and 30 nm or less), the effective L length can be increased by having the transistor 600 have the above structure. As an example, when the distance between the conductor 642a and the conductor 642b is 20 nm, the effective L length can be increased to 40 nm or more and 60 nm or less, which is approximately two to three times longer than the distance between the conductor 642a and the conductor 642b, i.e., the minimum processing dimension. Therefore, the memory circuit 860 shown in FIGS. 21A and 21B has a structure including the transistor 690, the transistor 790, and the capacitor 655, which are suitable for miniaturization.

[0269] <<Metal oxides>> A metal oxide that functions as an oxide semiconductor is preferably used as the oxide 630. Metal oxides that can be used as the oxide 630 according to the present invention will be described below.

[0270] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0271] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0272] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0273] [Metal oxide composition] Here, as an example of a metal oxide configuration, a cloud-aligned composite oxide semiconductor (CAC-OS) or a CAC-metal oxide will be described.

[0274] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0275] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0276] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0277] Furthermore, the CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0278] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0279] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0280] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure of oxide semiconductors will be explained using FIG. 26A. FIG. 26A is a diagram explaining the classification of the crystal structure of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0281] As shown in Figure 26A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes CAAC, nc, and CAC. Crystal includes single crystal and polycrystal.

[0282] The structure enclosed in the bold frame in Figure 26A belongs to the new crystalline phase. This structure is located in the boundary region between amorphous and crystalline. In other words, this structure is completely different from the energetically unstable amorphous and crystalline phases.

[0283] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) images. Figures 26B and 26C show the XRD spectra of silica glass and IGZO (also called crystalline IGZO), which has a crystal structure classified as Crystalline. Figure 26B shows the XRD spectrum of silica glass, and Figure 26C shows the XRD spectrum of crystalline IGZO. The crystalline IGZO shown in Figure 26C has a composition of In:Ga:Zn=4:2:3 [atomic ratio]. The crystalline IGZO shown in Figure 26C has a thickness of 500 nm.

[0284] As shown by the arrows in Figure 26B, the peaks in the XRD spectrum of silica glass are nearly symmetrical. On the other hand, as shown by the arrows in Figure 26C, the peaks in the XRD spectrum of crystalline IGZO are asymmetrical. The asymmetric peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, it cannot be said to be amorphous.

[0285] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0286] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS can be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0287] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current or field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0288] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0289] CAAC-OS is a metal oxide with high crystallinity. Because it is difficult to identify clear grain boundaries in CAAC-OS, it is unlikely that the electron mobility will decrease due to grain boundaries. Furthermore, because the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0290] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0291] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0292] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0293] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0294] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0295] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics.

[0296] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0297] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0298] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in and around a channel formation region of an oxide semiconductor, such as hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0299] Specifically, the concentration of the impurities measured by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, as determined by elemental analysis using EDX, is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0300] Furthermore, metal oxides with reduced impurity concentrations have a low defect state density, and therefore may also have a low trap state density.

[0301] In addition, when hydrogen enters an oxygen vacancy in a metal oxide, the oxygen vacancy and hydrogen bond to form V O May form H. V O H acts as a donor and can generate carrier electrons. Also, some of the hydrogen can bond with oxygen that bonds with metal atoms, generating carrier electrons.

[0302] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, the reliability of the transistor may be reduced if the oxide semiconductor contains a large amount of hydrogen.

[0303] That is, V in metal oxides O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygen addition treatment). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0304] In addition, it is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. To reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as being highly pure intrinsic or substantially highly pure intrinsic. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0305] In particular, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons, which serve as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0306] A defect where hydrogen has entered an oxygen vacancy (V O H) can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0307] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0308] The carrier concentration of the oxide semiconductor in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0309] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0310] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 630 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 630. For example, a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material) is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0311] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0312] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0313] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 630. Specific examples of transition metal chalcogenides that can be used as the oxide 630 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0314] <Memory circuit layout example> Next, an example of the arrangement of the memory circuit 860 will be described with reference to FIGS. 22 and 23. FIGS. 22 and 23 show a memory circuit block in which the memory circuits 860 are arranged in a 2×2×2 array. FIG. 22 is a top view of the memory circuit block. FIG. 23 is a cross-sectional view of the memory circuit block, corresponding to the portion indicated by the dashed line B1-B2 in FIG. 22. FIG. 23 shows a cross section of the transistor 600 in the channel length direction and a cross section of the transistor 700 in the channel width direction. Note that some elements are omitted from the top view of FIG. 22 for clarity. The X, Y, and Z directions shown in FIG. 22 are orthogonal or intersect with each other. Preferably, the X and Y directions are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0315] 22 and 23, a memory circuit 860_2 is arranged adjacent to memory circuit 860_1 in the X direction. Furthermore, memory circuits 860_3 and 860_4 are arranged adjacent to memory circuits 860_1 and 860_2 in the Y direction. Furthermore, memory circuits 860_5 and 860_6 are arranged adjacent to memory circuits 860_1 and 860_2 in the Z direction.

[0316] As shown in FIGS. 22 and 23, the components of the memory circuits 860_1 and 860_2 can be arranged symmetrically. In this case, it is preferable that the side of the conductor 640b contacts the conductor 642b of the memory circuit 860_1 and the conductor 642b of the memory circuit 860_2. In other words, it is preferable that the conductors 607, 615, 640b, 646b, and 657, which function as the bit line WBL, are electrically connected to one of the source and drain of the transistor 600 of the memory circuit 860_1 and one of the source and drain of the transistor 600 of the memory circuit 860_2. In this way, by sharing the wiring connected to the memory circuits 860_1 and 860_2, the area occupied by the memory circuits can be further reduced.

[0317] 23, the conductors 607, 615, 640b, 646b, and 657 functioning as the write bit lines WBL are also electrically connected to the transistors 600 of the memory circuits 860_5 and 860_6 arranged in the upper layer. As shown in FIG. 23, the conductors 657 of the memory circuits 860_1 and 860_2 correspond to the conductors 607 of the memory circuits 860_5 and 860_6. In this manner, the bit lines WBL can be extended in the Z direction. Although not shown in the cross-sectional view, the conductors 640d and the like functioning as the read bit lines RBL can also be extended in the Z direction.

[0318] 22, the conductor 660 of the memory circuit 860_1 is provided so as to extend into the memory circuit 860_3. In this manner, the word line WWL can be extended in the Y direction. Also, as shown in FIG. 22, the conductor 742a of the memory circuit 860_1 is provided so as to extend into the memory circuit 860_3. In this manner, the selection line SL can be extended in the Y direction. The selection line SL may be shared with a memory circuit 860 adjacent in the X direction. Also, as shown in FIG. 22, the conductor 605 of the memory circuit 860_1 is provided so as to extend into the memory circuit 860_3. In this manner, the wiring BGL1 can be extended in the Y direction. Also, as shown in FIG. 22, the conductor 705 of the memory circuit 860_1 is provided so as to extend into the memory circuit 860_3. In this manner, the wiring BGL1 can be extended in the Y direction.

[0319] 22 shows a structure in which the oxide 630c extends to overlap the conductor 660; however, the semiconductor device described in this embodiment is not limited to this. For example, the oxide 630c may be patterned for each memory circuit 860, and the oxide 630c may be provided separately for each transistor 600. Furthermore, for example, when the oxide 630c has a two-layer stacked structure, either the upper layer or the lower layer of the oxide 630c may be provided separately for each transistor 600.

[0320] <Configuration example of semiconductor device> Next, an example of a semiconductor device in which the above-mentioned memory circuits 860 are stacked will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view of a semiconductor device in which a plurality of memory circuit layers 870, each including a memory circuit 860, are stacked on a silicon layer 871. The semiconductor device shown in Fig. 24 corresponds to the accelerator 20 shown in Fig. 1 etc., with the silicon layer 871 corresponding to the arithmetic processing unit 21 and the memory circuit layer 870 corresponding to the memory unit 22.

[0321] First, a description will be given of the silicon layer 871. A plurality of transistors 800 are provided in the silicon layer 871, and form the arithmetic circuit 23 shown in FIG.

[0322] The transistor 800 is provided over a substrate 811 and includes a conductor 816 functioning as a gate, an insulator 815 functioning as a gate insulator, a semiconductor region 813 formed of part of the substrate 811, and low-resistance regions 814a and 814b functioning as source and drain regions. The transistor 800 may be either a p-channel type or an n-channel type.

[0323] Here, in the transistor 800 shown in FIG. 24, a semiconductor region 813 (a part of a substrate 811) where a channel is formed has a convex shape. In addition, a conductor 816 is provided to cover the side and top surfaces of the semiconductor region 813 with an insulator 815 interposed therebetween. Note that the conductor 816 may be made of a material that adjusts the work function. Such a transistor 800 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator that functions as a mask for forming the convex portion may be provided in contact with the top of the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0324] Note that the transistor 800 shown in FIG. 24 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0325] Furthermore, a wiring layer having an interlayer film, wiring, plugs, etc., may be provided between each structure. A plurality of wiring layers may be provided depending on the design. Here, a conductor having the function of a plug or wiring may have a plurality of structures collectively assigned the same reference numeral. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be integrated. That is, a portion of the conductor may function as a wiring, and a portion of the conductor may function as a plug.

[0326] For example, an insulator 820, an insulator 822, an insulator 824, and an insulator 826 are stacked in this order as an interlayer film over the transistor 800. A conductor 828, a conductor 830, and the like which function as a plug or a wiring are embedded in the insulator 820, the insulator 822, the insulator 824, and the insulator 826.

[0327] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 822 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0328] A wiring layer may be provided over the insulator 826 and the conductor 830. For example, in FIG. 24, an insulator 850, an insulator 852, and an insulator 854 are stacked in this order. A conductor 856 is formed in the insulator 850, the insulator 852, and the insulator 854. The conductor 856 functions as a plug or a wiring.

[0329] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0330] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0331] For example, insulators 820, 822, 826, 852, and 854 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having pores, or a resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having pores, and a resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore, by combining them with a resin, a thermally stable layered structure with a low dielectric constant can be achieved. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0332] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 824, 850, and the like can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0333] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0334] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0335] For example, the conductors 828, 830, and 856 can be formed using a single layer or a stack of conductive materials such as metals, alloys, metal nitrides, or metal oxides, which are formed using the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce wiring resistance.

[0336] An insulator 611 and an insulator 612 are disposed over the silicon layer 871, and memory circuit layers 870_1 to 870_n are stacked over the insulators 611 and 612. Note that the value of n is not particularly limited, but is 2 to 200, preferably 2 to 100, and more preferably 2 to 10. For example, 1≦n≦10, preferably 1≦n≦50, and more preferably 1≦n≦100.

[0337] In each memory circuit layer 870, memory circuits 860 and various wirings are arranged in a matrix, similar to Fig. 22. Furthermore, each memory circuit layer 870 adjacent to each other in the stacking direction is electrically connected by wirings such as write bit lines WBL, as shown in Fig. 23.

[0338] 24, in the lowest memory circuit layer 870_1, a conductor 607 is arranged so as to be embedded in an insulator 611 and an insulator 612. The conductor 607 is in contact with a conductor 857 provided in the same layer as the conductor 856.

[0339] Furthermore, the memory circuit layers 870_1 to 870_n preferably have a structure sealed with an insulator 611, an insulator 612, an insulator 687, an insulator 683, and an insulator 684. Here, the insulator 611 is disposed on the silicon layer 871, and the insulator 612 is disposed on the insulator 611. The memory circuit layers 870_1 to 870_n are disposed on the insulator 612, and the insulator 612 is also formed in the same pattern as the memory circuit layers 870_1 to 870_n in a top view. The insulator 687 is disposed in contact with the top surface of the insulator 611, the side surface of the insulator 612, and the side surface of the memory circuit layers 870_1 to 870_n. That is, the insulator 687 is formed in a sidewall shape with respect to the memory circuit layers 870_1 to 870_n. An insulator 683 is disposed to cover the insulator 611, the insulator 687, and the memory circuit layers 870_1 to 870_n.

[0340] Like insulator 682, insulators 611, 612, 687, 683, and 684 are preferably made of a barrier material.

[0341] Here, each memory circuit layer 870 is sealed by an insulator 687 and an insulator 683. It is preferable to use the same material for the insulator 687 and the insulator 683. It is also preferable to form the insulator 687 and the insulator 683 under the same conditions. When the insulator 687 and the insulator 683, which have the same film quality, are in contact with each other, a sealed structure with high airtightness can be achieved.

[0342] A material capable of capturing and fixing hydrogen is preferably used for the insulators 687 and 683. Specifically, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used.

[0343] Furthermore, the insulators 687 and 683 that are structures that seal the memory circuit layer 870 are further covered with an insulator 684 .

[0344] A material having a function of suppressing diffusion of hydrogen and oxygen is preferably used for the insulators 611, 612, and 683. In particular, silicon nitride or silicon nitride oxide is preferably used as a sealing material because it has high barrier properties against hydrogen.

[0345] An insulator 684 with high coverage is preferably provided above the insulator 683 that covers the upper side of the transistor 600. Note that the insulator 684 is preferably made of the same material as the insulators 612 and 683.

[0346] For example, the insulators 612 and 683 can be formed by a sputtering method, whereby a sealing structure can be provided using a film with a relatively low hydrogen concentration.

[0347] On the other hand, films formed by sputtering have relatively low coverage. Therefore, the insulators 611 and 684 can be formed by a CVD method or the like, which has high coverage, to further improve the sealing performance.

[0348] Therefore, it is preferable that the insulators 612 and 683 have lower hydrogen concentrations than the insulators 611 and 684.

[0349] As described above, by sealing the memory circuit layers 870_1 to 870_n with a barrier insulating film, hydrogen diffusing into the oxide semiconductor included in each memory circuit 860 can be reduced, and therefore a highly reliable memory device can be provided.

[0350] Preferably, a material having a barrier property against oxygen may be used for the insulators 611, 612, 682, 687, 683, and 684. When the sealing structure has a barrier property against oxygen, it can suppress outward diffusion of excess oxygen contained in the insulator 680 and efficiently supply the excess oxygen to the transistor 600.

[0351] An insulator 674 is preferably provided to bury the memory circuit layers 870_1 to 870_n and the insulator 684. The insulator 674 may be any insulator that can be used for the insulator 680. As shown in FIG. 24 , the heights of the top surfaces of the insulators 674 and 684 are preferably approximately the same.

[0352] 24, openings may be provided in the insulators 674, 684, 683, and 611, and a conductor 876 may be disposed in the opening. The bottom surface of the conductor 876 is in contact with the conductor 856. A conductor 878 that functions as wiring may be provided in contact with the top surface of the conductor 876. It is also preferable to provide an insulator 689 that functions as an interlayer film, covering the memory circuit layer 870_n, the insulator 674, and the conductor 878. With this structure, the upper wiring (conductor 878) and the circuit of the silicon layer 871 can be electrically connected without going through the memory circuit layer 870.

[0353] 24 shows a configuration in which the memory circuit layers 870_1 to 870_n are collectively sealed with the insulators 611, 612, 687, 683, and 684, but the semiconductor device according to the present embodiment is not limited to this. For example, as shown in FIG. 25, each memory circuit layer 870 may be sealed with the insulators 611, 612, 687, 683, and 684.

[0354] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0355] (Embodiment 5) In this embodiment, the configuration of an integrated circuit including the configuration of the semiconductor device 100 described in the above embodiment will be described with reference to FIGS.

[0356] FIG. 27 is an example of a block diagram for explaining an example of the configuration of an integrated circuit including the configuration of the semiconductor device 100.

[0357] The integrated circuit 390 shown in FIG. 27 includes a CPU 10, an accelerator 20, an on-chip memory 131, a DMAC (Direct Memory Access Controller) 141, a power supply circuit 160, a power management unit (PMU) 142, a security circuit 147, a memory controller 143, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) controller 144, a USB (Universal Serial Bus) interface circuit 145, a display interface circuit 146, a bridge circuit 150, an interrupt control circuit 151, an interface circuit 152, a battery control circuit 153, and an ADC (Analog-to-digital converter) / DAC (Digital-to-analog converter) interface circuit 154.

[0358] The CPU 10 includes, for example, a CPU core 111, an instruction cache 112, a data cache 113, and a bus interface circuit 114. The accelerator 20 includes a memory circuit 121, an arithmetic circuit 122, and a control circuit 123.

[0359] The CPU core 111 has multiple CPU cores. The instruction cache 112 may have a circuit configuration that temporarily stores instructions to be executed by the CPU core 111. The data cache 113 may have a circuit configuration that temporarily stores data to be processed by the CPU core 111 or data obtained by processing. The bus interface circuit 114 may have a circuit configuration that can send and receive signals such as data and addresses to and from a bus that connects the CPU 10 to other circuits in the semiconductor device.

[0360] The memory circuit 121 corresponds to a configuration including the memory circuit 24 described in the first embodiment. The memory circuit 121 may have a circuit configuration that stores data to be processed by the accelerator 20. The arithmetic circuit 122 corresponds to a configuration including the arithmetic circuit 23 described in the first embodiment. The arithmetic circuit 122 may have a circuit configuration that performs arithmetic processing of the data held in the memory circuit 121. The control circuit 123 may have a circuit configuration for controlling each circuit in the accelerator 20, as shown in FIG. 14B.

[0361] The high-speed bus 140A is a bus for transmitting and receiving various signals at high speed between the CPU 10, accelerator 20, on-chip memory 131, DMAC 141, power management unit 142, security circuit 147, memory controller 143, DDR SDRAM controller 144, USB interface circuit 145, and display interface circuit 146. As an example, an AMBA (Advanced Microcontroller Bus Architecture)-AHB (Advanced High-performance Bus) can be used as the bus.

[0362] The on-chip memory 131 has a circuit configuration for storing data or programs input / output to / from the circuitry included in the integrated circuit 390, such as the CPU 10 or the accelerator 20.

[0363] The DMAC 141 is a direct memory access controller. By including the DMAC 141, peripheral devices other than the CPU 10 can access the on-chip memory 131 without going through the CPU 10.

[0364] The power management unit 142 has a circuit configuration for controlling power gating of circuits such as a CPU core included in the integrated circuit 390 .

[0365] The security circuit 147 has a circuit configuration for enhancing the confidentiality of signals, such as by encrypting signals before transmitting and receiving them between the integrated circuit 390 and an external circuit.

[0366] The memory controller 143 has circuitry for writing or reading a program to be executed by the CPU 10 or the accelerator 20 from a program memory external to the integrated circuit 390 .

[0367] The DDR SDRAM controller 144 has circuitry for writing data to and reading data from a main memory such as a DRAM external to the integrated circuit 390 .

[0368] The USB interface circuit 145 has a circuit configuration for transmitting and receiving data to and from a circuit external to the integrated circuit 390 via a USB terminal.

[0369] Display interface circuit 146 includes circuitry for transmitting and receiving data to and from a display device external to integrated circuit 390 .

[0370] The power supply circuit 160 is a circuit for generating a voltage used in the integrated circuit 390. For example, it is a circuit for generating a negative voltage to be applied to the back gate of an OS transistor in order to stabilize the electrical characteristics.

[0371] The low-speed bus 140B is a bus for transmitting and receiving various signals at low speed between the interrupt control circuit 151, the interface circuit 152, the battery control circuit 153, and the ADC / DAC interface circuit 154. As an example, an AMBA-APB (Advanced Peripheral Bus) can be used as the bus. Various signals are transmitted and received between the high-speed bus 140A and the low-speed bus 140B via a bridge circuit 150.

[0372] The interrupt control circuit 151 has a circuit configuration for performing interrupt processing in response to a request received from a peripheral device.

[0373] The interface circuit 152 has a circuit configuration for enabling interfaces such as a universal asynchronous receiver / transmitter (UART), an inter-integrated circuit (I2C), or a serial peripheral interface (SPI) to function.

[0374] The battery control circuit 153 has circuitry for transmitting and receiving data relating to the charging and discharging of a battery external to the integrated circuit 390 .

[0375] The ADC / DAC interface circuit 154 has a circuit configuration for transmitting and receiving data to and from a device that outputs an analog signal, such as a MEMS (Micro Electro Mechanical Systems) device, located outside the integrated circuit 390 .

[0376] 28A and 28B are diagrams showing an example of the layout of circuit blocks when implemented as an SoC. As in the integrated circuit 390 shown in Fig. 28A, each component shown in the block diagram of Fig. 27 can be arranged in separate areas on a chip.

[0377] 27 can be configured with a memory circuit made up of OS transistors, such as NOSRAM. In other words, the on-chip memory 131 and the memory circuit 121 have the same circuit configuration. Therefore, when an SoC is implemented, the on-chip memory 131 and the memory circuit 121 can be integrated and placed in the same area, as in the integrated circuit 390E shown in FIG. 28B.

[0378] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0379] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0380] (Sixth embodiment) In this embodiment mode, electronic devices, mobile objects, and arithmetic systems to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS. 29A to 32. FIG.

[0381] Fig. 29A shows an external view of an automobile as an example of a moving body. Fig. 29B is a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also has various sensors (not shown) such as infrared radar, millimeter-wave radar, and laser radar.

[0382] The above-described integrated circuit 390 can be used for a camera 591 or the like in an automobile 590. The automobile 590 processes a plurality of images acquired by a camera 591 in a plurality of imaging directions 592 using the integrated circuit 390 described in the above embodiment, and analyzes the plurality of images collectively using a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and performing autonomous driving. The automobile 590 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0383] In the integrated circuit 390, the obtained image data is subjected to arithmetic processing such as neural networks, making it possible to perform processes such as increasing the image resolution, reducing image noise, facial recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0384] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0385] Fig. 30A is an external view showing an example of a portable electronic device. Fig. 30B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has printed circuit board 596, speaker 597, camera 598, microphone 599, etc.

[0386] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc. using integrated circuit 390 described in the above embodiment. In addition, the portable electronic device 595 can be used in systems that perform voice guidance, image search, etc.

[0387] In the integrated circuit 390, the obtained image data is subjected to arithmetic processing such as neural networks, making it possible to perform processes such as increasing the image resolution, reducing image noise, facial recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0388] A portable game console 1100 shown in FIG. 31A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, a video image displayed on the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated into a chip provided on a substrate of the housing 1102 or the housing 1103.

[0389] 31B shows a stick-type electronic device 1120 that is USB-connected. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 of the board 1124.

[0390] 31C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the integrated circuit 390 shown in the previous embodiment.

[0391] The integrated circuit 390 described in the above embodiment can be used in a server that communicates with the electronic device instead of being built into the electronic device. In this case, the electronic device and the server constitute a computing system. Figure 32 shows an example of the configuration of a system 3000.

[0392] The system 3000 is configured by an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an internet line 3003.

[0393] Server 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided in the racks, and integrated circuits 390 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. The results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This reduces the calculation load on electronic device 3001.

[0394] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0395] (Notes regarding the present specification) The above-described embodiment and each configuration in the embodiment will be described below with additional notes.

[0396] The configurations shown in each embodiment can be combined as appropriate with configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0397] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0398] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0399] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0400] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0401] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0402] Furthermore, the positional relationships of components shown in the drawings are relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" indicating the positional relationships may be used for convenience. The positional relationships of components are not limited to the content described in this specification, and can be rephrased appropriately depending on the situation.

[0403] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of a transistor can be appropriately changed to source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0404] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0405] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0406] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0407] In this specification, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" means a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0408] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0409] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0410] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0411] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." [Explanation of symbols]

[0412] BGL1: wiring, C11: capacitance element, CK1: node, D1: node, GCLK1: clock signal, I1: input layer, M1: hidden layer, M3: hidden layer, M11: transistor, M12: transistor, M13: transistor, O1: output layer, PSE0: signal, PSE1: signal, PSE2: signal, Q_N: output signal, Q_1: output signal, Q1: node, RBL_N: read bit line, RBL_1: read bit line, RWL_M: read word line, RWL_1: read word line, SLEEP1: signal, SN11: node, SW_N: switch, SW_1: switch ,SW1: transistor, t1: time, t2: time, t3: time, t4: time, t5: time, t6: time, t7: time, WBL_1: write bit line, WWL_M: write word line, WWL_1: write word line, 10: CPU, 20: accelerator, 21: arithmetic processing unit, 22: memory unit, 22_N: memory circuit layer, 22_1: memory circuit layer, 22_2: memory circuit layer, 23: arithmetic circuit, 23_N: arithmetic circuit, 23_1: arithmetic circuit, 24: memory circuit, 24_N: memory circuit, 24_P: memory circuit, 24A: memory circuit, 24B: memory circuit, 24C : memory circuit, 24D: memory circuit, 24E: memory circuit, 25: transistor, 25_N: transistor, 25_P: transistor, 25A: transistor, 25B: transistor, 26: transistor, 26_N: transistor, 26_P: transistor, 26B: transistor, 27: transistor, 27_N: transistor, 27_P: transistor, 28: capacitor, 28_N: capacitor, 28_P: capacitor, 28A: capacitor, 28B: capacitor, 29: semiconductor layer, 30: bus, 31: wiring, 32: transistor, 33A: transistor, 33B: transistor, 34: antenna, 35: driver circuit, 36A: insulator, 36B: insulator, 41: readout circuit, 42: bit product-sum calculator, 43: accumulator, 44: latch circuit, 45: encoding circuit, 46: inverter circuit, 47: logic circuit, 50: neuron, 51: layer, 52: layer, 53: layer, 54: layer, 61: controller, 62: row decoder, 63: word line driver, 64: column decoder, 65: driver, 66: precharge circuit, 67: sense amplifier, 68: selector, 71: input buffer, 72: arithmetic control circuit, 76: WA,100: semiconductor device, 110: drive circuit layer, 111: CPU core, 112: instruction cache, 113: data cache, 114: bus interface circuit, 121: memory circuit, 122: arithmetic circuit, 123: control circuit, 131: on-chip memory, 140A: high-speed bus, 140B: low-speed bus, 141: DMAC, 142: power management unit, 143: memory controller, 144: controller, 145: interface circuit, 146: display interface circuit, 147: security circuit, 150: bridge circuit, 15 1: control circuit, 152: interface circuit, 153: battery control circuit, 154: interface circuit, 160: power supply circuit, 193: PMU, 200: CPU core, 202: cache memory device, 203: cache memory device, 205: bus interface unit, 210: power switch, 211: power switch, 212: power switch, 214: level shifter, 220: flip-flop, 221: scan flip-flop, 221A: clock buffer circuit, 222: backup circuit, 390: integrated circuit, 390E: integrated circuit, 590: automobile, 591: camera, 592: imaging direction, 593: bus, 594: host controller, 595: portable electronic device, 596: printed wiring board, 597: speaker, 598: camera, 599: microphone, 600: transistor, 605: conductor, 605a: conductor, 605b: conductor, 607: conductor, 611: insulator, 612: insulator, 614: insulator, 615: conductor, 616: insulator, 622: insulator, 624: insulator, 630: oxide, 630a: oxide, 630b: oxide, 630c: oxide, 640: conductor, 640a : conductor, 640b: conductor, 640c: conductor, 640d: conductor, 642: conductor, 642a: conductor, 642b: conductor, 643: oxide, 643a: oxide, 643b: oxide, 646: conductor, 646a: conductor, 646b: conductor, 650: insulator, 655: capacitor, 656: conductor, 657: conductor, 660: conductor, 660a: conductor, 660b: conductor, 672: insulator, 673: insulator, 674: insulator, 680: insulator, 682: insulator, 683: insulator, 684: insulator, 685: insulator, 686: insulator, 687: insulator,688: Insulator, 689: Insulator, 690: Transistor, 700: Transistor, 705: Conductor, 705a: Conductor, 705b: Conductor, 715: Conductor, 730: Oxide, 730a: Oxide, 730b: Oxide, 730c: Oxide, 742: Conductor, 742a: Conductor, 742b: Conductor, 743: Oxide, 743a: Oxide, 743b: Oxide, 750: Insulator, 760: Conductor, 760a: Conductor, 760b: Conductor, 7 90: transistor, 800: transistor, 811: substrate, 813: semiconductor region, 814a: low resistance region, 814b: low resistance region, 815: insulator, 816: conductor, 820: insulator, 822: insulator, 824: insulator, 826: insulator, 828: conductor, 830: conductor, 850: insulator, 852: insulator, 854: insulator, 856: conductor, 857: conductor, 860: memory circuit, 860_1: memory circuit, 860_2: memory memory circuit, 860_3: ​​memory circuit, 860_4: memory circuit, 860_5: memory circuit, 860_6: memory circuit, 870: memory circuit layer, 870_n: memory circuit layer, 870_1: memory circuit layer, 871: silicon layer, 876: conductor, 878: conductor, 1100: portable game console, 1101: housing, 1102: housing, 1103: housing, 1104: display unit, 1105: connection unit, 1107: operation keys, 1108: housing, 1109: housing Body, 1120: Electronic device, 1121: Housing, 1122: Cap, 1123: USB connector, 1124: Board, 1125: Memory chip, 1126: Controller chip, 1130: Robot, 2101: Sensor, 2106: Sensor, 2110: Control circuit, 3000: System, 3001: Electronic device, 3002: Server, 3003: Internet line, 3004: Rack, 3005: Board, 3210: WA, 7654: WA,

Claims

1. It has an accelerator, the accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit; the first memory circuit has a first transistor; the second memory circuit has a second transistor; the first transistor and the second transistor each have a semiconductor layer having a metal oxide in a channel formation region; the arithmetic circuit includes a third transistor; the third transistor has a semiconductor layer having silicon in a channel formation region; a channel length direction of the transistor of the first memory circuit is parallel to an upper surface of a substrate; a channel length direction of the transistor of the second memory circuit is perpendicular to an upper surface of the substrate; a layer having the second transistor is provided on a layer having the first transistor; The semiconductor device, wherein the layer having the first transistor and the layer having the second transistor are provided on the layer having the third transistor.

2. In claim 1, The first memory circuit and the second memory circuit have a function of holding data input to the arithmetic circuit.

3. In claim 1 or 2, The second memory circuit has a circuit configuration different from that of the first memory circuit.

Images