Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a display area; and a bind area located on a first direction side of the display area, the display area comprising: a plurality of sub-pixels arranged in an array; and a plurality of data lines electrically connected to the plurality of sub-pixels, the bind area comprising: a plurality of data line leads connected to the plurality of data lines; and a plurality of pins connected to the plurality of data line leads, the plurality of pins being located on the side of the plurality of data line leads away from the display area, the bind area further comprising: a first wiring area, a bending area, and a second wiring area arranged in sequence along a first direction, the second wiring area comprising a first through hole, the first through hole being located between the plurality of data line leads, and the first through hole being configured to correspond to a first photosensitive element.

Description

[Technical Field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to the field of display technology, and in particular, but not exclusively, to display panels and display devices. [Background technology]

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display elements that have advantages such as autonomous light emission, wide viewing angles, high contrast, low power consumption, and extremely fast response speeds. With the development of display technology, flexible display devices that use OLEDs as light-emitting elements and perform signal control using thin film transistors (TFTs) have become the mainstream product in the current display field. Summary of the Invention [Means for solving the problem]

[0003] The following is a general overview of the subject matter discussed in detail in the text, which is not intended to limit the scope of protection of the claims.

[0004] In one aspect, an embodiment of the present disclosure provides a display panel, comprising: a display area; and a bind area located on a first direction side of the display area, wherein the display area comprises a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected to the plurality of sub-pixels, the bind area comprising a plurality of data line leads connected to the plurality of data lines and a plurality of pins connected to the plurality of data line leads, the plurality of pins being located on sides of the plurality of data line leads away from the display area, the bind area further comprising: a first wiring area, a bending area, and a second wiring area arranged in sequence along the first direction, the second wiring area comprising a first through hole, the first through hole being located between the plurality of data line leads, and the first through hole being configured to correspond to a first photosensitive element.

[0005] In another aspect, an embodiment of the present disclosure further provides a display device, comprising: a display panel according to any of the above embodiments; and a first photosensitive element, wherein the position of the first photosensitive element corresponds to the position of the first through hole.

[0006] Other features and advantages of the present disclosure will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by the practice of the present disclosure. Other advantages of the present disclosure may be realized and attained by the devices set forth in the description and drawings.

[0007] Other aspects may be understood after reading and understanding the accompanying drawings and detailed description.

[0008] The drawings are intended to facilitate a better understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect actual scale, and are intended only to schematically explain the contents of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1A is a schematic diagram of the structure of an OLED display device. [Figure 1B] FIG. 1B is a schematic diagram of an equivalent circuit of a pixel driving circuit. [Figure 1C] FIG. 1C is an operation timing diagram of the pixel driving circuit. [Figure 2] FIG. 2 is a structural schematic diagram of a display panel in an exemplary embodiment of the present disclosure. [Figure 3A] FIG. 3A is a structural schematic diagram of a display area in a display panel according to an exemplary embodiment of the present disclosure. [Figure 3B] FIG. 3B is another structural schematic diagram of a display area in a display panel according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 is a structural schematic diagram of a binding area in a display panel according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 5 is a side view of the display panel shown in FIG. [Figure 6A] FIG. 6A is a schematic diagram of the wiring layout of the bind area in the display panel shown in FIG. [Figure 6B] FIG. 6B is an enlarged schematic view of a first through-hole in a display panel according to an exemplary embodiment of the present disclosure. [Figure 6C] FIG. 6C is another enlarged schematic view of the first through-hole in the display panel according to the exemplary embodiment of the present disclosure. [Figure 6D] FIG. 6D is an enlarged schematic view of a second through-hole in a display panel according to an exemplary embodiment of the present disclosure. [Figure 6E] FIG. 6E is another enlarged schematic view of the second through-hole in the display panel according to the exemplary embodiment of the present disclosure. [Figure 7] FIG. 7 is an enlarged schematic diagram of the wiring in region A in the bind region shown in FIG. 6A. [Figure 8] FIG. 8 is an enlarged schematic diagram of the wiring in region B in the bind region shown in FIG. 6A. [Figure 9] FIG. 9 is a structural schematic diagram of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] While multiple embodiments are described herein, the descriptions are illustrative rather than restrictive, and many more embodiments and implementations may be within the scope of the embodiments described herein. While many possible combinations of features are shown in the drawings and considered in the exemplary embodiments, many other combinations of the disclosed features are possible. Unless otherwise limited, any feature or element of any embodiment can be used in combination with, or substituted for, any other feature or element of, any other embodiment.

[0011] In describing exemplary embodiments, the specification may present a method or process as a particular sequence of steps. However, to the extent that the method or process does not depend on the particular order of steps set forth herein, the method or process should not be limited to a particular order of steps. As will be understood by one of ordinary skill in the art, other orders of steps are possible. Accordingly, the particular order of steps set forth in the specification should not be construed as a limitation on the scope of the claims. Furthermore, claims to the method or process should not be limited to performing those steps in the order set forth; as will be readily understood by one of ordinary skill in the art, those orders can be varied and still fall within the spirit and scope of the embodiments of the present disclosure.

[0012] In the drawings, the size of each component, the thickness of a layer, or the area thereof may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shapes and sizes of each member in the drawings do not reflect the actual scale. Note that the drawings show ideal examples in a schematic manner, but one embodiment of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0013] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of elements and are not intended to limit the number of elements.

[0014] For convenience, terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used in this specification to describe the positional relationships of components with reference to the drawings. However, these terms are merely for the purpose of simplifying the description of this specification and do not explicitly or implicitly indicate that the indicated devices or elements have a specific orientation or are constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure. The positional relationships of components are appropriately changed depending on the direction in which each component is described. Therefore, no limitation is imposed on the terms described in this specification, and they can be appropriately substituted depending on the situation.

[0015] In this specification, unless otherwise clearly specified or limited, the terms "attached" and "connected" should be understood in a broad sense. For example, they may mean fixedly connected, detachably connected, or integrally connected, may be mechanically connected or electrically connected, may be directly connected, may be indirectly connected via an intermediate member, or may be in communication within two elements. Those skilled in the art can understand the meaning of the above terms in the present disclosure depending on the context.

[0016] In this specification, "electrical connection" includes cases where components are connected via an element having some electrical function. The "element having some electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" may be, for example, an electrode or wiring, a switching element such as a transistor, or other functional element such as a resistor, inductor, or capacitor.

[0017] In this specification, a transistor refers to an element having at least three terminals: a gate electrode (gate electrode or control electrode), a drain electrode (drain electrode terminal, drain region, or drain electrode), and a source electrode (source electrode terminal, source region, or source electrode). A transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, channel region, and source electrode. However, in this specification, the channel region refers to the region through which current mainly flows.

[0018] In this specification, in order to distinguish between two poles other than the gate electrode (gate electrode or control electrode) of a transistor, one of them is described as a first pole and the other as a second pole, and the first pole may be a drain electrode and the second pole may be a source electrode, or the first pole may be a source electrode and the second pole may be a drain electrode. When a transistor with reversed polarity is used, or when the current direction during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchangeable.

[0019] The transistors in the embodiments of the present disclosure may be thin film transistors (TFTs), field effect transistors (FETs), or other devices with the same characteristics. For example, thin film transistors used in the embodiments of the present disclosure include, but are not limited to, oxide TFTs or low temperature polysilicon TFTs (LTPS TFTs). The embodiments of the present disclosure are not limited thereto.

[0020] In this specification, "parallel" refers to a state in which the angle between two lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less. "Perpendicular" refers to a state in which the angle between two lines is 80° or more and 100° or less, and therefore also includes a state in which the angle is 85° or more and 95° or less.

[0021] In this disclosure, "about" refers to not strictly limiting the limits but allowing for numerical values ​​within the error range of process and measurement.

[0022] With the development of display technology, the form of display devices (e.g., mobile phones) is rapidly changing, and many flexible display devices (e.g., foldable display devices) have appeared on the market and are favored by many consumers. Current flexible display devices generally include a photosensitive element (e.g., a fingerprint recognition sensor, a camera assembly, an infrared sensor, etc.) to be integrated into the overall device assembly, which is disadvantageous for realizing a full screen.

[0023] 1A is a structural schematic diagram of an OLED display device. As shown in FIG. 1A, the OLED display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data drivers are respectively connected to a plurality of data signal lines (D1 to Dn). The scan drivers are respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting drivers are respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may include at least one scan signal line (which may also be referred to as a gate line), at least one data signal line (which may also be referred to as a data line), at least one light-emitting signal line, and a pixel driving circuit. In one exemplary embodiment, the timing controller may provide the data driver with grayscale values ​​and control signals suitable for the data driver's specifications, the scan driver with clock signals, scan start signals, etc. suitable for the scan driver's specifications, and the light-emitting driver with clock signals, light-emitting stop signals, etc. suitable for the light-emitting driver's specifications. The data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn using the grayscale values ​​and control signals received from the timing controller. For example, the data driver may sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signals, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm.For example, the scan driver may be configured in the form of a shift register, and may generate scan signals by sequentially transmitting a scan start signal provided in the form of an on-level pulse to a subsequent circuit under control of a clock signal, where m may be a natural number. The light-emitting driver may receive a clock signal, a light-emitting stop signal, etc. from a timing controller to generate light-emitting signals provided to the light-emitting signal lines E1, E2, E3, ..., and Eo. For example, the light-emitting driver may sequentially provide transmission signals having off-level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register, and may generate transmission signals by sequentially transmitting a transmission stop signal provided in the form of an off-level pulse to a subsequent circuit under control of a clock signal, where o may be a natural number.

[0024] In one exemplary embodiment, the pixel driving circuit may be, but is not limited to, a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure, etc. The embodiments of the present disclosure are not limited in this regard.

[0025] 1B is a schematic equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 1B, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7), one storage capacitor C, and seven signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0026] In one exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3, where the first node N1 is connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, and a second pole of the fifth transistor T5, respectively, and the second node N2 is connected to First transistor T1the second pole of the second transistor T2, the first pole of the third transistor T3, and the second end of the storage capacitor C, respectively; and the third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively.

[0027] In one exemplary embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, i.e., the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0028] A control electrode of the first transistor T1 is connected to the second scanning signal line S2, and a first electrode of the first transistor T1 is connected to the initial signal line INIT; First transistor T1 The second electrode of the third transistor T1 is connected to the second node N2. When an on-level scanning signal is applied to the second scanning signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0029] The control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scanning signal is applied to the first scanning signal line S1, the second transistor T2 connects the control electrode and second electrode of the third transistor T3.

[0030] The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first pole of the third transistor T3 is connected to the first node N1, and the second pole of the third transistor T3 is connected to the third node N3. The third transistor T3 may also be called a drive transistor, and the third transistor T3 determines the amount of drive current flowing between the first power supply line VDD and the second power supply line VSS based on the potential difference between its control electrode and first pole.

[0031] A control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may also be referred to as a switching transistor, a scanning transistor, etc. When an on-level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0032] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element. The fifth transistor T5 and the sixth transistor T6 may be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, thereby causing the light-emitting element to emit light.

[0033] The seventh transistor T7 has a control electrode connected to the first scanning signal line S1, a first electrode connected to the initial signal line INIT, and a second electrode connected to the first electrode of the light-emitting element. When an on-level scanning signal is applied to the first scanning signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting element to initialize or release the charge accumulated in the first electrode of the light-emitting element.

[0034] In one exemplary embodiment, the second electrode of the light-emitting element is connected to a second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n) and the second scan signal line S2 is S(n-1), and the second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row, so that the number of signal lines of the display panel can be reduced and a narrower bezel of the display panel can be achieved.

[0035] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of the display panel manufacturing process, and increase the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0036] In one exemplary embodiment, the first scanning signal line S1, the second scanning signal line S2, the light-emitting signal line E, and the initial signal line INIT may extend horizontally, and the second power supply line VSS, the first power supply line VDD, and the data signal line D may extend vertically.

[0037] In one exemplary embodiment, the light-emitting element may be an organic electroluminescent diode (OLED), which includes a stacked first electrode (e.g., as an anode), an organic light-emitting layer, and a second electrode (e.g., as a cathode).

[0038] FIG. 1C is an operation timing diagram of the pixel driving circuit. Next, an exemplary embodiment of the present disclosure will be described through the operation process of the pixel driving circuit exemplarily shown in FIG. 1B. The pixel driving circuit in FIG. 1B includes seven transistors (first transistor T1 to Seventh transistor T7), one storage capacitor C, and seven signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a light emission signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS), and all seven transistors are P-type transistors.

[0039] In one exemplary embodiment, the operation process of the pixel driving circuit may include the following three steps:

[0040] The first stage A1 is called the reset stage, in which the signal on the second scan signal line S2 is low, and the signals on the first scan signal line S1 and the light-emitting signal line E are high. The signal on the second scan signal line S2 is low, which turns on the first transistor T1 and provides the signal on the initialization signal line INIT to the second node N2 to initialize the storage capacitor C and erase the original data voltage on the storage capacitor. The signals on the first scan signal line S1 and the light-emitting signal line E are high, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the OLED does not emit light in this stage.

[0041] The second stage A2 is called the data writing stage or threshold compensation stage, in which the signal of the first scanning signal line S1 is low, the signals of the second scanning signal line S2 and the light-emitting signal line E are high, and the data signal line D outputs a data voltage. In this stage, the second end of the storage capacitor C is low, so the third transistor T3 is turned on. Because the signal of the first scanning signal line S1 is low, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. When the second transistor T2 and the fourth transistor T4 are turned on, the data voltage output from the data signal line D is provided to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end (second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output from the data signal line D and Vth is the threshold voltage of the third transistor T3. When the seventh transistor T7 is turned on, the initial voltage of the initial signal line INIT is provided to the first terminal of the OLED, initializing (resetting) the first terminal of the OLED and clearing its internal standby voltage, completing the initialization and preventing the OLED from emitting light. The signal of the second scan signal line S2 is a high-level signal, thereby turning off the first transistor T1. The signal on the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0042] The first stage A3 is called the light-emitting stage, in which the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the fifth transistor T5, the third transistor T3, and the sixth transistor T6 that are turned on, driving the OLED to emit light.

[0043] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is I=K * (Vgs-Vth) 2 =K * [(Vdd-Vd+|Vth|)-Vth] 2 =K * [(Vdd-Vd] 2 is.

[0044] Here, I is the driving current flowing through the third transistor T3, i.e., the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output from the data signal line D, and Vdd is the power supply voltage output from the first power supply line VDD.

[0045] In the embodiment of the present disclosure, the first direction DR1 may refer to a vertical direction, the second direction DR2 may refer to a horizontal direction, and the third direction DR3 may refer to a thickness direction of the display panel or a direction perpendicular to the plane of the display panel, etc. The first direction DR1 intersects with the second direction DR2, and the first direction DR1 intersects with the third direction DR3. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other, and the first direction DR1 and the third direction DR3 may be perpendicular to each other.

[0046] An embodiment of the present disclosure provides a display panel, the display panel may include a display area and a bind area located on a first direction side of the display area, the display area may include a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected to the plurality of sub-pixels, the bind area may include a plurality of data line leads connected to the plurality of data lines and a plurality of pins connected to the plurality of data line leads, the plurality of pins being located on the sides of the plurality of data line leads away from the display area, the bind area may further include a first wiring area, a bending area, and a second wiring area arranged in sequence along the first direction, the second wiring area may include a first through hole located between the plurality of data line leads and configured to correspond to a first photosensitive element, in this way, by drilling a hole in the bind area of ​​the display panel to avoid the first photosensitive element (e.g., a camera assembly), it is convenient to assemble the entire device and advantageous to realize a full screen.

[0047] In one exemplary embodiment, the second wiring region may include a first sub-region, the first through-holes are located in the first sub-region, the second wiring region has a centerline extending in a first direction, and the first through-holes are arranged symmetrically with respect to the centerline. In this way, it is possible to ensure uniformity of the wiring load around the first through-holes in the second wiring region, thereby ensuring consistency of the wiring impedance in the display panel and avoiding wiring pressure caused by wiring being concentrated on one side, thereby improving the display effect.

[0048] In one exemplary embodiment, the second wiring region may further include a second through hole located on the side of the first through hole along a second direction, the second through hole being configured to correspond to a second photosensitive element, and the second direction intersects with the first direction.

[0049] In one exemplary embodiment, the second wiring region may further include a dummy hole in which the second through hole is located on the side away from the first through hole along the second direction, and the first subregion may include a first hole region, a second hole region, and a third hole region arranged in sequence along the second direction, with the first through hole located in the second hole region, the second through hole located in the first hole region, and the dummy hole located in the third hole region.

[0050] In one exemplary embodiment, the shape of the dummy holes is the same as the shape of the second through holes, and the size of the second through holes is the same as the size of the dummy holes.

[0051] In one exemplary embodiment, the dummy holes and the second through holes may be arranged symmetrically with respect to the center line, and the second direction intersects with the first direction. By opening through holes in the binding region of the display panel, arranging the second through holes and the dummy holes symmetrically with respect to the center line, and arranging the first through holes symmetrically with respect to the center line, it is possible to ensure uniformity of the wiring load in the second wiring region, thereby ensuring consistency of the wiring impedance in the display panel and avoiding wiring pressure caused by wiring being concentrated on one side, thereby improving the display effect.

[0052] In one exemplary embodiment, the first hole region may further include a plurality of first wirings extending in the first direction and a plurality of second wirings extending in the first direction, the plurality of first wirings and the plurality of second wirings being located on both sides of the second through hole along the second direction, the length of the first wirings being greater than the length of the second wirings, and the width of the first wirings being greater than the width of the second wirings. In this way, by setting the width of the relatively long wirings (e.g., the first wirings) on both sides of the second through hole to be relatively wide and the width of the relatively short wirings (e.g., the second wirings) to be relatively narrow, the overall resistance of the relatively long wirings (e.g., the first wirings) can be reduced, thereby reducing the load on the relatively long wirings (e.g., the first wirings), and ensuring that the resistances of the wirings on both sides of the first through hole change uniformly and the loads are balanced relative to each other.

[0053] In one exemplary embodiment, the third hole region may further include a plurality of third wirings extending in the first direction and a plurality of fourth wirings extending in the first direction, the plurality of third wirings and the plurality of fourth wirings being respectively located on both sides of the dummy hole, the length of the third wirings being greater than the length of the fourth wirings, the width of the third wirings being greater than the width of the fourth wirings, the third wirings and the first wirings being arranged symmetrically about the center line, and the fourth wirings and the second wirings being arranged symmetrically about the center line. In this way, by setting the width of the relatively long wirings (e.g., the third wirings) on both sides of the dummy hole to be relatively wide and the width of the relatively short wirings (e.g., the fourth wirings) to be relatively narrow, the overall resistance of the relatively long wirings (e.g., the third wirings) can be reduced, thereby reducing the load on the relatively long wirings (e.g., the third wirings), and ensuring that the resistances of the wirings on both sides of the dummy hole change uniformly and the loads are balanced relative to each other. Furthermore, since the third wiring and the first wiring are arranged symmetrically with respect to the center line, and the fourth wiring and the second wiring are arranged symmetrically with respect to the center line, it is possible to ensure that the resistance of the wiring in the second wiring region changes uniformly.

[0054] In one exemplary embodiment, the display panel may further include a second sub-region and a third sub-region located on both sides of the first sub-region in the second direction, and the second sub-region and the third sub-region may be arranged symmetrically with respect to the center line. By providing the second and third sub-regions, the uniformity of the wiring load in the second wiring region can be ensured. This ensures that the wiring impedance in the display panel is consistent and avoids wiring pressure caused by wiring being concentrated on one side. This improves the display effect.

[0055] In one exemplary embodiment, the display panel may further include dummy wiring, including at least one of a first dummy wiring surrounding the first through hole and a second dummy wiring surrounding the second through hole. In this way, by arranging the dummy wiring around the through hole, the risk of crack defects around the through hole in the drilling process during the manufacturing process of the display panel can be reduced, and adverse effects on normal wiring around the through hole can be avoided, thereby increasing the yield of products.

[0056] 2 is a structural schematic diagram of a display panel in an exemplary embodiment of the present disclosure. As shown in FIG. 2, the display panel may include a display area 100 and a non-display area located around the display area 100. The non-display area may include a binding area 200 located on one side of the display area 100 and a frame area 300 located on the other side of the display area 100. For example, the binding area 200 may be located on the first direction DR1 side of the display area 100.

[0057] 2, the display area 100 may include a plurality of sub-pixels Pxij arranged in an array and a plurality of data lines (not shown) electrically connected to the plurality of sub-pixels Pxij, where i and j may be natural numbers. For example, the display area 100 may further include a plurality of gate lines electrically connected to the plurality of sub-pixels Pxij. Here, the sub-pixel Pxij may refer to a sub-pixel whose transistor is connected to the ith gate line and connected to the jth data line.

[0058] The display area will be described below with reference to the drawings.

[0059] 3A is a structural schematic diagram of a display area in a display panel in an exemplary embodiment of the present disclosure. As shown in FIG. 3A , in the exemplary embodiment, the display area 100 may include a plurality of pixel units P arranged in a matrix, where at least one of the pixel units P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. For example, the first sub-pixel P1 may be a red (R) sub-pixel, the second sub-pixel P2 may be a green (G) sub-pixel, and the third sub-pixel P3 may be a blue (B) sub-pixel. Alternatively, at least one of the pixel units P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 emitting different color light. For example, the pixel unit P may include four sub-pixels, e.g., a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The embodiments of the present disclosure are not limited in this respect.

[0060] In one exemplary embodiment, each sub-pixel may include a pixel driving circuit and a light-emitting element, wherein the pixel driving circuit in the sub-pixel is respectively connected to a scan signal line, a data signal line, and an emission signal line, the light-emitting element in the sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line under the control of the scan signal line and the emission signal line, and output a corresponding current to the light-emitting element, and the light-emitting element is configured to emit light of a corresponding brightness in response to the current output from the pixel driving circuit of the sub-pixel in which it is located.

[0061] In one exemplary embodiment, the sub-pixels in a pixel unit may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, an X-shape, a cross shape, a square shape, or the like. For example, if a pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square shape. For example, if a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square shape. The embodiments of the present disclosure are not limited thereto.

[0062] In one exemplary embodiment, the shape of the sub-pixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, although the embodiments of the present disclosure are not limited in this respect.

[0063] 3B is another structural schematic diagram of a display region in a display panel according to an exemplary embodiment of the present disclosure, illustrating the structure of three subpixels of an OLED display panel. As shown in FIG. 3B , in one exemplary embodiment, in a plane perpendicular to the display panel, the display panel may include a driving circuit layer 12 provided on a base substrate 10, a light-emitting structure layer 13 provided on a side of the driving circuit layer 12 away from the base substrate 10, and a packaging layer 14 provided on a side of the light-emitting structure layer 13 away from the base substrate 10. In some possible implementations, the display panel may include other film layers, such as spacer posts, and the present disclosure is not limited thereto.

[0064] In one exemplary embodiment, the base substrate 10 may be a flexible base substrate or a rigid base substrate. The driving circuit layer 12 of each subpixel may include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. FIG. 3B shows only one transistor 11A and one storage capacitor 11B as an example. The light-emitting structure layer 13 may include an anode 31, a pixel definition layer 32, an organic light-emitting layer 33, and a cathode 34. The anode 31 may be connected to the drain electrode of the transistor 11A through a through-hole. The pixel definition layer 32 covers the anode 31, and a pixel opening exposing the anode 31 is formed. The organic light-emitting layer 33 is connected to the anode 31 through the pixel opening, and the cathode 34 is connected to the organic light-emitting layer 33. The organic light-emitting layer 33 emits light of a corresponding color when the anode 31 and the cathode 34 are driven. The package layer 14 may include a stacked first package layer 41, a second package layer 42, and a third package layer 43. For example, the first package layer 41 and the third package layer 43 may be made of inorganic materials, and the second package layer 42 may be made of organic materials. The second package layer 42 is disposed between the first package layer 41 and the third package layer 43 to prevent external water vapor from entering the light-emitting structure layer 13.

[0065] In one exemplary embodiment, the driving circuit layer of each subpixel may include a first insulating layer disposed on the flexible base substrate, an active layer disposed on the first insulating layer, a second insulating layer covering the active layer, a gate electrode and a first capacitor electrode disposed on the second insulating layer, a third insulating layer covering the gate electrode and the first capacitor electrode, a second capacitor electrode disposed on the third insulating layer, a fourth insulating layer covering the second capacitor electrode, a source electrode and a drain electrode disposed on the fourth insulating layer, and a planar layer covering the above structure, wherein through holes are opened in the fourth insulating layer, exposing the active layer, and the source electrode and the drain electrode are respectively connected to the active layer through the through holes. The active layer, the gate electrode, the source electrode, and the drain electrode constitute a transistor, and the first capacitor electrode and the second capacitor electrode constitute a storage capacitor. In one exemplary embodiment, the active layer may employ materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, i.e., the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology, or organic technology.

[0066] In one exemplary embodiment, the organic light-emitting layer may include an emitting layer (EML) and one or more layers selected from the group consisting of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the hole injection layers of all subpixels may be a common layer connected to each other, the electron injection layers of all subpixels may be a common layer connected to each other, the hole transport layers of all subpixels may be a common layer connected to each other, the electron transport layers of all subpixels may be a common layer connected to each other, the hole blocking layers of all subpixels may be a common layer connected to each other, the emitting layers of adjacent subpixels may be slightly overlapping or separated, and the electron blocking layers of adjacent subpixels may be slightly overlapping or separated.

[0067] In one exemplary embodiment, each sub-pixel in the display panel may have a light-emitting area and a non-light-emitting area, where the organic light-emitting layer emits light in a pixel aperture area defined by the pixel definition layer, and the pixel aperture area is the light-emitting area FA of the sub-pixel, and the area other than the pixel aperture is the non-light-emitting area BF of the sub-pixel, and the non-light-emitting area BF is located between the light-emitting areas FA of adjacent sub-pixels.

[0068] The bind area will be described below with reference to the drawings.

[0069] FIG. 4 is a structural schematic diagram of a bind area in a display panel in an exemplary embodiment of the present disclosure. FIG. 5 is a side view of the display panel shown in FIG. 4. FIG. 6A is a schematic diagram of a wiring layout in the bind area in the display panel shown in FIG. 4. FIG. 6B is an enlarged schematic diagram of a first through hole in a display panel in an exemplary embodiment of the present disclosure. FIG. 6C is another enlarged schematic diagram of a first through hole in a display panel in an exemplary embodiment of the present disclosure. FIG. 6D is another enlarged schematic diagram of a second through hole in a display panel in an exemplary embodiment of the present disclosure. FIG. 6E is another enlarged schematic diagram of a second through hole in a display panel in an exemplary embodiment of the present disclosure. FIG. 7 is an enlarged schematic diagram of wiring in region A in the bind area shown in FIG. 6A, and FIG. 8 is an enlarged schematic diagram of wiring in region B in the bind area shown in FIG. 6A. The wiring in FIGS. 6A to 8 is merely illustrative, and the number of wiring does not represent the actual number. 4 to 8 are schematic illustrations of examples in which a circle is selected for the first through hole and a rectangle with rounded corners is selected for the second through hole, but the shapes of the through holes do not represent the actual shapes.

[0070] 4 and 5, the bind area 200 may include a plurality of data line leads (not shown) connected to a plurality of data lines (not shown), and a plurality of pins (not shown) connected to the plurality of data line leads (not shown), where the plurality of pins (not shown) are located on sides of the plurality of data line leads (not shown) that are away from the display area 100. In a plane parallel to the display panel, the bind area 200 may further include a first wiring area 201, a bending area 202, a second wiring area 203, and a composite circuit area 204, which are arranged in order along a first direction DR1 (i.e., a direction away from the display area 100). The first wiring area 201 is connected to the display area 100, the bending area 202 is connected to the first wiring area 201, and the second wiring area 203 is connected to the bending area 202, Complex circuit area 204 is connected to the second wiring area 203.

[0071] In one exemplary embodiment, the first wiring region may include a plurality of lead-out lines. For example, the plurality of lead-out lines may include a plurality of data line lead-out lines, a plurality of touch lead-out lines, a first power supply connecting line, or a second power supply connecting line. For example, the plurality of data line lead-out lines are configured to be connected to data signal lines (also referred to as data lines) in the display region in a fan-out wiring manner. For example, the plurality of scan connecting lines are configured to be connected to scan signal lines in the display region in a fan-out wiring manner. For example, the plurality of touch lead-out lines are configured to be connected to touch signal lines (e.g., touch driving signal TX lines and touch induction signal RX lines) in the frame region in a fan-out wiring manner, and the touch signal lines are configured to be connected to touch electrodes in the display region. For example, the first power supply connecting line is configured to be connected to a first power supply line (VDD) capable of providing a high voltage in the display region, and the second power supply connecting line is configured to be connected to a second power supply line (VSS) capable of providing a low voltage in the frame region. The embodiment of the present disclosure is not limited thereto.

[0072] In one exemplary embodiment, as shown in FIG. 5, the folding region 202 may include a composite insulating layer having a recessed groove configured to allow a portion of the binding region 200 to be folded onto the back surface of the display region 100. For example, as shown in FIG. 5, the folding region may include: 3rd direction DR3 The second wiring region 203 and the composite circuit region 204 may be bent at a single curvature in the bending region 202, and the surfaces of the second wiring region 203 and the composite circuit region 204 may be inverted, i.e., the upward-facing surfaces of the second wiring region 203 and the composite circuit region 204 may be turned to face downward by bending the bending region 202, and the third direction DR3 and the first direction DR1 may intersect. For example, when the bending region 202 is bent, the second wiring region 203 and the composite circuit region 204 may overlap with the display region 100 in the third direction DR3 (i.e., the thickness direction of the display panel).

[0073] In one exemplary embodiment, the composite circuit region may include an anti-static region, an integrated circuit (IC) region, and a bind electrode region, which are arranged in this order along the first direction DR1 (i.e., the direction away from the display region 100). For example, the anti-static region may include an anti-static circuit configured to prevent electrostatic damage to the display substrate by removing static electricity. For example, the integrated circuit region may include a touch and display driver integration (TDDI) configured to be connected to a plurality of data line leads. For example, the bind electrode region may include a plurality of bond pads configured to be bound and connected to an external flexible printed circuit (FPC). However, the embodiments of the present disclosure are not limited thereto.

[0074] In one exemplary embodiment, the second wiring region may include a plurality of data line leads drawn out in a fan-out wiring manner, a plurality of touch lead lines drawn out in a fan-out wiring manner, etc. The embodiment of the present disclosure is not limited thereto.

[0075] In one exemplary embodiment, as shown in FIGS. 4 and 6A, the second wiring region 203 may include a first sub-region 400, and a second sub-region 404 and a third sub-region 405 located on either side of the first sub-region 400 along the second direction DR2. The second wiring region 203 may have a centerline CL extending in the first direction DR1. For example, the second sub-region 404 and the third sub-region 405 may be arranged symmetrically with respect to the centerline CL. The centerline CL extends in the first direction DR1 and is parallel to the second wiring region 203 (or Bind area 200 ) may be a straight line equally dividing the second direction DR2 and the first direction DR1. The second direction DR2 and the first direction DR1 intersect. FIG. 4 shows an example in which the second sub-region 404, the first sub-region 400, and the third sub-region 405 are arranged in this order along the second direction DR2. The embodiments of the present disclosure are not limited thereto.

[0076] 4 and 6A, the first sub-region 400 may include a second hole region 402, and a first hole region 401 and a third hole region 403 located on both sides of the second hole region 402 along the second direction DR2. The second wiring region 203 may have a center line CL extending in the first direction DR1. The first hole region 401 is provided with a second through hole 501, the second hole region 402 is provided with a first through hole 503, the third hole region 403 is provided with a dummy hole 505, and the first through hole 503 is provided with a dummy hole 506. center line CL The center line CL extends in the first direction DR1 and is aligned with the second wiring region 203 (or Bind area 200 ) may be a straight line equally dividing the second direction DR2 and the first direction DR1. The second direction DR2 and the first direction DR1 intersect. FIG. 4 shows an example in which the first hole region 401, the second hole region 402, and the third hole region 403 are provided in this order along the second direction DR2. The embodiments of the present disclosure are not limited thereto.

[0077] In one exemplary embodiment, the first through-hole 503 may be a hole that penetrates through a membrane layer.

[0078] In one exemplary embodiment, the second through-hole 501 may be a hole that penetrates through a membrane layer.

[0079] In one exemplary embodiment, the dummy holes 505 may not penetrate any membrane layers, or may be holes that penetrate membrane layers, although the embodiments of the present disclosure are not limited thereto.

[0080] In one exemplary embodiment, the shape of the dummy hole may be the same as the shape of the second through hole, and the size of the second through hole may be the same as the size of the dummy hole. For example, the second through hole 501 and the dummy hole 505 may be arranged symmetrically with respect to the center line CL, where the size may include one or more of the characteristic size of the second through hole in the first direction DR1 and the characteristic size of the second through hole in the second direction DR2.

[0081] In one exemplary embodiment, the first aperture region may have a function of avoiding the second photosensitive element.

[0082] In one exemplary embodiment, the position of the second through-hole may correspond to the position of the second photosensitive element. In this manner, the second through-hole can be formed in the first hole region of the binding region to avoid the second photosensitive element. For example, the second photosensitive element may be a fingerprint recognition assembly, a camera assembly (e.g., a multi-level diffractive lens (MDL)), an infrared sensor, or the like. The embodiments of the present disclosure are not limited thereto.

[0083] In one exemplary embodiment, in a plane parallel to the display panel, the shape of the second through-holes and the shape of the dummy holes may be selected from any of a rectangle, a rectangle with rounded corners, an ellipse, a polygon, and a circle. For example, as shown in FIGS. 4 and 6A, the shape of the second through-holes 501 and the shape of the dummy holes 505 may be a rectangle with rounded corners. However, the embodiment of the present disclosure is not limited thereto.

[0084] For example, if the shape of the second through hole and the shape of the dummy hole are both rounded rectangles, the size of the rounded rectangle may include the length of the rounded rectangle (e.g., the characteristic size of the rounded rectangle in the first direction DR1) and the width (e.g., the characteristic size of the rounded rectangle in the second direction DR2). For example, if the shape of the second through hole and the shape of the dummy hole are both circular, the size of the circle may include the diameter of the circle (e.g., the characteristic size of the circle in the first direction DR1 or the second direction DR2). For example, if the shape of the second through hole and the shape of the dummy hole are both elliptical, the size of the ellipse may include the major axis of the ellipse (e.g., the characteristic size of the ellipse in the first direction DR1) and the minor axis of the ellipse (e.g., the characteristic size of the ellipse in the second direction DR2).

[0085] In one exemplary embodiment, as shown in FIGS. 4 and 6A, the shape of the second through hole 501 and the shape of the dummy hole 505 are assumed to be rectangular with rounded corners. The length of the rounded rectangle in the first direction DR1 may be approximately 2 millimeters (mm) to 15 mm, and the width of the rounded rectangle in the second direction DR2 may be approximately 2 mm to 5 mm. For example, the length of the rounded rectangle in the first direction may be approximately 7.3 mm or 10 mm. For example, the width of the rounded rectangle in the second direction DR2 may be approximately 3 mm or 4.2 mm. Here, the length may refer to the feature size in the first direction DR1, and the width may refer to the feature size in the second direction DR2. The embodiments of the present disclosure are not limited thereto.

[0086] In one exemplary embodiment, the second through-holes 501 and the dummy holes 505 are circular, and the diameter of the circle may be approximately 2 mm to 5 mm. For example, the diameter of the circle may be approximately 3 mm or 3.6 mm. The embodiment of the present disclosure is not limited thereto.

[0087] In one exemplary embodiment, the second aperture region may function to avoid the first photosensitive element.

[0088] In one exemplary embodiment, the position of the first through-hole may correspond to the position of the first photosensitive element. In this manner, by opening the first through-hole in the binding region, the first photosensitive element can be avoided. For example, the first photosensitive element may be a fingerprint recognition assembly, a camera assembly, an infrared sensor, or the like. However, the embodiments of the present disclosure are not limited thereto.

[0089] In one exemplary embodiment, in a plane parallel to the display panel, the shape of the first through hole and the shape of the second through hole may be selected from one or more of a circle, a rectangle, a rounded rectangle, an ellipse, and a polygon.

[0090] In one exemplary embodiment, the shape of the first through-hole 503 in a plane parallel to the display panel may be selected from the following: a circle, a rectangle, a rounded rectangle, an ellipse, and a polygon. For example, as shown in FIGS. 4 and 6A, the shape of the first through-hole 503 may be a circle.

[0091] In one exemplary embodiment, the first through hole has a circular shape, and the diameter of the circle may be about 2 mm to 5 mm. For example, the diameter of the circle may be about 3 mm or 3.6 mm, etc. However, the embodiments of the present disclosure are not limited thereto.

[0092] In one exemplary embodiment, the first hole region may further have the function of placing wiring, and the wiring is connected to the lead-out line in the first wiring region.

[0093] 6A to 8, the first hole region 401 may further include a plurality of first wirings L1 extending in the first direction DR1 and a plurality of second wirings L2 extending in the first direction DR1, the first wirings L1 being located on both sides of the second through-hole 501 along the second direction DR2, wherein the length of the first wirings L1 is greater than the length of the second wirings L2, and the width w1 of the first wirings L1 is greater than the width w2 of the second wirings L2. Here, the width of the wirings may refer to the characteristic size in the second direction DR2, and the length of the wirings may refer to the characteristic size in the first direction DR1. In this way, by making the width of the relatively long wiring (e.g., the first wiring L1) of the wirings on both sides of the second through hole relatively wide and making the width of the relatively short wiring (e.g., the second wiring L2) relatively narrow, the overall resistance of the relatively long wiring (e.g., the first wiring L1) can be reduced, thereby reducing the load on the relatively long wiring (e.g., the first wiring L1), and ensuring that the resistance of the wirings on both sides of the second through hole changes uniformly and that the loads are relatively balanced.

[0094] In one exemplary embodiment, as shown in FIGS. 6A to 8, the width w1 of the first wiring L1 may be approximately 4.5 micrometers to 6.5 micrometers, and the width w2 of the second wiring L2 may be approximately 2.5 micrometers to 4.4 micrometers. For example, the width w1 of the first wiring L1 may be approximately 5.4 micrometers, and the width w2 of the second wiring L2 may be approximately 3.4 micrometers. Here, the width of the wiring may refer to the feature size in the second direction. The embodiments of the present disclosure are not limited in this respect.

[0095] 6A to 8, in the second direction DR2, the pitch pitch1 between adjacent first wirings L1 and the pitch pitch2 between adjacent second wirings L2 may be the same. The pitch between adjacent wirings (which may also be referred to as the center distance) may refer to the distance in the second direction DR2 between the center points of two adjacent wirings, or may refer to the distance in the second direction DR2 between the sides on the same side of two adjacent wirings.

[0096] 6A to 8, in the second direction DR2, at least one of the pitch pitch1 between adjacent first wirings L1 and the pitch pitch2 between adjacent second wirings L2 may be approximately 16 micrometers to 20 micrometers. For example, the pitch pitch1 between adjacent first wirings L1 and the pitch pitch2 between adjacent second wirings L2 may both be 18 micrometers. The embodiment of the present disclosure is not limited thereto.

[0097] In one exemplary embodiment, the first wiring L1 and the second wiring L2 may be a plurality of data line leads drawn out in a fan-out wiring manner, a plurality of touch lead lines drawn out in a fan-out wiring manner, etc. The embodiment of the present disclosure is not limited thereto.

[0098] In one exemplary embodiment, the third hole region may further have the function of placing wiring, which is connected to the lead-out line in the first wiring region.

[0099] 6A , the third hole region 403 may further include a plurality of third wirings L3 extending in the first direction DR1 and a plurality of fourth wirings L4 extending in the first direction DR1, the plurality of third wirings L3 being located on both sides of the dummy holes 505 along the second direction DR2, wherein the length of the third wirings L3 is greater than the length of the fourth wirings L4, the width of the third wirings L3 is greater than the width of the fourth wirings L4, the third wirings L3 and the first wirings L1 may be arranged symmetrically with respect to the center line CL, and the fourth wirings L4 and the second wirings L2 may be arranged symmetrically with respect to the center line CL. Here, the width of the wirings may refer to the feature size in the second direction DR2, and the length of the wirings may refer to the feature size in the first direction DR1. In this way, by making the width of the relatively long wiring (e.g., the third wiring L3) of the wirings on both sides of the dummy hole relatively wide and making the width of the relatively short wiring (e.g., the fourth wiring L4) relatively narrow, the overall resistance of the relatively long wiring (e.g., the third wiring L3) can be reduced, thereby reducing the load on the relatively long wiring (e.g., the third wiring L3), and ensuring that the resistances of the wirings on both sides of the dummy hole change uniformly and that the loads are relatively balanced. Furthermore, since the third wiring L3 and the first wiring L1 are arranged symmetrically with respect to the center line CL, and the fourth wiring L4 and the second wiring L2 are arranged symmetrically with respect to the center line CL, it can be ensured that the resistances of the wirings in the second wiring region change uniformly.

[0100] In one exemplary embodiment, the width of the third wiring L3 may be the same as the width of the first wiring L1, for example, the width of the third wiring L3 may be approximately 4.5 micrometers to 6.5 micrometers. For example, the width of the third wiring L3 may be approximately 5.4 micrometers. Here, the width of the wiring may refer to the feature size in the second direction. The embodiments of the present disclosure are not limited thereto.

[0101] In one exemplary embodiment, the width of the fourth wiring L4 may be the same as the width of the second wiring L2. For example, the width of the fourth wiring L4 may be approximately 2.5 micrometers to 4.4 micrometers. For example, the width of the fourth wiring L4 may be approximately 3.4 micrometers. Here, the width of the wiring may refer to the feature size in the second direction. The embodiments of the present disclosure are not limited thereto.

[0102] In one exemplary embodiment, the pitch between adjacent third wirings L3 and the Between the first wiring L1 The pitch between adjacent fourth wirings L4 and the pitch between adjacent second wirings L2 may be the same. The pitch between adjacent fourth wirings L4 and the pitch between adjacent second wirings L2 may be the same. The pitch between adjacent wirings (which may also be referred to as the center distance) may refer to the distance in the second direction DR2 between the center points of two adjacent wirings, or may refer to the distance in the second direction DR2 between sides on the same side of two adjacent wirings.

[0103] In one example embodiment, in the second direction DR2, at least one of the pitch between adjacent third wirings L3 and the pitch between adjacent fourth wirings L4 may be approximately 16 micrometers to 20 micrometers. For example, the pitch between adjacent third wirings L3 and the pitch between adjacent fourth wirings L4 may both be 18 micrometers. The embodiment of the present disclosure is not limited thereto.

[0104] In one exemplary embodiment, the third wiring L3 and the fourth wiring L4 may be a plurality of data line leads drawn out in a fan-out wiring manner, a plurality of touch lead lines drawn out in a fan-out wiring manner, etc. The embodiment of the present disclosure is not limited thereto.

[0105] In one exemplary embodiment, as shown in FIG. 6A, the second subregion 404 may have a fifth wiring L5 extending in the first direction DR1, and the third subregion 405 may have a sixth wiring L6 extending in the first direction DR1, and the fifth wiring L5 and the sixth wiring L6 may be arranged symmetrically with respect to the center line CL.

[0106] In one exemplary embodiment, the width of the sixth wiring L6 and the width of the fifth wiring L5 may be the same. For example, the width of the sixth wiring L6 and the width of the fifth wiring L5 may be approximately 2 micrometers to 7 micrometers. For example, the width of the sixth wiring L6 and the width of the fifth wiring L5 may be approximately 5.4 micrometers. The embodiment of the present disclosure is not limited thereto.

[0107] In one exemplary embodiment, the pitch between adjacent sixth wirings L6 and the pitch between adjacent fifth wirings L5 may be the same. For example, in the second direction DR2, at least one of the pitch between adjacent sixth wirings L6 and the pitch between adjacent fifth wirings L5 may be approximately 16 micrometers to 20 micrometers. For example, the pitch between adjacent sixth wirings L6 and the pitch between adjacent fifth wirings L5 may both be 18 micrometers. The pitch between adjacent wirings (which may also be referred to as the center distance) may refer to the distance in the second direction DR2 between the center points of two adjacent wirings, or may refer to the distance in the second direction DR2 between the sides of two adjacent wirings on the same side. The embodiment of the present disclosure is not limited thereto.

[0108] 4 , the display panel may further include dummy wiring, which may include at least one of a second dummy wiring 502 located within the first hole region 401 and surrounding the second through hole 501, and a first dummy wiring 504 located within the second hole region 402 and surrounding the first through hole 503. In this manner, arranging the dummy wiring around the through holes reduces the risk of crack defects around the through holes during the drilling process during the display panel manufacturing process, avoids adverse effects on normal wiring around the through holes, and increases the yield of products. The embodiments of the present disclosure are not limited thereto.

[0109] For example, if the dummy hole does not penetrate any film layer, a third dummy trace may be arranged around the dummy hole. Alternatively, if the dummy hole may be a hole that penetrates a film layer, a third dummy trace may not be arranged around the dummy hole. Alternatively, if the dummy hole may be a hole that penetrates a film layer, a third dummy trace may be arranged around the dummy hole. This reduces the risk of crack defects around the dummy hole during the drilling process, avoids adverse effects on normal traces around the through hole, and increases the yield of products. The embodiments of the present disclosure are not limited thereto.

[0110] In one exemplary embodiment, as shown in FIG. 4, the shape of the first dummy wiring 504 is: The shape of the first through hole 503 The embodiments of the present disclosure are not limited in this respect.

[0111] 4, the shape of the second dummy wiring 502 may be the same as the shape of the second through hole 501. The embodiment of the present disclosure is not limited thereto.

[0112] In one exemplary embodiment, the dummy wiring may include one or more of a continuous closed wiring and a discontinuous non-closed wiring. For example, in the case where the dummy wiring includes a discontinuous non-closed wiring, the dummy wiring may include a plurality of dummy wiring line segments and an intermittent portion located between two adjacent dummy wiring lines. However, the embodiment of the present disclosure is not limited thereto.

[0113] In one exemplary embodiment, as shown in FIG. 4, the first dummy wiring 504 may be a continuous wiring. Alternatively, as shown in FIGS. 6B and 6C, the first dummy wiring 504 may be a discontinuous wiring, and the first dummy wiring 504 may include a plurality of first dummy wiring segments 504-1 and a first intermittent portion 504-2 located between two adjacent first dummy wiring segments 504-1. While FIGS. 6B and 6C illustrate a schematic example of eight first dummy wiring segments 504-1 and four first intermittent portions 504-2 in the first dummy wiring 504, this does not represent the actual number of first dummy wiring segments and the actual number of first intermittent portions. Furthermore, FIGS. 6B and 6C illustrate a schematic example of the first dummy wiring 504 including a combination of continuous dummy closed wirings and discontinuous dummy wirings. However, the embodiments of the present disclosure are not limited thereto.

[0114] 6C , the first gap 504-2 may include a first sub-mark structure 61. For example, the first sub-mark structure 61 may include, but is not limited to, one or more of an inverted "T" shape, a rectangular structure, or a cross structure. The embodiments of the present disclosure are not limited thereto.

[0115] 6C , the first through-hole 503 may include a second sub-mark structure 62. For example, the second sub-mark structure 62 may include, but is not limited to, one or more of an inverted "T" shape, a rectangular structure, or a cross structure. The embodiments of the present disclosure are not limited thereto.

[0116] 6B and 6C, a first cutting line 71 may be provided outside the second sub-mark structure, and the shape of the first cutting line 71 is the same as the outline of the first through-hole 503. After the film layer manufacturing process of the display motherboard is completed, a cutting device can cut the display motherboard along the first cutting line 71 to form the first through-holes 503 in the plurality of display panels.

[0117] In one exemplary embodiment, as shown in FIG. 4, the second dummy wiring 502 may be a continuous wiring. Alternatively, as shown in FIGS. 6D and 6E, the second dummy wiring 502 may be a discontinuous wiring, and the second dummy wiring 502 may include a plurality of second dummy wiring segments 502-1 and a second intermittent portion 502-2 located between two adjacent second dummy wiring segments 502-1. FIGS. 6D and 6E schematically illustrate the second dummy wiring 502 by way of example, with eight second dummy wiring segments 502-1 and four second intermittent portions 502-2. However, this does not represent the actual number of second dummy wiring segments and the actual number of second intermittent portions. Also, FIGS. 6D and 6E schematically illustrate the second dummy wiring 502 by way of example, with the second dummy wiring 502 including a combination of continuous dummy closed wirings and discontinuous dummy wirings. However, the embodiments of the present disclosure are not limited thereto.

[0118] 6E, the second gap 502-2 may include a third sub-mark structure 63. For example, the third sub-mark structure 63 may include, but is not limited to, one or more of an inverted "T" shape, a rectangular structure, or a cross structure. The embodiments of the present disclosure are not limited thereto.

[0119] 6E, the second through-hole 501 may include a fourth sub-mark structure 64. For example, the fourth sub-mark structure 64 may include, but is not limited to, one or more of an inverted "T" shape, a rectangular structure, or a cross structure. The embodiments of the present disclosure are not limited thereto.

[0120] 6D and 6E, a second cutting line 72 may be provided outside the fourth sub-mark structure 64, and the shape of the second cutting line 72 is the same as the outline of the second through-hole 501. After the film layer manufacturing process of the display motherboard is completed, a cutting device can cut the display motherboard along the second cutting line 72 to form the second through-holes 501 in the plurality of display panels.

[0121] In one exemplary embodiment, the width of the second dummy wiring 502 may be the same as the width of the first dummy wiring 504. Here, the width of the wiring may refer to the feature size in the second direction DR2.

[0122] In one exemplary embodiment, the width of the second dummy wiring 502 and the width of the first dummy wiring 504 may be approximately 3 micrometers to 8 micrometers. For example, the width of the second dummy wiring 502 and the width of the first dummy wiring 504 may be approximately 5.4 micrometers. The embodiment of the present disclosure is not limited thereto.

[0123] In one example embodiment, the binding area may be an irregular binding area, where an irregular binding area may refer to a binding area that differs from a binding area having a regular shape (e.g., a rectangular binding area).

[0124] In one exemplary embodiment, as shown in FIG. 6A, in a plane parallel to the display panel, the contour shape of the binding area 200 may include a first edge 200-1 (e.g., the top edge), a second edge 200-2 (e.g., the bottom edge arranged opposite the top edge), a third edge 200-3 (e.g., the left edge), and a fourth edge 200-4 (e.g., the right edge arranged opposite the left edge) that form an irregular shape.

[0125] In one exemplary embodiment, as shown in FIG. 6A , the first edge 200-1 may extend in the second direction DR2 and be located closer to the display area 100, the second edge 200-2 may extend in the second direction DR2 and be located farther from the display area 100 than the first edge 200-1, and the third edge 200-3 may extend in the first direction DR1, First direction DR1The fourth edge 200-4 may extend in the first direction DR1, and the fourth edge 200-4 may be First direction DR1 The first and second directions DR1 and DR2 intersect. In FIG. 6A, the bottom edge of the display area 100 (i.e., the edge closer to the bind area 200) is aligned with the top edge of the bind area 200 (i.e., the edge closer to the display area 100). 1st Edge 200-1 ) can be overlapped.

[0126] An embodiment of the present disclosure further provides a display device, which may include the display panel and the first photosensitive element in one or more of the above exemplary embodiments, and the arrangement position of the first photosensitive element corresponds to the arrangement position of the first through-hole.

[0127] In one exemplary embodiment, the display device may further include a second photosensitive element, and the second wiring region may further include a second through hole located on the second direction side of the first through hole, and the arrangement position of the second photosensitive element corresponds to the arrangement position of the second through hole.

[0128] 9 is a structural schematic diagram of a display device according to an exemplary embodiment of the present disclosure. As shown in FIG. 9, in one exemplary embodiment, the display device may include a display panel, a first photosensitive element 600, and a second photosensitive element (not shown). The display panel may include a display area 100 and a bind area 200 located on a first direction DR1 side of the display area 100. The bind area 200 may include a first wiring area 201, a bending area 202, a second wiring area 203, and a composite circuit area 204, which are arranged in this order along the first direction DR1 (i.e., the direction away from the display area 100). The second wiring region 203 may include a first sub-region and a second sub-region (not shown) and a third sub-region (not shown) located on both sides of the first sub-region in the second direction DR2, and the first sub-region may include a second hole region and a first hole region (not shown) and a third hole region (not shown) located on both sides of the second hole region in the second direction DR2, and the first hole region has a second through-hole (not shown) formed therein, a first through-hole 503 formed therein, and a dummy hole (not shown) formed in the third hole region. The position of the first photosensitive element 600 may correspond to the position of the first through-hole 503, and the position of the second photosensitive element may correspond to the position of the second through-hole. In this way, by arranging the first through-holes symmetrically about the centerline in the binding area of ​​the display panel, it is possible to ensure uniformity of the wiring load in the second wiring area, thereby ensuring a consistent wiring impedance in the display panel and avoiding wiring pressure caused by wiring being concentrated on one side. This improves the display effect. In addition, by arranging the photosensitive elements in correspondence with the through-holes in the binding area, it is not necessary to open holes in the display area, which is advantageous for realizing a full screen.

[0129] In one exemplary embodiment, the first photosensitive element may be a fingerprint recognition assembly, a camera assembly, an infrared sensor, or the like. For example, the first photosensitive element may include a camera assembly, and the camera assembly may be an MDL element, for example. The embodiments of the present disclosure are not limited in this regard.

[0130] In one exemplary embodiment, the second photosensitive element may be a fingerprint recognition assembly, a camera assembly, an infrared sensor, or the like. For example, the second photosensitive element may include a fingerprint recognition assembly. For example, the fingerprint recognition assembly may be an optical fingerprint recognition assembly, an ultrasonic fingerprint recognition assembly, or the like, and the embodiments of the present disclosure are not limited thereto.

[0131] In one exemplary embodiment, the display device may be, but is not limited to, an OLED display device or an AMOLED (active-matrix organic light-emitting diode) display device, etc., although embodiments of the present disclosure are not limited in this regard.

[0132] In one exemplary embodiment, the display device may be any product or component having a display function, such as, but not limited to, a mobile phone, a tablet PC, a television, a display, a notebook PC, a digital photo frame, or a navigation system, although the embodiments of the present disclosure are not limited thereto.

[0133] The above description of the display device embodiment is similar to the description of the display panel embodiment described above, and has similar beneficial effects as the display panel embodiment. For technical details not disclosed in the display device embodiment of the present disclosure, those skilled in the art can refer to the description of the display panel embodiment of the present disclosure to understand them, and will not be repeated here.

[0134] Although the embodiments disclosed in the present disclosure are as above, the contents of the description are merely embodiments adopted for understanding the present disclosure and are not intended to limit the present disclosure. Those skilled in the art may make modifications and changes in the implementation form and details without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present disclosure should be in accordance with the scope described in the claims. [Explanation of symbols]

[0135] 10 Base board 11A transistor 11B storage capacitor 12 Drive circuit layer 13 Light-emitting structure layer 14 Package Layer 31 Anode 32 Pixel Definition Layer 33 Organic light-emitting layer 34 Cathode 41 First Package Layer 42 Second Package Layer 43 Third Package Layer

Claims

1. A display panel comprising: a display area; and a bind area located on a first direction side of the display area, wherein the display area comprises a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected to the plurality of sub-pixels, and the bind area comprises a plurality of data line leads connected to the plurality of data lines and a plurality of pins connected to the plurality of data line leads, the plurality of pins being located on sides of the plurality of data line leads away from the display area, the binding region further includes a first wiring region, a bending region, and a second wiring region, which are sequentially arranged along a first direction, the second wiring region including a first through hole, the first through hole being located between the plurality of data line leads, and the first through hole being configured to correspond to a first photosensitive element; the second wiring region includes a first sub-region, and the first through-hole is located in the first sub-region; the second wiring region further includes a second through hole located on a side of the first through hole along a second direction, the first sub-region includes a first hole region, a second hole region, and a third hole region that are sequentially arranged along the second direction, the first through-hole being located in the second hole region, and the second through-hole being located in the first hole region; a display panel, wherein the first hole region includes a plurality of first wirings extending in the first direction and a plurality of second wirings extending in the first direction, the plurality of first wirings and the plurality of second wirings being located on both sides of the second through hole along the second direction, the length of the first wirings being greater than the length of the second wirings, and the width of the first wirings being greater than the width of the second wirings.

2. A display panel as described in claim 1, wherein the second wiring region has a center line extending in the first direction, and the first through holes are arranged symmetrically with respect to the center line.

3. A display panel as described in claim 2, wherein the second through hole is configured to correspond to a second photosensitive element, and the second direction intersects with the first direction.

4. The display panel of claim 3, wherein the second wiring region further includes a dummy hole located on a side of the first through hole that is away from the second through hole along the second direction, and the dummy hole is located in the third hole region.

5. The display panel according to claim 4 , wherein the shape of the dummy holes is the same as the shape of the second through holes, and the size of the second through holes is the same as the size of the dummy holes.

6. The display panel according to claim 5 , wherein the shape of the second through holes and the shape of the dummy holes in a plane parallel to the display panel are selected from the group consisting of a rectangle, a rectangle with rounded corners, an ellipse, a polygon, and a circle.

7. The display panel of claim 6, wherein in a plane parallel to the display panel, the shape of the second through hole is a rounded rectangle, the length of the rounded rectangle in the first direction is 2 mm to 15 mm, and the width of the rounded rectangle in the second direction is 2 mm to 5 mm.

8. The display panel according to claim 1 , wherein the pitch between adjacent first wirings and the pitch between adjacent second wirings in the second direction are the same.

9. 5. The display panel of claim 4, wherein the third hole region further comprises a plurality of third wirings extending in the first direction and a plurality of fourth wirings extending in the first direction, the plurality of third wirings and the plurality of fourth wirings being respectively located on both sides of the dummy hole, the length of the third wirings being greater than the length of the fourth wirings, the width of the third wirings being greater than the width of the fourth wirings, the third wirings and the first wirings being arranged symmetrically with respect to the center line, and the fourth wirings and the second wirings being arranged symmetrically with respect to the center line.

10. 4. The display panel of claim 3, wherein the second wiring region further comprises dummy wiring, the dummy wiring including at least one of a first dummy wiring surrounding the first through hole and a second dummy wiring surrounding the second through hole.

11. The display panel according to claim 10 , wherein the first dummy wiring has the same shape as the first through-hole, and the second dummy wiring has the same shape as the second through-hole.

12. The display panel according to claim 10 , wherein the width of the first dummy wiring is the same as the width of the second dummy wiring.

13. 11. The display panel according to claim 10, wherein the dummy wiring includes a plurality of dummy wiring line segments and an intermittent portion located between two adjacent dummy wiring line segments.

14. The second wiring region further includes:

3. The display panel of claim 2, further comprising a second sub-region and a third sub-region located on either side of the first sub-region along a second direction, the second sub-region and the third sub-region being arranged symmetrically with respect to the center line, and the second direction intersecting the first direction.

15. 15. The display panel of claim 14, wherein the second sub-region includes a fifth wiring extending in a first direction, the third sub-region includes a sixth wiring extending in the first direction, and the fifth wiring and the sixth wiring are arranged symmetrically with respect to the center line.

16. The display panel according to claim 15 , wherein the width of the sixth wiring is the same as the width of the fifth wiring.

17. The display panel of claim 3 , wherein the shape of the first through hole and the shape of the second through hole in a plane parallel to the display panel are selected from one or more of a circle, a rectangle, a rounded rectangle, an ellipse, and a polygon.

18. A display device comprising: a display panel according to any one of claims 1 to 17; and a first photosensitive element, wherein the arrangement position of the first photosensitive element corresponds to the arrangement position of the first through hole.

19. 19. The display device of claim 18, further comprising a second photosensitive element, wherein the second wiring region further comprises a second through hole located on the second direction side of the first through hole, and the position of the second photosensitive element corresponds to the position of the second through hole.

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