Receiving circuit and control method thereof

Abstract

To provide a receiving circuit, a semiconductor memory device, and a control method for the semiconductor memory device that can appropriately detect an input signal.SOLUTION: A receiving circuit 1 includes an amplifier 10 that amplifies an input signal VIN, and a control unit 20 that controls the amplifier 10 such that the amplitude of an output signal V1 becomes smaller when an input signal VIN with an amplitude greater than or equal to a predetermined value is input to the amplifier 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a receiving circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device. [Background technology]

[0002] BACKGROUND ART Known semiconductor memory devices (for example, dynamic random access memories (DRAMs)) include a receiving circuit that includes an amplifier that amplifies a signal input from the outside (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-103098 Summary of the Invention [Problem to be solved by the invention]

[0004] In such a receiving circuit, the greater the amplitude of the input signal, the greater the amplitude of the output signal from the amplifier. However, as the pulse width of the input signal becomes shorter in order to improve the signal transmission speed between the semiconductor memory device and other devices, it may become more difficult for the receiving circuit to properly detect the input signal (its logic level (high level or low level)) with a large amplitude.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a receiving circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device that are capable of appropriately detecting an input signal. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a receiving circuit comprising an amplifier that amplifies an input signal, and a control unit that controls the amplitude of the output signal of the amplifier to be reduced when an input signal having an amplitude greater than a predetermined value is input to the amplifier.

[0007] According to this invention, when an input signal having an amplitude equal to or greater than a predetermined value is input to the amplifier, the amplitude of the output signal of the amplifier is reduced, and the receiver circuit can operate using this small-amplitude output signal. As a result, the receiver circuit can properly detect the logic level of the input signal, even when, for example, a signal having a large amplitude and a short pulse width is input.

[0008] The present invention also provides a semiconductor memory device comprising the receiving circuit of the present invention.

[0009] Furthermore, the present invention provides a method for controlling a semiconductor memory device, wherein a receiving circuit of the semiconductor memory device comprises an amplifier that amplifies an input signal and a control unit, and the control unit controls the amplifier so that the amplitude of the output signal is reduced when an input signal having an amplitude greater than or equal to a predetermined value is input to the amplifier. [Effects of the Invention]

[0010] According to the receiving circuit, the semiconductor memory device, and the control method for the semiconductor memory device of the present invention, it is possible to appropriately detect an input signal. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a receiving circuit according to an embodiment of the present invention. [Figure 2] 1A is a time chart showing the time transition of signals in a receiving circuit according to a comparative example, and FIG. 1B is a time chart showing the time transition of signals in a receiving circuit according to an embodiment. [Figure 3] FIG. 10 is a diagram illustrating an example of the configuration of a receiving circuit according to a first modified example of the present invention. [Figure 4]FIG. 10 is a diagram illustrating an example of the configuration of a receiving circuit according to a second modified example of the present invention. [Figure 5] FIG. 10 is a diagram illustrating an example of the configuration of a receiving circuit according to a third modified example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] FIG. 1 is a block diagram showing an example of the configuration of a receiving circuit 1 according to one embodiment of the present invention. The receiving circuit 1 according to this embodiment is provided in a semiconductor memory device (e.g., a DRAM such as a DDR4 SDRAM (Double-Data-Rate 4 Synchronous Dynamic Random Access Memory)) and is configured to receive a signal input to the semiconductor memory device from an external device. In this embodiment, the receiving circuit 1 includes an amplifier 10 and a control unit 20. Note that, for the sake of simplicity, other well-known components of the semiconductor memory device (e.g., a memory cell array, a power supply circuit, a command decoder, a clock generator, etc.) are not shown here.

[0013] In this embodiment, the amplifier 10 is a differential amplifier having a first input terminal (negative terminal) to which an input signal VIN is input and a second input terminal (positive terminal) to which a predetermined reference signal VREF is input. This allows the amplifier 10 to amplify (inverting amplification in this embodiment) the difference between the voltage of the input signal VIN and the voltage of the reference signal VREF and easily remove common-mode noise. The receiver circuit 1 detects the logical value of the input signal VIN as "1" when the voltage of the input signal VIN is higher than the voltage of the reference signal VREF, and detects the logical value of the input signal VIN as "0" when the voltage of the input signal VIN is lower than the voltage of the reference signal VREF. The amplifier 10 amplifies (inverting amplification in this embodiment) the difference between the voltage of the input signal VIN and the voltage of the reference signal VREF and outputs the amplified signal as an output signal V1. If the semiconductor memory device complies with the DDR4 SDRAM specification, the voltage of the reference signal VREF may be half the input / output voltage (I / O voltage) VDDQ (i.e., VDDQ / 2). The input signal VIN may also be an address signal or a command signal input from the outside.

[0014] When an input signal VIN having an amplitude equal to or greater than a predetermined value is input to the amplifier 10, the control unit 20 controls the amplifier 10 so that the amplitude of the output signal V1 is reduced.

[0015] Furthermore, the control unit 20 may perform control so that, when an input signal VIN having an amplitude equal to or greater than a predetermined value is input to the amplifier 10, the amplitude of the output signal V1 of the amplifier 10 is reduced by increasing the amount of reduction in the amplitude of the output signal V1 of the amplifier 10. This makes it possible to easily reduce the amplitude of the output signal V1 of the amplifier 10 in accordance with the increase in the amount of reduction in the amplitude of the output signal V1 of the amplifier 10, even when an input signal VIN having an amplitude equal to or greater than a predetermined value is input to the amplifier 10.

[0016] Furthermore, when an input signal VIN having an amplitude equal to or greater than a predetermined value is input to the amplifier 10, the control unit 20 may control the amplitude of the output signal V1 of the amplifier 10 to be reduced by increasing the amplitude of a feedback signal that is an inverted signal of the output signal V1 and is added to the output signal V1 of the amplifier 10. This makes it possible to easily reduce the amplitude of the output signal V1 of the amplifier 10 in accordance with the increase in the amplitude of the feedback signal, even when an input signal VIN having an amplitude equal to or greater than a predetermined value is input to the amplifier 10.

[0017] In this embodiment, the control unit 20 includes an inverter circuit 21, a first resistor section 22, a first switch section 23, a second resistor section 24, and one or more (two in this embodiment) other inverter circuits 25 and 26. Here, the inverter circuit 21 is an example of the "logic inversion circuit" of the present invention, and the other inverter circuits 25 and 26 are examples of the "one or more other logic inversion circuits" of the present invention.

[0018] The inverter circuit 21 is configured to receive the output signal V1 of the amplifier 10. One end of the first resistor section 22 is connected to the output of the inverter circuit 21, and the other end is connected to the first switch section 23 and the second resistor section 24.

[0019] The first switch section 23 has one end connected to the other end of the first resistor section 22 and the other end connected to the output of the amplifier 10. The first switch section 23 is configured to be turned on when the amplitude of the input signal V IN is equal to or greater than a predetermined value. In this embodiment, the first switch section 23 is configured to include a transfer transistor, and the input signal V IN is input to each gate terminal of a P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) of the transfer transistor and an N-channel MOSFET of the transfer transistor. In this embodiment, the first switch section 23 is configured to be turned on when the amplitude of the input signal V IN on the side where the logical value of the input signal V IN is "1" (high side) is equal to or greater than a predetermined value, and the P-channel MOSFET of the transfer transistor is turned on when the amplitude of the input signal V IN on the side where the logical value of the input signal V IN is "0" (low side) is equal to or greater than the predetermined value. As a result, the first switch section 23 is turned on when the amplitude of the input signal VIN is equal to or greater than a predetermined value, regardless of whether the logical value of the input signal VIN is 1 or 0. The first switch section 23 may be configured with a circuit other than a transfer transistor.

[0020] The second resistor section 24 is connected in parallel with the first switch section 23 between the other end of the first resistor section 22 and the output of the amplifier 10. Specifically, one end of the second resistor section 24 is connected to the other end of the first resistor section 22, and the other end is connected to the output of the amplifier 10.

[0021] Also, the input terminals of the other inverter circuit 25 are connected to the output terminals of the inverter circuit 21. Further, the input terminals of the other inverter circuit 26 are connected to the output terminals of the other inverter circuit 25. Then, the other inverter circuit 26 logically inverts the signal input from the other inverter circuit 25 and outputs the logically inverted signal as the output signal VOUT of the reception circuit 1. In the present embodiment, by providing the other inverter circuits 25 and 26, it becomes possible to shape the amplitude of the output waveform to a predetermined level (for example, VDDQ / VSSQ, etc.).

[0022] Referring to FIG. 2, the operation of the reception circuit 1 in the present embodiment will be described. FIG. 2(a) is a time chart showing the time transition of signals in the reception circuit according to the comparative example, and (b) is a time chart showing the time transition of signals in the reception circuit 1 according to the present embodiment. Here, a case will be described where a reception circuit in which the first switch section 23 and the second resistance section 24 of the control section 20 are not provided in the reception circuit 1 shown in FIG. 1 is assumed as the reception circuit according to the comparative example.

[0023] In the reception circuit according to the comparative example, when the input signal VIN and the reference signal VREF are input to the amplifier 10, the amplifier 10 amplifies the difference between the voltage of the input signal VIN and the voltage of the reference signal VREF, and outputs the amplified signal as the output signal V1. This output signal V1 is logically inverted in the inverter circuit 21, and the signal output from the inverter circuit 21 is added to the output signal V1 via the first resistance section 22 as a feedback signal. In this case, as shown in FIG. 2(a), the output signal V1 is represented by a waveform with a maximum amplitude A1 (0 < A1) based on the voltage of the reference signal VREF. By the way, when the pulse width of the input signal VIN (in the example shown in FIG. 2(a), the high-level pulse width of the input signal VIN) becomes short, the output signal V1 may change state before the voltage of the output signal V1 reaches the saturation voltage (in the example shown in FIG. 2(a), VREF - A1). In this case, since the low-level (L-level) pulse width of the output signal V1 becomes short, there is a possibility that it becomes difficult to detect the high level of the input signal VIN in the reception circuit.

[0024] On the other hand, in the receiving circuit 1 according to the present embodiment, when the amplitude of the input signal VIN is less than a predetermined value, the first switch section 23 is turned off. Therefore, the signal output from the inverter circuit 21 is added to the output signal V1 as a feedback signal via the first resistor section 22 and the second resistor section 24. That is, when the resistance value of the first resistor section 22 is R1 and the resistance value of the second resistor section 24 is R2, the feedback resistance when the amplitude of the input signal VIN is less than the predetermined value is R1 + R2. Further, in the receiving circuit 1 according to the present embodiment, when the amplitude of the input signal VIN is greater than or equal to the predetermined value, the first switch section 23 is turned on. Therefore, the signal output from the inverter circuit 21 is added to the output signal V1 as a feedback signal via the first resistor section 22 and the first switch section 23. That is, the feedback resistance when the amplitude of the input signal VIN is greater than or equal to the predetermined value is R1.

[0025] That is, in the receiving circuit 1 according to the present embodiment, when the amplitude of the input signal VIN becomes greater than or equal to a predetermined value (here, the value at which the first switch section 23 is turned on), the feedback resistance becomes smaller (that is, the amplitude of the feedback signal added to the output signal V1 of the amplifier 10 becomes larger). Therefore, it becomes possible to reduce the amplitude of the output signal V1 of the amplifier 10. As a result, as shown in FIG. 2(b), even when the pulse width of the input signal VIN (in the example shown in FIG. 2(b), the pulse width of the high level of the input signal VIN) becomes short, it becomes possible to invert the state of the output signal V1 after the voltage of the output signal V1 reaches the saturation voltage (in the example shown in FIG. 2(b), VREF - A2 (0 < A2 < A1)). In this case, since the pulse width of the low level (L level) of the output signal V1 becomes longer than that in the comparative example shown in FIG. 2(a), it is possible to appropriately detect the high level of the input signal VIN in the receiving circuit 1.

[0026] As described above, according to the receiver circuit 1, semiconductor memory device, and control method thereof of this embodiment, when an input signal VIN having an amplitude equal to or greater than a predetermined value is input to the amplifier 10, the amplitude of the output signal V1 of the amplifier 10 decreases, and the receiver circuit 1 can operate using this small-amplitude output signal V1. As a result, the receiver circuit 1 can properly detect the logic level of the input signal VIN even when, for example, a signal having a large amplitude and a short pulse width is input.

[0027] 3 is a diagram showing an example of the configuration of a receiver circuit 1 according to a first modified example of the present invention. In this modified example, the control unit 20 of the receiver circuit 1 is different from the above-described embodiment in that a second switch unit 27 and a third resistor unit 28 are provided instead of the first switch unit 23. The second switch unit 27 is an example of each of the "second switch unit" and "switch unit" of the present invention.

[0028] The second switch section 27 has one end connected to the other end of the first resistor section 22, and the other end connected to the output of the amplifier 10. The third resistor section 28 has one end connected to the input signal VIN, and the other end connected to the second switch section 27.

[0029] Furthermore, the second switch section 27 is configured to be turned on when the amplitude of the input signal VIN is equal to or greater than a predetermined value. In this embodiment, the second switch section 27 is configured to include a transfer transistor, and the input signal VIN is input to the gate terminals of the P-channel MOSFET of the transfer transistor and the N-channel MOSFET of the transfer transistor via the third resistor section 28. In this embodiment, when the amplitude of a signal on the side (high side) of a logic value "1" at the other end of the third resistor section 28 is equal to or greater than a predetermined value, the N-channel MOSFET of the transfer transistor is turned on, and when the amplitude of a signal on the side (low side) of a logic value "0" at the other end of the third resistor section 28 is equal to or greater than a predetermined value, the P-channel MOSFET of the transfer transistor is turned on. As a result, the second switch section 27 is turned on when the amplitude of the signal is equal to or greater than a predetermined value, regardless of whether the logical value of the signal on the other end of the third resistor section 28 is "1" or "0." Note that the second switch section 27 may be configured with a circuit other than a transfer transistor.

[0030] In the above-described embodiment, the first switch section 23 is directly controlled by the input signal V IN , and therefore the first switch section 23 can become operable before the output signal V1 is output from the amplifier 10. On the other hand, in this modification, the input signal V IN is input to the second switch section 27 via the third resistor section 28. Therefore, for example, the larger the resistance value of the third resistor section 28, the more delayed the timing at which the second switch section 27 turns on (i.e., the timing at which the amplitude of the output signal V1 is reduced). As a result, for example, by adjusting the resistance value of the third resistor section 28 in accordance with the response time of the amplifier 10 (the time required for the amplification process), it becomes possible to appropriately reduce the amplitude of the output signal V1 while taking the response time of the amplifier 10 into consideration.

[0031] 4 is a diagram showing an example of the configuration of a receiving circuit 1 according to a second modified example of the present invention. In this modified example, the control unit 20 of the receiving circuit 1 has a configuration that combines the above-described embodiment and first modified example, which is different from the above-described embodiment and first modified example.

[0032] In this modified example, compared to the above-described embodiment and the first modified example, the period during which at least one of the first switch section 23 and the second switch section 27 is on is longer (i.e., the period during which the amplitude of the output signal V1 is reduced is longer), so that the receiving circuit 1 can operate using a small-amplitude output signal V1 for a longer period.

[0033] The above-described embodiments have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments are intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0034] For example, in the above-described embodiment and each modified example, an input signal VIN such as a command signal and an address signal, and a reference signal VREF are input to the amplifier 10. However, the present invention is not limited to this. For example, a clock signal (input signal) and a complementary signal of the clock signal may be input to the amplifier 10. In this case, as in the above-described embodiment and each modified example, it is possible to appropriately detect the logic level of the clock signal. Furthermore, other signals having a complementary relationship with the clock signal may be input to the amplifier 10. Furthermore, a data signal may be input to the amplifier 10 as the input signal VIN.

[0035] FIG. 5 shows a configuration example of a receiver circuit 1 according to a third modification of the present invention. This modification differs from the above-described embodiment and the first to second modifications in that a complementary signal / VIN of the input signal VIN can be input to the second input terminal (+ terminal) of the amplifier 10 instead of the reference signal VREF. Furthermore, in this modification, the second switch section 27 is configured to include a transfer transistor, as in the first to second modifications, but differs from the first to second modifications in that the reference signal VREF or the complementary signal / VIN is input to each gate terminal of the P-channel MOSFET of the transfer transistor and the N-channel MOSFET of the transfer transistor. That is, in this modification, the second switch section 27 is configured to be turned on when the difference between the voltage of the reference signal VREF and a predetermined reference voltage (e.g., VDDQ / 2) is equal to or greater than the predetermined value, or when the amplitude of the complementary signal / VIN is equal to or greater than a predetermined value.

[0036] In this modification, the second switch section 27 is configured to turn on when the difference between the voltage of the reference signal VREF and a predetermined reference voltage (e.g., VDDQ / 2) is equal to or greater than a predetermined value. Therefore, for example, the greater the difference between the voltage of the reference signal VREF and the reference voltage (e.g., VDDQ / 2) due to noise being added to the reference signal VREF, the greater the voltage of the feedback signal output from the inverter circuit 21 can be. This prevents the operating point of the input signal VIN from approaching the power supply (e.g., VDDQ / VSSQ). Furthermore, in this modification, the second switch section 27 is configured to turn on when the amplitude of the complementary signal / VIN is equal to or greater than a predetermined value. This allows the input capacitances of the input signal VIN and the complementary signal / VIN to be matched. This effectively reduces common-mode noise.

[0037] In addition, in the above-described embodiment and each modification, the semiconductor memory device is a DRAM, but the present invention is not limited to this. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a pSRAM (Pseudo-Static Random Access Memory), a flash memory, or another semiconductor memory device.

[0038] Furthermore, the configurations of the amplifier 10 and the control unit 20 shown in FIGS. 1, 3, and 4 are merely examples, and may be changed as appropriate, or well-known configurations or various other configurations may be adopted. [Explanation of symbols]

[0039] 1...Receiver circuit 10...Amplifier 20...Control unit 21, 25, 26...Inverter circuit 22...1st resistance section 23...First switch section 24…Second resistance section 27...Second switch section 28...Third resistance section VIN: Input signal VREF: Reference signal / VIN: Complementary signal V1: Amplifier output signal

Claims

1. an amplifier including a plurality of input terminals and an output terminal, the amplifier receiving an input signal at any one of the plurality of input terminals and amplifying the input signal to generate an output signal at the output terminal; a control unit that receives the output signal and controls a feedback resistor based on the output signal, the control unit controls the feedback resistance so that the feedback resistance when the amplitude of the input signal is equal to or greater than a predetermined value is smaller than the feedback resistance when the amplitude of the input signal is less than the predetermined value. Receiver circuit.

2. the control unit is configured to reduce the amplitude of the output signal of the amplifier to a saturation voltage when the amplitude of the input signal is equal to or greater than a predetermined value, and to invert the output signal after the output signal reaches the saturation voltage.

2. The receiving circuit according to claim 1.

3. the control unit is further configured to invert the output signal to generate a feedback signal coupled to the output terminal of the amplifier, and when the amplitude of the input signal is equal to or greater than the predetermined value, control the amplitude of the output signal of the amplifier to be reduced by increasing the amplitude of the feedback signal.

2. The receiving circuit according to claim 1.

4. The control unit a logic inversion circuit to which the output signal is input; a first resistor portion having one end connected to the output of the logic inversion circuit; a switch circuit having one end connected to the other end of the first resistor and the other end connected to the output of the amplifier, the switch circuit being turned on when the amplitude of the input signal is equal to or greater than the predetermined value; a second resistor connected in parallel with a switch circuit between the other end of the first resistor and the output terminal of the amplifier, 4. The receiving circuit according to claim 1.

5. the switch circuit includes a transfer transistor; the control unit includes one or more other logic inversion circuits connected in series to the output of the logic inversion circuit; 5. The receiving circuit according to claim 4.

6. The control unit a third resistor unit having one end connected to the input signal and the other end connected to the switch circuit; the switch circuit is turned on when the amplitude of the signal at the other end of the third resistor portion is equal to or greater than the predetermined value.

5. The receiving circuit according to claim 4.

7. the switch circuit includes a first switch section and a second switch section, the input signal is input to a gate terminal of the first switch section, and the input signal that has passed through the third resistor section is input to a gate terminal of the second switch section; 7. The receiving circuit according to claim 6.

8. the input signal and a reference signal are input to the plurality of input terminals of the amplifier; the switch circuit includes a first switch section and a second switch section, the input signal is input to a gate terminal of the first switch section, and the reference signal is input to a gate terminal of the second switch section; the second switch unit is conductive when a difference between a voltage of the reference signal and a predetermined reference voltage is equal to or greater than the predetermined value.

5. The receiving circuit according to claim 4.

9. The voltage of the reference signal is half of the input / output voltage.

9. The receiving circuit according to claim 8.

10. the input signal and a complementary signal of the input signal are input to the plurality of input terminals of the amplifier; the switch circuit includes a first switch section and a second switch section, the input signal is input to a gate terminal of the first switch section, and the complementary signal is input to a gate terminal of the second switch section; the second switch unit is conductive when the amplitude of the complementary signal is equal to or greater than the predetermined value.

5. The receiving circuit according to claim 4.

11. The input signal is an address signal or a command signal.

2. The receiving circuit according to claim 1.

12. the control unit is configured to adjust the pulse width of the output signal when the pulse width of the input signal becomes shorter so that the pulse width of the output signal when the amplitude of the input signal is equal to or greater than the predetermined value becomes equal to or greater than the pulse width when the amplitude of the input signal is less than the predetermined value.

2. The receiving circuit according to claim 1.

13. A method for controlling a receiving circuit, comprising: an amplifier provided in the receiving circuit receiving and amplifying an input signal to generate an output signal; a step in which a control unit provided in the receiving circuit receives the output signal and controls a feedback resistance based on the output signal, wherein the control unit controls the feedback resistance so that the feedback resistance when the amplitude of the input signal is equal to or greater than a predetermined value is smaller than the feedback resistance when the amplitude of the input signal is less than the predetermined value; A method for controlling a receiving circuit.

14. a step of the control unit reducing the amplitude of the output signal of the amplifier to a saturation voltage when the amplitude of the input signal is equal to or greater than a predetermined value, and inverting the output signal after the output signal reaches the saturation voltage, The control method for a receiving circuit according to claim 13.

15. The method further includes the steps of: the control unit inverting the output signal to generate a feedback signal that is coupled to the output terminal of the amplifier; and when the amplitude of the input signal is equal to or greater than the predetermined value, the control unit increasing the amplitude of the feedback signal and decreasing the amplitude of the output signal of the amplifier. The control method for a receiving circuit according to claim 13.

16. The method further includes a step in which the amplifier receives a reference signal, and the control unit controls the feedback resistance when a difference between a voltage of the reference signal and a predetermined reference voltage is equal to or greater than the predetermined value to be smaller than the feedback resistance when the difference between the voltage of the reference signal and the predetermined reference voltage is less than the predetermined value. The control method for a receiving circuit according to claim 13.

17. The method further includes a step in which the amplifier receives a complementary signal of the input signal, and the control unit controls the feedback resistance when the amplitude of the complementary signal is equal to or greater than the predetermined value to be smaller than the feedback resistance when the amplitude of the complementary signal is less than the predetermined value. The control method for a receiving circuit according to claim 13.

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