High-frequency amplifier

Abstract

To provide a high frequency amplifier capable of securely reducing third-order intermodulation distortion (IMD3) while assuring high gain.SOLUTION: In a high frequency amplifier, bias power supply is supplied through the drain of a second transistor 102 to a lower stage gate bias circuit 501 for supplying gate bias to a first transistor 101 and to an upper stage gate bias circuit 502 for supplying gate bias to the second transistor 102. In the upper stage gate bias circuit 502, an upper stage resistor 201 and a lower stage resistor 202 are connected in series between a bias power supply terminal 14 and the ground, and a first diode-connected transistor 103 is connected in parallel to the upper stage resistor 201. Reduction of IMD3 is realized by the first diode-connected transistor 103 and a high-linearity high frequency amplifier can be provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a high-frequency amplifier used in wireless communication devices, and more particularly to a low-noise amplifier MMIC (Monolithic Microwave Integrated Circuit) that is designed to improve linearity and the like. [Background technology]

[0002] In recent years, mobile phone systems have expanded the data communication bandwidth by using an increasing number of frequency bands and by using signal multiplexing techniques within frequency bands, such as OFDM (Orthogonal Frequency-Division Multiplexing) and Massive MIMO (Multiple-Input and Multiple-Output).In this environment, wireless devices are required to have higher linearity, and at the same time, semiconductor devices for base stations are required to be smaller and less expensive in order to accommodate the increase in the number of wireless communication chains, i.e., the increase in the number of RF (Radio Frequency) front-end units in base stations.

[0003] An RF front-end receiver is usually equipped with an LNA (Low Noise Amplifier). One indicator that is often used to evaluate the linearity of an LNA is IP3 or TOI (Third Order Intercept Point), which is derived as follows: First, plot the f1 and f2 curves, which are the fundamental waves, and the IMD3 (3rd order intermodulation distortion) curve on the two-tone input / output power linear characteristic graph (Pin-Pout). The fundamental wave at small signals is represented by a straight line approximation with a slope of 1, and IMD3 is represented by a straight line approximation with a slope of 3, and these straight lines are plotted on the graph.

[0004] The point where the approximate line of the fundamental wave and IMD3 intersect is the IP3, which is called the IIP3 (Input 3rd order Intercept Point) when read in terms of input power, and the OIP3 (Output 3rd order Intercept Point) when read in terms of output power. To improve the IP3, it is necessary to reduce the IMD3 level. Another index of linearity is P-1dB (1dB compression point), but while P-1dB is an index of linearity at large signals, IP3 is an index of linearity derived from IMD3 at small signals, and is often used to evaluate the linearity of highly linear devices and small signal devices. It is generally known that the IMD3 level can be minimized by optimizing the operating point taking into account the DC static characteristic curve of the amplifying transistor.

[0005] To further improve linearity, one method for reducing the IMD3 level of an amplifier is to increase the size of the amplifier transistors. For example, if two amplifiers are operated in parallel, the input level per amplifier circuit will decrease by 3 dB, resulting in a 9 dB decrease in the IMD3 level. However, combining the outputs of the two amplifier circuits will increase the level by 3 dB, resulting in a final IMD3 decrease of 6 dB. This principle can also be achieved by increasing the size of the amplifier transistors in a single amplifier circuit with appropriate circuit design. However, this method has the disadvantages of increasing costs due to the increased transistor size and tending to degrade the noise figure (NF), an important characteristic of LNAs.

[0006] Another method for reducing an amplifier's IMD3 level is feedback. Direct feedback between the amplifier's input and output terminals is a commonly used technique in the audio frequency range to reduce nonlinear distortion. High-frequency amplifiers are prone to unintended feedback paths due to semiconductor chip layout and bonding wires during package assembly, and they are also prone to significant high-frequency phase rotation within the semiconductor chip or package. When applying this technique to high-frequency amplifiers, increasing the amount of feedback to a level that significantly reduces nonlinear distortion can result in unexpected positive feedback, increasing the risk of oscillation. In addition, increasing the amount of feedback requires sufficient gain margin in the amplifier transistor, which is typically unavailable in high-frequency amplifiers. For this reason, direct feedback in high-frequency amplifiers is often used with a small amount of feedback to stabilize the gain.

[0007] A technique that uses feedback to reduce nonlinear distortion in a high-frequency amplifier is disclosed in, for example, Patent Document 1. Patent Document 1 discloses a technology using Darlington-connected transistors as the circuit topology for a high-frequency amplifier. In the circuit shown in Figure 2 of the document, IMD3 generated by the Darlington-connected input transistor M1 and output transistor M2 is fed back to the high-frequency input terminal via parallel feedback. At the same time, the IMD3 of the source output of the input transistor M1 is input to the bias transistor M3 via an RC tuning circuit and mixed with the high-frequency input terminal while changing its phase and amplitude. As a result, the IMD3 level at the high-frequency output terminal is reduced. In this case, the signal level in the high-frequency path of the bias circuit is sufficiently small compared to the signal level in the amplifier's main high-frequency path, making it possible to reduce the IMD3 level without affecting the main characteristics of the high-frequency amplifier.

[0008] FIG. 10 shows a conventional example of a FET amplifier used as an LNA disposed in an RF front-end receiver, and this conventional circuit will be described below with reference to the same figure. First, as is well known, conventionally, this type of amplifier has employed a configuration in which transistors are stacked vertically in two stages to reuse current, with the lower stage amplifier transistor having a common source (CS) and the upper stage amplifier transistor having a common gate (CG), which is called a cascode-connected amplifier.

[0009] 10, both the lower amplifier transistor 101X and the upper amplifier transistor 102X are source-grounded, and for convenience of explanation, this conventional circuit configuration will be referred to as a "CS-CS stack-configured amplifier." Similarly, the above-mentioned cascode-connected amplifier will be referred to as a "CS-CG stack-configured amplifier."

[0010] The size of the amplifier transistors 101X and 102X of the conventional circuit is a total gate width of 1 mm for both the upper and lower stages, and the main characteristics are an operating voltage of 5 V, an operating current of 50 mA, an operating frequency range of 3.3 to 5.0 GHz, and a power gain of 26 dB, a noise figure of 0.5 dB, and P-1 dB = 19 dBm at an operating frequency of 3.6 GHz.

[0011] FIG. 11 shows an example of the measurement results of the two-tone input / output power linearity characteristics in a conventional circuit, and this figure will be explained below. 11, the solid line is a characteristic line showing the change in the fundamental wave output, and the dashed line is a characteristic line showing the change in the IMD3. The dotted lines are auxiliary lines used to derive IIP3 and OIP3, and the calculated OIP3 is 35.4 dBm at an operating frequency of 4.0 GHz.

[0012] The conventional circuit shown in FIG. 10 is a CS-CS stack configuration amplifier using the lower amplifier transistor 101X and the upper amplifier transistor 102X as described above, in which the lower amplifier transistor 101X receives a gate bias from the gate bias circuit 501X, and the upper amplifier transistor 102X receives a gate bias from the gate bias circuit 502X.

[0013] A filter circuit 503X using a bypass capacitor 305X that separates the gate bias circuits 501X and 502X at high frequencies is provided between them. In this conventional circuit, an enhancement-type GaAs pHEMT (Pseudomorphic High Electron Mobility Transistor), which is a type of field-effect transistor, is used as the transistor.

[0014] Next, the operation of the conventional circuit having such a configuration will be described. First, the DC operation will be described. The operating current IDD of the CS-CS stack configuration amplifier flows from the power supply terminal VDD through the choke inductor 401X between the drain and source of the upper-stage amplifier transistor 102X, and then through the choke inductor 402X between the drain and source of the lower-stage amplifier transistor 101X. Current reuse allows the two-stage amplifier to operate with the current equivalent to that of a single amplifier stage, but because the operating voltage VDD is divided by the two-stage amplifier, P-1dB is lower than that of a normal two-stage amplifier.

[0015] The gate bias circuit is similar to that of a cascode-connected amplifier, with the gate bias circuit 501X forming a current mirror circuit with the lower amplifier transistor 101X to enable bias supply, and the gate bias circuit 502X enabling bias supply to the upper amplifier transistor 102X via a resistive divider circuit.

[0016] Next, the RF operation will be described. A high-frequency signal in a CS-CS stack-configured amplifier is input from a high-frequency input terminal RFIN through a DC-cut capacitor 301X to the gate of a lower-stage amplifier transistor 101X, and then output to the drain of the lower-stage amplifier transistor 101X. After that, the signal is input to the gate of an upper-stage amplifier transistor 102X through a DC-cut capacitor 304X. The high-frequency signal input to the gate of the upper-stage amplifier transistor 102X is output to the drain and also reaches the high-frequency output terminal RFOUT through a DC-cut capacitor 302X. A CS-CS stack-configured amplifier has a feature that it can obtain a higher gain than a CS-CG stack-configured amplifier because the upper-stage amplifier is source-grounded. Such CS-CS stack-configured amplifiers are well known, for example, as disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] U.S. Patent No. 8,390,380 [Patent Document 2] Japanese Patent Application Publication No. 9-102717 Summary of the Invention [Problem to be solved by the invention]

[0018] As mentioned above, CS-CS stacked amplifiers can achieve higher gain than CS-CG stacked amplifiers, but the two configurations have in common the problem that there is generally a trade-off between improvements in linearity and NF, which are indicators of LNA characteristics.

[0019] The present invention has been made in consideration of the above circumstances, and provides a high-frequency amplifier that can reliably reduce third-order intermodulation distortion (IMD3) without degrading NF while maintaining high gain. [Means for solving the problem]

[0020] In order to achieve the above object of the present invention, a high-frequency amplifier according to the present invention comprises: The gate of the second transistor is connected to the drain of the first transistor, the source of which is grounded, via a capacitor, and The drain of the first transistor The source of the second transistor is connected via an inductor, and the source of the second transistor is grounded via a shunt capacitor for high frequency, so that high frequency can be output from the drain of the second transistor. are stacked vertically in two layers In the high frequency amplifier configured as a lower-stage gate bias circuit that supplies a gate bias to the first transistor; an upper stage gate bias circuit is provided to supply a gate bias to the second transistor; the upper-stage gate bias circuit is configured such that an upper-stage resistor and a lower-stage resistor are connected in series between a bias power supply terminal and ground, and a first diode-connected transistor is connected in parallel to the upper-stage resistor, and a voltage at a junction point between the upper-stage resistor and the lower-stage resistor can be supplied as a gate bias to the second transistor; the bias power supply terminal is provided so that a bias voltage is supplied from the power supply terminal via a choke inductor, the drain of the second transistor, and a bias distribution resistor; the first diode-connected transistor has a drain and a gate connected to one end of the upper-stage resistor and a source connected to a connection point between the upper-stage resistor and the lower-stage resistor; The lower stage gate bias circuit and the upper stage gate bias circuit are connected to the drain of the second transistor. to the bias distribution resistor and the bias power supply terminal Bias power is supplied via This creates an IMD3 feedback path. This is what happens. [Effects of the Invention]

[0021] According to the present invention, IMD3 fed back from the second transistor is modulated by passing through a diode-connected transistor provided in the upper-stage gate bias circuit, and is mixed with IMD3 that has passed through the first transistor, thereby reducing distortion, and it is possible to obtain a high-frequency amplified output with a reliably reduced IMD3 level. Furthermore, by providing a filter circuit in each of the upper and lower feedback paths and making it possible to adjust the amount of feedback by the filter circuit, it becomes easy to optimize the operating frequency of the IMD3 characteristics. Furthermore, by providing an anti-parallel connected diode-connected transistor in the upper-stage gate bias circuit, the size of the diode-connected transistor is essentially reduced compared to when one diode-connected transistor is provided, and therefore the IMD3 level can be reduced while expanding the adjustment range of the circuit. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a circuit diagram showing an example of a basic circuit configuration of a high-frequency amplifier according to an embodiment of the present invention; [Figure 2] FIG. 3 is a characteristic diagram showing the results of measurements of two-tone input / output power linearity characteristics of the high-frequency amplifier according to the embodiment of the present invention. [Figure 3] FIG. 10 is a characteristic diagram showing actual measurement results of the OIP3 frequency characteristics of the high-frequency amplifier according to the embodiment of the present invention, together with an example of the characteristics of a conventional circuit. [Figure 4] 1 is a circuit diagram showing a first specific example of a circuit configuration of a high-frequency amplifier according to an embodiment of the present invention. [Figure 5] FIG. 4 is a circuit diagram showing a second specific example of the circuit configuration of the high-frequency amplifier according to the embodiment of the present invention. [Figure 6] FIG. 10 is a circuit diagram showing a third specific example of the circuit configuration of the high-frequency amplifier according to the embodiment of the present invention. [Figure 7] FIG. 10 is a circuit diagram showing a fourth specific example of the circuit configuration of the high-frequency amplifier according to the embodiment of the present invention. [Figure 8] FIG. 10 is a circuit diagram showing a fifth specific example of the circuit configuration of the high-frequency amplifier according to the embodiment of the present invention. [Figure 9] FIG. 10 is a circuit diagram showing a sixth specific circuit configuration example of the high-frequency amplifier according to the embodiment of the present invention. [Figure 10] FIG. 1 is a circuit diagram showing an example of a conventional high-frequency amplifier. [Figure 11]FIG. 11 is a characteristic diagram showing the measurement results of the two-tone input / output power linearity characteristics of the conventional circuit shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The components, arrangements, etc. described below do not limit the present invention, and various modifications can be made within the scope of the present invention. First, an example of the basic circuit configuration of a high-frequency amplifier according to an embodiment of the present invention will be described with reference to FIG. The high frequency amplifier according to the embodiment of the present invention is configured by stacking two stages of a lower stage amplifier transistor 101 and an upper stage amplifier transistor 102, both of which have their sources grounded. In the embodiment of the present invention, the lower stage amplifier transistor 101 as a first transistor and the upper stage amplifier transistor 102 as a second transistor are both field effect transistors, and for example, an enhancement type GaAs pHEMT (Pseudomorphic High Electron Mobility Transistor) is used.

[0024] The source of the lower amplifier transistor 101 constituting the lower amplifier is grounded, while the gate is connected to the lower gate bias circuit 501 via the gate resistor 205 and to the high frequency input terminal (denoted as "RFIN" in Figure 1) 11 via the DC cut capacitor 301. The lower stage gate bias circuit 501 does not need to be limited to a specific circuit configuration, and may be a conventionally well-known circuit configuration such as a current mirror or a resistance feed, which will be described later. As will be described later, the voltage required for gate bias operation by the lower-stage gate bias circuit 501 is supplied from the drain of the upper-stage amplifier transistor 102 via a bias power supply terminal (denoted as "VBIAS" in FIG. 1) 14. In conventional circuits, a bias power supply is supplied to the bias power supply terminal from an external source, but in the embodiment of the present invention, there is no need to supply a bias power supply from an external source, and a bias is supplied from a power supply terminal (denoted as "VDD" in FIG. 1) 13 via a choke inductance 401 to the drain of the upper-stage amplifier transistor 102 and a bias distribution resistor 206, thereby supplying a bias voltage to the bias power supply terminal.

[0025] The source of the upper amplifier transistor 102 constituting the upper amplifier is grounded for high frequency via a shunt capacitor 303, and is also connected to the drain of the lower amplifier transistor 101 via a choke inductor 402 as a DC path. In addition, the drain of the lower amplifier transistor 101 is connected to the gate of the upper amplifier transistor 102 via a DC blocking capacitor 304, so that the drain output of the lower amplifier transistor 101 is input to the gate of the upper amplifier transistor 102.

[0026] Furthermore, the drain of the upper amplifier transistor 102 is connected to a high-frequency output terminal (denoted as "RFOUT" in FIG. 1) 12 via a DC-cut capacitor 302, and is also connected to a power supply terminal (denoted as "VDD" in FIG. 1) 13 via a choke inductor 401. The gate of the upper stage amplifier transistor 102 is connected to the upper stage gate bias circuit 502 via the gate resistor 203 and receives a gate bias from the upper stage gate bias circuit 502 .

[0027] The upper-stage gate bias circuit 502 includes an upper-stage resistor 201, a lower-stage resistor 202, and a diode-connected transistor 103, and forms a resistor divider circuit. That is, one end of the upper resistor 201 is connected to the bias power supply terminal 14, while the other end of the upper resistor 201 is connected to one end of the lower resistor 202, and the other end of the lower resistor 202 is grounded, so that the upper resistor 201 and the lower resistor 202 are connected in series between the bias power supply terminal 14 and the ground. One end of the gate resistor 203 is connected to the mutual connection point of the upper resistor 201 and the lower resistor 202.

[0028] In addition, the diode-connected transistor 103 has a source connected to the mutual junction of the upper resistor 201 and the lower resistor 202, while its drain and gate are mutually connected, and this junction is connected to one end of the upper resistor 201, i.e., the bias power supply terminal 14.

[0029] In addition, a filter circuit 503 is provided between the lower stage gate bias circuit 501 and the upper stage gate bias circuit 502 . That is, the filter circuit 503 is configured using a shunt capacitor 305, one end of which is connected to the bias power supply terminal 14, while the other end is grounded. Furthermore, the drain of the upper-stage amplifier transistor 102 is connected to the bias power supply terminal 14 via a bias distribution resistor 206, and the power supply voltage is supplied from the drain connected to the power supply terminal 13 to the lower-stage gate bias circuit 501 and the upper-stage gate bias circuit 502.

[0030] Next, the operation of the basic circuit in the above configuration will be described. First, a high frequency signal input to high frequency input terminal 11 is amplified by lower stage amplifier transistor 101 and upper stage amplifier transistor 102 in the same manner as in the conventional case, and is output to high frequency output terminal 12 . Along with this conventional amplification operation, a feedback loop is formed in which the drain output of the upper amplifier transistor 102 passes through the lower gate bias circuit 501 and the upper gate bias circuit 502 to the gates of the lower amplifier transistor 101 and the upper amplifier transistor 102.

[0031] In the upper-stage gate bias circuit 502, the upper-stage resistor 201 and the diode-connected transistor 103 are connected in parallel, and therefore the modulation degree of IMD3 passing through the upper-stage feedback path (the path that is fed back from the drain of the upper-stage amplifier transistor 102, via the upper-stage gate bias circuit 502, to the gate of the upper-stage amplifier transistor 102) is adjusted by the ratio between the applied voltage of the diode-connected transistor 103 and the current flowing through the upper-stage resistor 201 and the diode-connected transistor 103.

[0032] To give a specific example of the circuit constants, the upper resistor 201 has a resistance of 2 KΩ, the lower resistor 202 has a resistance of 8 KΩ, and the diode-connected transistor 103 has a gate width of 5 μm. In this case, the gate-source voltage Vgs of the diode-connected transistor 103 needs to be made close to the gate-source voltage Vgs of the lower-stage amplifier transistor 101 and the upper-stage amplifier transistor 102 . The amount of feedback can be adjusted by providing a filter circuit 503 on the upper feedback path and the lower feedback path (a path that feeds back from the drain of the upper amplifier transistor 102 via the lower gate bias circuit 501 to the gate of the lower amplifier transistor 101). Note that the filter circuit 503 is not the only one that functions as a filter; resistors 203, 205, and 206 also function as filters.

[0033] The shunt capacitor 305 that constitutes the filter circuit 503 affects the amount of feedback with frequency characteristics, resulting in a frequency peak appearing in the final IP3 characteristics. The IMD3 that passes through the lower-stage feedback path is amplified by the lower-stage amplifier and mixed with the IMD3 that passes through the upper-stage feedback path. The modulation of IMD3 in the upper-stage feedback path involves phase rotation, and the IMD3 that is vector-combined with the IMD3 output of the lower-stage amplifier is amplified by the upper-stage amplifier. In this way, the IMD3 generated in each of the upper and lower amplifier stages and the IMD3 that passes through the feedback path are mixed together, resulting in a reduced IMD3 level at the output of the upper amplifier.

[0034] FIG. 2 shows a characteristic diagram illustrating the results of measurements of the two-tone input / output power linearity characteristics of the high-frequency amplifier according to the embodiment of the present invention, and this diagram will be described below. In the figure, the horizontal axis represents the change in input power PIN, and the vertical axis represents the change in output power POUT and the change in IMD3. In FIG. 2, the solid characteristic line indicates the change characteristics of the fundamental wave output, the dashed-dotted characteristic line indicates the change characteristics of IMD3, and the dotted characteristic lines are auxiliary lines for deriving IIP3 and OIP3. According to the figure, at an operating frequency of 4.0 GHz, the OIP3 is calculated to be 40.0 dBm.

[0035] FIG. 3 shows characteristic lines indicating the results of measurements of the OIP3 frequency characteristics in the high-frequency amplifier according to the embodiment of the present invention, together with similar characteristic lines for a conventional circuit (see FIG. 10), and this figure will be described below. In FIG. 3, the horizontal axis represents frequency, and the vertical axis represents the OIP3 signal level. Also, in the same figure, the solid characteristic line shows the change characteristic of OIP3 with changes in input frequency of the high-frequency amplifier in the embodiment of the present invention, and the dashed double-dashed characteristic line shows the similar change characteristic of the conventional circuit (see Figure 10). According to the figure, it can be seen that the high-frequency amplifier according to the embodiment of the present invention has an improved OIP3 compared to the conventional circuit, and that a frequency peak appears in the OIP3 characteristics, unlike the conventional circuit.

[0036] Next, a first specific circuit configuration example of a high-frequency amplifier according to an embodiment of the present invention will be described with reference to FIG. The same components as those in the circuit configuration example shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. This first specific circuit configuration example is an example that uses a lower-stage gate bias circuit 501A configured as a current mirror, and the remaining parts have basically the same configuration as the basic circuit shown in Figure 1.

[0037] That is, the lower stage gate bias circuit 501 A is configured to include a mirror transistor 106 and a mirror resistor 204 . The mirror transistor 106 has its gate and drain connected to each other to form a diode connection, and its gate is connected to the gate of the lower amplifier transistor 101 via a gate resistor 205 . The source of the mirror transistor 106 is grounded, while the drain is connected to the bias power supply terminal 14 via a mirror resistor 204 .

[0038] In this configuration, the mirror transistor 106 serves as the input stage, and mirrors the bias current to the lower stage amplifier transistor 101, which serves as the output stage of the current mirror. Such a configuration is common in stacked LNAs.

[0039] Next, a second specific circuit configuration example of the high-frequency amplifier according to the embodiment of the present invention will be described with reference to FIG. The same components as those in the circuit configuration examples shown in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. This second specific circuit configuration example is provided with an upper stage gate bias circuit 502A configured using two diode-connected transistors connected in antiparallel, and the remaining parts have basically the same configuration as the first specific circuit configuration example shown in Figure 4.

[0040] That is, the upper-stage gate bias circuit 502A is provided with a second diode-connected transistor 104 connected in anti-parallel to the diode-connected transistor 103 (hereinafter, for convenience of explanation, referred to as the “first diode-connected transistor”), and the second diode-connected transistor 104 has its gate and drain connected to each other to be in a diode-connected state, and its connection point is connected to the source of the first diode-connected transistor 103.

[0041] On the other hand, the source of the second diode-connected transistor 104 is connected to the drain of the first diode-connected transistor 103 . In this configuration, the gate width of the second diode-connected transistor 104 is set to a small value of about 5 μm, similar to the diode-connected transistor 103 described above. In this way, by connecting the first diode-connected transistor 103 and the second diode-connected transistor 104 in the opposite direction in parallel, an effect is achieved that is similar to that of substantially reducing the size of the diode-connected transistor with respect to modulation of IMD3 in the upper-stage feedback path, and therefore it is possible to avoid restrictions on circuit design such as minimum layout dimensions and transistor breakdown voltage.

[0042] Next, a third specific circuit configuration example of the high-frequency amplifier according to the embodiment of the present invention will be described with reference to FIG. The same components as those in the circuit configuration examples shown in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. This third specific circuit configuration example includes second and third filter circuits 503B and 503C in addition to filter circuit 503A using an RC series circuit, and the remaining parts have basically the same configuration as the first specific circuit configuration example shown in Figure 4.

[0043] That is, first, in filter circuit 503A, shunt capacitor 305 and filter resistor 209 are connected in series between bias power supply terminal 14 and ground in the order of shunt capacitor 305 and filter resistor 209 from the bias power supply terminal 14 side, thereby forming an RC series circuit. The second filter circuit 503B is configured as an RC parallel circuit made up of a gate resistor 203 and a filter capacitor 306 connected in parallel thereto.

[0044] Incidentally, the gate resistor 203 is originally intended to prevent oscillation in the low frequency range outside the operating band, and therefore the degree of freedom in adjusting the filter characteristics is low, so it is preferable to adjust the amount of feedback using the filter capacitor 306.

[0045] The third filter circuit 503C is configured as an RC parallel circuit made up of a bias distribution resistor 206 and a filter capacitor 307 connected in parallel thereto. Incidentally, since bias distribution resistor 206 is originally intended to supply bias voltage to the bias power supply terminal, the degree of freedom in adjusting the filter characteristics is low, so it is preferable to adjust the amount of feedback using filter capacitor 307. From the viewpoint of preventing deterioration of NF, it is desirable not to provide parallel-connected capacitors such as filter capacitors 306 and 307 in the lower feedback path.

[0046] Next, a fourth specific circuit configuration example of the high-frequency amplifier according to the embodiment of the present invention will be described with reference to FIG. The same components as those in the circuit configuration examples shown in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. This fourth specific circuit configuration example is provided with filter circuits 503D and 503E using inductors, and the remaining parts have basically the same configuration as the first specific circuit configuration example shown in Figure 4. Specifically, first, the filter circuit 503D is configured using an inductor 403, which is provided in place of the gate resistor 203 (see FIG. 4) and is connected in series between the upper-stage gate bias circuit 502 and the gate of the upper-stage amplifier transistor 102. The gate resistor 203 is originally intended to prevent oscillation in the low-frequency range outside the operating band, so if this is not necessary, it is also possible to adjust the amount of feedback using an inductor.

[0047] Next, the filter circuit 503 E is configured to include a gate resistor 205 and an inductor 404 . That is, one end of the gate resistor 205 is connected to the gate of the mirror transistor 106 of the lower-stage gate bias circuit 501, while the other end of the gate resistor 205 is connected to one end of the inductor 404. The other end of the inductor 404 is connected to the gate of the lower-stage amplifier transistor 101. In this way, by adding an inductor to the feedback path, it becomes possible to adjust the amount of feedback without changing the DC operating points of the lower-stage amplifier transistor 101 and the upper-stage amplifier transistor 102.

[0048] Next, a fifth specific circuit configuration example of the high-frequency amplifier according to the embodiment of the present invention will be described with reference to FIG. The same components as those in the circuit configuration examples shown in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. This fifth specific circuit configuration example is configured by using an upper gate bias circuit 502B having the configuration described below instead of the upper gate bias circuit 502 having the configuration shown in Figure 4, and the remaining parts have basically the same configuration as the first specific circuit configuration example shown in Figure 4.

[0049] That is, the upper-stage gate bias circuit 502B is configured to include an upper-stage resistor 201, a lower-stage resistor 202, and two diode-connected transistors 103 and 105. That is, the upper resistor 201 and the lower resistor 202 are connected in series, and one end of the upper resistor 201 is connected to the bias power supply terminal 14, which is the same as the configuration example shown in Figure 4, but a diode-connected transistor 105 is provided between the lower resistor 202 and ground. The diode-connected transistor 105 has a gate and a drain connected to each other, a connection point between the gate and the drain being connected to the lower resistor 202, and a source being grounded.

[0050] The diode-connected transistor 103 connected in parallel to the upper-stage resistor 201 has a pinch-off voltage that varies due to process variations, which in turn causes the gate voltage of the upper-stage amplifier transistor 102 to vary as well. In this configuration example, the variation in the pinch-off voltage of the diode-connected transistor 103 on the upper resistor 201 side and the variation in the pinch-off voltage of the diode-connected transistor 105 on the lower resistor 201 side are linked, resulting in a more stable supply of gate voltage to the upper amplifier transistor 102 compared to when the diode-connected transistor 105 on the lower resistor 202 side is not present.

[0051] Next, a sixth specific circuit configuration example of the high-frequency amplifier according to the embodiment of the present invention will be described with reference to FIG. The same components as those in the circuit configuration examples shown in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. In this sixth specific circuit configuration example, a lower stage gate bias circuit 501B having the configuration described below is used instead of the lower stage gate bias circuit 501A having the configuration shown in FIG.

[0052] Furthermore, a buffer transistor 107 is inserted between the bias power supply terminal 14 and each of the lower-stage gate bias circuit 501B and the upper-stage gate bias circuit 502, and a logic circuit 504 is provided for controlling the operation of the buffer transistor 107. The remaining parts have basically the same configuration as the first specific circuit configuration example shown in FIG.

[0053] First, the lower stage gate bias circuit 501B is configured using a current mirror, and the configuration of the current mirror in FIG. 9 is basically the same as that disclosed in, for example, Japanese Patent No. 6502623. That is, the lower stage gate bias circuit 501B is configured to include a mirror transistor 106 , a mirror resistor 204 , a gate resistor 205 , a drain-gate resistor 207 , and a shunt resistor 208 .

[0054] One end of the mirror resistor 204 is connected to the source of the buffer transistor 107 , and the drain of the buffer transistor 107 is connected to the bias power supply terminal 14 .

[0055] The other end of the mirror resistor 204 is connected to the drain of the mirror transistor 106, and this drain is connected to the gate of the mirror transistor 106 via a drain-gate resistor 207 and a gate resistor 205. The mutual connection point between the drain-gate resistor 207 and the gate resistor 205 is connected to the gate of the lower-stage amplifier transistor 101. The gate of the mirror transistor 106 is grounded via a shunt resistor 208, and the source of the mirror transistor 106 is directly grounded. By using a current mirror with such a configuration, it is possible to reduce process variations in the operating current IDD.

[0056] A logic circuit 504 is connected to the gate of the buffer transistor 107. This logic circuit 504 generates and outputs a gate voltage required to turn on and off the buffer transistor 107, and has a configuration similar to that of a well-known conventional circuit of this type. In this way, by using logic circuit 504 to control the conduction / non-conduction of buffer transistor 107, it becomes possible to add a shutdown function to the LNA, thereby providing a more practical LNA. [Industrial Applicability]

[0057] This technology can be applied to high-frequency amplifiers that require high gain and high linearity while also ensuring a reliable reduction in third-order intermodulation distortion. [Explanation of symbols]

[0058] 101...Lower amplifier transistor 102...Upper amplifier transistor 103...Diode-connected transistor 104...Diode-connected transistor 206...Bias divider resistor 501, 501A, 501B...Lower gate bias circuit 502, 502A, 502B...Upper gate bias circuit

Claims

1. a gate of a second transistor is connected to the drain of a first transistor whose source is grounded via a capacitor, a source of the second transistor is connected to the drain of the first transistor via an inductor, the source of the second transistor is grounded for high frequency signals via a shunt capacitor, and the first and second transistors are stacked in two stages so that a high frequency signal can be output from the drain of the second transistor; a lower stage gate bias circuit that supplies a gate bias to the first transistor; an upper stage gate bias circuit is provided to supply a gate bias to the second transistor; the upper-stage gate bias circuit is configured such that an upper-stage resistor and a lower-stage resistor are connected in series between a bias power supply terminal and ground, and a first diode-connected transistor is connected in parallel to the upper-stage resistor, and a voltage at a junction point between the upper-stage resistor and the lower-stage resistor can be supplied as a gate bias to the second transistor; the bias power supply terminal is provided so that a bias voltage is supplied from the power supply terminal via a choke inductor, the drain of the second transistor, and a bias voltage dividing resistor; the first diode-connected transistor has a drain and a gate connected to one end of the upper-stage resistor, and a source connected to a connection point between the upper-stage resistor and the lower-stage resistor; The high-frequency amplifier is characterized in that an IMD3 feedback path is formed in the lower-stage gate bias circuit and the upper-stage gate bias circuit by supplying bias power from the drain of the second transistor via the bias distribution resistor and the bias power supply terminal.

2. 2. The high-frequency amplifier according to claim 1, wherein a filter circuit is provided on each of a lower-stage feedback path extending from the drain of the second transistor via the lower-stage gate bias circuit to the gate of the first transistor, and an upper-stage feedback path extending from the drain of the second transistor via the upper-stage gate bias circuit to the gate of the second transistor.

3. 3. The high-frequency amplifier according to claim 1, wherein a second diode-connected transistor having a reverse polarity to the first diode-connected transistor is connected in parallel to the first diode-connected transistor.

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