Pixel circuit, driving method thereof, display substrate, and display device

Abstract

A pixel circuit, its driving method, display substrate and display device. The pixel circuit includes a driving subcircuit, a data writing subcircuit, a compensation subcircuit, a first switch subcircuit and a first light emission control subcircuit. The driving subcircuit includes a control end connected to a first node, a first end connected to a second node and a second end connected to a third node, and is configured to control a driving signal for driving a light emitting element from the first node to a third node according to a voltage of the first node, the first switch subcircuit is configured to control the conduction of the driving signal between the third node and the fourth node in response to a first switch control signal, and the first light emission control subcircuit is connected to a first electrode of the light emitting element by the fifth node and is configured to control the conduction of the driving signal between the fourth node and the fifth node in response to a first light emission control signal. The pixel circuit can effectively improve the uniformity of the display.

Description

[Technical Field]

[0001] The embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, a display substrate, and a display device. [Background technology]

[0002] Currently, the display screens of display devices are becoming larger and full-screen. Generally, display devices (e.g., mobile phones, tablet computers, etc.) have a photographing device (or imaging device), which is generally installed on one side of the display screen, outside the display area. However, the installation of the imaging device requires a certain amount of space, which is disadvantageous for full-screen and narrow-frame display designs. For example, the imaging device may be combined with the display area of ​​the display screen, reserving a position for the imaging device within the display area to maximize the display area of ​​the display screen. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment of the present disclosure provides a pixel circuit including a driving subcircuit, a data writing subcircuit, a compensation subcircuit, a first switch subcircuit, and a first light-emitting control subcircuit, wherein the driving subcircuit includes a control end connected to a first node, a first end connected to a second node, and a second end connected to a third node, the driving subcircuit is configured to control a drive signal for driving a light-emitting element from the first node to the third node based on a voltage of the first node, the data writing subcircuit is connected to the second node and configured to write a data signal to the second node in response to a first scanning signal, and the compensation subcircuit is connected to the first node and the third node and configured to conduct the first node and the third node in response to a second scanning signal, thereby controlling a pixel circuit based on the data signal written to the second node. the first switch subcircuit is configured to control the conduction of the drive signal between the third node and the fourth node based on the voltage of the third node in response to a first switch control signal; the first light-emitting control subcircuit is connected to the fourth node and a fifth node and connected to a first electrode of the light-emitting element by the fifth node; and the first light-emitting control subcircuit is configured to control the conduction of the drive signal between the fourth node and the fifth node in response to a first light-emitting control signal so that the drive signal can be applied to the light-emitting element.

[0004] In some examples, the pixel circuit further includes a first reset sub-circuit connected to the fifth node and configured to write a first reset voltage to the fifth node in response to a first reset control signal.

[0005] In some examples, the pixel circuit further includes a first reset sub-circuit connected to the fourth node and configured to write a first reset voltage to the fourth node in response to a first reset control signal.

[0006] In some examples, the pixel circuit further includes a first reset sub-circuit and a second switch sub-circuit, wherein the first reset sub-circuit is connected to a sixth node and connected to the second switch sub-circuit by the sixth node, the first reset sub-circuit configured to write a first reset voltage to the sixth node in response to a first reset control signal, and the second switch sub-circuit is connected to the fourth node and the sixth node and configured to control conduction between the fourth node and the sixth node in response to a second switch control signal so that the first reset voltage from the first reset sub-circuit can be written to the fourth node.

[0007] In some examples, the pixel circuit further includes a second light-emitting control sub-circuit connected to the second node and a first power supply voltage terminal and configured to write a first power supply voltage from the first power supply voltage terminal to the second node in response to a second light-emitting control signal.

[0008] In some examples, the pixel circuit further includes a storage subcircuit having a first end and a second end, the first end and second end of the storage subcircuit being connected to the first power supply voltage end and the first node, respectively.

[0009] In some examples, the pixel circuit further includes a second reset sub-circuit connected to the first node and configured to write a second reset voltage to the first node in response to a second reset control signal.

[0010] In some examples, the pixel circuit further includes a first capacitor including a first electrode and a second electrode, the first electrode of the first capacitor being connected to the fourth node, and the second electrode of the first capacitor being configured to apply the same voltage as the second electrode of the light-emitting element.

[0011] In some examples, the pixel circuit further includes a second capacitor, a first electrode of the second capacitor connected to the fourth node, and a first electrode of the light-emitting element serving as a second electrode of the second capacitor.

[0012] At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a plurality of sub-pixels arranged in an array on the base substrate along a first direction and a second direction, the plurality of sub-pixels including a first sub-pixel including a pixel circuit and the light-emitting element according to any of the above embodiments, the display substrate including a first display area and a second display area, the first display area at least partially surrounding the second display area, a driving sub-circuit and a first switch sub-circuit of the pixel circuit both located in the first display area, and a first light-emitting control sub-circuit of the pixel circuit and the light-emitting element located in the second display area. In some examples, the display substrate further includes a connecting line having one end electrically connected to the first light-emitting control subcircuit and the other end extending to the first display area so as to be electrically connected to the first switch subcircuit, and the material of the connecting line is a transparent conductive material.

[0013] In some examples, the connecting line at least partially overlaps the first electrode of the light emitting element in a direction perpendicular to the base substrate.

[0014] In some examples, the first light-emitting control subcircuit includes a light-emitting control transistor, a first electrode of the light-emitting control transistor being electrically connected to the connecting line by a first via hole, and a second electrode of the light-emitting control transistor being electrically connected to the first electrode of the light-emitting element by a second via hole.

[0015] In some examples, the display substrate further includes a first connection electrode located on one side of the connection line adjacent to the base substrate, and a first electrode of the light-emitting control transistor is electrically connected to the connection line by the first connection electrode.

[0016] In some examples, the orthogonal projection of the first electrode of the light emitting element onto the base substrate covers the orthogonal projection of the first connecting electrode onto the base substrate.

[0017] In some examples, the first electrode of the light-emitting element includes an electrode body portion and an electrode protrusion portion protruding from the electrode body portion, the electrode body portion is used to contact the light-emitting layer of the light-emitting element, the electrode protrusion portion is electrically connected to the second electrode of the light-emitting control transistor by the second via hole, and the orthogonal projection of the second via hole onto the base substrate is farther from the orthogonal projection of the electrode body portion onto the base substrate than the orthogonal projection of the first via hole onto the base substrate.

[0018] In some examples, the display substrate further includes an emission control line located in the second display area, the material of the emission control line is a transparent conductive material, and the emission control line is electrically connected to the gate of the emission control transistor to provide the first emission control signal.

[0019] In some examples, in a direction perpendicular to the base substrate, the light-emitting control line is located on one side where the connecting line is adjacent to the first electrode of the light-emitting element.

[0020] In some examples, when the pixel circuit further includes a second switch subcircuit, the second switch subcircuit is located in the first display area, the display substrate further includes an auxiliary light-emitting control line located in the first display area, the second switch subcircuit is connected to the auxiliary light-emitting control line to receive the second switch control signal, and the auxiliary light-emitting control line is electrically connected to the light-emitting control line.

[0021] At least one embodiment of the present disclosure further provides a display device including a display substrate according to any of the above embodiments.

[0022] In some examples, the display device further includes a sensor, wherein the display substrate has a first side for display and a second side opposite the first side, and the sensor is disposed on the second side of the display substrate and configured to receive and sense light passing through the second display area from the first side of the display substrate.

[0023] At least one embodiment of the present disclosure further provides a pixel circuit driving method for driving the pixel circuit according to any of the above embodiments, the driving method including: in a data writing and compensation step, turning on the data writing subcircuit and turning off the first switch subcircuit and the first light-emitting control subcircuit so as to write the data signal to the second node and perform compensation for the drive subcircuit; in a pre-charge step, turning on the first switch subcircuit and turning off the first light-emitting control subcircuit so as to charge the fourth node so that the potential of the fourth node reaches a predetermined value; and in a light-emitting step, turning on the first switch subcircuit and the first light-emitting control subcircuit, applying the potential of the fourth node to the fifth node, and applying the drive signal to the light-emitting element to cause the light-emitting element to emit light. [Brief explanation of the drawings]

[0024] In order to more clearly explain the technical solutions of the embodiments of the present invention, the following briefly introduces the accompanying drawings of the present embodiments. It is obvious that the accompanying drawings in the following description only relate to some embodiments of the present invention and are not a limitation on the present invention. [Figure 1A] FIG. 1 is a schematic diagram of a pixel circuit in accordance with at least one embodiment of the present disclosure. [Figure 1B] FIG. 1B is a circuit diagram of a specific example implementation of the pixel circuit shown in FIG. 1A. [Figure 1C] FIG. 2 is a timing signal diagram for a pixel circuit in accordance with at least one embodiment of the present disclosure. [Figure 2A] FIG. 2 is a schematic diagram of a pixel circuit according to some further embodiments of the present disclosure. [Figure 2B]FIG. 2B is a circuit diagram of a specific example implementation of the pixel circuit shown in FIG. 2A. [Figure 3A] FIG. 10 is a schematic diagram of a pixel circuit according to yet another embodiment of the present disclosure. [Figure 3B] FIG. 3B is a circuit diagram of a specific example implementation of the pixel circuit shown in FIG. 3A. [Figure 4A] 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 4B] 2 is a second schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] 3 is a third schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 5B] FIG. 5B is a cross-sectional view taken along the line II' in FIG. 5A. [Figure 5C] FIG. 5B is a cross-sectional view taken along the line II-II' in FIG. 5A. [Figure 6] FIG. 4 is a fourth schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 7A] FIG. 5 is a fifth schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 7B] FIG. 6 is a sixth schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 8A] FIG. 7 is a seventh schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 8B] FIG. 8 is an eighth schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 9A] FIG. 9 is a ninth schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 9B] FIG. 10 is a tenth schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 10A] 1 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. [Figure 10B] FIG. 10B is a cross-sectional view taken along the cross-sectional line CC' in FIG. 10A. DETAILED DESCRIPTION OF THE INVENTION

[0025] In order to more clearly explain the objectives, technical solutions and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is clear that the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Any other embodiments that a person skilled in the art can obtain based on the described embodiments of the present disclosure without any creative work are within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, technical or scientific terms used in this disclosure have the ordinary meaning understood by those skilled in the art. As used in this disclosure, the terms "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, the terms "one," "an," "the," and similar terms do not denote a quantity, but rather indicate the presence of at least one. Similar terms such as "comprise" and "comprises" mean that the element or thing preceding the term includes the element or thing listed thereafter and their equivalents, but do not exclude other elements or things. Similar terms such as "connected" and "connected to each other" are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," and "right" are merely used to indicate relative positions, and if the absolute position of the described object is changed, the relative positions may change accordingly.

[0027] In a display device with integrated imaging elements, arranging the imaging elements in the display area of ​​the display device helps to improve the occupancy rate of the display screen, such as realizing full-screen display. Because a display device is fabricated in the display area, it affects the transmittance of light reaching the imaging elements, thereby affecting the sensing effect. For example, light-emitting elements in sub-pixels, non-light-transmitting routing, etc., may block the light capture of the imaging elements, thereby affecting imaging quality. For example, by reducing the number of pixel circuit structures installed in the display area where the imaging elements are installed, the light transmittance of the area can be improved, and the display area where the imaging elements are installed is called, for example, a light-transmitting display area. For example, pixel circuits connected to light-emitting elements in the light-transmitting display area can be installed in a display area outside the light-transmitting display area, i.e., some light-emitting elements connected to pixel circuits are moved to the light-transmitting display area and do not emit light in situ, thereby improving display uniformity and improving the light transmittance of the light-transmitting display area.

[0028] For example, one implementation is to form the light-transmitting display area by reducing the number of pixel circuits without changing the size of the pixel circuits. For example, the pixel circuits originally located in the light-transmitting display area can be directly removed. Since the pixel circuits correspond to the number of light-emitting elements they drive, the number of light-emitting elements must be reduced accordingly. For example, the effective installation density of light-emitting elements in the light-transmitting display area can be reduced. This method reduces the uniformity of the display brightness.

[0029] For example, one method is to compress the pixel size to secure space in the light-transmitting display area without changing the number of pixel circuits. For example, the size of the pixel circuit is compressed horizontally (row direction) but not changed vertically (column direction). In this way, by providing sufficient pixel circuits, it is possible to drive the same number of light-emitting elements, and therefore the installation density of the light-emitting elements is not affected. For example, the light-emitting elements have a consistent density in the display area. This method can further improve display uniformity and reduce the impact of the installation of the light-transmitting display area on the display effect.

[0030] The pixel electrode of a light-emitting element usually needs to be connected to a pixel circuit that drives the light-emitting element by a connecting line or a connecting electrode. The inventors have discovered that a parasitic capacitance generated between the connecting line or the connecting electrode and other conductive structures can adversely affect the display effect of the light-emitting element. For example, the parasitic capacitance increases the charging time of the pixel electrode, thereby delaying the lighting time of the light-emitting element and shortening the light-emitting time.

[0031] For example, a light-emitting element located in a light-transmitting display region needs to be connected to a pixel circuit structure outside the light-transmitting display region that drives the light-emitting element by a relatively long connecting line, resulting in a relatively large parasitic capacitor on the pixel electrode, which increases the charging time required for the pixel electrode during the light-emitting stage, for example, it takes longer to charge the pixel electrode to the lighting voltage of the light-emitting element during the light-emitting stage (compared to, for example, sub-pixels that emit light in situ in display regions other than the light-transmitting display region), thereby shortening the light-emitting time and ultimately causing brightness unevenness.In addition, in the light-transmitting display region, differences in the length, shape, or position of the connecting line connected to the pixel electrode of the light-emitting element cause differences in the size of the parasitic capacitor, which causes the lighting times of the light-emitting elements to be inconsistent during the light-emitting stage, resulting in display unevenness.

[0032] At least one embodiment of the present disclosure provides a pixel circuit including a driving subcircuit, a data writing subcircuit, a compensation subcircuit, a first switch subcircuit, and a first light-emitting control subcircuit, wherein the driving subcircuit includes a control end connected to a first node, a first end connected to a second node, and a second end connected to a third node, the driving subcircuit is configured to control a drive signal for driving a light-emitting element from the first node to the third node based on a voltage of the first node, the data writing subcircuit is connected to the second node and configured to write a data signal to the second node in response to a first scanning signal, and the compensation subcircuit is connected to the first node and the third node and configured to conduct the first node and the third node in response to a second scanning signal, thereby writing the data signal to the second node. and configured to control the drive subcircuit to write a compensation voltage to the first node based on a signal, the first switch subcircuit configured to control conduction of the drive signal between the third node and the fourth node based on a voltage of the third node in response to a first switch control signal, the first light-emitting control subcircuit connected to a fifth node and connected to a first electrode of the light-emitting element by the fifth node, and the first light-emitting control subcircuit configured to control conduction of the drive signal between the fourth node and the fifth node in response to the first light-emitting control signal so that the drive signal can be applied to the light-emitting element.

[0033] For example, the drive signal may be a drive voltage or a drive current for driving the light emitting element.

[0034] In the pixel circuit according to the embodiment of the present disclosure, the fourth node N4, where parasitic capacitance is likely to occur, in the first light-emitting control sub-circuit is spaced from the fifth node N5, which is directly connected to the light-emitting element, so that the first light-emitting control sub-circuit can control the conduction between the fourth node N4 and the fifth node N5 and charge the fourth node early before the light-emitting stage arrives, for example, by providing enough time to charge the fourth node before the light-emitting stage begins, the impact of the parasitic capacitance at the fourth node on the lighting time of the light-emitting element can be reduced after the circuit enters the light-emitting stage, and the display uniformity can be improved. For example, in the light-emitting stage, the first light-emitting control subcircuit turns on in response to the first light-emitting control signal, thereby conducting the driving signal at the fourth node and the fifth node, and copying the potential of the fourth node to the fifth node connected to the light-emitting element; since the fourth node is already charged early, the potential of the fifth node can quickly reach the lighting voltage of the light-emitting element, so that the light-emitting time is not affected by the parasitic capacitor at the fourth node N4.

[0035] 1A is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure, which includes a driving subcircuit 122, a data writing subcircuit 126, a compensation subcircuit 128, a first switch subcircuit 124, and a first emission control subcircuit 170.

[0036] The driving sub-circuit 122 includes a control end 122a connected to a first node N1, a first end 122b connected to a second node N2, and a second end 122c connected to a third node N3, and is configured to control a driving signal for driving the light emitting element 120 from the first node N1 to the third node N3 based on the voltage of the first node N1. For example, the driving signal may be a driving voltage or a driving current for driving the light emitting element.

[0037] The data writing sub-circuit 126 is connected to the second node N2 and configured to write a data signal Vd to the second node N2 in response to a first scanning signal Ga1. For example, the data writing sub-circuit 126 includes a control end 126a, a first end 126b, and a second end 126c, where the control end 126a is configured to receive the first scanning signal Ga1, the first end 126b is configured to receive the data signal Vd, and the second end 126c is connected to the second node N2. For example, in the data writing and compensation phase, the data writing sub-circuit 126 can be turned on in response to the first scanning signal Ga1, thereby writing a data signal to the first end 122b (second node N2) of the driving sub-circuit 122, storing the data signal, and generating a drive signal to drive the light emitting element 120 to emit light based on the data signal, for example, during the light emitting phase.

[0038] The compensation sub-circuit 128 is connected to the first node N1 and the third node N3 and is configured to control the driving sub-circuit 122 to write a compensation voltage to the first node N1 based on the data signal Vd written to the second node N2 by making the first node N1 and the third node N3 conductive in response to a second scanning signal Ga2. For example, the compensation sub-circuit 128 includes a control end 128a, a first end 128b, and a second end 128c, where the control end 128a is configured to receive the second scanning signal Ga2, the first end 128b is connected to the third node N3, and the second end 128c is connected to the first node N1.

[0039] For example, the first scanning signal Ga1 is the same as the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to the same signal output terminal. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted by the same scanning line.

[0040] In some other examples, the first scanning signal Ga1 may be different from the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to different signal output terminals. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted by different scanning lines.

[0041] The first switch sub-circuit 124 is configured to control conduction of a drive signal between the third node N3 and a fourth node N4 based on the voltage of the third node N3 in response to a first switch control signal SW1. For example, the first switch sub-circuit 124 includes a control end 124a, a first end 124b, and a second end 124c, where the control end 124a is configured to receive the first switch control signal SW1, and the first end 124b and the second end 124c are connected to the third node N3 and the fourth node N4, respectively.

[0042] The first light-emitting control sub-circuit 170 is connected to a fifth node N5 and is connected to the first electrode 134 of the light-emitting element 120 by the fifth node N5, and is configured to control the conduction of a drive signal between the fourth node N4 and the fifth node N5 in response to a first light-emitting control signal EM1 so that the drive signal can be applied to the light-emitting element 120. For example, the first light-emitting control sub-circuit 170 includes a control end 170a, a first end 170b, and a second end 170c, where the control end 170a is configured to receive the first light-emitting control signal EM1, and the first end 170b and the second end 170c are connected to the fourth node N4 and the fifth node N5, respectively.

[0043] The first light-emitting control subcircuit 170 is disposed at a distance between the fourth node N4 and the pixel electrode (i.e., the first electrode 134 of the light-emitting element). By avoiding direct connection of the fourth node N4 to the pixel electrode, the influence of a parasitic capacitor Cp (an example of a second capacitor in the present disclosure) that may be present at the fourth node N4 on the pixel electrode can be effectively reduced. For example, before the light-emitting stage, the first switch subcircuit 124 is turned on and the first light-emitting control subcircuit 170 is turned off, thereby precharging the fourth node N4 (e.g., charging it to the lighting voltage of the light-emitting element). During the light-emitting stage, the first switch subcircuit 124 and the first light-emitting control subcircuit 170 are simultaneously turned on, and the driving current quickly copies the potential on the fourth node N4 to the fifth node N5. This avoids the phenomenon of uneven display (mura) caused by the time required to charge the parasitic capacitor taking up the entire light-emitting time, and improves the uniformity of light emission.

[0044] For example, in the light-emitting stage, the first light-emitting control subcircuit 170 turns on in response to the first light-emitting control signal EM1 provided by the first light-emitting control terminal EM1, and also turns on the first switch subcircuit 124, so that the driving subcircuit 122 is electrically connected to the light-emitting element 120 by the first switch subcircuit 124 and the first light-emitting control subcircuit 170, thereby driving the light-emitting element 120 to emit light under the control of the driving signal; in the non-light-emitting stage, the first light-emitting control subcircuit 170 turns off in response to the first light-emitting control signal EM1, thereby preventing current from flowing through the light-emitting element 120 to emit light, and thereby improving the contrast of the display device accordingly.

[0045] For example, the parasitic capacitor Cp includes a first electrode Cpa and a second electrode Cpb, where the first electrode Cpa is connected to the fourth node and the second electrode Cpb may be, for example, the first electrode 134 of the light-emitting element 120 or other signal routing, i.e., the parasitic capacitor Cp is formed between the second end 170b of the first light-emitting control subcircuit 170 and the first electrode 134 of the light-emitting element 120 or other signal routing.

[0046] For example, the pixel circuit may further include an analog capacitor Cm (an example of a first capacitor in the present disclosure). The analog capacitor Cm includes a first electrode Cma and a second electrode Cmb, where the first electrode Cma is connected to a fourth node, and the second electrode Cmb is configured to apply the same voltage as the second electrode 135 of the light emitting element 120, for example, the second power supply voltage VSS. This allows the analog capacitor Cm to simulate the capacitor of the light emitting element 120 itself, thereby creating an environment at the fourth node N4 that is the same as or similar to the fifth node N5, making it easy to quickly copy the potential of the fourth node N4 to the fifth node N5 during the light emitting stage.

[0047] For example, the pixel circuit may further include a first reset sub-circuit 129 connected to the fifth node N5 and configured to write a first reset voltage Init1 to the fourth node N4 in response to a first reset control signal Rst1.

[0048] For example, the pixel circuit may further include a second reset sub-circuit 125 connected to the first node N1 and configured to write a second reset voltage Init2 to the first node N1 in response to a second reset control signal Rst2.

[0049] For example, the pixel circuit may further include a second light-emitting control sub-circuit 123 connected to a first power supply voltage end VDD and a second node N2 and configured to write the first power supply voltage VDD from the first power supply voltage end VDD to the second node N2 in response to a second light-emitting control signal EM2. For example, the second light-emitting control signal and the first switch control signal SW1 may be the same signal or different signals.

[0050] Also for example, during an initialization stage, the second light-emitting control subcircuit 124 can be turned on in response to a second light-emitting control signal, thereby coupling the reset circuit to perform a reset operation on the drive subcircuit 122 and the light-emitting element 120.

[0051] For example, the first reset voltage Init1 and the second reset voltage Init2 may be the same voltage signal or different voltage signals. For example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same signal or different signals.

[0052] For example, the first reset sub-circuit 129 and the second reset sub-circuit 125 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, thereby applying a first reset voltage Init1 to the first electrode 134 of the light-emitting element 120 and a second reset voltage Init2 to the first node N1, respectively, to perform a reset operation on the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting element 120, and to eliminate the effects of the previous light-emitting stage.

[0053] For example, the pixel circuit may further include a storage sub-circuit 127 including a first end 127a and a second end 127b, the first end 127a and the second end 127b being connected to the first power supply voltage end VDD and a first node N1, respectively. For example, in a data writing and compensation stage, the compensation sub-circuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127. At the same time, the compensation sub-circuit 128 can make the first node N1 and the third node N3 conductive, i.e., electrically connect the control end 122a and the second end 122c of the driving sub-circuit 122, so that information related to the threshold voltage of the driving sub-circuit 122 can be stored in the storage sub-circuit accordingly, so that the stored data signal and threshold voltage can be used to control and compensate the driving sub-circuit 122, for example, in a light-emitting stage.

[0054] For example, the light-emitting element 120 includes a first electrode 134 and a second electrode 135, and the first electrode 134 of the light-emitting element 120 is configured to be connected to the second end 122c of the driving subcircuit 122, and the second electrode 135 of the light-emitting element 120 is configured to be connected to the second power supply voltage end VSS.

[0055] In the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node, and the sixth node described below do not necessarily represent components that actually exist, but rather represent the junctions of connections of related circuits in the circuit diagram.

[0056] In the description of the embodiments of the present disclosure, the symbol Vd can represent a data signal terminal or the level of a data signal. Similarly, the symbols Ga1 and Ga2 can represent a first scanning signal and a second scanning signal, or a first scanning signal terminal and a second scanning signal terminal. The symbols EM1 and EM2 can represent a first light-emitting control signal and a second light-emitting control signal, or a first light-emitting control terminal and a second light-emitting control terminal. The symbols Rst1 and Rst2 can represent a first reset control signal and a second reset control signal, or a first reset control terminal and a second reset control terminal. The symbols Init1 and Init2 can represent a first reset voltage terminal and a second reset voltage terminal, or a first reset voltage and a second reset voltage. The symbol VDD can represent a first power supply voltage terminal or a first power supply voltage. The symbol VSS can represent a second power supply voltage terminal or a second power supply voltage. The following embodiments are similar to this, and their descriptions will be omitted.

[0057] Figure 1B shows a circuit diagram of one specific implementation of the circuit shown in Figure 1A. As shown in Figure 1B, the pixel circuit includes first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 and a storage capacitor Cst.

[0058] 1B, the driving sub-circuit 122 can be implemented as a first transistor T1 (i.e., a driving transistor). A gate of the first transistor T1 is connected to a first node N1 as a control end 122a of the driving sub-circuit 122, a first electrode of the first transistor T1 is connected to a second node N2 as a first end 122b of the driving sub-circuit 122, and a second electrode of the first transistor T1 is connected to a third node N3 as a second end 122c of the driving sub-circuit 122.

[0059] 1B, the data writing sub-circuit 126 can be realized as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second electrode of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.

[0060] 1B, the compensation sub-circuit 128 can be realized as a third transistor T3 (i.e., a compensation transistor). The gate, first electrode, and second electrode of the third transistor T3 are the control end 128a, first end 128b, and second end 128c of the compensation sub-circuit, respectively. The gate of the third transistor T3 is connected to the second scan line (second scan signal end Ga2) to receive the second scan signal, the first electrode of the third transistor T3 is connected to the second end 122c (third node N3) of the driving sub-circuit 122, and the second electrode of the third transistor T3 is connected to the control end 122a (first node N1) of the driving sub-circuit 122.

[0061] 1B, the first light-emitting control sub-circuit 170 can be realized as an eighth transistor T8 (an example of a light-emitting control transistor of the present disclosure). A gate of the eighth transistor T8 is connected to a first light-emitting control line (a first light-emitting control terminal EM1) to receive a first light-emitting control signal EM1, a first electrode of the eighth transistor T8 is connected to a fourth node N4, and a second electrode of the eighth transistor T8 is connected to a fifth node N5.

[0062] 1B, the second light-emitting control sub-circuit 123 can be realized as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the second light-emitting control line (second light-emitting control terminal EM2) to receive the second light-emitting control signal EM2, the first electrode of the fourth transistor T4 is connected to the first power supply voltage terminal VDD to receive the first power supply voltage VDD, and the second electrode of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.

[0063] 1B , the first switch sub-circuit 124 can be realized as a fifth transistor T5, and the gate, first electrode, and second electrode of the fifth transistor T5 are respectively the control end 124a, first end 124b, and second end 124c of the first switch sub-circuit 124. For example, the second light-emitting control signal EM2 is also the first switch control signal SW1. In this situation, the second light-emitting control line or second light-emitting control end is also connected to the gate of the fifth transistor T5 to provide the first switch control signal SW1, and the first electrode of the fifth transistor T5 is connected to the second end 122c (third node N3) of the driving sub-circuit 122, and the second electrode of the fifth transistor T5 is connected to the first end 170b (fourth node N4) of the first light-emitting control sub-circuit 170.

[0064] For example, as shown in FIG. 1B, the memory sub-circuit 127 can be realized as a storage capacitor Cst, which includes a first capacitor electrode Ca and a second capacitor electrode Cb, where the first capacitor electrode Ca is connected to a first power supply voltage terminal VDD and the second capacitor electrode Cb is connected to the control terminal 122a of the driving sub-circuit 122.

[0065] For example, the first reset sub-circuit 129 can be implemented as a seventh transistor T7, and the second reset sub-circuit 125 can be implemented as a sixth transistor T6. The seventh transistor T7 has a gate connected to a first reset control terminal Rst1 and configured to receive a first reset control signal Rst1, a first electrode connected to a first reset voltage terminal Init1 and configured to receive a first reset voltage Init1, and a second electrode connected to a fifth node N5. The sixth transistor T6 has a gate connected to a second reset control terminal Rst2 and configured to receive a second reset control signal Rst2, a first electrode connected to a second reset voltage terminal Init2 and configured to receive a second reset voltage Init2, and a second electrode connected to a first node N4. For example, the first reset voltage terminal Init1 and the second reset voltage terminal Init2 may be the same voltage terminal.

[0066] For example, the light-emitting element 120 may be specifically realized as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a miniature light-emitting diode (micro LED) or a miniature OLED. For example, the light-emitting element 120 may have a top-emission structure, a bottom-emission structure, or a double-sided emission structure. The light-emitting element 120 may emit red light, green light, blue light, white light, or the like. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the light-emitting element 120 includes a first electrode 134, a second electrode 135, and a light-emitting layer interposed between the first electrode 134 and the second electrode 135.

[0067] For example, the first electrode 134 (also called a pixel electrode, e.g., an anode) of the light-emitting element 120 is connected to the fourth node N4 and configured to be connected to the second end 122c of the driving sub-circuit 122 by the second light-emitting control sub-circuit 124, and the second electrode 135 (e.g., a cathode) of the light-emitting element 120 is connected to the second power supply voltage end VSS and configured to receive the second power supply voltage VSS, and the voltage flowing from the second end 122c of the driving sub-circuit 122 to the light-emitting element 120 determines the brightness of the light-emitting element. For example, the second power supply voltage end may be grounded, i.e., VSS may be 0V. For example, the second voltage power supply voltage VSS may be a negative voltage.

[0068] The transistors employed in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching elements with the same characteristics, and the embodiments of the present disclosure will be described using thin film transistors as an example. The source and drain of the transistor employed here may be structurally symmetrical, and therefore the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish between the two electrodes other than the gate of the transistor, one electrode is directly described as a first electrode and the other electrode is directly described as a second electrode.

[0069] Note that transistors can be divided into N-type and P-type transistors according to their characteristics. If the transistor is a P-type transistor, the on-voltage is a low-level voltage (e.g., 0 V, −5 V, −10 V, or other suitable voltage) and the off-voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage). If the transistor is an N-type transistor, the on-voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage) and the off-voltage is a low-level voltage (e.g., 0 V, −5 V, −10 V, or other suitable voltage). For example, the transistors (T1-T9) employed by at least some embodiments of the present disclosure are all P-type transistors, such as low-temperature polysilicon thin-film transistors. However, embodiments of the present disclosure do not limit the type of transistor. If the type of transistor is changed, the connection relationship in the circuit can be adjusted accordingly.

[0070] The following describes the operation principle of the pixel circuit shown in Figure 1B in conjunction with the signal timing chart shown in Figure 1C. As shown in Figure 1C, the display process of each frame image includes four stages: initialization stage 1, data writing and compensation stage 2, pre-charge stage 3, and light-emitting stage 4.

[0071] 1C , in this embodiment, the first scanning signal Ga1 and the second scanning signal Ga2 are the same signal, the first switch control signal SW1 and the second light-emitting control signal EM2 are the same signal, the first reset control signal Rst1 has the same waveform as the first scanning signal Ga1 / second scanning signal Ga2, i.e., the second reset control signal Rst2 and the first scanning signal Ga1 / second scanning signal Ga2 may be the same signal, and the second reset signal Rst2 of the subpixel in the current row has the same waveform as the first scanning signal Ga1 / second scanning signal Ga2 of the subpixel in the previous row, i.e., the same signal. However, this is not a limitation of the present disclosure. In other embodiments, different signals may be used for the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals may be used for the first switch control signal SW1 and the second light-emitting control signal EM2.

[0072] In the initialization stage 1, the second reset control signal Rst2 is input to turn on the sixth transistor T6, and the second reset voltage Init2 is applied to the gate of the first transistor T1, thereby resetting the first node N1.

[0073] In the data writing and compensation stage 2, the first scanning signal Ga1, the second scanning signal Ga2, and the data signal Vd are input to turn on the second transistor T2 and the third transistor T3. The data signal Vd is written from the second transistor T2 to the second node N2 and charges the first node N1 via the first transistor T1 and the third transistor T3, turning off the first transistor T1 until the potential of the first node N1 changes to Vd+Vth, where Vth is the threshold voltage of the first transistor T1. The potential of the first node N1 is stored and maintained in the storage capacitor Cst, i.e., the voltage information including the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, and is used to provide grayscale display data and compensate for the threshold voltage of the first transistor T1 itself during the subsequent light-emitting stage.

[0074] In the data writing and compensation stage 2, the fifth node N5 can be reset by further inputting a first reset control signal Rst1 to turn on the seventh transistor T7 and applying a first reset voltage Init1 to the fifth node N5. For example, the reset to the fifth node N5 can be performed in the initialization stage 1, and the first reset control signal Rst1 and the second reset control signal Rst2 can be the same. The embodiment of the present disclosure is not limited thereto.

[0075] In the pre-charge stage 3, the first switch control signal SW1, the second light-emitting control signal EM2, and the first light-emitting control signal EM1 are input to respectively turn on the fifth transistor T5, the fourth transistor T4, and turn off the eighth transistor T8, thereby charging the fourth node N4 so that the potential of the fourth node N4 reaches a predetermined value, for example, the lighting voltage V0 of the light-emitting element 120. For example, the voltage difference between the lighting voltage V0 and the voltage of the second end 135 of the light-emitting element 120 (for example, the second power supply voltage VSS) is the on-voltage of the light-emitting element 120. For example, the on-voltage is the voltage difference between both ends when the light-emitting element emits light with a brightness of 1 cd / m2. When the second end 135 of the light-emitting element 120 is grounded, the lighting voltage V0 is equal to the value of the on-voltage of the light-emitting element. For example, the time length of the precharge stage 3 is related to the magnitude of the parasitic capacitor Cp at the fourth node N4, and the larger the capacitance value of the parasitic capacitor Cp, the longer the time length of the precharge stage 3.

[0076] In the light-emitting stage 4, the first switch control signal SW1, the second light-emitting control signal EM2, and the first light-emitting control signal EM1 are input to turn on the fifth transistor T5, the fourth transistor T4, and the eighth transistor T8, respectively. The eighth transistor T8 applies the potential of the fourth node N4 to the fifth node N5, and applies a driving current to the OLED to emit light. Since the potential of the fourth node N4 has already been pre-charged, the voltage difference across the OLED can quickly reach the on-voltage of the light-emitting element 120, thereby lighting up the light-emitting element 120. The value of the driving current I flowing through the OLED can be calculated using the following formula: I=K(VGS-Vth)2=K[(Vdata+Vth-VDD)-Vth]2=K(Vdata-VDD)2, where K is the conductivity coefficient of the first transistor.

[0077] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and source (here, the first electrode) of the first transistor T1, and K represents a constant value related to the first transistor T1 itself. As can be seen from the above calculation formula for I, the driving current I flowing through the OLED is independent of the threshold voltage Vth of the first transistor T1, which can realize compensation for the pixel circuit, solve the problem of threshold voltage drift of the driving transistor (the first transistor T1 in the embodiment of the present disclosure) caused by process and long-term operation, and eliminate the influence on the driving current I, thereby improving the display effect of the display device adopting it.

[0078] 2A is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure. The main difference between the pixel circuit according to this embodiment and the pixel circuit shown in FIG. 1A is that the first reset subcircuit 129 is connected to the fourth node N4 and configured to write a first reset voltage Init1 to the fourth node N4 in response to a first reset control signal. After the first light-emitting control subcircuit 170 is turned on, the potential of the fourth node N4 can be quickly copied to the fifth node N5, so that the reset to the fourth node N4 corresponds to the reset to the fifth node N5. For example, referring to FIG. 1C , in the data writing and compensation stage 2, the first reset subcircuit 129 turns on the reset to the fourth node N4 in response to the first reset control signal Rst1, and the first light-emitting control subcircuit 170 turns on in response to the first light-emitting control signal EM1 to copy the potential of the fourth node N4 to the fifth node N5, thereby realizing the reset to the fifth node N5.

[0079] FIG. 2B shows a circuit diagram of one specific implementation of the circuit shown in FIG. 2A, and the specific description may refer to the description of FIG. 1B, and will not be further described.

[0080] Figure 3A is a schematic diagram of a pixel circuit according to yet another embodiment of the present disclosure, the main difference between this pixel circuit and the pixel circuit shown in Figure 1A is that this pixel circuit further includes a second switch sub-circuit 180 connected to a fourth node N4, and a first reset sub-circuit 129 connected to and by a sixth node N6.

[0081] The first reset subcircuit 129 is configured to write a first reset voltage Init1 to the sixth node in response to a first reset control signal Rst1, and the second switch subcircuit 180 is configured to control conduction between the fourth node N4 and the sixth node N6 in response to a second switch control signal SW2, and to reset the fourth node N4 by writing the first reset voltage Init1 from the first reset subcircuit 129 to the fourth node N4.

[0082] 1C , in the data writing and compensation stage 2, the first light-emitting control signal EM1 / second switch control signal SW2 are ON signals, which turn on the second switch sub-circuit 180, so that the second switch sub-circuit 180 does not affect the reset operation of the fourth node N4 by the first reset sub-circuit 129.

[0083] In the circuit layout of an actual display substrate, the second switch sub-circuit 180 can function as an auxiliary sub-circuit for improving the uniformity (eg, etching uniformity) of the display substrate in terms of process.

[0084] 3B shows a circuit diagram of a specific implementation of the circuit shown in FIG. 3A. For example, as shown in FIG. 3B, the second switch sub-circuit 180 can be implemented as a ninth transistor T9, the gate of which is configured to receive the second switch control signal SW2, and the first and second electrodes of which are connected to the fourth node N4 and the sixth node N6, respectively. For a specific description, please refer to the description of FIG. 1B, and no further description will be given.

[0085] At least one embodiment of the present disclosure further provides a pixel circuit driving method for driving the pixel circuit according to any of the above embodiments. The driving method includes at least: a data writing and compensation step, turning on the data writing subcircuit and turning off the first switch subcircuit and the first light-emitting control subcircuit so as to write the data signal to the second node and perform compensation on the driving subcircuit; a precharge step, turning on the first switch subcircuit and turning off the first light-emitting control subcircuit so as to charge the fourth node until the potential of the fourth node reaches a predetermined value; and a light-emitting step, turning on the first switch subcircuit and the first light-emitting control subcircuit, applying the potential of the fourth node to the fifth node, and applying the drive signal to the light-emitting element to cause the light-emitting element to emit light. For details, please refer to the above description and no further description will be provided. For example, the drive signal may be a drive voltage or a drive current for driving the light-emitting element.

[0086] At least one embodiment of the present disclosure further provides a display substrate including a pixel circuit according to any of the above embodiments.

[0087] FIG. 4A is a schematic plan view of a display substrate according to an embodiment of the present disclosure. FIG. 4A illustrates the layout of a display area of ​​the display substrate. As shown in FIG. 4A, the display area 101 of the display substrate 20 is divided into a primary display area 21 and an associated area of ​​a photosensitive element (e.g., a camera). For example, the associated area includes a first display area 22 and a second display area 23, where the first display area at least partially surrounds or completely surrounds the second display area 23. For example, the photosensitive element is disposed corresponding to the second display area 23.

[0088] FIG. 4B is a second schematic plan view of a display substrate according to an embodiment of the present disclosure. FIG. 4B shows a pixel layout diagram of the display substrate. As shown in FIG. 4B, the display substrate 20 includes a plurality of pixel circuits 100 located in a display region 101, and FIG. 4B shows the pixel circuits 100 as rectangular blocks. For example, each pixel circuit 100 may employ a pixel circuit according to any embodiment of the present disclosure. For example, the structure of the pixel circuit 100 can be adjusted accordingly depending on the region in which the pixel circuit 100 is located.

[0089] 4B, the pixel circuits 100 are arranged in rows and columns along a first direction D1 and a second direction D2, which are different from each other, e.g., perpendicular to each other. For example, the pixel rows and pixel columns do not necessarily extend along straight lines but may extend along curves (e.g., broken lines), which generally extend along the first direction D1 or the second direction D2, respectively. For example, the density of pixel circuits in the first display area 22 and the main display area 21 is the same, which improves process uniformity.

[0090] For example, in the main display area 21, the connecting lines between the pixel circuit of each sub-pixel and its driving light-emitting element are relatively short, and the pixel circuit and light-emitting element of the sub-pixel are both located in the main display area, thereby realizing in-situ light emission. For example, the pixel circuit 100 in the main display area 21 may be the pixel circuit shown in Figures 1A-1B or 2A-2B.

[0091] For example, the second display area 23 may not have a complete pixel circuit structure, but may have a partial pixel circuit structure, in order to improve the light transmittance of the second display area 23 and thereby improve the photosensitivity of the photosensitive elements. For example, to improve display uniformity, light-emitting elements may be installed in the second display area 23, but the main structure of the pixel circuit for driving the light-emitting elements may be installed in the first display area 21 around the second display area 23. FIG. 4B schematically shows the light-emitting elements in the second display area 23 as circles, and the light-emitting elements are connected to the pixel circuit structures or signal lines in the first display area 21 by connecting lines (shown as broken lines in FIG. 4B ). When photosensitive elements are installed on one side of the display substrate opposite the display side, light to be detected reaches the photosensitive elements mainly via the second display area 23, as will be described in detail below.

[0092] For example, in the first display area 22, the pixel circuits of a partial sub-pixel are used to drive light-emitting elements located in the second display area 23. For ease of explanation, hereinafter this partial sub-pixel will be referred to as the first sub-pixel.

[0093] For example, the size of the pixel circuits in the first display region 22 is compressed in the first direction D1, so that the number of pixel circuits is greater than the number of light-emitting elements. For example, the pixel circuits of the sub-pixels in this portion may employ the pixel circuits shown in Figures 3A-3B. For example, some sub-pixels in the first display region 22 emit light in situ.

[0094] For example, the first subpixel driving subcircuit 122 and the first switch subcircuit 124 are located in the first display area 22, the first light-emitting control subcircuit 170 and the light-emitting element 120 are located in the second display area 23, the second end of the first light-emitting control subcircuit is electrically connected to the first electrode of the light-emitting element 120, and the first end of the first light-emitting subcircuit is electrically connected to the first switch subcircuit located in the first display area 22 by a connecting line (corresponding to the fourth node N4).

[0095] For example, the connecting line extends from the second display area 23 to the first display area 22, and is prone to forming parasitic capacitors with other conductive structures during the extension process. By placing the first light-emitting control subcircuit 170 in the second display area, i.e., at one end of the connecting line close to the light-emitting elements, the connecting line can be effectively spaced from the light-emitting elements and avoided from being directly connected to the light-emitting elements, thereby effectively reducing the adverse effects of the parasitic capacitors on light emission. For example, before the light-emitting stage arrives, the first switch subcircuit 124 can be turned on and the first light-emitting control subcircuit 170 can be turned off to precharge the connecting line (e.g., charge it to the lighting voltage of the light-emitting elements). During the light-emitting stage, the first switch subcircuit 124 and the first light-emitting control subcircuit 170 can be turned on simultaneously, and the potential on the connecting line can be quickly copied to the pixel electrodes by the driving signal. This avoids the phenomenon of uneven display (mura) caused by the time required to charge the parasitic capacitor taking up the entire light-emitting time, and improves light-emission uniformity.

[0096] As shown in FIG. 4B , the display substrate includes a plurality of gate lines 11 and a plurality of data lines 12. For example, the gate lines 11 extend along a first direction D1, and the data lines 12 extend along a second direction D2. FIG. 4B only shows a rough positional relationship between the gate lines 11, the data lines 12, and the pixel circuits 100 on the display substrate, and specific arrangements can be made according to actual needs. Although FIG. 4B shows each gate line 11 and each data line 12 passing through a first display area 21 and a second display area 22, this is for convenience of illustration and does not limit the present disclosure.

[0097] 4B, the display substrate 20 includes a non-display area 102 located outside the display area 101. The display substrate 20 may further include a gate driving circuit 13 and a data driving circuit 14 located in the non-display area. The gate driving circuit 13 is connected to the pixel circuit units 100 via gate lines 11 to provide various scanning signals and control signals, and the data driving circuit 14 is connected to the pixel circuits 100 via data lines 12 to provide a data signal Vd.

[0098] For example, the display substrate 20 may further include a control circuit (not shown). For example, the control circuit may be configured to control the data driving circuit 14 to apply the data signals and to control the gate driving sub-circuit to apply the scan signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, including, for example, a memory containing executable code and a processor that runs the executable code to perform the detection method.

[0099] For example, the processor may be a central processing unit (CPU) or other type of processing device having data processing and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0100] For example, the storage device may include one or more computer program products, which may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or high-speed cache memory (cache). Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program commands may be stored on the computer-readable storage medium, allowing a processor to perform the desired functions of the program commands. Various application programs and various data may also be stored on the computer-readable storage medium.

[0101] In the following, the structure of a display substrate according to at least one embodiment of the present disclosure will be described in combination with Figures 5A-5C, 6, 7A-7B, 8A-8B, and 9A-9B, taking the first sub-pixel as an example employing the pixel circuit shown in Figures 3A-3B, but this is not intended to limit the present disclosure.

[0102] Figure 5A is a schematic diagram of a first sub-pixel in a display substrate 20 according to at least one embodiment of the present disclosure. Figure 5B is a cross-sectional view taken along line I-I' in Figure 5A. Figure 5C is a cross-sectional view taken along line II-II' in Figure 5A. For clarity, Figures 5B and 5C omit structures that are not directly electrically connected along the cross-sectional line.

[0103] 5A-5B , the first light-emitting control subcircuit (T8) and other subcircuits in the pixel circuit of the first subpixel are all located in the first display area 22, and the first light-emitting control subcircuit and the light-emitting element 120 of the first subpixel are located in the second display area 23. The first light-emitting control subcircuit is connected to the pixel structure located in the first display area 22 by a connecting line 270. One end of the connecting line 270 is electrically connected to the first light-emitting control subcircuit by a via hole 352, and extends from the second display area 23 to the first display area 22 to electrically connect to the first switch subcircuit and the second switch subcircuit. For example, the other end of the connecting line 270 is electrically connected to the second end of the first switch subcircuit (i.e., T5d) and the first end of the second switch subcircuit (i.e., T9s) by a via hole 351. For example, the connecting line 270 is made of a transparent conductive material, which helps to improve the light transmittance of the second display area 23. In FIG. 5A, only the connecting structure at both ends of the connecting line 270 is shown, and the structure of the middle part of the connecting line is schematically shown by a dashed line. The cross-sectional line I-I' extends along the connecting line 270 from the first display area 22 to the second display area 23.

[0104] As can be seen from Figures 5A-5C, a semiconductor layer 102, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a third conductive layer 203, a fourth insulating layer 304, a fourth conductive layer 204, a fifth insulating layer 305, a fifth conductive layer 205, a sixth insulating layer 306, a sixth conductive layer 206, a seventh insulating layer 307 and a seventh conductive layer 207 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate shown in Figure 5A.

[0105] Figure 6 shows the semiconductor layer 102 and first conductive layer (gate layer) 201 of transistors T1-T7 and T9 located in the first display area 22 in the pixel circuit of the first sub-pixel, corresponding to Figure 5A. Figure 7A shows the second conductive layer 202. Figure 7B shows the second conductive layer 202 based on Figure 6. Figure 8A shows the third conductive layer 203. Figure 8B shows the third conductive layer 203 based on Figure 7B. Figures 9A and 9B show the fourth conductive layer 204 and the fifth conductive layer 205, respectively.

[0106] For convenience of explanation, in the following description, Tng, Tns, Tnd, and Tna represent the gate, first electrode, second electrode, and active layer of the n-th transistor Tn, respectively, where N is 1-9.

[0107] In this disclosure, "located in the same layer" refers to two (or more) structures formed by the same deposition process and patterned by the same patterning process, and the materials may be the same or different. In this disclosure, "integral structure" refers to two (or more) structures formed by the same deposition process and patterned by the same patterning process, and the materials may be the same or different.

[0108] For example, as shown in Fig. 6, the first conductive layer 201 includes the gates of each transistor, some scan lines, and control lines, and the gates T1g-T7g and T9g of the transistors T1-T7 and T9 in the first sub-pixel are indicated by dashed lines in Fig. 6.

[0109] The semiconductor layer 102 includes active layers T1a-T7a and T9a of transistors T1-T7 and T9. As shown in FIG. 6, the active layers of transistors T1-T7 and T9 are connected to each other in an integrated structure. For example, referring also to FIG. 5C, the first conductive layer further includes a gate T8g of an eighth transistor T8 located in the second display area 23, and the semiconductor layer 102 further includes an active layer T8a of the eighth transistor T8.

[0110] For example, the display substrate 20 employs a self-alignment process, and performs a conductive treatment (e.g., doping treatment) on the semiconductor layer 102 using the first conductive layer 201 as a mask, thereby making the portions of the semiconductor layer 102 that are not covered by the first conductive layer 201 conductive, thereby making the portions of the semiconductor layer located on both sides of the active layer (channel region) of each transistor conductive, thereby forming the first electrode and second electrode of the transistor, respectively.

[0111] The stability of the gate voltage of the driving transistor has a significant impact on the display uniformity of the display substrate. For example, if the gate leakage of the driving transistor is severe, the gate voltage of the driving transistor will cause insufficient compensation in the threshold compensation stage, i.e., the threshold voltage of the driving transistor will not be fully compensated, so that the driving current in the light-emitting stage is still related to the threshold voltage Vth of the driving transistor, resulting in poor brightness uniformity of the display device.

[0112] For example, as shown in FIG. 6, the third transistor T3 and the sixth transistor T6 each employ a double-gate structure, which improves the scorotron radiation capability of the transistor and reduces leakage current. Because the third transistor T3 and the sixth transistor T6 are both directly connected to the gate of the first transistor T1 (i.e., the driving transistor), the stability of the third transistor T3 and the sixth transistor T6 directly affects the stability of the gate (N1 node) voltage of the first transistor T1. The double-gate structure improves the scorotron radiation capability of the third transistor T3 and the sixth transistor T6, reduces the transistor leakage current, and maintains the voltage at the N1 node. This helps ensure that the threshold voltage of the first transistor T1 is adequately compensated during the compensation phase, further improving the display uniformity of the display substrate during the light-emitting phase.

[0113] For example, the first conductive layer 201 further includes a plurality of scan lines 210, a plurality of reset control lines 220, and a plurality of emission control lines 230, which are insulated from each other. For example, as shown in FIG. 6, each row of sub-pixels corresponds to one reset control line 220, one scan line 210, one second emission control line 230, and one first emission control line (280, 290).

[0114] The scanning line 210 is electrically connected (or integrally structured) with the gate of the second transistor T2 in the sub-pixel of the corresponding row to provide the first scanning signal Ga1, the reset control line 220 is electrically connected with the gate of the sixth transistor T6 in the sub-pixel of the corresponding row to provide the second reset control signal Rst2, and the second light-emitting control line 230 is electrically connected with the gate of the fourth transistor T4 in the sub-pixel of the corresponding row to provide the second light-emitting control signal EM2.

[0115] For example, as shown in FIG. 6, the scanning line 210 is further electrically connected to the gate of the third transistor T3 to provide the second scanning signal Ga2, i.e., the first scanning signal Ga1 and the second scanning signal Ga2 may be the same signal, and the light-emitting control line 230 is further electrically connected to the gate of the fifth transistor T5 to provide the first switch control signal SW1, i.e., the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same signal.

[0116] 5A and 5C , the first light-emitting control line includes a first light-emitting control line portion 280 (an example of an auxiliary light-emitting control line of the present disclosure) located in the first display area 22 and a second light-emitting control line portion 290 located in the second display area 23, and the first light-emitting control line portion 280 and the second light-emitting control line portion 290 are electrically connected to each other (indicated by a dashed line in FIG. 5A ). The second light-emitting control line portion 290 provides a first light-emitting control signal EM1 electrically connected to (or integrally formed with) the gate of an eighth transistor T8 (an example of a light-emitting control transistor of the present disclosure) of a corresponding row of sub-pixels, and the first light-emitting control line portion 280 provides a second switch control signal SW2 electrically connected to (or integrally formed with) the gate of a ninth transistor T9 of a corresponding row of sub-pixels. That is, in the embodiment of the present disclosure, the first light-emitting control signal EM1 and the second switch control signal SW2 are the same signal, but this is not a limitation of the present disclosure. For example, the material of the second light-emitting control line portion 290 is a transparent conductive material that improves the light transmittance of the second display area 23.

[0117] For example, if a second subpixel is disposed in the main display area 21, e.g., the second subpixel is an in-situ light-emitting subpixel, and all subcircuits (transistors) in the pixel circuit of the second subpixel are located in the main display area 21, i.e., the separation between the first light-emitting control subcircuit and other subcircuits as shown in FIG. 5A does not occur. For example, the pixel circuit of the second subpixel may not include a second switch subcircuit and may employ, for example, the pixel circuit shown in FIG. 1A-1B or FIG. 2A-2B. In this situation, the first light-emitting control subcircuit may be located at the position where the second switch subcircuit is located as shown in FIG. 5A, i.e., the eighth transistor T8 is located at the position where the ninth transistor T9 is located, and the first light-emitting control line portion 280 shown in FIG. 5A functions as a first light-emitting control signal EM1 that controls the first light-emitting control subcircuit.

[0118] Therefore, in the pixel circuit shown in FIG. 5A, the provision of the second switch sub-circuit (T9) and the first light-emitting control line portion 280 helps to improve the uniformity of the pixel circuit arrangement in the second display area 23 and the first display area 21, thereby improving the process uniformity in the fabrication process.

[0119] For example, the gate of the seventh transistor T7 of the pixel circuit of the current row is electrically connected to the reset control line 220 corresponding to the pixel circuit of the next row (i.e., the pixel circuit row in which the scanning line that is turned on after the current scanning line is located according to the scanning order of the scanning lines) and receives the first reset control signal Rst1.

[0120] 7A-7B, the second conductive layer 202 includes a first capacitor electrode Ca. The first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the base substrate 101 to form a storage capacitor Cst, i.e., the gate T1g of the first transistor T1 functions as a second capacitor electrode Cb of the storage capacitor Cst. For example, the first capacitor electrode Ca includes an opening 222 that exposes at least a portion of the gate T1g of the first transistor T1 to facilitate electrical connection of the gate T1g with another structure.

[0121] For example, the second conductive layer 202 may further include a plurality of reset voltage lines 240 connected to the subpixels in the plurality of rows in a one-to-one correspondence and extending along the first direction D1, and the reset voltage lines 240 are electrically connected to the first electrodes of the sixth transistors T6 in the corresponding subpixels in the plurality of rows to provide the second reset voltage Init2.

[0122] For example, referring to FIGS. 7B and 8B, the first electrode of the seventh transistor T7 in the subpixel of the present row is electrically connected to the reset voltage line 240 corresponding to the subpixel of the next row to receive the first reset voltage Init1.

[0123] 7A-7B , the second conductive layer 202 may further include a shielding electrode 221. For example, the shielding electrode 221 can protect the signal at the first electrode T2s of the second transistor T2 from other signals by overlapping with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101. Because the first electrode T2s of the second transistor T2 is configured to receive a data signal Vd that determines the display grayscale of the subpixel, the shielding electrode 221 improves the stability of the data signal, thereby improving display performance.

[0124] For example, referring to FIG. 7B and FIG. 6, the shielding electrode 221 further at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 101, improving the stability of the signal on the second electrode T6d, thereby improving the stability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0125] For example, the shielding electrode 221 forms a stabilizing capacitor with the first electrode T2s of the second transistor T2 and the second electrode T6d of the sixth transistor T6, which are directly opposite (overlapping) it. For example, the shielding electrode 221 is configured to load a fixed voltage, and the voltage difference across the capacitor cannot change, thereby improving the stability of the voltages on the first electrode T2s of the second transistor T2, the conductive region T3c of the third transistor T3, and the second electrode T6d of the sixth transistor T6. For example, the shielding electrode 221 is electrically connected to the power line 250 in the third conductive layer 203 and loads the first power supply voltage VDD.

[0126] 7A-7B, the shielding electrode 221 may be L- or V-shaped and include a first branch 221a and a second branch 221b extending in different directions. The first branch 221a at least partially overlaps the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 101, and the second branch 221b at least partially overlaps the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101. For example, the first branch 221a extends along the second direction D2, and the second branch 221b extends along the first direction D1.

[0127] 8A-8B, the third conductive layer 203 includes a plurality of power supply lines 250 extending along the second direction D2. For example, the plurality of power supply lines 250 are electrically connected to a plurality of columns of subpixels in a one-to-one correspondence to provide a first power supply voltage VDD. Referring to FIG. 6, the power supply line 250 is electrically connected to the first capacitor electrode Ca of the corresponding column of subpixels by a via hole 342 and to the first electrode T4d of the fourth transistor T4 by a via hole 343. For example, the power supply line 250 is further electrically connected to the shielding electrode 221 by a via hole 341, thereby providing the shielding electrode 221 with a fixed potential and improving the shielding ability of the shielding electrode. For example, the via holes 342 and 341 both penetrate the third insulating layer 303 , and the via hole 343 penetrates the first insulating layer 301 , the second insulating layer 302 and the third insulating layer 303 .

[0128] For example, the third conductive layer 203 further includes a plurality of data lines 12 extending along the second direction D2. For example, the plurality of data lines 12 are electrically connected to a plurality of columns of sub-pixels in a one-to-one correspondence to provide data signals. For example, the data lines 12 are electrically connected to the first electrodes T2s of the second transistors T2 in the corresponding columns of sub-pixels by via holes 346 to provide the data signals. For example, the via holes 346 penetrate the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.

[0129] For example, the data line 12 includes a data line body extending along the second direction D2, and the line width of the data line body is relatively small, so that the via hole can be easily installed. The data line 12 further includes a data line protrusion 121 extending from the data line body, and the data line protrusion 121 at least partially overlaps with the via hole 346 in a direction perpendicular to the base substrate.

[0130] 5A-5B and 8A-8B, the third conductive layer 203 further includes a connection electrode 231. One end of the connection electrode 231 is electrically connected to the gate T1g of the first transistor T1, i.e., the second capacitor electrode Cb, through the opening 222 in the first capacitor electrode Ca and the via hole 344 in the insulating layer, and the other end is electrically connected to the second electrode T3d of the third transistor T3 through a via hole 345, thereby electrically connecting the second capacitor electrode Cb and the second electrode T3d of the third transistor T3. For example, the via hole 344 penetrates the second insulating layer 302 and the third insulating layer 303. For example, the via hole 345 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.

[0131] 5A-5B, 6, and 8A-8B, the third conductive layer 203 further includes a connection electrode 232 electrically connected to the second electrode T5d of the fifth transistor T5 through a via hole 349 and electrically connected to the connection line 270 through a via hole 351. For example, the via hole 349 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303. The via hole 351 penetrates the fourth insulating layer 304 and the fifth insulating layer 305.

[0132] 8A-8B , the third conductive layer 203 further includes a connecting electrode 233, one end of which is electrically connected to the reset voltage line 240 by a via hole 348 and the other end of which is electrically connected to the first electrode T7s of the seventh transistor T7 by a via hole 347, so that the first electrode T7s of the seventh transistor T7 can receive the first reset voltage Init1 from the reset voltage line 240. For example, the via hole 348 penetrates the third insulating layer 303. For example, the via hole 347 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.

[0133] 8A-8B, the third conductive layer 203 further includes a connecting electrode 234 electrically connected to the first electrode T9s of the ninth transistor T9 and the second electrode T7d of the seventh transistor T7 by a via hole (not shown). The connecting electrode 234 is disposed to match the pattern of the third conductive layer 203 in the primary display area 21 to improve etching uniformity. For example, in the primary display area 21, the second electrode T7d of the seventh transistor T7 is electrically connected to the first electrode of the light emitting element T7 by the connecting electrode 234.

[0134] For example, FIG. 8B shows two reset voltage lines 240, where the reset voltage line 240 correspondingly connected to the first electrode of the seventh transistor T7 in the subpixel of the previous row is connected to the first end of the sixth transistor T6 in the subpixel of the current row to provide the second reset voltage Init2, and the reset voltage line 240 correspondingly connected to the first electrode of the seventh transistor T7 in the subpixel of the current row is connected to the sixth transistor T6 in the subpixel of the next row to provide the second reset voltage Init2.

[0135] 9A, the fourth conductive layer 204 includes a connecting electrode 241 and a shielding electrode 242. Referring to FIG. 3A, the connecting electrode 241 is electrically connected to the connecting electrode 234 by a via hole (not shown). The connecting electrode 241 is disposed to match the pattern of the fourth conductive layer 204 in the main display area 21 to improve etching uniformity. For example, in the main display area 21, the second electrode T7d of the seventh transistor is electrically connected to the first electrode of the light emitting element by the connecting electrode 234 and the connecting electrode 241.

[0136] For example, the shielding electrode 242 at least partially overlaps the connecting electrode 231 in a direction perpendicular to the base substrate, shielding the connecting electrode 231 and thereby improving the stability of the gate signal of the first transistor T1 (i.e., the driving transistor). For example, the pixel circuit in the first display area 22 is electrically connected to the first light-emitting control sub-circuit in the second pixel area 23 by a connecting line (see the connecting line 270′ in FIG. 9B ). The connecting line is likely to overlap the connecting electrode 231 in a direction perpendicular to the base substrate during the stretching process, and the signal on the connecting line is likely to affect the gate signal on the connecting electrode 231. The installation of the shielding electrode 242 can improve the stability of the gate signal of the driving transistor, thereby improving display quality. For example, the shielding electrode 242 is electrically connected to the power supply line 250 by a via hole (not shown) to load the first power supply voltage VDD.

[0137] For example, the shielding electrode 242 is orthogonally projected onto the base substrate, and the connection electrode 231 covers the orthogonally projected onto the base substrate, thereby improving the shielding effect.

[0138] For example, the shielding electrode 242 further at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 101, thereby improving the stability of the signal on the second electrode T6d, thereby improving the stability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0139] 9B shows a pattern of the position where the first subpixel is located corresponding to the fifth conductive layer 205. As shown in FIG. 9B, the fifth conductive layer 205, in addition to including the bottom connecting line 270 connected to the first subpixel, further includes a plurality of connecting lines 270′ connected to other subpixels, and the connecting lines 270′ pass through the position where the first subpixel is located during the stretching process.

[0140] 5A and 5C, the third conductive layer 203 may further include a connecting electrode 235 located in the second display area 23, and the fourth conductive layer 204 may further include a connecting electrode 243 located in the second display area 23. The connecting electrode 235 and the connecting electrode 243 are disposed corresponding to the eighth transistor T8, for example, the number of the connecting electrodes 235 and the connecting electrodes 243 is two, and the two connecting electrodes 235 are disposed corresponding to the two connecting electrodes 243, respectively, and are disposed corresponding to both ends of the gate T8g of the eighth transistor T8, respectively, and both ends of the gate T8g are electrically connected to the upper second light-emitting control line portion 290 by the corresponding connecting electrodes 235, 243, respectively.

[0141] 5A-5C , the third conductive layer 203 may further include a connection electrode 236 (an example of a first connection electrode in the present disclosure) and a connection electrode 237 located in the second display area 23. The connection electrodes 236 and 237 are disposed corresponding to the first electrode T8s and the second electrode T8d of the eighth transistor T8, respectively. The connection electrode 236 is electrically connected to the first electrode T8s of the eighth transistor T8 by a via hole 355 (an example of a first via hole in the present disclosure), and the connection electrode 237 is electrically connected to the second electrode T8d of the eighth transistor T8 by a via hole 354 (an example of a second via hole in the present disclosure). The connection electrode 236 is further electrically connected to an upper connection line 270 by a via hole 352 (another example of a first via hole in the present disclosure), thereby electrically connecting the first electrode T8s of the eighth transistor T8 and the connection line 270. For example, the fourth conductive layer 204 may further include a connection electrode 244, which is located corresponding to the connection electrode 237 and is electrically connected to the connection electrode 236 by a via hole 353 (another example of a second via hole in the present disclosure), and the connection electrode 236 is electrically connected to the first electrode 134 of the upper light-emitting element by a via hole 340, thereby electrically connecting the second electrode T8d of the eighth transistor T8 to the first electrode 134 of the light-emitting element.

[0142] The above-mentioned connection electrodes 235, 236, 237, 243, and 244 are all relay electrodes that pull out the first electrode / second electrode of the transistor located below and electrically connect it to the conductive structure (signal line or electrode) above. This installation can prevent via holes from directly penetrating the base substrate in a direction perpendicular to the substrate, which would otherwise cause the conductive material to be filled too deeply, resulting in poor connection, disconnection, or unevenness. The installation of relay electrodes reduces the depth of the via holes and improves the rate of good contacts.

[0143] As shown in FIG. 5B, the via holes 340, 353, and 354 in the second electrode of the eighth transistor T8 do not overlap any of the via holes in the direction perpendicular to the base substrate.

[0144] 5A-5C, the fifth conductive layer 205 includes a connecting line 270, which extends from the first display area 22 to the second display area 23 and connects the circuit structure located in the first display area 22 with the circuit structure located in the second display area 23. One end of the connecting line 270 is electrically connected to the second electrode T5d of the fifth transistor T5 / the first electrode T9s of the ninth transistor T9 by a via hole 351, and the other end is electrically connected to the first electrode T8s of the eighth transistor T8 by a via hole 352.

[0145] 5A-5C, the sixth conductive layer 206 includes a second light-emitting control line portion 290, for example, the second light-emitting control line portion 290 is located in the second display area 23, and the second light-emitting control line portion 290 is electrically connected to the lower connection electrode 243 by a via hole, thereby connecting to the gate T8g of the eighth transistor T8 to provide the first light-emitting control signal EM1.

[0146] 5A-5B, the seventh conductive layer 207 includes the first electrode 134 of the light-emitting element 120. As shown in FIG.

[0147] 5A-5B, the display substrate 20 may further include a pixel-defining layer 308 on the first electrode located in the light-emitting element. An opening exposing at least a portion of the pixel electrode 134 is formed in the pixel-defining layer 308 to define an opening area (i.e., an effective light-emitting area) 600 of each subpixel of the display substrate. The light-emitting layer 136 of the light-emitting element 120 is formed at least within the opening (the light-emitting layer 136 may further cover a portion of the pixel-defining layer on one side of the light-emitting element away from the first electrode), and a second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120. For example, the second electrode 135 is a common electrode and is disposed over the entire surface of the display substrate 20. For example, the pixel electrode 134 is an anode of the light-emitting element, and the second electrode 135 is a cathode of the light-emitting element.

[0148] 5A illustrates the location of the opening region 600 on the first electrode of the light-emitting element. For example, the first electrode 134 includes an electrode body 134a and an electrode protrusion 134b. The electrode body 134a is used to contact the light-emitting layer 136 of the light-emitting element. The electrode protrusion 134b is electrically connected to the connection electrode 244 through a via hole 340. The electrode body 134a does not overlap the via hole 340 in a direction perpendicular to the base substrate, thereby preventing the via hole 340 from affecting the flatness of the light-emitting layer in the opening region and thus the light-emitting quality. For example, the shape of the electrode body 134a is polygonal, such as a square, pentagon, or hexagon. For example, the electrode body 134a has a symmetry axis extending along the second direction.

[0149] 5A-5B, when the first electrode 134 of the light emitting element is orthogonally projected onto the base substrate, the connecting electrode 236 completely covers the orthogonally projected surface of the base substrate. Because the connecting electrode 236 is typically made of a metal material with a relatively low light transmittance, this arrangement can prevent the connecting electrode 236 from affecting the light transmittance of the second display area 23 and also prevent the connecting electrode 236 from occupying the effective aperture area, thereby improving the aperture ratio of the display substrate.

[0150] For example, as shown in Figures 5A-5B, the orthogonal projection of the via holes 340 / 353 / 354 in the second electrode of the eighth transistor T8 onto the base substrate is farther from the orthogonal projection of the electrode body portion 134a of the first electrode of the light-emitting element onto the base substrate than the orthogonal projection of the via holes 352 / 355 in the first electrode of the eighth transistor T8 onto the base substrate.

[0151] Since the number of via holes in the second electrode of the eighth transistor T8 is relatively large, the overall depth is relatively deep, and the impact on the flatness of the first electrode of the upper light-emitting element is relatively large, the via holes in the second electrode of the eighth transistor T8 are positioned away from the electrode body 134a, so that the via holes can be prevented from affecting the flatness of the electrode body 134a and the light-emitting layer above it, thereby affecting the light-emitting quality.

[0152] 5A-5B , the connecting line 270 tends to at least partially overlap with other conductive structures (e.g., the first electrode 134 of the light-emitting element of the first subpixel and / or the first electrodes of the light-emitting elements of other subpixels) in the direction perpendicular to the base substrate during the extension process, resulting in the formation of a parasitic capacitor Cp. By providing an eighth transistor T8 between the connecting line 270 and the first electrodes of the light-emitting elements, the connecting line 270 is prevented from being directly connected to the light-emitting elements, thereby effectively reducing the adverse effect of the parasitic capacitor on light emission. For example, the connecting line can be precharged (e.g., charged to the lighting voltage of the light-emitting element) before the light-emitting stage begins. After the light-emitting stage begins, the potential prepared on the connecting line 270 can be quickly copied to the first electrodes of the light-emitting elements. This avoids the phenomenon of uneven display (mura) caused by the time required to charge the parasitic capacitor taking up the entire light-emitting time, thereby improving the uniformity of light emission.

[0153] 5A-5B, in a direction perpendicular to the base substrate, the connecting line 270 at least partially overlaps with the electrode body portion of the first electrode of the light emitting element, and the second light-emitting control line portion 290 at least partially overlaps with the first electrode of the light emitting element but does not overlap or barely overlaps with the electrode body portion 134a. For example, in a direction perpendicular to the base substrate, the second light-emitting control line portion 290 is located on one side where the connecting line 270 is close to the first electrode 134 of the light emitting element, thereby preventing the connecting line 270 from affecting the flatness of the light emitting layer in the opening region.

[0154] For example, the base substrate 101 may be a rigid substrate, such as a glass substrate or a silicon substrate, or may be formed from a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylic ester, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC).

[0155] For example, the material of the semiconductor layer 102 includes, but is not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (sexithiophene, polythiophene, etc.).

[0156] For example, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining these metals, or conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0157] For example, the material of the fifth conductive layer 205 and the sixth conductive layer 206 is a transparent conductive material, such as a metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0158] For example, the light-emitting element 120 has a top-emission structure, the first electrode (i.e., pixel electrode) 134 is reflective, and the second electrode 135 is transmissive or semi-transmissive. For example, the first electrode 134 is an anode, and the second electrode 135 is a cathode. For example, the first electrode 134 has an ITO / Ag / ITO stacked structure, where the transparent conductive material ITO is a high-work function material that directly contacts the light-emitting material to improve the cavity injection efficiency, and the metal material Ag helps to improve the reflectivity of the first electrode. For example, the second electrode 135 is a low-work function material that functions as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0159] For example, the first insulating layer 301, the second insulating layer 302, the third insulating layer 303, the fourth insulating layer 304, the fifth insulating layer 305, and the sixth insulating layer 306 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, silicon nitride oxide, or other silicon oxides, silicon nitride, or insulating materials containing metal nitride oxides, such as alumina and titanium nitride. For example, the seventh insulating layer 307 and the pixel defining layer 308 are each made of an organic insulating material, such as polyimide (PI), acrylic ester, epoxy resin, polymethyl methacrylate (PMMA), or other organic insulating material. For example, the seventh insulating layer 307 is a planarization layer, and the material of the seventh insulating layer 307 is, for example, a photoresist material.

[0160] At least one embodiment of the present disclosure further provides a display device including a display substrate 20 and a sensor according to any of the above embodiments. Figure 10A shows a structural schematic diagram of a display device 40 according to some embodiments of the present disclosure. Figure 10B is a cross-sectional view taken along the line CC' in Figure 10A.

[0161] 10A , the sensor 401 is disposed corresponding to the second display region 23 of the display substrate 20 and is disposed on one side of the display substrate facing the display side, for example, on one side of the base substrate 101 away from the light-emitting elements. The sensor 401 is, for example, a photoelectric sensor, and is configured to receive light from a first side of the display substrate and convert the light into an electrical signal to form an image. For example, the light reaches the sensor from the display side through the second display region 23, and the light is, for example, visible light or infrared light. For example, the sensor 401 at least partially overlaps with the first light-emitting control sub-circuit (for example, the eighth transistor T8) of the first sub-pixel in a direction perpendicular to the base substrate.

[0162] For example, the display device 40 further includes a package layer 208 and a cover plate 209 disposed on the display substrate 20. The package layer 208 is configured to seal the light-emitting elements on the display substrate 20 to prevent external moisture and oxygen from penetrating into the light-emitting elements and driving circuits, thereby damaging the device. For example, the package layer 208 may include an organic film or a structure in which organic and inorganic films are alternately stacked. For example, a water-absorbing layer (not shown) configured to absorb water vapor or sol remaining in the previous fabrication process of the light-emitting elements may be further disposed between the package layer 208 and the display substrate 20. The cover plate 208 is, for example, a glass cover plate. For example, the cover plate 209 and the package layer 208 may be an integral structure.

[0163] For example, the sensor 401 may be attached to the rear surface (the surface opposite to the display surface) of the display substrate 20. As shown in Fig. 10B, the imaging element 401 is attached to one side of the base substrate 101 that is away from the second electrodes 136 of the light-emitting elements. The sensor 401 can be realized as, for example, a camera.

[0164] The display device may be any product or component with a display function, such as a digital photo frame, an intelligent handling device, an intelligent watch, a mobile phone, a tablet computer, a display, a notebook computer, a navigator, etc.

[0165] What has been described above is only an exemplary embodiment of the present invention, and is not intended to limit the protection scope of the present invention, which is determined by the appended claims.

Claims

1. A display substrate, A base substrate; a plurality of sub-pixels arranged in an array on the base substrate along a first direction and a second direction; the plurality of sub-pixels include a first sub-pixel including a pixel circuit and a light emitting element; The pixel circuit a drive subcircuit including a control end connected to a first node, a first end connected to a second node, and a second end connected to a third node, the drive subcircuit being configured to control a drive signal for driving the light emitting element from the second node to the third node based on a voltage of the first node; a data write subcircuit coupled to the second node and configured to write a data signal to the second node in response to a first scan signal; a compensation subcircuit connected to the first node and the third node and configured to control the drive subcircuit to write a compensation voltage to the first node based on a data signal written to the second node by conducting the first node and the third node in response to a second scan signal; a first switch subcircuit configured to control conduction of the drive signal between the third node and a fourth node based on a voltage at the third node in response to a first switch control signal; a first light emission control subcircuit connected to the fourth node and a fifth node, connected to a first electrode of the light emitting element by the fifth node, and configured to control conduction of the drive signal between the fourth node and the fifth node in response to a first light emission control signal so that the drive signal can be applied to the light emitting element; the display substrate includes a first display area and a second display area, the first display area at least partially surrounding the second display area; the first display area and the second display area do not overlap each other, and the light transmittance of the second display area is higher than the light transmittance of the first display area; a driving sub-circuit and a first switch sub-circuit of the pixel circuit are both located in the first display area, and a first light-emitting control sub-circuit of the pixel circuit and the light-emitting element are located in the second display area.

2. the pixel circuit further includes a first reset sub-circuit; 2. The display substrate of claim 1, wherein the first reset subcircuit is connected to the fifth node and configured to write a first reset voltage to the fifth node in response to a first reset control signal.

3. the pixel circuit further includes a first reset sub-circuit; 2. The display substrate of claim 1, wherein the first reset subcircuit is connected to the fourth node and configured to write a first reset voltage to the fourth node in response to a first reset control signal.

4. the pixel circuit further includes a first reset sub-circuit and a second switch sub-circuit; the first reset subcircuit is connected to a sixth node and connected to the second switch subcircuit by the sixth node, the first reset subcircuit being configured to write a first reset voltage to the sixth node in response to a first reset control signal; 2. The display substrate of claim 1, wherein the second switch subcircuit is connected to the fourth node and the sixth node and is configured to control conduction between the fourth node and the sixth node in response to a second switch control signal so that the first reset voltage from the first reset subcircuit can be written to the fourth node.

5. the pixel circuit further includes a second light-emission control sub-circuit; A display substrate as described in any one of claims 1 to 4, wherein the second light-emitting control sub-circuit is connected to the second node and a first power supply voltage terminal and is configured to write a first power supply voltage from the first power supply voltage terminal to the second node in response to a second light-emitting control signal.

6. the pixel circuit further includes a storage sub-circuit; 6. The display substrate of claim 5, wherein the storage subcircuit includes a first end and a second end, the first end and the second end of the storage subcircuit being connected to the first power supply voltage end and the first node, respectively.

7. the pixel circuit further includes a second reset sub-circuit; 7. The display substrate of claim 1, wherein the second reset sub-circuit is connected to the first node and configured to write a second reset voltage to the first node in response to a second reset control signal.

8. the pixel circuit further includes a first capacitor; A display substrate as described in any one of claims 1 to 7, wherein the first capacitor includes a first electrode and a second electrode, the first electrode of the first capacitor is connected to the fourth node, and the second electrode of the first capacitor is configured to apply the same voltage as the second electrode of the light-emitting element.

9. further including a connecting line; the connecting line has one end electrically connected to the first light-emission control sub-circuit and the other end extending to the first display area so as to be electrically connected to the first switch sub-circuit; 9. The display substrate according to claim 1, wherein the material of the connection lines is a transparent conductive material.

10. The display substrate according to claim 9 , wherein the connecting lines at least partially overlap the first electrodes of the light-emitting elements in a direction perpendicular to the base substrate.

11. the first light emission control subcircuit includes a light emission control transistor; a first electrode of the light-emitting control transistor is electrically connected to the connection line through a first via hole; The display substrate according to claim 9 , wherein the second electrode of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through a second via hole.

12. further including a first connection electrode; the first connection electrode is located on one side of the connection line that is adjacent to the base substrate; The display substrate according to claim 11 , wherein the first electrode of the light-emitting control transistor is electrically connected to the connection line by the first connection electrode.

13. The display substrate of claim 12 , wherein the first electrodes of the light-emitting elements are orthogonally projected onto the base substrate and the first connecting electrodes are orthogonally projected onto the base substrate.

14. the first electrode of the light emitting element includes an electrode body and an electrode protrusion protruding from the electrode body; the electrode body is used to contact the light-emitting layer of the light-emitting element, and the electrode protrusion is electrically connected to the second electrode of the light-emitting control transistor through the second via hole; A display substrate described in any one of claims 11 to 13, wherein the second via hole is projected onto the base substrate so that the electrode main body is further away from the orthogonal projection onto the base substrate than the first via hole is projected onto the base substrate.

15. further comprising a light-emitting control line located in the second display area; the light-emitting control line is made of a transparent conductive material; 15. The display substrate of claim 11, wherein the light-emitting control line is electrically connected to the gate of the light-emitting control transistor to provide the light-emitting control signal.

16. The display substrate of claim 15 , wherein the light-emitting control line is located on one side of the connecting line adjacent to the first electrode of the light-emitting element in a direction perpendicular to the base substrate.

17. A display device comprising a display substrate described in any one of claims 1 to 16.

18. further comprising a sensor; the display substrate has a first side for display and a second side opposite the first side; 18. The display device of claim 17, wherein the sensor is disposed on a second side of the display substrate and configured to receive and sense light passing through the second display area from the first side of the display substrate.

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