Vertical SIC semiconductor devices with improved durability.

Abstract

To provide a vertical semiconductor device with improved radiation tolerance.SOLUTION: A vertical semiconductor device has a substrate having a first doping type, a drift layer on the substrate having a first doping type, and a diffusion layer on the drift layer having a first doping type, the substrate and drift layer contain silicon carbide, the maximum doping concentration of the diffusion layer is greater than the maximum doping concentration of the drift layer, and the doping concentration of the substrate is greater than the doping concentration of the drift layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to vertical semiconductor devices, and more particularly to vertical semiconductor devices for power applications having improved durability due to enhanced radiation hardness. [Background technology]

[0002] There are several types of vertical semiconductor devices, each of which can be used for different applications. One notable application of vertical semiconductor devices is high-power applications. In particular, devices such as PiN diodes, Schottky diodes, and vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) can be rated for high blocking voltages and are therefore often used in these power applications. For illustrative purposes, FIG. 1 shows the general structure of a conventional vertical semiconductor device 10. The conventional vertical semiconductor device 10 includes a substrate 12 and a drift layer 14 above the substrate 12. A graph shows the relative doping concentrations of the substrate 12 and the drift layer 14. As shown, the substrate 12 is much more heavily doped than the drift layer 14. Implant regions, additional semiconductor layers, and / or metal layers may be added to the conventional vertical semiconductor device 10 to provide a PiN diode, Schottky diode, MOSFET, or any other type of device. When completed, the conventional vertical semiconductor device 10 can provide a high blocking voltage and, therefore, can be useful for high-power applications, as described above. However, conventional vertical semiconductor devices 10 may fail at high blocking voltages due to radiation intolerance. Summary of the Invention

[0003] The present disclosure relates to vertical semiconductor devices, and more particularly to vertical semiconductor devices for power applications having improved durability due to enhanced radiation hardness.

[0004] In a first embodiment, a vertical semiconductor device includes a substrate, a buffer layer, a drift layer, and a diffusion layer. The substrate has a first doping type. The buffer layer is on the substrate and has the first doping type. The drift layer is on the buffer layer and has the first doping type. The diffusion layer is on the drift layer and has the first doping type, and the substrate, buffer layer, and drift layer are formed from silicon carbide.

[0005] The doping concentration of the buffer layer can be at least 10 times the doping concentration of the drift layer, and may be 10-30 times the doping concentration of the drift layer, or 15-25 times the doping concentration of the drift layer.

[0006] The thickness of the buffer layer can be 10 to 30% of the thickness of the drift layer, or 15 to 25% of the thickness of the drift layer. For example, the doping concentration of the buffer layer can be 10 to 30 times the doping concentration of the drift layer, and the thickness of the buffer layer can be 10 to 30% of the thickness of the drift layer. Alternatively, the doping concentration of the buffer layer can be 15 to 25 times the doping concentration of the drift layer, and the thickness of the buffer layer can be 15 to 25% of the thickness of the drift layer.

[0007] The diffusion layer may have a doping concentration that is 2 to 1000 times the doping concentration of the drift layer. The buffer layer and drift layer may be uniformly doped in certain configurations, with the thickness of the diffusion layer being less than the thickness of the drift layer.

[0008] In one configuration, the drift layer doping concentration is 1×10 13 cm -3 ~1×10 17 cm -3 The drift layer has a thickness of 1 to 4 micrometers. The doping concentration of the buffer layer is 1×10 17 cm -3 ~5×10 18 cm -3 may be.

[0009] In a second embodiment, a vertical semiconductor device includes a substrate formed of silicon carbide, a buffer layer, first and second drift layers, and a diffusion layer. The substrate has a first doping type. The first and second drift layers are on the substrate and have the first doping type, and the second drift layer is between the first drift layer and the substrate. The diffusion layer is on the first drift layer and has the first doping type.

[0010] In one configuration, the doping concentration of the second drift layer is higher than the doping concentration of the first drift layer. For example, the doping concentration of the second drift layer may be 1.1 to 3 times the doping concentration of the first drift layer. The thickness of the second drift layer may be smaller than the thickness of the first drift layer. For example, the doping concentrations of the first drift layer and the second drift layer may be 1×10 13 cm -3 ~1×10 17 cm -3 The thickness of the first drift layer may be 2 to 50 micrometers, and the thickness of the second drift layer may be 1 to 30 micrometers. In this embodiment, a buffer layer does not have to be provided between the substrate and either the first drift layer or the second drift layer.

[0011] In a third embodiment, a vertical semiconductor device includes a substrate formed of silicon carbide, a buffer layer, a drift layer, and a diffusion layer. The substrate has a first doping type. The buffer layer is on the substrate and has the first doping type. The first and second drift layers are on the buffer layer and have the first doping type, and the second drift layer is between the first drift layer and the substrate. The diffusion layer is on the first drift layer and has the first doping type.

[0012] In one configuration, the doping concentration of the second drift layer is higher than the doping concentration of the first drift layer. The doping concentration of the second drift layer may be higher than the doping concentration of the first drift layer, and the thickness of the second drift layer may be smaller than the thickness of the first drift layer. For example, the doping concentration of the second drift layer is 1.1 to 3 times the doping concentration of the first drift layer. The doping concentration of the buffer layer may be at least 10 times the average doping concentration of the first drift layer and the second drift layer, or 10 to 30 times the average doping concentration of the first drift layer and the second drift layer. The thickness of the buffer layer may be 10 to 30% of the combined thickness of the first drift layer and the second drift layer.

[0013] In one configuration, the doping concentration of the buffer layer is 10 to 30 times that of the drift layer, and the thickness of the buffer layer is 10 to 30% of the thickness of the drift layer. The diffusion layer may have a doping concentration that is 2 to 1000 times that of the drift layer. Both the buffer layer and the drift layer may be uniformly doped or graded doped. The thickness of the diffusion layer may be less than the combined thickness of the first and second drift layers.

[0014] In one configuration, the doping concentration of the first drift layer and the second drift layer is 1×10 13 cm -3 ~1×10 17 cm -3 The thickness of the first drift layer may be 2 to 50 micrometers, and the thickness of the second drift layer may be 1 to 30 micrometers. The doping concentration of the buffer layer may be 1×10 17 cm -3 ~5×10 18 cm -3 may be.

[0015] In a fourth embodiment, a vertical semiconductor device includes a substrate formed of silicon carbide, a drift layer, and a diffusion layer. The substrate has a first doping type. The drift layer overlies the substrate and has the first doping type and a graded doping profile. The diffusion layer overlies the drift layer and has the first doping type. The graded doping profile may increase continuously through the drift layer from the diffusion layer to the substrate. The doping profile of the diffusion layer may be graded or uniform throughout the diffusion layer.

[0016] In one configuration, the maximum doping concentration of the diffusion layer may be higher than the maximum doping concentration of the drift layer. The doping concentration of the substrate may be higher than the maximum doping concentration of the drift layer. The doping concentration of the graded doping profile may range from 1×10 13 cm -3 ~1×10 17 cm -3 The drift layer may have a thickness of 1 to 4 micrometers.

[0017] In one configuration, the graded doping profile increases continuously through the drift layer from the diffusion layer to the substrate, the doping concentration of the diffusion layer is uniform throughout the diffusion layer, the maximum doping concentration of the diffusion layer is greater than the maximum doping concentration of the drift layer, and there is no buffer layer between the substrate and the drift layer. The doping concentration range of the graded doping profile is from 1×10 13 cm -3 ~1×10 17 cm -3 may be.

[0018] In a fifth embodiment, a vertical semiconductor device includes a substrate formed of silicon carbide, a buffer layer, a drift layer, and a diffusion layer. The substrate has a first doping type. The buffer layer overlies the substrate and has the first doping type. The drift layer overlies the buffer and has the first doping type and a graded doping profile. The diffusion layer overlies the drift layer and has the first doping type.

[0019] In one configuration, the graded doping profile may increase continuously through the drift layer from the diffusion layer to the substrate. The doping profile of the diffusion layer may be graded or uniform throughout the diffusion layer. The maximum doping concentration of the diffusion layer may be higher than the maximum doping concentration of the drift layer.

[0020] The doping concentration of the substrate may be higher than the doping concentration of the drift layer, and the doping concentration of the graded doping profile may range from 1×10 13 cm -3 ~1×10 17 cm -3 The drift layer may have a thickness of 1 to 4 micrometers.

[0021] In one configuration, the graded doping profile increases continuously through the drift layer from the diffusion layer to the substrate, the doping concentration of the diffusion layer is uniform throughout the diffusion layer, and the maximum doping concentration of the diffusion layer is higher than the maximum doping concentration of the drift layer.

[0022] In one configuration, the graded doping profile increases continuously through the drift layer from the diffusion layer to the substrate, the graded doping profile of the diffusion layer decreases continuously through the diffusion layer from the top of the diffusion layer to the drift layer, and the graded doping profile of the buffer layer increases continuously through the buffer layer from the diffusion layer to the substrate. The maximum doping concentration of the diffusion layer may be higher than the maximum doping concentration of the drift layer.

[0023] In another embodiment, a vertical semiconductor device includes a substrate, a buffer layer over the substrate, and a drift layer over the buffer layer. The substrate has a first doping type and a first doping concentration. The buffer layer has the first doping type and a second doping concentration less than the first doping concentration. The drift layer has the first doping type and a third doping concentration less than the second doping concentration. The provision of the substrate, buffer layer, and drift layer improves the radiation tolerance of the vertical semiconductor device, thereby improving its durability.

[0024] In yet another embodiment, a method includes providing a substrate, providing a buffer layer over the substrate, and providing a drift layer over the buffer layer. The substrate has a first doping type and a first doping concentration. The buffer layer has the first doping type and a second doping concentration less than the first doping concentration. The drift layer has the first doping type and a third doping concentration less than the second doping concentration. Providing the substrate, buffer layer, and drift layer in this manner improves the radiation tolerance and durability of the vertical semiconductor device.

[0025] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0026] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 illustrates a conventional vertical semiconductor device. [Figure 2] 1 is a graph showing the operating characteristics of a conventional vertical semiconductor device. [Figure 3] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 4A]1 is a graph illustrating the operating characteristics of a vertical semiconductor device according to one embodiment of the present disclosure. [Figure 4B] 10 is a graph illustrating another operational characteristic of a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 4C] 10 is a graph illustrating yet another operational characteristic of a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 5] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 6] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 7] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 8] 1 is a graph illustrating the operating characteristics of a vertical semiconductor device according to various embodiments of the present disclosure. [Figure 9] FIG. 1 illustrates a PiN diode according to an embodiment of the present disclosure. [Figure 10] FIG. 1 illustrates a Schottky barrier diode according to an embodiment of the present disclosure. [Figure 11] FIG. 1 illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to one embodiment of the present disclosure. [Figure 12] 1 is a flowchart illustrating a method for fabricating a vertical semiconductor device according to one embodiment of the present disclosure. [Figure 13A] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 13B] 13B is a graph showing the electric field in a vertical semiconductor device for the embodiment of FIG. 13A. [Figure 13C] 13B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 13A. [Figure 14A] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 14B] 14B is a graph showing the electric field in a vertical semiconductor device for the embodiment of FIG. 14A. [Figure 14C] 14B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 14A. [Figure 15A] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 15B] 15B is a graph showing the electric field in a vertical semiconductor device for the embodiment of FIG. 15A. [Figure 15C] 15B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 15A. [Figure 16A] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 16B] 16B is a graph showing the electric field in a vertical semiconductor device for the embodiment of FIG. 16A. [Figure 16C] 16B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 16A. [Figure 17A] FIG. 1 illustrates a vertical semiconductor device according to an embodiment of the present disclosure. [Figure 17B] 17B is a graph illustrating relative graded doping center levels across various layers of a vertical semiconductor device for the embodiment of FIG. 17A. [Figure 17C] 17B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 17A. [Figure 18] FIG. 1 illustrates a vertical power device according to an embodiment of the present disclosure. [Figure 19] 19 is a graph illustrating relative graded doping center levels across various layers of a vertical semiconductor device for the embodiment of FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0028] The embodiments described below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best modes for practicing the embodiments. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically addressed herein. It is understood that these concepts and applications are within the scope of this disclosure and the appended claims.

[0029] Although terms such as "first," "second," etc. may be used herein to describe various elements, it should be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] When an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it is understood that it can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it is understood that it can be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0031] Relative terms such as "below" or "above" or "upper" or "bottom" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms and those described above are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "including," and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and related art, and are not to be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0034] FIG. 2 is a graph illustrating an exemplary relationship between the current through a conventional vertical semiconductor device 10 and the voltage across the conventional vertical semiconductor device 10. As shown, the current through the device maintains a relatively consistent leakage current of 1 picoampere for blocking voltages up to 1600 volts (this graph is applicable to devices rated for blocking voltages up to 1200 volts and forward currents up to 50 amperes, and similar curves show the same general characteristics for devices having other ratings). Above 1600 volts, the conventional vertical semiconductor device 10 begins to experience avalanche breakdown, and thus the current through the device increases sharply. Above 1 ampere, the conventional vertical semiconductor device 10 experiences a second breakdown, in which the current through the device continues to increase and the voltage across the device drops sharply. The extent to which the conventional vertical semiconductor device 10 suffers this second breakdown (i.e., the voltage at which the second breakdown occurs) is proportional to the device's ability to withstand radiation. This is because when operating at high voltages, radiation particles such as terrestrial neutrons or heavy ions collide with charged particles in the device, knocking these charged particles off and causing a cascade effect that causes the device to "jump" from the bottom of the curve shown in Figure 2 to the top where a second breakdown occurs. When this occurs, the conventional vertical semiconductor device 10 fails catastrophically.

[0035] In light of the above, there is a need for vertical semiconductors with improved radiation resistance and, therefore, improved durability. Accordingly, FIG. 3 illustrates the basic structure of a vertical semiconductor device 16 according to one embodiment of the present disclosure. The vertical semiconductor device 16 includes a substrate 18, a buffer layer 20 on the substrate 18, and a drift layer 22 on the buffer layer 20. A graph illustrates the relative doping concentrations of the substrate 18, the buffer layer 20, and the drift layer 22. As illustrated, the substrate 18 is more highly doped than the buffer layer 20, which is more highly doped than the drift layer 22. Notably, the substrate 18, the buffer layer 20, and the drift layer 22 are all doped in a relatively consistent manner, thus forming a step doping profile as illustrated. By providing the buffer layer 20 with a doping concentration higher than the drift layer 22 but lower than the substrate 18, a buffer is formed for charge particles that may be accelerated by collision with radiated particles, allowing these accelerated charge particles to recombine instead of passing through the vertical semiconductor device 16.

[0036] In particular, the thicknesses and doping concentrations of the substrate 18, buffer layer 20, and drift layer 22 are merely exemplary. In particular, these thicknesses and doping concentrations are shown for a device rated at 1200 volts. Those skilled in the art will readily appreciate that a higher blocking voltage may dictate a greater thickness and / or a reduced doping concentration of the drift layer 22, and in some embodiments, the buffer layer 20. However, the relationship between the thickness and doping concentration of these layers remains relatively constant. In one embodiment, the thickness of the buffer layer 20 may be 5% to 35% of the thickness of the drift layer 22. In certain embodiments, the thickness of buffer layer 20 may be 5% to 10% of the thickness of drift layer 22, 10% to 15% of the thickness of drift layer 22, 15% to 20% of the thickness of drift layer 22, 20% to 25% of the thickness of drift layer 22, 25% to 30% of the thickness of drift layer 22, 30% to 35% of the thickness of drift layer 22, 15% to 15% of the thickness of drift layer 22, and 25% to 35% of the thickness of drift layer 22. Additionally, the doping concentration of buffer layer 20 may vary between 20% and 90% of the doping concentration of substrate 18 while remaining at least 20% higher than the doping concentration of drift layer 22. In certain embodiments, the doping concentration of buffer layer 20 may be 20% to 30% of the doping concentration of substrate 18, 30% to 40% of the doping concentration of substrate 18, 40% to 50% of the doping concentration of substrate 18, 50% to 60% of the doping concentration of substrate 18, 60% to 70% of the doping concentration of substrate 18, 70% to 80% of the doping concentration of substrate 18, and 80% to 90% of the doping concentration of substrate 18.

[0037] In one embodiment, the substrate 18, buffer layer 20, and drift layer 22 are silicon carbide (SiC). Thus, the buffer layer 20 may be an epitaxial layer grown on the substrate 18 before the drift layer 22. The drift layer 22 may then be grown on top of the buffer layer 20. The buffer layer 20 may be grown in an environment with a dopant to provide the desired doping concentration, or may be grown and subsequently implanted (e.g., via ion implantation) to the desired doping concentration. In other embodiments, the buffer layer 20 may be an implanted region within the surface of the substrate 18. Because the substrate 18 is more highly doped than the desired doping level of the buffer layer 20, the substrate 18 may be doped with the opposite doping type to reduce its net doping concentration (e.g., if the substrate 18 is an n-type substrate, it may be doped with a p-type dopant). Notably, the principles of the present disclosure apply equally to n-type or p-type substrates, buffer layers, and drift layers. That is, the principles of the present disclosure can be applied equally to n-type and p-type devices.

[0038] FIG. 4A is a graph illustrating the effect of buffer layer 20 on second breakdown of vertical semiconductor device 16. In particular, FIG. 17 cm -3 4A illustrates the relationship between the current through the vertical semiconductor device 16 and the voltage across the vertical semiconductor device 16 for several different thicknesses of the buffer layer 20 at a doping concentration of 0.1 V. As illustrated, as the thickness of the buffer layer 20 increases, the voltage at which second breakdown occurs also increases. As defined herein, the second breakdown voltage is the lowest voltage at which second breakdown occurs and reflects the left endpoint at the top of the graph shown in FIG. 4A. Increasing the second breakdown voltage can significantly improve the radiation tolerance, and therefore the ruggedness, of the vertical semiconductor device 16. In one embodiment, the buffer layer 20 increases the second breakdown voltage so that it is greater than the avalanche voltage.

[0039] FIG. 4B is a graph illustrating the effect of the buffer layer 20 on both the avalanche breakdown voltage and the second breakdown voltage. In particular, FIG. 4B shows the relationship between the avalanche breakdown voltage and the second breakdown voltage versus the doping concentration of the buffer layer 20 when the buffer layer is 1 μm thick. As shown, as the doping concentration of the buffer layer 20 increases, the second breakdown voltage also increases up to a point where it begins to drop rapidly. Note that the doping concentration of the buffer layer 20 has only a small effect on the avalanche breakdown voltage, so the use of the buffer layer 20 does not degrade the performance of the vertical semiconductor device 16.

[0040] 4C is a graph illustrating the effect of buffer layer 20 on the failure rate of vertical semiconductor device 16. In particular, FIG. 4C shows the relationship between failure rate (as a function of device time) and voltage across the device. The first line shows the failure rate for devices without buffer layer 20, and the second line shows the failure rate for devices including buffer layer 20. As shown, the failure rate for devices including buffer layer 20 is significantly lower for a given device voltage.

[0041] FIG. 5 illustrates a vertical semiconductor device 16 according to an additional embodiment of the present disclosure. The vertical semiconductor device 16 illustrated in FIG. 5 is substantially similar to that illustrated in FIG. 3 , except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 20 provides a linearly graded doping concentration that decreases in proportion to the distance from the drift layer 22, such that the overall doping profile of the device includes a step between the drift layer 22 and the buffer layer 20 and another step between the buffer layer 20 and the substrate 18. In this embodiment, the buffer layer 20 may be thicker to allow for a linear transition in its doping profile. Such a doping profile may be formed by first growing the buffer layer 20 and then performing ion implantation thereon, or by growing the buffer layer 20 in an environment in which the concentration of dopants is controlled throughout the growth process. Notably, this doping profile is merely exemplary, and any linearly graded doping concentration may be substituted for that illustrated in FIG. 5 without departing from the principles of the present disclosure.

[0042] FIG. 6 illustrates a vertical semiconductor device 16 according to an additional embodiment of the present disclosure. The vertical semiconductor device 16 illustrated in FIG. 6 is substantially similar to that illustrated in FIG. 3 , except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 20 provides a substantially smooth transition between the doping concentration of the drift layer 22 and the doping concentration of the substrate 18. In this embodiment, the buffer layer 20 may be substantially thick to enable a transition in its doping profile. Such a doping profile may be formed by first growing the buffer layer 20 and then performing ion implantation thereon, or by growing the buffer layer 20 in an environment in which the concentration of dopants is controlled throughout the growth process. Notably, this doping profile is merely exemplary, and a linear or any other graded doping concentration may be substituted for that illustrated in FIG. 6 without departing from the principles of the present disclosure.

[0043] FIG. 7 illustrates a vertical semiconductor device 16 according to an additional embodiment of the present disclosure. The vertical semiconductor device 16 illustrated in FIG. 7 is substantially similar to that illustrated in FIG. 3, except for the doping profile of the device and the relative thicknesses of the layers. Notably, the buffer layer 20 is provided as a doping “spike” and is not directly on the substrate 18. In this embodiment, the buffer layer 20 may be thinned. Such a doping profile may be formed by separate growth on a small portion of the drift layer 22, or by growing a small portion of the drift layer 22, performing ion implantation to form the buffer layer 20, and then growing the remainder of the drift layer 22. Notably, this doping profile is merely exemplary, and any “spike” doping profile may be substituted for that illustrated in FIG. 7 without departing from the principles of the present disclosure.

[0044] 8 illustrates the effect of the buffer layer 20 of the embodiments shown in FIGS. 3, 5, 6, and 7 on the second breakdown of the vertical semiconductor device 16. As illustrated, the buffer layer 20 significantly increases the second breakdown voltage for each embodiment when compared to a conventional vertical semiconductor device that does not include the buffer layer 20. As discussed above, this significantly increases the radiation tolerance and therefore the ruggedness of the vertical semiconductor device 16.

[0045] As mentioned above, some implants, additional semiconductor layers, and / or metal layers may determine the device type, and therefore the functionality, of the vertical semiconductor device 16. In one embodiment, the vertical semiconductor device 16 is a PiN diode, as shown in FIG. 9. Accordingly, the vertical semiconductor device 16 includes a p-layer 24 on the drift layer 22, an anode 26 on the p-layer 24, and a cathode 28 on the substrate 18 opposite the buffer layer 20. In another embodiment, the vertical semiconductor device 16 is a Schottky diode, as shown in FIG. 10. Accordingly, the vertical semiconductor device 16 includes an anode 30 on the drift layer 22 and a cathode 32 on the substrate 18 opposite the buffer layer 20. One or more Schottky barrier regions 34 having a doping type opposite that of the drift layer may be provided below the anode 30 to create a Schottky barrier diode (SBD). In yet another embodiment, the vertical semiconductor device 16 is a MOSFET, as shown in FIG. 11. Thus, vertical semiconductor device 16 includes a pair of junction implant regions 36 laterally separated from one another and including a source region 36A and a well region 36B, a gate oxide layer 38 extending between junction implant regions 36, a gate contact 40 on gate oxide layer 38, a pair of source contacts 42 on portions of junction implant regions 36, and a drain contact 44 on substrate 18 opposite buffer layer 20. Those skilled in the art will understand that additional implant regions, semiconductor layers, and / or metal layers may be provided to provide any number of different types of semiconductor devices, all of which are contemplated herein.

[0046] FIG. 12 is a flow diagram illustrating a method for fabricating a vertical semiconductor device according to one embodiment of the present disclosure. First, a substrate is provided (Step 100). The substrate may be silicon carbide (SiC), as described above, and has a first doping type and a first doping concentration. Then, a buffer layer is provided on the substrate (Step 102). The buffer layer has a first doping type and a second doping concentration that is lower than the first doping concentration. The buffer layer may be epitaxially grown in an environment containing dopants designed to form a desired doping profile, or may be grown and subsequently implanted (e.g., via ion implantation) to produce the desired doping profile. Next, a drift layer is provided on the buffer layer (Step 104). The drift layer has a first doping type and a third doping concentration that is lower than the second doping concentration. The drift layer may be epitaxially grown on the buffer layer. Finally, one or more additional implant regions, semiconductor layers, and / or metal layers may be provided to provide a desired type of semiconductor device (step 106). For example, a PiN diode, a Schottky diode, a MOSFET, or any other type of semiconductor device may be created by providing different implant regions, semiconductor layers, and / or metal layers.

[0047] The following disclosure provides further concepts for achieving radiation hardening of SiC power diodes and MOSFETs. These devices can potentially suffer catastrophic failure from high-energy particles (i.e., neutrons, protons, or heavy ions) or energetic bombardment (i.e., gamma rays, X-rays) while exposed to high blocking fields. This concept also supports better bipolar switching for most power devices that rapidly switch in a bipolar charge state. The concepts disclosed herein allow diode and MOSFET components to operate at higher voltages without the need for voltage derating, as is currently done. Devices fabricated from SiC or other semiconductor materials can benefit from these approaches, including, but not limited to, vertical power diodes, MOSFETs, trench MOSFETs, IGBTs, and the like. Additional embodiments are provided below, and each of the following embodiments may be implemented as any of these device types.

[0048] Typically, for better resistance to radiation-induced breakdown at high operating voltages (high electric fields), it is known that the resistance of the drift layer can be increased by increasing the drift layer thickness or decreasing the drift layer doping. However, this means that the device has a higher resistance and therefore more power loss in normal use. Similarly, the device can be operated at a lower voltage to avoid radiation-induced breakdown, but this voltage limitation may render the component unusable for its intended application.

[0049] SiC and Si devices can fail due to terrestrial neutron or heavy ion bombardment at high semiconductor fields, but they are known to behave differently. For Si devices, modifications to the drift layer design have been shown to improve the radiation tolerance of devices under heavy ion bombardment. Silicon device durability can be correlated to device breakdown, specifically an event called "second breakdown" that occurs after a device at high stopping fields enters bipolar conduction mode. The higher the onset of second breakdown voltage, the better the device's durability in a radiation environment.

[0050] Studies have shown that drift design modifications to Si devices to keep device resistance constant can increase the second breakdown voltage, but this redesign reduces the avalanche voltage and makes the device more susceptible to other "classic" failure modes at high drift fields. Furthermore, device ruggedness is related to the drift punch-through voltage (V(PT)), and drift designs that increase the punch-through voltage (V(PT)) value improve high-voltage blocking ruggedness and reduce switching transients that are harmful to the circuit (i.e., diode reverse recovery transients are reduced), so increasing this value is also an important factor related to drift ruggedness in general.

[0051] Additionally, it is known that defects in SiC substrates can drive basal plane dislocations into the drift layer if electric fields are allowed to reach the substrate during bipolar current flow. The following concept reduces this occurrence by preventing vacancies from reaching the substrate surface.

[0052] In particular, there are important differences between Si and SiC semiconductors, resulting in significantly different design solutions. For example, for a given blocking voltage device, the doping level and thickness of the drift layer 22 differ by more than an order of magnitude between these materials, and therefore SiC-based devices require unique solutions. The bipolar effect involved in this type of breakdown event is influenced by the different characteristics of hole lifetime and mobility in SiC compared to Si. For example, a 1200V vertical power device in SiC has a blocking voltage of 1×10 16 cm -3 The Si device has a drift layer about 10 μm thick, doped with 14 cm -3 The drift design limits of SiC devices are therefore completely different from those of Si devices and cannot be used as a reference.

[0053] As will become apparent, the following concepts achieve over an order of magnitude reduction in radiation failure rate at a given device voltage without substantially changing device resistance and without substantially changing avalanche voltage levels. Additionally, the disclosed non-punch-through design (NPT) provides improved switching performance.

[0054] Typically, SiC-based power devices are designed for the lowest possible resistance, which involves the use of a punch-through drift design, in which the drift layer 22 is fully depleted at blocking and the electric field assumes a trapezoidal form. Therefore, the doping level in the drift layer 22 is relatively low and the thickness is thin, thereby providing low resistance and good blocking voltage. However, the electric field punches through the drift layer 22 at very low voltages, and the bipolar breakdown (i.e., second breakdown) voltage is also low. As such, the power device may be susceptible to failure mechanisms associated with high electric fields, high currents, and fast switching.

[0055] As shown in FIG. 13A, in certain cases, a relatively thin but more heavily doped diffusion layer 46 is provided on the drift layer 22 to help current spread before reaching the lightly doped drift layer 22. Thus, a typical SiC or other wide-bandgap vertical semiconductor device 16 may have a thin, heavily doped upper region as the diffusion layer 46, a thicker, lightly doped drift layer 22, and a relatively thin substrate 18, which is shown thin in FIG. 13A to conserve space. FIG. 13B is a graph of the electric field within the vertical semiconductor device 16 versus distance from the top of the vertical semiconductor device 16. In avalanche, the electric field is highest at the top surface of the diffusion layer 46 and decreases in intensity through the diffusion layer 46 and the drift layer 22, but at different rates. In particular, the electric field remains at a significant level at the interface between the drift layer 22 and the substrate 18 (i.e., the top surface of the substrate 18). Thus, as shown in FIG. 13B, the electric field effectively punches through (PT) the entire drift layer 22. Figure 13C shows that this type of punchthrough can occur well before avalanche breakdown, and that second breakdown can occur at lower voltages than avalanche for such structures. In particular, Figure 13C is a graph showing the electric field at the bottom of drift layer 22 and the drain-source current (Ids) as the drain-source voltage (Vds) increases in the blocking mode of a FET or diode configuration of vertical semiconductor device 16. The punchthrough voltage V(PT), as well as the voltages for second breakdown and avalanche breakdown, are observed.

[0056] To avoid or mitigate electric field punchthrough to the substrate, a buffer layer 20 may be used in conjunction with the diffusion layer 46, as shown in FIG. 14A. The doping concentration of the buffer layer 20 may be between that of the drift layer 22 and that of the substrate 18. The inclusion of the buffer layer 20 tends to direct the electric field away from the top surface of the substrate 18, increasing the second breakdown voltage. In the illustrated embodiment, as shown in FIG. 14B, the electric field at the avalanche voltage punches through the drift layer 22 but is stopped by the buffer layer 20, thus not punching through the substrate 18. The inclusion of the buffer layer 20 increases the second breakdown voltage, improves ruggedness under high-field bipolar conditions, and directs the electric field away from the substrate 18. Directing the electric field away from the substrate minimizes the effects of basal plane dislocation motion from the substrate 18 to the drift layer 22. 14C shows the electric field at the bottom of the drift layer 22 and the drain-source current (Ids) as the drain-source voltage (Vds) increases in the blocking mode of the FET or diode configuration of the vertical semiconductor device 16. In the buffer layer 20, the avalanche (Vaval) and punch-through voltage V(PT) do not change, but the voltage for second breakdown increases significantly.

[0057] In particular embodiments, the diffusion layer 46 has a doping level of typically 1E×10 16 ~1×10 17 cm -3 The doping of the drift layer 22 depends on the voltage rating of the device, and for devices rated at 300 V to 300 kV, it is in the range of 1×10 13 ~1×10 17 cm -3 The doping range of the buffer layer 20 can vary from 1×10 to 2 μm and the thickness can vary from 2 μm to 300 μm. 18 The doping is lower than the substrate 18, which is often doped to 1×10 or more, but high enough so as not to be significantly depleted in blocking. Thus, the buffer layer 20 needs to be doped to perform as needed, at least 1×10 depending on the doping. 17 ~5×1018 cm -3 and may be in the range of 0.5 μm to 5 μm thick. The thickness of the substrate 18 may be in the range of 50 to 500 micrometers. The concept associated with the embodiment of FIG. 14A adds little resistance to the structure, but aids durability performance.

[0058] Alternative doping concentration ranges for the embodiment of FIG. 14A include: 1 × 10 in the diffusion layer 46 16 ~5×10 16 cm -3 ; In the drift layer 22, 1 × 10 13 ~1×10 17 cm -3 ; 5 × 10 for buffer layer 46 16 ~5×10 18 cm -3 ; and 5 x 10 for board 18 17 ~1×10 20 cm -3 .

[0059] 15A, multiple drift layers are provided within vertical semiconductor device 16, referred to as an upper first drift layer 22A and a lower second drift layer 22B. Buffer layer 20 is not included. First drift layer 22A is located between diffusion layer 46 and second drift layer 22B. Second drift layer 22B is located between first drift layer 22A and substrate 18.

[0060] The lower second drift layer 22B may have a slightly higher doping level than the upper first drift layer 22A in an effort to thicken the drift from the prior art. Additionally, the first drift layer 22A may be thinner than the drift layer 22 of the embodiment of FIG. 14A, while still having a slightly higher doping level to keep the overall drift resistance low. Compared to the previous embodiment, these changes increase both the punch-through voltage (V(PT)) and the second breakdown voltage.

[0061] In certain embodiments, the second drift layer 22B is 1 to 3 times the doping level of the first drift layer 22A, but may be any thickness close to or less than the doping level of the first drift layer 22A. This embodiment enhances ruggedness by preventing too high an electric field from penetrating into the substrate 18. In selected embodiments, as shown in FIG. 15B, the first drift layer 22A and the second drift layer 22B of the vertical semiconductor device 16 may be designed to prevent any electric field from punching through the second drift layer 22B to the substrate 18. FIG. 15B shows the electric field in the vertical semiconductor device 16 at an avalanche voltage. Note that the electric field stops at the second drift layer 22B, just short of the substrate 18.

[0062] 15C shows the electric field at the bottom of the second drift layer 22B and the drain-source current (Ids) as the drain-source voltage (Vds) increases in the blocking mode of the FET or diode configuration of the vertical semiconductor device 16. By adding the lower second drift layer 22B, the avalanche voltage (Vaval) can be kept constant, while both the punch-through voltage V(PT) and the second breakdown voltage increase beyond the avalanche voltage (Vaval).

[0063] The use of multiple drift layers, such as first drift layer 22A and second drift layer 22B, can aid in the durability of the overall device under high electric field, high current, and fast switching conditions. Switching snap is reduced and the electric field is maintained outside the substrate 18, preventing basal plane dislocations from migrating into the first drift layer 22A or second drift layer 22B. Similar results can be achieved using three or more drift layers.

[0064] Exemplary doping concentration ranges for the embodiment of FIG. 15A include: 1 × 10 in the diffusion layer 46 16 ~5×10 16 cm -3 ; 1×10 in the first drift layer 22A13 ~4×10 16 cm -3 ; In the second drift layer 22B, 2×10 13 ~8×10 16 cm -3 ; and 5 x 10 for board 18 17 ~1×10 20 cm -3 . An alternative set of ranges includes: 1 × 10 in the diffusion layer 46 16 ~5×10 16 cm -3 ; 1×10 in the first drift layer 22A 15 ~2×10 16 cm -3 ; In the second drift layer 22B, 2×10 15 ~3×10 16 cm -3 ; and 1×10 for board 18 18 ~1×10 20 cm -3 . Exemplary thickness ranges include: 1 to 4 micrometers in the diffusion layer 46; 2 to 50 micrometers for the first drift layer 22A; 1 to 30 micrometers in second drift layer 22B; and For substrate 18, it is 50 to 500 micrometers.

[0065] The embodiment shown in FIG. 16A builds on the embodiment of FIG. 15A by adding a buffer layer 20 between the second drift layer 22B and the substrate 18. As with the previous embodiment, the electric field at the avalanche voltage does not punch through the second drift layer 22B and therefore stops short of the buffer layer 20, as shown in FIG. 16B. A further advantage of this embodiment is more readily apparent in FIG. 16C, which shows the electric field at the bottom of the drift layer 22B and the Ids current as the drain-source voltage (Vds) increases in blocking mode when the vertical semiconductor device 16 is configured as a FET or diode. With the addition of the buffer layer 20, the avalanche voltage (Vaval) and punch-through voltage (V(PT)) remain relatively constant, while the second breakdown voltage is further increased to provide additional field reduction under high-field, high-current discharge conditions.

[0066] Exemplary doping concentration ranges for the embodiment of FIG. 16A include: 1 × 10 in the diffusion layer 46 16 ~5×10 16 cm -3 ; 1×10 in the first drift layer 22A 13 ~5×10 16 cm -3 ; In the second drift layer 22B, 2×10 13 ~1×10 17 cm -3 ; 5 × 10 for buffer layer 46 16 ~5×10 18 cm -3 ; and 1×10 for board 18 18 ~1×10 20 cm -3 . An alternative set of ranges includes: 1 × 10 in the diffusion layer 46 16 ~5×10 16 cm -3 ; 1×10 in the first drift layer 22A 15 ~2×1016 cm -3 ; In the second drift layer 22B, 2×10 15 ~3×10 16 cm -3 ; 1×10 for buffer layer 46 17 ~1×10 18 cm -3 ; and 1×10 for board 18 18 ~1×10 20 cm -3 . Exemplary thickness ranges include: 1-5 micrometers in the diffusion layer 46; 2 to 50 micrometers for the first drift layer 22A; 1 to 30 micrometers for the second drift layer 22B; 1 to 20 micrometers for the buffer layer 46; and For substrate 18, it is 50 to 500 micrometers. The first drift layer 22A and the second drift layer 22B may have the same or different doping concentrations and the same or different doping profiles. For example, both the first drift layer 22A and the second drift layer 22B may have the same or different graded or constant doping concentrations. Also, one of the first drift layer 22A and the second drift layer 22B may have a graded doping profile and the other may be constant. In certain embodiments, the diffusion layer has a higher doping concentration than at least one, if not both, of the first and second drift layers.

[0067] The embodiment of FIG. 17A provides a vertical semiconductor device 16 having a drift layer 22 with graded doping. In the illustrated embodiment, there is only one drift layer 22 and no buffer layer 20 is present. The doping concentration within the drift layer 22 increases from the bottom of the drift layer 22 (i.e., the substrate interface) to the top of the drift layer 22 (i.e., the interface with the diffusion layer 46). Thus, the doping concentration is slightly higher at the bottom of the drift layer 22 and lower near the top of the drift layer 22. As shown in FIG. 17B, the doping concentration is at a relatively constant level throughout the diffusion layer 46, decreases to a first level at the top of the drift layer 22, increases continuously throughout the drift layer 22 to a level at or below the diffusion layer 46, and then jumps to a much higher, relatively constant level within the substrate 18. The doping concentrations in FIG. 17B are shown on a logarithmic scale.

[0068] With the appropriate doping concentration, profile, and thickness, an increase in both punch-through voltage (V(PT)) and second breakdown voltage is provided, as shown in Figure 17C. The graded drift layer 22 allows the avalanche voltage (Vaval) to remain constant, while the second breakdown voltage and punch-through voltage V(PT) increase beyond the avalanche voltage (Vaval) limit. This results in further field degradation under high-field, high-current discharge conditions.

[0069] Durability under high electric field, high current, and high switching speed conditions is improved by not allowing any or high electric fields to penetrate into the substrate 18. The snapping tendency of the bipolar device upon switching is also reduced. As with the other embodiments, keeping the electric field outside of the substrate 18 prevents basal plane dislocations from migrating into the drift layer 22.

[0070] Exemplary doping concentration ranges for the embodiment of FIGS. 17A and 17B include: 1 × 10 in the diffusion layer 46 -16 ~5×10 -16 cm -3 ; In the drift layer 22, 1 × 10-13 and 5×10 -18 cm -3 Between ~__1E15__×10 -X and __5E17__×10 -X cm -3 Between; and 1×10 for board 18 -18 ~1×10 -20 cm -3 . An alternative set of ranges includes: 1 × 10 in the diffusion layer 46 -16 ~5×10 -16 cm -3 ; In drift layer 22, 5 × 10 -15 and 5×10 -17 cm -3 Between ~1×10 -16 and 1×10 -17 cm -3 Between; and 1×10 for board 18 -18 ~5×10 -19 cm -3 . Exemplary thickness ranges include: 1-5 micrometers in the diffusion layer 46; 3 to 200 micrometers in the drift layer 22; and For substrate 18, it is 50 to 500 micrometers.

[0071] Referring now to FIG. 18 , a buffer layer 20 and a graded drift layer 22 are provided between the diffusion layer 46 and the substrate 18. In this embodiment, the diffusion layer 46 and buffer layer 20 are uniformly doped, and the drift layer 22 is graded as described above. In other embodiments, the doping of the diffusion layer 46 and / or buffer layer 20 is graded. The graph in FIG. 19 provides an example doping profile on a logarithmic scale. As shown in FIG. 17B , the doping concentration decreases continuously from a first level at the top of the diffusion layer 46 to a second level at the bottom of the diffusion layer 46, increases continuously from the second level at the top of the drift layer 22 to a third level lower than the first level at the bottom of the drift layer 22, and increases continuously from the second level to a fourth level across the buffer layer 20. The doping across the substrate 18 is shown to be uniform at the fourth level. In the illustrated embodiment, the doping levels across the illustrated layers are continuous in that there are no abrupt changes in doping concentration within a given layer or at layer junctions.

[0072] Exemplary doping concentration ranges for fully graded embodiments include: 5 × 10 for diffusion layer 46 -16 and 1×10 -14 cm -3 Between ~3×10 -16 and 5×10 -15 cm -3 Between; In the drift layer 22, 1 × 10 -13 and 1×10 -17 cm -3 Between ~5×10 -15 and 5×10 -16 cm -3 Between; 5 × 10 for buffer layer 20 -16 and 1×10 -20 cm -3 Between ~1×10 -17 and 1×10 -20 cm -3 Between; and 1×10 for board 18 -18 ~1×10 -20 cm -3 . Exemplary thickness ranges include: 1-5 micrometers in the diffusion layer 46; 3 to 200 micrometers in the drift layer 22; 1 to 20 micrometers for the buffer layer 20; and For substrate 18, it is 50 to 500 micrometers. The properties, thicknesses, doping concentrations, thickness and / or doping concentration relationships, etc. of the substrate 18, buffer layer 20, and drift layer 22 of the embodiments of Figures 3 to 12 may, but need not, be applied to any of the embodiments of Figures 13 to 19, and vice versa.

[0073] Any of the above vertical semiconductor embodiments can be implemented as any of the previously identified vertical semiconductor components by adding contacts (30, 32, 40, 42, 44) and appropriate doping regions / implants (34, 36A, 36B), as identified in FIGS. 10 and 11 , where the doping regions extend into one or more of the diffusion layer 46, drift layer 22, first drift layer 22A, and / or second drift layer 22B. Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are believed to be within the scope of the concepts disclosed herein and in the following claims.

Claims

1. a substrate having a first doping type; a drift layer provided on the substrate and having the first doping type; a diffusion layer provided on the drift layer and having the first doping type; the substrate and the drift layer comprise silicon carbide; a maximum doping concentration of the diffusion layer is greater than a maximum doping concentration of the drift layer; the doping concentration of the substrate is greater than the doping concentration of the drift layer; a top portion of the diffusion layer having a first doping concentration and a bottom portion of the diffusion layer adjacent the drift layer having a second doping concentration that is lower than the first doping concentration.

2. The vertical semiconductor device of claim 1 , wherein the diffusion layer has a graded doping profile.

3. 3. The vertical semiconductor device of claim 2, wherein the graded doping profile of the diffusion layer decreases continuously through the diffusion layer from the top of the diffusion layer to the drift layer.

4. 4. The vertical semiconductor device of claim 1, wherein the drift layer has a graded doping profile, a top of the drift layer having a third doping concentration, and a bottom of the drift layer having a fourth doping concentration that is higher than the third doping concentration.

5. a buffer layer having a first doping type between the substrate and the drift layer; the doping concentration of the buffer layer is less than the doping concentration of the substrate; 4. The vertical semiconductor device according to claim 1, wherein the doping concentration of the drift layer is lower than the doping concentration of the buffer layer.

6. 6. The vertical semiconductor device of claim 5, wherein the thickness of the buffer layer is 5% to 35% of the thickness of the drift layer.

7. The vertical semiconductor device of claim 5 , wherein the doping profile of the buffer layer is substantially constant.

8. 6. The vertical semiconductor device of claim 5, wherein the doping profile of the buffer layer varies linearly such that the doping concentration of the buffer layer decreases proportionally with distance toward the drift layer.

9. 6. The vertical semiconductor device of claim 5, wherein a doping profile of the buffer layer provides a substantially smooth transition between the doping concentration of the drift layer and the doping concentration of the substrate.

10. 6. The vertical semiconductor device of claim 5, wherein the doping profile of the buffer layer has a linear transition of doping concentration from the doping concentration of the drift layer to the doping concentration of the buffer layer and back to the doping concentration of the drift layer.

11. A semiconductor device comprising: a substrate having a first doping type; a drift layer provided on the substrate and having the first doping type; a diffusion layer provided on the drift layer and having the first doping type; the substrate and the drift layer comprise silicon carbide; a maximum doping concentration of the diffusion layer is greater than a maximum doping concentration of the drift layer; the doping concentration of the substrate is greater than the doping concentration of the drift layer; the drift layer has a first drift layer and a second drift layer, The vertical semiconductor device, wherein the first drift layer is between the diffusion layer and the second drift layer.

12. a doping concentration of the second drift layer is greater than a doping concentration of the first drift layer; The vertical semiconductor device of claim 11 , wherein the second drift layer has a thickness less than the thickness of the first drift layer.

13. The vertical semiconductor device of claim 1, wherein the diffusion layer has a thickness of 1 to 5 micrometers.

Images