Semiconductor device, integrated circuit and manufacturing method thereof

Abstract

Provided are a semiconductor device such that even when MOS elements are vertically stacked, the MOS elements can have the same level of threshold voltage, an integrated circuit, and a method for manufacturing the same. In a semiconductor device 1, the region of a portion of a semiconductor pillar 12 that is surrounded by a lower end of a gate insulating layer 17 and a first electrode 14 is symmetrical with the region of a portion thereof that is surrounded by an upper end of the gate insulating layer 17 and a second electrode 21. Of the semiconductor pillar 12, a region 6 which is one of a source region and a drain region between one end surface of a channel that can be formed surrounded by the gate insulating layer 17 and a portion surrounded by the first electrode 14 is symmetrical, in electrical characteristics, with a region 7 which is the other of the source region and the drain region between the other end surface of the channel and a portion surrounded by the second electrode 21. Such semiconductor devices 1 are stacked in a plurality of levels to form an integrated circuit.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, integrated circuits and methods for manufacturing the same. [Background technology]

[0002] There is a semiconductor device with a vertical gate-all-around-FET (GAA-FET) structure in which a gate is provided around a semiconductor pillar erected on a substrate. A gate electrode surrounds a part of the semiconductor pillar with a gate insulating layer interposed therebetween, and a source electrode and a drain electrode are provided in the source region and drain region above and below the part of the semiconductor pillar (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 7-99311 (Fig. 103) Summary of the Invention [Problem to be solved by the invention]

[0004] However, semiconductor devices with such vertical GAA-FET structures are fabricated from bottom to top through various processes such as film deposition and etching. As a result, the source region below a part of the semiconductor pillar and the drain region above it do not have the same shape. In particular, in semiconductor devices with two GAA-FETs stacked one on top of the other, the threshold voltage of one transistor is different from that of the other.

[0005] Therefore, an object of the present invention is to provide a semiconductor device, an integrated circuit, and a method for manufacturing the same, in which the threshold voltages of the MOSs are at the same level even when the MOSs are stacked one above the other. [Means for solving the problem]

[0006] The concept of the present invention is as follows. [1] A semiconductor pillar provided on a substrate; a gate insulating layer provided so as to surround a portion of the semiconductor pillar; a gate electrode provided so as to surround the gate insulating layer; a first electrode that serves as either a source electrode or a drain electrode and that is provided so as to surround a portion of the semiconductor pillar; a second electrode serving as the other of a source electrode and a drain electrode, the second electrode being spaced apart from the first electrode in the upward direction with the gate insulating layer and the gate electrode sandwiched therebetween and surrounding a part of the semiconductor pillar; It is equipped with a region of the semiconductor pillar between the lower end of the gate insulating layer and the portion surrounded by the first electrode is symmetrical to a region of the semiconductor pillar between the upper end of the gate insulating layer and the portion surrounded by the second electrode. [2] A semiconductor pillar provided on a substrate; a gate insulating layer provided so as to surround a portion of the semiconductor pillar; a gate electrode provided so as to surround the gate insulating layer; a first electrode that serves as one of a source electrode and a drain electrode and that is provided so as to surround a part of the semiconductor pillar; a second electrode, which is the other of the source electrode and the drain electrode, provided so as to be spaced apart from the first electrode in the vertical direction with the gate insulating layer and the gate electrode interposed therebetween and to surround a part of the semiconductor pillar; It is equipped with A semiconductor device, wherein one of the source region and the drain region between one end face of a channel of the semiconductor pillar that may be formed along the gate insulating layer and a portion surrounded by the first electrode has symmetrical electrical characteristics to the other of the source region and the drain region between the other end face of the channel and a portion surrounded by the second electrode. [3] A semiconductor pillar provided on a substrate; a plurality of gate insulating layers provided at different heights so as to surround a portion of the semiconductor pillar; a plurality of gate electrodes each provided to surround a corresponding one of the gate insulating layers; a plurality of first electrodes each of which is provided at a different height so as to surround a part of the semiconductor pillar and serves as either a source electrode or a drain electrode; a plurality of second electrodes, each of which is provided at a different height so as to surround a part of the semiconductor pillar and serves as the other of the source electrode and the drain electrode; It is equipped with a plurality of field effect transistors each of which is configured by the gate insulating layer, the gate electrode, the first electrode, the second electrode, and a portion of the semiconductor pillar; a semiconductor device in which, in the plurality of field effect transistors, one of the source region and the drain region between one end face of a channel that may be formed along the gate insulating layer of the semiconductor pillar and a portion surrounded by the first electrode has symmetrical electrical characteristics to the other of the source region and the drain region between the other end face of the channel and a portion surrounded by the second electrode. [4] The semiconductor device according to [3], wherein the plurality of field effect transistors are separated from each other. [5] A semiconductor device according to [3] or [4] above, the semiconductor pillars include a first semiconductor pillar and a second semiconductor pillar standing on the same substrate, In the first semiconductor pillar, first and second p-channel FETs are configured by the gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the semiconductor pillar, each of which corresponds to the other; In the second semiconductor pillar, first and second n-channel FETs are configured by the gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the semiconductor pillar, each of which corresponds to the other, the gate electrode of the first p-channel FET is connected to the gate electrode of the first n-channel FET, and the drain electrode of the first p-channel FET is connected to the drain electrode of the first n-channel FET; the gate electrode of the second p-channel FET is connected to the gate electrode of the second n-channel FET, and the drain electrode of the second p-channel FET is connected to the drain electrode of the second n-channel FET. [6] A semiconductor device according to [3] or [4], the semiconductor pillars include a first semiconductor pillar and a second semiconductor pillar standing on the same substrate, 10. An integrated circuit, wherein the first semiconductor pillar has a different diameter than the second semiconductor pillar and / or is composed of a different material than the second semiconductor pillar. [7] A semiconductor device according to [3] or [4], the semiconductor pillars include a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar that are erected on the same substrate; In the second semiconductor pillar, a first FET capable of forming a channel of either a first p-channel FET or a first n-channel FET, and a second FET capable of forming a channel of either a second p-channel FET or a second n-channel FET are configured by the gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar, each of which corresponds to the other; In the first semiconductor pillar, the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar constitute an FET capable of forming a channel of the other of a first p-channel FET and a first n-channel FET, In the third semiconductor pillar, the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the third semiconductor pillar constitute an FET capable of forming a channel of the other of a second p-channel FET and a second n-channel FET, the gate electrode of the first p-channel FET is connected to the gate electrode of the first n-channel FET, and the drain electrode of the first p-channel FET is connected to the drain electrode of the first n-channel FET; the gate electrode of the second p-channel FET is connected to the gate electrode of the second n-channel FET, and the drain electrode of the second p-channel FET is connected to the drain electrode of the second n-channel FET. [8] A semiconductor device according to [3] or [4] above, the semiconductor pillars include first, second, and third semiconductor pillars that are erected on the same substrate; a first NMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar, and a first PMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar, a second PMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar, and a second NMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the third semiconductor pillar, a third NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar; a fourth NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the third semiconductor pillar. [9] the first, second, and third semiconductor pillars are arranged in this order; The integrated circuit according to [8], wherein the drain electrode in the first CMOS partially faces the drain electrode in the second CMOS with an insulating layer interposed therebetween, and extends in opposite directions in the direction of arrangement of the first, second, and third semiconductor pillars.

[10] The gate electrode of the first CMOS is connected to either a source electrode or a drain electrode of the fourth NMOS and a drain electrode of the second CMOS in a plane including the first, second, and third semiconductor pillars, a plane parallel to the plane, or a plane intersecting the plane; The integrated circuit according to [8] or [9], wherein the gate electrode of the second CMOS is connected to either a source electrode or a drain electrode of the third NMOS and a drain electrode of the first CMOS in a plane including the first, second, and third semiconductor pillars, a plane parallel to the plane, or a plane intersecting the plane.

[11] A semiconductor device according to [3] or [4], the semiconductor pillars include first, second, third, and fourth semiconductor pillars that are erected on the same substrate; a first CMOS including a first NMOS configured with the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the third semiconductor pillar, and a first PMOS configured with the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar; a second PMOS including the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the second semiconductor pillar, and a second NMOS including the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the third semiconductor pillar; a third NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar; a fourth NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the fourth semiconductor pillar.

[12] The first, second, third, and fourth semiconductor pillars are erected in this order on the same substrate, a drain electrode of the first CMOS partially faces a drain electrode of the second CMOS via an insulating layer, and extends in opposite directions in a direction in which the first, second, third, and fourth semiconductor pillars are arranged; the gate electrode of the first CMOS is connected to either a source electrode or a drain electrode of the fourth NMOS and the drain electrode of the second CMOS at the top and bottom in any one of a plane including the first, second, third, and fourth semiconductor pillars, a plane parallel to the plane, and a plane intersecting the plane;

[11] The integrated circuit according to

[11] , wherein the gate electrode in the second CMOS is connected to either the source electrode or the drain electrode of the third NMOS and the drain electrode in the first CMOS above and below in any one of a plane including the first, second, third, and fourth semiconductor pillars, a plane parallel to said plane, and a plane intersecting said plane.

[13] First to sixth semiconductor pillars standing on a substrate; first to sixth gate insulating layers provided corresponding to the first to sixth semiconductor pillars, respectively; first to sixth gate electrodes provided corresponding to the first to sixth semiconductor pillars, with corresponding first to sixth gate insulating layers interposed therebetween; first to sixth source electrodes provided corresponding to the first to sixth semiconductor pillars, respectively; first to sixth drain electrodes provided corresponding to the first to sixth semiconductor pillars, respectively; Equipped with the first gate electrode and the second gate electrode at the same height as the first gate electrode are connected to the third drain electrode and the fourth drain electrode at the same height as the third drain electrode by a first wiring portion in a vertical direction, the third gate electrode and the fourth gate electrode at the same height as the third gate electrode are connected to the first drain electrode and the second drain electrode at the same height as the first drain electrode by a second wiring portion in the up-down direction, one of the fifth source electrode and the fifth drain electrode provided on the fifth semiconductor pillar arranged outside the first and second semiconductor pillars is connected at the same height as the first and second drain electrodes; one of the sixth source electrode and the sixth drain electrode provided on the sixth semiconductor pillar arranged outside the third and fourth semiconductor pillars is connected at the same height as the third and fourth drain electrodes; an integrated circuit, wherein a source region between one end surface of a channel that can be formed along a corresponding one of the first to sixth semiconductor pillars along the gate insulating layer and a portion surrounded by the corresponding one of the source electrodes has symmetrical electrical characteristics to a drain region between the other end surface of the channel and a portion surrounded by the drain electrode.

[14] The integrated circuit according to

[13] , wherein the first to sixth semiconductor pillars are provided on the same plane.

[15] The integrated circuit described in

[13] or

[14] , wherein either or both of the first wiring portion and the second wiring portion are provided on a surface including the first to sixth semiconductor pillars or on a surface different from that surface.

[16] The first, second, and fifth semiconductor pillars are provided on a first surface; the third, fourth, and sixth semiconductor pillars are provided on a second surface different from the first surface, The integrated circuit according to

[13] , wherein the first wiring portion and the second wiring portion are provided on a surface that intersects with the first surface and the second surface.

[17] A semiconductor device according to any one of [1] to [4] above; a first capacitor electrode provided on the same surface as the first electrode; a second capacitor electrode provided so as to face the first capacitor electrode; 1. An integrated circuit comprising:

[18] The integrated circuit according to

[17] , wherein the second capacitor electrode is provided on the same surface as the second electrode.

[19] The first capacitor electrode and the second capacitor electrode are thinner than the first electrode; 18. The integrated circuit of claim 17, wherein the second capacitor electrode is spaced from the first capacitor electrode by a distance less than a thickness of the first electrode.

[20] The integrated circuit according to

[17] , further comprising a connection electrode that connects the first electrode and the first capacitor electrode in the same plane.

[21] A semiconductor device according to any one of [1] to [4] above; a first capacitor electrode provided on the same surface as the first electrode; a second capacitor electrode provided on the same surface as the second electrode; a third capacitor electrode provided opposite to the first capacitor electrode and spaced apart by a distance shorter than the thickness of the first electrode; a fourth capacitor electrode provided opposite the second capacitor electrode and spaced apart by a distance shorter than the thickness of the second electrode; a fifth capacitor electrode that vertically connects the first capacitor electrode and the fourth capacitor electrode; a sixth capacitor electrode connecting the second capacitor electrode and the third capacitor electrode in the vertical direction; 1. An integrated circuit comprising:

[22] The integrated circuit according to

[17] , further comprising any one of a phase change film, a dielectric film, and a resistance change film between the first capacitor electrode and the second capacitor electrode.

[23] An integrated circuit according to any one of [5] to

[22] above, wherein basic units constituting any of CMOS, DRAM and SRAM are stacked in multiple layers, or at least two types of basic units out of the three types of basic units constituting CMOS, DRAM and SRAM, respectively, are stacked.

[24] A method of manufacturing a semiconductor device comprising: providing a substrate having a stack including at least one pair of first sacrificial layers that can be formed in an axial direction and that surround the semiconductor pillar and are spaced apart in the axial direction; forming a first hole in the stack to reach the first sacrificial layer; removing the mating first sacrificial layer; a pair of conductive layers that will form a pair of source and drain electrodes is deposited to surround the region of the semiconductor pillar exposed by removing the first sacrificial layer. Specifically, a substrate is provided having a stack including at least one pair of first sacrificial layers that can form at least one semiconductor pillar in an axial direction and are spaced apart from each other in the axial direction, the first sacrificial layers surrounding the semiconductor pillar; forming a first through-hole in the stack so as to penetrate the pair of first sacrificial layers; removing the mating first sacrificial layer; a pair of conductive layers that will form a pair of source and drain electrodes is deposited to surround the region of the semiconductor pillar exposed by removing the first sacrificial layer.

[25] The stack includes a second sacrificial layer that surrounds the semiconductor pillar and is provided so as not to overlap the first sacrificial layer in a plan view at a height between the pair of first sacrificial layers; moreover, forming a second hole different from the first hole in the stack to reach the second sacrificial layer; removing the second sacrificial layer; forming a gate insulating layer to surround the region of the semiconductor pillar exposed by removing the second sacrificial layer; The manufacturing method according to

[24] above, wherein a conductive layer that will become a gate electrode is deposited so as to surround the gate insulating layer. Specifically, the stacked body includes a second sacrificial layer that surrounds the semiconductor pillar and is provided so as not to overlap the first sacrificial layer in a plan view at a height between the pair of first sacrificial layers, moreover, forming a second through hole different from the first through hole in the laminate so as to penetrate the second sacrificial layer; removing the second sacrificial layer; forming a gate insulating layer to surround the region of the semiconductor pillar exposed by removing the second sacrificial layer; The manufacturing method according to

[24] above, wherein a conductive layer that will become a gate electrode is deposited so as to surround the gate insulating layer.

[26] The manufacturing method described in

[24] above, wherein the stack includes multiple pairs of the first sacrificial layers.

[27] The stack includes a plurality of pairs of the first sacrificial layers and the same number of pairs of the second sacrificial layers as the number of pairs of the first sacrificial layers;

[25] The manufacturing method according to

[26] , wherein each of the second sacrificial layers has the same thickness so that the gate lengths of the respective gate electrodes are equal, or some of the second sacrificial layers have a different thickness from the others of the second sacrificial layers so that the gate lengths of some of the plurality of gate electrodes are different from the gate lengths of the other of the plurality of gate electrodes.

[28] forming a third hole in the stack to reach the first sacrificial layer; forming a separation layer in the third hole; forming a fourth hole in the separation layer adjacent to the pair of first sacrificial layers; removing a portion of the first sacrificial layer exposed by the fourth hole; The manufacturing method according to any one of

[24] to

[27] above, wherein a conductive layer that becomes an electrode for a capacitor is formed in each of the areas from which the first sacrificial layer has been removed. Specifically, a third through-hole is formed in the stack so as to penetrate the pair of first sacrificial layers; forming a separation layer in the third through hole; forming a fourth through-hole in the separation layer adjacent to the paired first sacrificial layer; removing a portion of the first sacrificial layer exposed by the fourth through hole; The manufacturing method according to any one of

[24] to

[27] above, wherein a conductive layer that becomes an electrode for a capacitor is formed in each of the areas from which the first sacrificial layer has been removed.

[29] The manufacturing method according to

[28] , further comprising forming a conductive layer for connecting either the source electrode or the drain electrode to one of the capacitor electrodes.

[30] The stacked body includes a second sacrificial layer that surrounds the semiconductor pillar and is provided so as not to overlap the first sacrificial layer in a planar view at a height between the pair of first sacrificial layers, and an insulating layer that is provided between the pair of first sacrificial layers, removing portions of the first sacrificial layer and the insulating layer that are sandwiched between the upper and lower capacitor electrodes; The manufacturing method according to

[28] or

[29] , wherein a material to become any one of a phase change film, a dielectric film, and a resistance change film is deposited in the area from which the first sacrificial layer and the insulating layer have been removed.

[31] A substrate is provided having a laminate including: a P-type semiconductor pillar and an N-type semiconductor pillar that can be formed in an axial direction so that the P-type semiconductor pillar and the N-type semiconductor pillar are spaced apart in a plan view; at least one pair of first sacrificial layers that surround the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and are spaced apart in the axial direction; and a second sacrificial layer that surrounds the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and is provided so as not to partially overlap the first sacrificial layer in a plan view at a height between one first sacrificial layer and the other first sacrificial layer that constitutes the pair; forming a hole in the stack to access the second sacrificial layer; removing the second sacrificial layer; simultaneously forming a gate insulating layer to surround the P-type semiconductor pillar and the N-type semiconductor regions exposed by removing the second sacrificial layer; A manufacturing method in which a conductive layer that will become a gate electrode is simultaneously deposited so as to surround the gate insulating layer.

[32] A substrate is provided having a laminate including at least one pair of first sacrificial layers that can be formed in an axial direction so as to be spaced apart from the P-type semiconductor pillar and the N-type semiconductor pillar in a planar view, and that surround the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and are spaced apart from each other in the axial direction; forming a hole in the stack to access one of the pair of first sacrificial layers; removing one of the first sacrificial layers; a pair of conductive layers that become drain electrodes are simultaneously deposited so as to surround regions of the P-type semiconductor pillar and the N-type semiconductor pillar that are exposed by removing one of the first sacrificial layers, thereby simultaneously forming the drain electrodes of the P-type semiconductor pillar and the N-type semiconductor pillar, and a portion that connects the two.

[33] A substrate is provided having a laminate including at least one pair of first sacrificial layers that can be formed in an axial direction so as to be spaced apart from each other in a plan view, and that surround the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and are spaced apart from each other in the axial direction; forming a hole in the stack to access one of the pair of first sacrificial layers; removing one of the first sacrificial layers; a conductive layer is deposited to surround regions of the P-type semiconductor pillar and the N-type semiconductor pillar that are exposed by removing one of the first sacrificial layers, and then the conductive layer between the P-type semiconductor pillar and the N-type semiconductor pillar is partially removed to form a source electrode for the P-type semiconductor pillar and a source electrode for the N-type semiconductor pillar. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device, an integrated circuit, and a method for manufacturing the same, in which the source region (or drain region) provided below a part of a semiconductor pillar and the drain region (or source region) provided above the same are the same, and particularly in a semiconductor device in which GAA-FETs are stacked in two layers, one above the other, the threshold voltage of one transistor is at the same level as the threshold voltage of the other transistor. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view schematically showing a semiconductor device according to a second embodiment of the present invention. [Figure 3] FIG. 3 is a diagram schematically illustrating a semiconductor device according to a third embodiment of the present invention. [Figure 4] FIG. 4 is a diagram schematically illustrating a semiconductor device according to a fourth embodiment of the present invention. [Figure 5] FIG. 5 is a diagram showing a circuit in which two inverter circuits are cross-connected. [Figure 6] FIG. 6 is a diagram showing the input / output relationship between the first node NL and the second node NR of the circuit shown in FIG. [Figure 7] FIG. 7 is a diagram schematically showing one memory cell in a memory array of an SRAM as an integrated circuit according to a fifth embodiment of the present invention. [Figure 8] FIG. 8 is an equivalent circuit diagram of one memory cell in the memory array of the SRAM. [Figure 9] FIG. 9 is a diagram schematically showing one memory cell in a memory array of an SRAM as an integrated circuit according to a sixth embodiment of the present invention. [Figure 10] FIG. 10 is a diagram schematically showing one memory cell in a memory array of an SRAM as an integrated circuit according to a modification of the sixth embodiment of the present invention. [Figure 11] FIG. 11 is a diagram schematically showing one memory cell in a memory array of an SRAM as an integrated circuit according to the seventh embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view showing one memory cell in a memory array of an SRAM as an integrated circuit according to an eighth embodiment of the present invention. [Figure 13] FIG. 13 is a diagram schematically showing an integrated circuit according to a ninth embodiment of the present invention. [Figure 14] FIG. 14 is an enlarged view of a part of FIG. [Figure 15]FIG. 15 is a diagram schematically showing an integrated circuit according to a tenth embodiment of the present invention. [Figure 16] FIG. 16 is a plan view schematically showing an integrated circuit according to an eleventh embodiment of the present invention, showing gate electrodes, drain electrodes and wiring portions on the plane indicated by the dotted lines. [Figure 17] FIG. 17 is a plan view schematically showing an integrated circuit according to an eleventh embodiment of the present invention, showing gate electrodes, drain electrodes and wiring portions on a plane at a different height from that shown in FIG. 16, indicated by dotted lines. [Figure 18] FIG. 18 is a cross-sectional view taken along line II in FIGS. [Figure 19] FIG. 19 is a cross-sectional view taken along line II-II in FIGS. [Figure 20] FIG. 20 is a cross-sectional view showing the configuration of a DRAM as an integrated circuit according to a twelfth embodiment of the present invention. [Figure 21] FIG. 21 is a basic equivalent circuit diagram of a DRAM. [Figure 22] FIG. 22 is a cross-sectional view schematically showing one cell of a DRAM as an integrated circuit according to the thirteenth embodiment of the present invention. [Figure 23] FIG. 23 is a cross-sectional view schematically showing one cell of a DRAM as an integrated circuit according to the fourteenth embodiment of the present invention. [Figure 24] FIG. 24 is a cross-sectional view schematically showing a cell of an integrated circuit according to a fifteenth embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view taken along line XX in FIG. [Figure 26] FIG. 26 is a cross-sectional view schematically showing an integrated circuit according to a fifteenth embodiment of the present invention, which is different from FIG. [Figure 27] FIG. 27 is a cross-sectional view schematically showing an integrated circuit according to a fifteenth embodiment of the present invention, which is different from that shown in FIGS. [Figure 28] FIG. 28 is a cross-sectional view taken along line XX in FIG. [Figure 29]FIG. 29 is a cross-sectional view schematically showing an integrated circuit according to the sixteenth embodiment of the present invention. [Figure 30] FIG. 30 is a diagram schematically showing an integrated circuit according to a seventeenth embodiment of the present invention. [Figure 31A] FIG. 31A is a cross-sectional view of a step of forming a stack in a method for fabricating a semiconductor device according to an eighteenth embodiment of the present invention. [Figure 31B] FIG. 31B is a cross-sectional view of a step subsequent to FIG. 31A in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31C] FIG. 31C is a cross-sectional view of a step subsequent to FIG. 31B in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31D] FIG. 31D is a cross-sectional view of a step subsequent to FIG. 31C in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31E] FIG. 31E is a cross-sectional view of a step subsequent to FIG. 31D in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31F] FIG. 31F is a cross-sectional view of a step subsequent to FIG. 31E in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31G] FIG. 31G is a cross-sectional view of a step subsequent to FIG. 31F in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31H] FIG. 31H is a cross-sectional view of a step subsequent to FIG. 31G in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31I] FIG. 31I is a cross-sectional view of a step subsequent to FIG. 31H in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31J] FIG. 31J is a cross-sectional view of a step subsequent to FIG. 31I in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31K] FIG. 31K is a cross-sectional view of a step subsequent to FIG. 31J in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31L] FIG. 31L is a cross-sectional view of a step subsequent to FIG. 31K in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31M] FIG. 31M is a cross-sectional view of a step subsequent to FIG. 31L in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31N] FIG. 31N is a cross-sectional view of a step subsequent to FIG. 31M in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31O] FIG. 31O is a cross-sectional view of a step subsequent to FIG. 31N in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 31P] FIG. 31P is a cross-sectional view of a step subsequent to FIG. 31O in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention. [Figure 32A] FIG. 32A is a cross-sectional view showing a step of forming a stack in a method for manufacturing a DRAM as an integrated circuit according to a 19th embodiment of the present invention. [Figure 32B] FIG. 32B is a cross-sectional view showing a step subsequent to FIG. 32A in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32C] FIG. 32C is a cross-sectional view showing a step subsequent to FIG. 32B in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32D] FIG. 32D is a cross-sectional view showing a step subsequent to FIG. 32C in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32E] FIG. 32E is a cross-sectional view showing a step subsequent to FIG. 32D in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32F] FIG. 32F is a cross-sectional view showing a step subsequent to FIG. 32E in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32G] FIG. 32G is a cross-sectional view showing a step subsequent to FIG. 32F in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32H] FIG. 32H is a cross-sectional view showing a step subsequent to FIG. 32G in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32I] FIG. 32I is a cross-sectional view showing a step subsequent to FIG. 32H in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32J] FIG. 32J is a cross-sectional view showing a step subsequent to FIG. 32I in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32K] FIG. 32K is a cross-sectional view showing a step subsequent to FIG. 32J in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32L] FIG. 32L is a cross-sectional view showing a step subsequent to FIG. 32K in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32M] FIG. 32M is a cross-sectional view showing a step subsequent to FIG. 32L in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32N] FIG. 32N is a cross-sectional view showing a step subsequent to FIG. 32M in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32O] FIG. 32O is a cross-sectional view showing a step subsequent to FIG. 32N in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32P] FIG. 32P is a cross-sectional view showing a step subsequent to FIG. 32O in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 32Q] FIG. 32Q is a cross-sectional view showing a step subsequent to FIG. 32P in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33A] FIG. 33A is a cross-sectional view of a method for fabricating a DRAM as an integrated circuit according to a 19th embodiment of the present invention, showing a stage before one of the capacitor electrodes constituting upper and lower capacitors is connected to each other. [Figure 33B]FIG. 33B is a cross-sectional view showing a step subsequent to FIG. 33A in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33C] FIG. 33C is a cross-sectional view showing a step subsequent to FIG. 33B in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33D] FIG. 33D is a cross-sectional view showing a step subsequent to FIG. 33C in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33E] FIG. 33E is a cross-sectional view showing a step subsequent to FIG. 33D in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33F] FIG. 33F is a cross-sectional view showing a step subsequent to FIG. 33E in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33G] FIG. 33G is a cross-sectional view showing a step subsequent to FIG. 33F in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33H] FIG. 33H is a cross-sectional view showing a step subsequent to FIG. 33G in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33I] FIG. 33I is a cross-sectional view showing a step subsequent to FIG. 33H in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33J] FIG. 33J is a cross-sectional view showing a step subsequent to FIG. 33I in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33K] FIG. 33K is a cross-sectional view showing a step subsequent to FIG. 33J in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33L] FIG. 33L is a cross-sectional view showing a step subsequent to FIG. 33K in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 33M]FIG. 33M is a cross-sectional view showing a step subsequent to FIG. 33L in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 34A] FIG. 34A is a cross-sectional view taken along the line XX in FIG. 33M, showing a method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 34B] FIG. 34B is a cross-sectional view showing a step subsequent to FIG. 34A in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 34C] FIG. 34C is a cross-sectional view showing a step subsequent to FIG. 34B in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 34D] FIG. 34D is a cross-sectional view showing a step subsequent to FIG. 34C in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 34E] FIG. 34E is a cross-sectional view showing a step subsequent to FIG. 34D in the method for fabricating a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 34F] FIG. 34F is a cross-sectional view showing a step subsequent to FIG. 34E in the method for manufacturing a DRAM as an integrated circuit according to the nineteenth embodiment of the present invention. [Figure 35A] FIG. 35A is a cross-sectional view at a stage of forming a capacitor in a method of manufacturing a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 35B] FIG. 35B is a cross-sectional view showing a step subsequent to FIG. 35A in the method for fabricating a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 35C] FIG. 35C is a cross-sectional view showing a step subsequent to FIG. 35B in the method for manufacturing a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 35D] FIG. 35D is a cross-sectional view showing a step subsequent to FIG. 35C in the method for manufacturing a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 35E]FIG. 35E is a cross-sectional view showing a step subsequent to FIG. 35D in the method for fabricating a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 35F] FIG. 35F is a cross-sectional view showing a step subsequent to FIG. 35E in the method for fabricating a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 35G] FIG. 35G is a cross-sectional view showing a step subsequent to FIG. 35F in the method for manufacturing a DRAM as an integrated circuit according to the twentieth embodiment of the present invention. [Figure 36A] FIG. 36A is a cross-sectional view at a certain stage in the process of a method for fabricating a DRAM as an integrated circuit according to the 21st embodiment of the present invention. [Figure 36B] FIG. 36B is a cross-sectional view at another stage in the manufacturing method of a DRAM as an integrated circuit according to the twenty-first embodiment of the present invention. [Figure 37A] FIG. 37A is a cross-sectional view at a certain stage in the process of a method for fabricating a DRAM as an integrated circuit according to the 22nd embodiment of the present invention. [Figure 37B] FIG. 37B is a cross-sectional view of a step subsequent to FIG. 37A in the method for fabricating an integrated circuit according to the 22nd embodiment of the present invention. [Figure 37C] FIG. 37C is a cross-sectional view showing a step subsequent to FIG. 37B in the method for manufacturing a DRAM as an integrated circuit according to the 22nd embodiment of the present invention. [Figure 37D] FIG. 37D is a cross-sectional view showing a step subsequent to FIG. 37C in the method for fabricating a DRAM as an integrated circuit according to the 22nd embodiment of the present invention. [Figure 37E] FIG. 37E is a cross-sectional view showing a step subsequent to FIG. 37D in the method for fabricating a DRAM as an integrated circuit according to the 22nd embodiment of the present invention. [Figure 38A] FIG. 38A is a cross-sectional view of a method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention, at a stage prior to connecting a capacitor and a GAA-MOSFET. [Figure 38B]FIG. 38B is a cross-sectional view showing a step subsequent to FIG. 38A in the method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention. [Figure 38C] FIG. 38C is a cross-sectional view showing a step subsequent to FIG. 38B in the method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention. [Figure 38D] FIG. 38D is a cross-sectional view showing a step subsequent to FIG. 38C in the method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention. [Figure 38E] FIG. 38E is a cross-sectional view showing a step subsequent to FIG. 38D in the method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention. [Figure 38F] FIG. 38F is a cross-sectional view showing a step subsequent to FIG. 38E in the method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention. [Figure 38G] FIG. 38G is a cross-sectional view showing a step subsequent to FIG. 38F in the method for fabricating a DRAM as an integrated circuit according to the twenty-third embodiment of the present invention. [Figure 38H] FIG. 38H is a cross-sectional view showing a step subsequent to FIG. 38G in the method for fabricating a DRAM as an integrated circuit according to the twenty-third embodiment of the present invention. [Figure 39] FIG. 39 is a diagram for explaining that the electrical characteristics of the semiconductor device according to the embodiment of the present invention are symmetrical. [Figure 40A] FIG. 40A is a cross-sectional view of a step of forming a stack in a method for fabricating a semiconductor device according to a 24th embodiment of the present invention. [Figure 40B] FIG. 40B is a cross-sectional view of a step subsequent to FIG. 40A in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40C] FIG. 40C is a cross-sectional view of a step subsequent to FIG. 40B in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40D] FIG. 40D is a cross-sectional view of a step subsequent to FIG. 40C in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40E]FIG. 40E is a cross-sectional view of a step subsequent to FIG. 40D in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40F] FIG. 40F is a cross-sectional view of a step subsequent to FIG. 40E in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40G] FIG. 40G is a cross-sectional view of a step subsequent to FIG. 40F in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40H] FIG. 40H is a cross-sectional view of a step subsequent to FIG. 40G in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40I] FIG. 40I is a cross-sectional view of a step subsequent to FIG. 40H in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40J] FIG. 40J is a cross-sectional view of a step subsequent to FIG. 40I in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40K] FIG. 40K is a cross-sectional view of a step subsequent to FIG. 40J in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40L] FIG. 40L is a cross-sectional view of a step subsequent to FIG. 40K in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40M] FIG. 40M is a cross-sectional view of a step subsequent to FIG. 40L in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40N] FIG. 40N is a cross-sectional view of a step subsequent to FIG. 40M in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40O] FIG. 40O is a cross-sectional view of a step subsequent to FIG. 40N in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40P] FIG. 40P is a cross-sectional view of a step subsequent to FIG. 40O in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40Q]FIG. 40Q is a cross-sectional view of a step subsequent to FIG. 40P in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40R] FIG. 40R is a cross-sectional view of a step subsequent to FIG. 40Q in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40S] FIG. 40S is a cross-sectional view of a step subsequent to FIG. 40R in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40T] FIG. 40T is a cross-sectional view of a step subsequent to FIG. 40S in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40U] FIG. 40U is a cross-sectional view of a step subsequent to FIG. 40T in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40V] FIG. 40V is a cross-sectional view of a step subsequent to FIG. 40U in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 40W] FIG. 40W is a cross-sectional view of a step subsequent to FIG. 40V in the method for fabricating a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 41A] FIG. 41A is a cross-sectional view of a step of forming a stack in a method for fabricating a semiconductor device according to a 25th embodiment of the present invention. [Figure 41B] FIG. 41B is a cross-sectional view of a step subsequent to FIG. 41A in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41C] FIG. 41C is a cross-sectional view of a step subsequent to FIG. 41B in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41D] FIG. 41D is a cross-sectional view of a step subsequent to FIG. 41C in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41E] FIG. 41E is a cross-sectional view of a step subsequent to FIG. 41D in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41F]FIG. 41F is a cross-sectional view of a step subsequent to FIG. 41E in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41G] FIG. 41G is a cross-sectional view of a step subsequent to FIG. 41F in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41H] FIG. 41H is a cross-sectional view of a step subsequent to FIG. 41G in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41I] FIG. 41I is a cross-sectional view of a step subsequent to FIG. 41H in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41J] FIG. 41J is a cross-sectional view of a step subsequent to FIG. 41I in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41K] FIG. 41K is a cross-sectional view of a step subsequent to FIG. 41J in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41L] FIG. 41L is a cross-sectional view of a step subsequent to FIG. 41K in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41M] FIG. 41M is a cross-sectional view of a step subsequent to FIG. 41L in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41N] FIG. 41N is a cross-sectional view of a step subsequent to FIG. 41M in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41O] FIG. 41O is a cross-sectional view of a step subsequent to FIG. 41N in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41P] FIG. 41P is a cross-sectional view of a step subsequent to FIG. 41O in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41Q] FIG. 41Q is a cross-sectional view of a step subsequent to FIG. 41P in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41R]FIG. 41R is a cross-sectional view of a step subsequent to FIG. 41Q in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41S] FIG. 41S is a cross-sectional view of a step subsequent to FIG. 41R in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41T] FIG. 41T is a cross-sectional view of a step subsequent to FIG. 41S in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41U] FIG. 41U is a cross-sectional view of a step subsequent to FIG. 41T in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 41V] FIG. 41V is a cross-sectional view of a step subsequent to FIG. 41U in the method for fabricating a semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 42A] FIG. 42A is a cross-sectional view of a step of forming a stack in a method for fabricating a semiconductor device according to a 26th embodiment of the present invention. [Figure 42B] FIG. 42B is a cross-sectional view of a step subsequent to FIG. 42A in the method for fabricating a semiconductor device according to the 26th embodiment of the present invention. [Figure 42C] FIG. 42C is a cross-sectional view of a step subsequent to FIG. 42B in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42D] FIG. 42D is a cross-sectional view of a step subsequent to FIG. 42C in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42E] FIG. 42E is a cross-sectional view of a step subsequent to FIG. 42D in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42F] FIG. 42F is a cross-sectional view of a step subsequent to FIG. 42E in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42G] FIG. 42G is a cross-sectional view of a step subsequent to FIG. 42F in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42H]FIG. 42H is a cross-sectional view of a step subsequent to FIG. 42G in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42I] FIG. 42I is a cross-sectional view of a step subsequent to FIG. 42H in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42J] FIG. 42J is a cross-sectional view of a step subsequent to FIG. 42I in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42K] FIG. 42K is a cross-sectional view of a step subsequent to FIG. 42J in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42L] FIG. 42L is a cross-sectional view of a step subsequent to FIG. 42K in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42M] FIG. 42M is a cross-sectional view of a step subsequent to FIG. 42L in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42N] FIG. 42N is a cross-sectional view of a step subsequent to FIG. 42M in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42O] FIG. 42O is a cross-sectional view of a step subsequent to FIG. 42N in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42P] FIG. 42P is a cross-sectional view of a step subsequent to FIG. 42O in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42Q] FIG. 42Q is a cross-sectional view of a step subsequent to FIG. 42P in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42R] FIG. 42R is a cross-sectional view of a step subsequent to FIG. 42Q in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42S] FIG. 42S is a cross-sectional view of a step subsequent to FIG. 42R in the method for fabricating a semiconductor device according to the 26th embodiment of the present invention. [Figure 42T]FIG. 42T is a cross-sectional view of a step subsequent to FIG. 42S in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42U] FIG. 42U is a cross-sectional view of a step subsequent to FIG. 42T in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 42V] FIG. 42V is a cross-sectional view of a step subsequent to FIG. 42U in the method for fabricating a semiconductor device according to the twenty-sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. The details of the preferred embodiments of the present invention may be modified without departing from the scope of the present invention.

[0010] [First embodiment] FIG. 1 is a cross-sectional view schematically showing a semiconductor device 1 according to a first embodiment of the present invention. In the semiconductor device 1 according to the first embodiment of the present invention, at least one field effect transistor (FET) is provided using at least one semiconductor pillar 12. The semiconductor device 1 according to the first embodiment of the present invention includes a substrate 11, a semiconductor pillar 12 standing on the substrate 11, a first isolation layer 13 provided on the substrate 11 so as to cover the connection portion of the semiconductor pillar 12 with the substrate 11 with an insulating material, a first electrode 14 which is either a source electrode or a drain electrode and is provided on the first isolation layer 13 so as to surround a portion of the semiconductor pillar 12, a first insulating layer 15 provided on the first isolation layer 13 and having the same thickness as the first electrode 14, a second isolation layer 16 provided on the first electrode 14 and the first insulating layer 15, and a second isolation layer 16 provided on the second isolation layer 16 so as to surround a portion of the semiconductor pillar 12. a gate insulating layer 17 formed on the second isolation layer 16, a gate electrode 18 provided on the second isolation layer 16 so as to surround the gate insulating layer 17, a second insulating layer 19 provided on the second isolation layer 16 and having the same thickness as the gate electrode 18, a third isolation layer 20 provided on the gate insulating layer 17, the gate electrode 18 and the second insulating layer 19, a second electrode 21 which is the other of the source electrode and the drain electrode provided on the third isolation layer 20 so as to cover a part of the semiconductor pillar 12, a third insulating layer 22 provided on the third isolation layer 20 and having the same thickness as the second electrode 21, and a fourth isolation layer 23 provided on the second electrode 21 and the third insulating layer 22. An electrode via 24 is provided extending vertically through the second isolation layer 16, the second insulating layer 19, the third isolation layer 20, the third insulating layer 22, and the fourth isolation layer 23, and an electrode via 25 is provided extending vertically through the fourth isolation layer 23, the electrode vias 24 and 25 being connected to the first electrode 14 and the second electrode 21, respectively, and an electrode via (not shown) extending vertically through the second insulating layer 19, the third isolation layer 20, the third insulating layer 22, and the fourth isolation layer 23 is connected to the gate electrode 18. The second isolation layer 16 is an insulating layer for vertically isolating the first electrode 14 and the first insulating layer 15 from the gate insulating layer 17, the gate electrode 18, and the second insulating layer 19.The third isolation layer 20 is an insulating layer for vertically isolating the gate insulating layer 17, the gate electrode 18, and the second insulating layer 19 from the second electrode 21 and the third insulating layer 22. In FIG. gate is the gate length, and D is the outer diameter of the semiconductor pillar 12.

[0011] In the semiconductor device 1 according to the first embodiment of the present invention, a semiconductor pillar 12 is provided extending in the vertical direction relative to a substrate 11. Here, the vertical direction refers to the direction (stacking direction) in which a first electrode 14, which is one of the source and drain electrodes, and a second electrode 21, which is the other of the source and drain electrodes, are stacked with a second isolation layer 16 and a third isolation layer 20 sandwiched therebetween. The vertical direction is also referred to as the axial direction or longitudinal direction of the semiconductor pillar 12. The semiconductor device 1 according to the first embodiment of the present invention, including other embodiments described later, relates to a so-called vertical FET in which a channel, which can be formed by applying a gate voltage to a gate electrode 18 via a gate insulating layer 17 interposed in a part of the semiconductor pillar 12, is formed along the axial direction of the semiconductor pillar 12.

[0012] The portion of the semiconductor pillar 12 surrounded by the first electrode 14 and the second isolation layer 16 is symmetrical with the portion of the semiconductor pillar 12 surrounded by the second electrode 21 and the third isolation layer 20 with respect to the upper and lower mid-plane of the gate insulating layer 17 of the semiconductor pillar 12. Here, "symmetrical" means that the electrical characteristics of the semiconductor device 1 when the portion of the semiconductor pillar 12 surrounded by the first electrode 14 and the second isolation layer 16 is defined as either the source region or the drain region (assuming the source region) 6 and the portion of the semiconductor pillar 12 surrounded by the second electrode 21 and the third isolation layer 20 is defined as the other region of the source region or the drain region (assuming the drain region) 7 are symmetrical with the electrical characteristics of the semiconductor device when the portion of the semiconductor pillar 12 surrounded by the first electrode 14 and the second isolation layer 16 is defined as the drain region and the portion of the semiconductor pillar 12 surrounded by the second electrode 21 and the third isolation layer 20 is defined as the source region. In this sense, "symmetrical" includes approximate symmetry.

[0013] For example, the shape and dimensions of the portion of the semiconductor pillar 12 surrounded by the first electrode 14 and the second isolation layer 16 are identical in terms of characteristics to the shape and dimensions of the portion surrounded by the second electrode 21 and the third isolation layer 20. "Identical in terms of characteristics" means that if the resistivity and conductivity are evaluated to be in the same range, the voltage drop occurring in that portion is evaluated to be the same. In such a case, the materials are the same and the shapes and dimensions are the same so that electrical parameters such as resistivity are equal.

[0014] 1 , a first electrode 14 is provided below the gate insulating layer 17 and the gate electrode 18 for the semiconductor pillar 12 with a second isolation layer 16 interposed therebetween, and a second electrode 21 is provided above the gate insulating layer 17 and the gate electrode 18 for the semiconductor pillar 12 with a third isolation layer 20 interposed therebetween. Here, the first electrode 14 has the same thickness as the second electrode 21 and is made of the same material as the second electrode 21. Furthermore, the second isolation layer 16 is made of the same material as the third isolation layer 20 and has the same thickness.

[0015] Therefore, the electrical characteristics of the semiconductor pillar 12 can be evaluated as symmetrical between a portion (referred to as the "first portion") surrounded by the first electrode 14 and the second isolation layer 16, with one end face of a channel that can be formed along the gate insulating layer 17 as the upper end, and a portion (referred to as the "second portion") surrounded by the second electrode 21 and the third isolation layer 20, with the other end face of the channel that can be formed along the gate insulating layer 17 as the lower end. The term "electrical characteristics can be evaluated as symmetrical" means that the electrical parameters fall within a range of ±5% of the threshold voltage, for example.

[0016] In the first embodiment of the present invention, a current flows between the electrode via 24 and the electrode via 25, i.e., between the first electrode 14, the region 6 of either the source region or the drain region, the region 7 of the other of the channel, the source region, or the drain region, and the second electrode 21. Although the first electrode 14 and the second electrode 21 are conductive, the region 6 of either the source region or the drain region and the region 7 of the other of the source region or the drain region have significantly higher resistivity than the materials of the first electrode 14 and the second electrode 21. Therefore, it is extremely significant that the electrical characteristics are symmetrical when the region 6 of either the source region or the drain region and the region 7 of the other of the source region or the drain region are reversed. This also applies to the other embodiments described below. In this way, in a single FET formed using a portion of the semiconductor pillar 12, the electric field distributions in the source region and the drain region are symmetrical vertically, and therefore the electrical characteristics in the source region and the drain region are symmetrical. Therefore, for example, the temperature rise due to Joule heat in the source region and the drain region is the same, and therefore the influence of the temperature rise due to use is the same.

[0017] If the source and drain regions are asymmetric, their electrical characteristics will differ, leading to different temperature rises due to Joule heating in both regions, and the characteristics will change over time, for example, the threshold voltages will differ, which will affect the specifications of an integrated circuit that includes the semiconductor device.

[0018] [Second embodiment] A second embodiment of the present invention will be described. FIG. 2 is a cross-sectional view schematically showing a semiconductor device 1 according to the second embodiment of the present invention. In the semiconductor device 1 according to the second embodiment, multiple FETs are configured at different heights using at least one semiconductor pillar 12. That is, in the semiconductor device 1, the FETs are configured adjacent to each other vertically. The semiconductor device 1 according to the second embodiment includes a substrate 11, a semiconductor pillar 12 standing on the substrate 11, and a first isolation layer 13 provided on the substrate 11 so as to cover the connection portion of the semiconductor pillar 12 with the substrate 11 with an insulating material. For each semiconductor pillar 12, the device is also provided with multiple gate insulating layers 17 (17a, 17b), multiple gate electrodes 18 (18a, 18b), multiple first electrodes 14 (14a, 14b), and multiple second electrodes 21 (21a, 21b). The multiple gate insulating layers 17 (17a, 17b) are provided at different heights above and below so as to surround a portion of the semiconductor pillar 12. The multiple gate electrodes 18 (18a, 18b) are provided so as to surround the corresponding gate insulating layer 17 (17a, 17b). The gate lengths of adjacent FETs are preferably the same. However, when multiple FETs are provided vertically in multiple stages, such as in a sensor device, the gate lengths of the upper and lower FETs may be different among FETs of different heights. The multiple first electrodes 14 (14a, 14b) are provided so as to surround a portion of the semiconductor pillar 12, and are provided at different heights. They serve as either a source electrode or a drain electrode. Each first electrode 14 (14a, 14b) is connected to a corresponding electrode via 24 (24a, 24b). The plurality of second electrodes 21 (21a, 21b) are each provided so as to surround a portion of the semiconductor pillar 12, and are provided at different heights to serve as the other of the source electrode and drain electrode. Each second electrode 21 (21a, 21b) is connected to a corresponding electrode via 25 (25a, 25b).Gate electrodes 18 (18a, 18b) are provided outside the gate insulating layer 17 (17a, 17b) to surround the gate insulating layer 17 (17a, 17b), and first electrodes 14 (14a, 14b) are provided below them with isolation layers (second isolation layers) 16 (16a, 16b) interposed between them. Second electrodes 21 (21a, 21b) are provided on the gate electrodes 18 (18a, 18b) with another isolation layer (third isolation layer) 20 (20a, 20b) interposed between them. Electrode vias 26 (26a, 26b) are connected to each gate electrode 18 (18a, 18b). Therefore, multiple field effect transistors 27 (27a, 27b) are each composed of a corresponding gate insulating layer 17 (17a, 17b), gate electrode 18 (18a, 18b), first electrode 14 (14a, 14b), second electrode 21 (21a, 21b), and part of semiconductor pillar 12. The first stacked layer is composed of a first electrode 14a, a first insulating layer 15a, a second isolation layer 16a, a gate insulating layer 17a, a gate electrode 18a, a second insulating layer 19a, a third isolation layer 20a, a second electrode 21a, and a third insulating layer 22a, while the second stacked layer is composed of a first electrode 14b, a first insulating layer 15b, a second isolation layer 16b, a gate insulating layer 17b, a gate electrode 18b, a second insulating layer 19b, a third isolation layer 20b, a second electrode 21b, and a third insulating layer 22b. A fourth isolation layer 23a is provided between the first and second layers.

[0019] In each field-effect transistor 27, one of the source region and the drain region between the lower end face and the portion surrounded by the first electrode 14 (14a, 14b) as one end face of a channel that can be formed along the gate insulating layer 17 (17a, 17b) of the semiconductor pillar 12 has symmetrical electrical characteristics to the other of the source region and the drain region between the upper end face and the portion surrounded by the second electrode 21 (21a, 21b) as the other end face of the channel. Furthermore, between the upper and lower field-effect transistors 27a, 27b, the source region of the first field-effect transistor 27a and the source region of the second field-effect transistor 27b have the same characteristics, and the drain region of the first field-effect transistor 27a and the drain region of the second field-effect transistor 27b have the same characteristics.

[0020] Therefore, the source region and drain region of the first field-effect transistor 27a are symmetrical, and the source region and drain region of the second field-effect transistor 27b are symmetrical, and the characteristics of the field-effect transistors 27 are also identical. Therefore, the changes in the characteristics of the field-effect transistors 27 due to use are also identical, including within the tolerance range, and the impact on the specifications of the integrated circuit including the semiconductor device 1 is also identical. Furthermore, the threshold voltages of the first field-effect transistor 27a and the second field-effect transistor 27b are at the same level. Here, "the threshold voltages are at the same level" means that the variation in threshold voltage falls within a certain tolerance range, for example, ±5%.

[0021] Since the source and drain regions of the first field-effect transistor 27a are symmetrical, and the source and drain regions of the second field-effect transistor 27b are symmetrical, the combination of the first electrode 14a, the first electrode 14b, the second electrode 21a, and the second electrode 21b in FIG. 2 can be arbitrarily set, providing a high degree of design freedom. First, the first electrode 14a may be the source electrode, the first electrode 14b may be the source electrode, the second electrode 21a may be the drain electrode, and the second electrode 21b may be the drain electrode. Second, the first electrode 14a may be the source electrode, the first electrode 14b may be the drain electrode, the second electrode 21a may be the drain electrode, and the second electrode 21b may be the source electrode. Third, the first electrode 14a may be the drain electrode, the first electrode 14b may be the source electrode, the second electrode 21a may be the source electrode, and the second electrode 21b may be the drain electrode. Fourth, the first electrode 14a may be a drain electrode, the first electrode 14b may be a drain electrode, the second electrode 21a may be a source electrode, and the second electrode 21b may be a source electrode. This allows, for example, the source electrode of one FET and the drain electrode of another FET to be adjacent to each other above or below the isolation layer 23a or laterally, the drain electrode of one FET and the drain electrode of another FET to be adjacent to each other above or below the isolation layer 23a, or the source electrode of one FET and the source electrode of another FET to be adjacent to each other above or below the isolation layer 23a or laterally, thereby minimizing the wiring length connecting field-effect transistors. Alternatively, the source electrode or drain electrode of one FET may be connected to the gate electrode of another FET. This has the advantage of achieving a higher degree of integration and reducing the effects of Joule heat and the like.

[0022] When multiple field-effect transistors 27 (27a, 27b) are stacked in the vertical direction, it is preferable that the field-effect transistors 27 (27a, 27b) are configured to be electrically isolated so as not to be connected by the semiconductor pillars 12. Several isolation configurations are possible. For example, as a first configuration, as shown in FIG. 2, the space between the first electrode 14b of the upper field-effect transistor 27b and the second electrode 21a of the lower field-effect transistor 27a, which are adjacent to each other in the vertical direction, of the semiconductor pillars 12, is partially removed or insulated by oxidation. As a second configuration, the space between the first electrode 14b of the upper field-effect transistor 27b and the second electrode 21a of the lower field-effect transistor 27a, which are adjacent to each other in the vertical direction, is spaced apart by a predetermined distance or more, for example, 10 nm or more. As a third method, separation may be achieved by providing an electrode (not shown) for applying a reverse bias between the first electrode 14 of the upper field-effect transistor 27b and the second electrode 21a of the lower field-effect transistor 27a, which are adjacent to each other in the vertical direction, so as to surround a portion of the semiconductor pillar 12. By taking at least one of these measures, leakage current is suppressed in the multiple field-effect transistors 27 (27a, 27b) stacked in the vertical direction, and therefore the multiple field-effect transistors 27 (27a, 27b) stacked in the vertical direction do not affect each other. Here, the number of stacked field-effect transistors 27 is not limited to two. The number of field-effect transistors 27 may be three, four, five or more.

[0023] [Third embodiment] FIG. 3 is a diagram schematically illustrating a semiconductor device 1 according to a third embodiment of the present invention. In the third embodiment, two semiconductor pillars 12 (12a, 12b) are formed on a substrate 11, and each semiconductor pillar 12 has a field-effect transistor 27 configured along the vertical direction, as in the second embodiment. PMOSs are configured on both the top and bottom using the first semiconductor pillar 12a, which is one of the semiconductor pillars 12, and NMOSs are configured on both the top and bottom using the second semiconductor pillar 12b, which is the other semiconductor pillar 12. Adjacent PMOSs and NMOSs on the left and right are connected to form a first inverter circuit 5a and a second inverter circuit 5b, which are separated into upper and lower inverter circuits and cross-connected. The source electrodes 21 of the PMOSs and NMOSs in the first and second inverter circuits 5a and 5b are respectively connected to the respective voltages V by peripheral circuits. dd , V ss is applied. Electrode vias 24a, 26a, 24b, 26b are connected to the drain electrode and gate electrode 18 serving as the first electrode 14 of the first inverter circuit 5a, and the drain electrode and gate electrode 18 serving as the first electrode 14 of the second inverter circuit 5b, respectively. As described in the first and second embodiments, the source region and drain region of each field effect transistor 27 are configured to be identical in at least one of shape, size, material, and electrical parameters, and the electrical characteristics of the source region and drain region of each upper and lower field effect transistor 27 are evaluated to be symmetrical.

[0024] [Fourth embodiment] FIG. 4 is a diagram schematically illustrating a semiconductor device 1 according to a fourth embodiment of the present invention. Among the first, second, and third semiconductor pillars 12 (12a, 12b, 12c), the second semiconductor pillar 12b in the middle is configured with two field-effect transistors 27, one at the top and one at the bottom of the first semiconductor pillar 12a, and one field-effect transistor 27 at the top of the third semiconductor pillar 12c. Either a PMOS or an NMOS transistor is configured in the second semiconductor pillar 12b, and either a PMOS or an NMOS transistor is configured in the first semiconductor pillar 12a or the third semiconductor pillar 12c. The left and right PMOS and NMOS transistors are connected to form a first inverter circuit 5a and a second inverter circuit 5b, which are cross-connected. The source electrodes of the PMOS and NMOS in the first and second inverter circuits 5a and 5b are respectively connected to the respective voltages V dd , V ss In the illustrated embodiment, the second semiconductor pillar 12b has a PMOS arranged above and below it, but an NMOS may also be arranged above and below it. The source electrodes as second electrodes 21 of the PMOS and NMOS in the first and second inverter circuits 5a and 5b are connected to the respective voltages V dd , V ss is applied. Electrode vias 24a, 26a, 24b, and 26b are connected to the drain electrode and gate electrode 18 serving as the first electrode 14 of the first inverter circuit 5a, and the drain electrode and gate electrode 18 serving as the first electrode 14 of the second inverter circuit 5b, respectively. As described in the first and second embodiments, the source region and the drain region of each field-effect transistor 27 are configured to be identical, and the electrical characteristics of the source region and the drain region of each upper and lower field-effect transistor 27 are evaluated to be symmetrical. As shown in FIG. 4, the drain electrode serving as the first electrode 14, the source electrode serving as the second electrode 21, and the gate electrode 18 of the PMOS and NMOS adjacent to each other on the left and right are positioned at the same height.

[0025] FIG. 5 shows a circuit in which two inverter circuits are cross-connected, and FIG. 6 illustrates the input / output relationship between the first node NL and the second node NR of the circuit. With this configuration, as shown in FIG. 5, the input voltage to the first inverter circuit 5a is V1 and the output voltage is V2. The input voltage to the second inverter circuit 5b is V2 and the output voltage is V3. The output node of the second inverter circuit 5b and the input node to the first inverter circuit 5a are the same node, and V3 = V1. That is, the first node NL is the output of the first inverter circuit 5a and the input of the second inverter circuit 5b, and the second node NR is the input of the first inverter circuit 5a and the output of the second inverter circuit 5b. The electrical characteristics of each field-effect transistor 27 are equal, e.g., the threshold voltages are equal. The voltage at the first node NL is varied from 0 V to Vdd, and the voltage at the second node NR is observed. The relationship between NR and NL is plotted. The voltage at the second node NR is then varied from 0V to Vdd, and the voltage at the first node NL is observed. The NL-NR relationship is plotted. As shown in Figure 6, the PMOS and NMOS in the first inverter circuit 5a and the PMOS and NMOS in the second inverter circuit 5b are symmetrical, so the curves showing the NR-NL relationship and the NL-NR relationship are symmetrical with respect to a 45-degree line passing through the origin. Furthermore, if two squares of the largest size are drawn within the area enclosed by these two curves, both squares will be equal in size, and the diagonal lengths of the squares will also be equal. This diagonal length is called the static noise margin (SNM).

[0026] Here, we will explain the advantage of having symmetrical source and drain regions. The error range of the electrical resistance of the two regions is σ, and the electrical resistance of the drain and source regions is r A , r B If the resistance of the drain region is r A is the resistance of the source region, r B Larger than r A ≧r B>0. The variance is {r A ×(1+σ)-r B ×(1-σ)} / {(r A +r B ) / 2}. Then, the variance is calculated as 2×{(1-r B / r A ) / (1+r B / r A )}+2σ. r A =r B In other words, when the resistances of the source and drain regions are equal, the variance reaches its minimum value at 2σ. Considering the semiconductor device process, σ is less than 10%. Therefore, by making the source and drain regions symmetrical, the variation in electrical characteristics is reduced.

[0027] In the semiconductor devices 1 according to the third and fourth embodiments, by adjusting the diameter or impurity density of the semiconductor pillars 12, it is possible to configure the same type of MOS in each semiconductor pillar 12, with the threshold voltages being equalized. This allows a flip-flop to be configured with two PMOSs and two NMOSs in an SRAM integrated circuit using the semiconductor devices 1 according to the third and fourth embodiments.

[0028] [Fifth embodiment] 7 is a diagram schematically showing one memory cell in an SRAM memory array as an integrated circuit 2 according to a fifth embodiment of the present invention. FIG. 8 is an equivalent circuit diagram of one memory cell in an SRAM memory array. The fifth embodiment of the present invention relates to one memory cell in an SRAM memory cell array as an integrated circuit 2. One memory cell is a 6Tr consisting of an inverter loop made up of NMOS transistors (M1, M3) and PMOS transistors (M2, M4), and two access transistors, NMOS transistors (M5, M6), whose gates are connected to a word line WL and whose sources or drains are connected to a bit line BL or a bit bar line BBL.

[0029] In this circuit structure, three semiconductor pillars, namely, first, second, and third semiconductor pillars 12a, 12b, and 12c, are arranged in this order on a substrate 11. In the fifth embodiment, a first PMOS (M2) is configured at the bottom of the second semiconductor pillar 12b, and a second PMOS (M4) is configured at the top. A first NMOS (M1) is configured at the bottom of the first semiconductor pillar 12a. A second NMOS (M3) is configured at the top of the third semiconductor pillar 12c. A third NMOS (M5) is configured as an access transistor at the top of the first semiconductor pillar 12a. A fourth NMOS (M6) is configured as an access transistor at the bottom of the third semiconductor pillar 12c.

[0030] The drain electrode 31a of the first NMOS (M1) and the drain electrode 31b of the first PMOS (M2) are connected at the same height on the same surface (the lower surface of the isolation layer 23a). The gate electrode 32a of the first NMOS (M1) and the gate electrode 32b of the first PMOS (M2) are connected at the same height. As a result, the first NMOS (M1) and the first PMOS (M2) form a first CMOS circuit 41a. The source electrode 33a of the first NMOS (M1) and the source electrode 33b of the first PMOS (M2) are provided at the same height on the same surface (the upper surface of the isolation layer 13) without being connected to each other.

[0031] The drain electrode 34a of the second NMOS (M3) and the drain electrode 34b of the fourth PMOS (M4) are connected at the same height on the same surface (the upper surface of the isolation layer 23a). The gate electrode 35a of the second NMOS (M3) and the gate electrode 35b of the second PMOS (M4) are connected at the same height. As a result, the second NMOS (M3) and the second PMOS (M4) form a second CMOS circuit 41b. The source electrode 36a of the second NMOS (M3) and the source electrode 36b of the second PMOS (M4) are provided at the same height on the same surface (the lower surface of the isolation layer 23b) and are not connected to each other.

[0032] Either the source electrode or the drain electrode 34c of the third NMOS (M5) is connected to the gate electrodes 35a, 35b of the second CMOS circuit 41b via a first wiring portion 42, a portion of which is on the same plane (the upper surface of the isolation layer 23a) as the drain electrodes 34a, 34b of the second CMOS circuit 41b at the same height. The first wiring portion 42 is composed of a horizontal wiring portion 42a that is on the same plane as the drain electrodes 34a, 34b of the second CMOS circuit 41b and a vertical wiring portion 42b that extends in the direction in which the semiconductor pillar 12 is erected, and has a substantially T-shaped cross section. The horizontal wiring portion 42a is connected to either the source electrode or the drain electrode 34c of the third NMOS (M5) on the same plane, and the vertical wiring portion 42b connects the horizontal wiring portion 42a to the gate electrodes 35a and 35b of the second CMOS circuit 41b and the drain electrodes 31a and 31b of the first CMOS circuit 41a. The other electrode 36c of the source electrode or the drain electrode of the third NMOS (M5) is provided on the same plane (the lower surface of the isolation layer 23b) as the source electrodes 36a and 36b of the second CMOS circuit 41b at the same height and unconnected to each other. The gate electrode 35c of the third NMOS (M5) is provided at the same height as the gate electrodes 35a and 35b of the second CMOS circuit 41b and unconnected to each other.

[0033] Either the source electrode or the drain electrode 31c of the fourth NMOS (M6) is connected to the gate electrodes 32a and 32b of the first CMOS circuit 41a via a second wiring portion 43, a portion of which is on the same plane (the lower surface of the isolation layer 23a) and at the same height as the drain electrodes 31a and 31b of the first CMOS circuit 41a. The second wiring portion 43 is composed of a horizontal wiring portion 43a that is on the same plane and at the same height as the drain electrodes 31a and 31b of the first CMOS circuit 41a, and a vertical wiring portion 43b that extends in the direction in which the semiconductor pillar 12 is erected, and has a substantially T-shaped cross section. The horizontal wiring portion 43a is connected to either the source electrode or the drain electrode 31c of the fourth NMOS (M6) on the same plane, and the vertical wiring portion 43b connects the horizontal wiring portion 43a to the gate electrodes 32a and 32b of the first CMOS circuit 41a and the drain electrodes 34a and 34b of the second CMOS circuit 41b. The other electrode 33c of the source electrode or the drain electrode of the fourth NMOS (M6) is provided on the same plane (the upper surface of the first isolation layer 13) as the source electrodes 33a and 33b of the first CMOS circuit 41a and at the same height. The gate electrode 32c of the fourth NMOS (M6) is provided at the same height as the gate electrodes 32a and 32b of the first CMOS circuit 41a.

[0034] A gate electrode 35c of the third NMOS (M5) and a gate electrode 32c of the fourth NMOS (M6) are connected to the word line WL through electrode vias 28a and 28b, respectively. The other of the source and drain electrodes 36c of the third NMOS (M5) is connected to the bit bar line BBL through an electrode via 29b, and the other of the source and drain electrodes 33c of the fourth NMOS (M6) is connected to the bit line BL through an electrode via 29a.

[0035] The drain electrodes 31a, 31b of the first CMOS circuit 41a and the horizontal wiring portion 43a of the second wiring portion 43 are provided below and in contact with the isolation layer 23a, and the horizontal wiring portion 42a of the first wiring portion 42 and the drain electrodes 34a, 34b of the second CMOS circuit 41b are provided above and in contact with the isolation layer 23a. The drain electrodes 31a, 31b of the first CMOS circuit 41a and the drain electrodes 34a, 34b of the second CMOS circuit 41b partially overlap each other above and below with the isolation layer 23a in between, and extend in opposite directions to each other along the direction in which the first to third semiconductor pillars 12a, 12b, 12c are arranged.

[0036] In the fifth embodiment of the present invention, the PMOS and NMOS transistors configured in the first to third semiconductor pillars 12a, 12b, and 12c all have symmetrical source and drain regions. In particular, the first NMOS (M1), the second NMOS (M3), the first PMOS (M2), and the second PMOS (M4) configure a flip-flop and serve as a region for storing one bit of data. By configuring this region with vertically stacked PMOS and NMOS transistors, the operating margin of the SRAM is increased.

[0037] In particular, the first wiring section 42 connects the drain electrodes 31a and 31b of the first CMOS circuit 41a to the gate electrodes 35a and 35b of the second CMOS circuit 41b in close proximity, and the second wiring section 43 connects the drain electrodes 34a and 34b of the second CMOS circuit 41b to the gate electrodes 32a and 32b of the first CMOS circuit 41a in close proximity. The first wiring section 42 connects to the third NMOS (M5) serving as an access transistor, and the second wiring section 43 connects to the fourth NMOS (M6) serving as an access transistor. The first wiring section 42, the second wiring section 43, and the drain electrodes 31a, 31b, 34a, and 34b of the first CMOS circuit 41a and the second CMOS circuit 41b are vertically adjacent to each other with the isolation layer 23a interposed therebetween, thereby shortening the wiring. This minimizes the generation of Joule heat. The wiring of the circuits that make up the flip-flop and the wiring to the access transistors are short, allowing for a high degree of freedom in design.

[0038] [Sixth embodiment] 9 is a diagram schematically illustrating one memory cell in an SRAM memory array as an integrated circuit 2 according to a sixth embodiment of the present invention. Similar to the fifth embodiment, the sixth embodiment of the present invention relates to one memory cell in an SRAM memory cell array as an integrated circuit 2. Four semiconductor pillars 12, namely, first, second, third, and fourth semiconductor pillars 12a, 12b, 12c, and 12d, are erected in this order on a substrate 11.

[0039] In the sixth embodiment, a first PMOS (M2) is configured in the lower part of the second semiconductor pillar 12b, and a second PMOS (M4) is configured in the upper part. A first NMOS (M1) is configured in the lower part of the third semiconductor pillar 12c. A second NMOS (M3) is configured in the upper part of the third semiconductor pillar 12c. A third NMOS (M5) is configured as an access transistor in the upper part of the first semiconductor pillar 12a. A fourth NMOS (M6) is configured as an access transistor in the upper part of the fourth semiconductor pillar 12d.

[0040] The drain electrode 31a of the first NMOS (M1) and the drain electrode 31b of the first PMOS (M2) are connected in the same plane. The gate electrode 32a of the first NMOS (M1) and the gate electrode 32b of the first PMOS (M2) are connected. As a result, the first NMOS (M1) and the first PMOS (M2) form a first CMOS circuit 41a.

[0041] The drain electrode 34a of the second NMOS (M3) and the drain electrode 34b of the second PMOS (M4) are connected on the same plane at the same height. The gate electrode 35a of the second NMOS (M3) and the gate electrode 35b of the second PMOS (M4) are connected at the same height. As a result, the second NMOS (M3) and the second PMOS (M4) form a second CMOS circuit 41b.

[0042] Either the source electrode or the drain electrode 34c of the third NMOS (M5) is connected to the drain electrodes 31a and 31b of the first CMOS circuit 41a and the gate electrodes 35a and 35b of the second CMOS circuit 41b via a first wiring portion 42, part of which is on the same plane as the drain electrodes 34a and 34b of the second CMOS circuit 41b and at the same height. The first wiring portion 42 is composed of a horizontal wiring portion 42a, which is on the same plane as the drain electrodes 34a and 34b of the second CMOS circuit 41b, and a vertical wiring portion 42b, which extends in the direction in which the semiconductor pillar 12 is erected. The horizontal wiring portion 42a is connected to either the source electrode or the drain electrode 34c of the third NMOS (M5) on the same plane, and the vertical wiring portion 42b is connected to the gate electrodes 35a and 35b of the second CMOS circuit 41b above the horizontal wiring portion 42a and to the drain electrodes 31a and 31b of the first CMOS circuit 41a below the vertical wiring portion 42b. The other electrode 36c of the source electrode or the drain electrode of the third NMOS (M5) is provided on the same plane and at the same height as the source electrodes 36a and 36b of the second CMOS circuit 41b. The gate electrode 35c of the third NMOS (M5) is provided at the same height as the gate electrodes 35a and 35b of the second CMOS circuit 41b.

[0043] One of the source electrode and drain electrode 34d of the fourth NMOS (M6) is connected to the gate electrodes 32a and 32b of the first CMOS circuit 41a and the drain electrodes 34a and 34b of the second CMOS circuit 41b via a second wiring portion 43, part of which is on the same plane as and at the same height as the drain electrodes 34a and 34b of the second CMOS circuit 41b. The second wiring portion 43 is composed of a horizontal wiring portion 43a, part of which is on the same plane as and at the same height as the drain electrodes 34a and 34b of the second CMOS circuit 41b, and a vertical wiring portion 43b, which extends in the direction in which the semiconductor pillars 12 are erected. The horizontal wiring portion 43a connects either the source or drain electrode 34d of the fourth NMOS (M6) to the drain electrodes 34a and 34b of the second CMOS circuit 41b on the same plane, and the vertical wiring portion 43b connects the horizontal wiring portion 43a to the gate electrodes 32a and 32b of the first CMOS circuit 41a. The other electrode 36d of the source or drain electrode of the fourth NMOS (M6) is provided on the same plane and at the same height as the source electrodes 36a and 36b of the second CMOS circuit 41b. The gate electrode 35d of the fourth NMOS (M6) is provided at the same height as the gate electrodes 35a and 35b of the second CMOS circuit 41b.

[0044] A gate electrode 35c of the third NMOS (M5) and a gate electrode 35d of the fourth NMOS (M6) are connected to a word line WL through electrode vias 28a and 28b, respectively. The other of the source and drain electrodes 36c of the third NMOS (M5) is connected to a bit line BL through an electrode via 29a, and the other of the source and drain electrodes 36d of the fourth NMOS (M6) is connected to a bit bar line BBL through an electrode via 29b.

[0045] In the sixth embodiment of the present invention, the PMOS and NMOS transistors configured in the first to fourth semiconductor pillars 12a, 12b, 12c, and 12d all have symmetrical source and drain regions. In particular, the first NMOS (M1), the second NMOS (M3), the first PMOS (M2), and the second PMOS (M4) configure a flip-flop and serve as a region for storing one bit of data. By configuring this region with vertically stacked PMOS and NMOS transistors, the operating margin of the SRAM is increased.

[0046] The sixth embodiment is characterized in that the distances between the bit line BL, the bit bar line BBL, and the word line WL within the memory cell are shorter than those in the fifth embodiment. That is, the gate electrodes 35c and 35d of the third NMOS (M5) and the fourth NMOS (M6) are located at the same height as the gate electrodes 35a and 35b of the second NMOS (M3) and the second PMOS (M4), and the source electrodes and drain electrodes 34c and 34d of the third NMOS (M5) and the fourth NMOS (M6) are located at the same height as the drain electrodes 34a and 34b of the second NMOS (M3) and the second PMOS (M4).

[0047] In the sixth embodiment, drain electrodes 31a and 31b of a first CMOS circuit 41a are provided on and in contact with a first isolation layer 13, source electrodes 33a and 33b of the first CMOS circuit 41a are provided below and in contact with an isolation layer 23a provided between the first CMOS circuit 41a and a second CMOS circuit 41b, and drain electrodes 34a and 34b of a second CMOS circuit 41b are provided on and in contact with the isolation layer 23a.

[0048] 10 is a diagram schematically illustrating one memory cell in an SRAM memory array as an integrated circuit 2 according to a modification of the sixth embodiment. Unlike Fig. 9, source electrodes 33a and 33b of a first CMOS circuit 41a are provided on and in contact with a first isolation layer 13, drain electrodes 31a and 31b of the first CMOS circuit 41a are provided below and in contact with an isolation layer 23a provided between the first CMOS circuit 41a and the second CMOS circuit 41b, and drain electrodes 34a and 34b of the second CMOS circuit 41b are provided on and in contact with the isolation layer 23a. That is, the drain electrodes 31a and 31b of the first CMOS circuit 41a and the drain electrodes 34a and 34b of the second CMOS circuit 41b partially overlap each other in plan view with the isolation layer 23a sandwiched therebetween, and extend in opposite directions along the direction in which the first and second semiconductor pillars 12a and 12b are aligned. As a result, the vertical wiring portion 42b of the first wiring portion 42 can be made shorter than in the configuration shown in FIG.

[0049] [Seventh embodiment] 11 is a diagram schematically illustrating one memory cell in an SRAM memory array as an integrated circuit 2 according to a seventh embodiment of the present invention. Similar to the fifth and sixth embodiments, the seventh embodiment of the present invention relates to one memory cell in an SRAM memory cell array as an integrated circuit 2. Three semiconductor pillars 12, namely, first, second, and third semiconductor pillars 12a, 12b, and 12c, are arranged upright on a substrate 11 in this order.

[0050] In the seventh embodiment, a first PMOS (M2) is configured in the lower part of the first semiconductor pillar 12a, and a second PMOS (M4) is configured in the upper part. A first NMOS (M1) is configured in the lower part of the second semiconductor pillar 12b. A second NMOS (M3) is configured in the upper part of the second semiconductor pillar 12b. A third NMOS (M5) is configured as an access transistor in the lower part of the third semiconductor pillar 12c. A fourth NMOS (M6) is configured as an access transistor in the upper part of the third semiconductor pillar.

[0051] The drain electrode 31a of the first NMOS (M1) and the drain electrode 31b of the first PMOS (M2) are connected on the same plane at the same height. The gate electrode 32a of the first NMOS (M1) and the gate electrode 32b of the first PMOS (M2) are connected at the same height. As a result, the first NMOS (M1) and the first PMOS (M2) form a first CMOS circuit 41a.

[0052] The drain electrode 34a of the second NMOS (M3) and the drain electrode 34b of the second PMOS (M4) are connected on the same plane at the same height. The gate electrode 35a of the second NMOS (M3) and the gate electrode 35b of the second PMOS (M4) are connected at the same height. As a result, the second NMOS (M3) and the second PMOS (M4) form a second CMOS circuit 41b.

[0053] The drain electrodes 31a, 31b of the first CMOS circuit 41a are configured to have a horizontal wiring portion 43a extending in the opposite direction to the arrangement direction of the first, second, and third semiconductor pillars 12a, 12b, and 12c, and the gate electrodes 35a, 35b of the second CMOS circuit 41b are configured to have a horizontal wiring portion 43c extending in the opposite direction to the arrangement direction of the first and second semiconductor pillars 12a, 12b, and the vertical wiring portion 43b of the second wiring portion 43 is provided along the erection direction of the semiconductor pillars 12 and connects the horizontal wiring portions 43a, 43c, so that the drain electrodes 31a, 31b of the first CMOS circuit 41a are connected to the gate electrodes 35a, 35b of the second CMOS circuit 41b.

[0054] Either the source electrode or the drain electrode 31c of the third NMOS (M5) is connected to the same surface and at the same height as the drain electrodes 31a and 31b of the first CMOS circuit 41a.

[0055] One of the source electrode and drain electrode 34c of the fourth NMOS (M6) is connected to the gate electrodes 32a and 32b of the first CMOS circuit 41a and the drain electrodes 34a and 34b of the second CMOS circuit 41b via a first wiring portion 42, part of which is on the same plane as the drain electrodes 34a and 34b of the second CMOS circuit 41b. The first wiring portion 42 is composed of a horizontal wiring portion 42a that is on the same plane as the drain electrodes 34a and 34b of the second CMOS circuit 41b and at the same height, and a vertical wiring portion 42b that extends in the direction in which the semiconductor pillar 12 is erected. The horizontal wiring portion 42a is connected to either the source electrode or the drain electrode 34c of the fourth NMOS (M6) on the same plane and at the same height, and the vertical wiring portion 42b connects the horizontal wiring portion 42a to the gate electrodes 32a and 32b of the first CMOS circuit 41a.

[0056] A gate electrode 32c of the third NMOS (M5) and a gate electrode 35c of the fourth NMOS (M6) are connected to a word line WL through electrode vias 28a and 28b, respectively. A source electrode 33c as the other of the source and drain electrodes of the third NMOS (M5) is on the same plane and at the same height as the source electrodes 33a and 33b of the first CMOS circuit 41a and is connected to a bit line BL through an electrode via 29a. A source electrode 36c as the other of the source and drain electrodes of the fourth NMOS (M6) is on the same plane and at the same height as the source electrodes 36a and 36b of the second CMOS circuit 41b and is connected to a bit bar line BBL through an electrode via 29b.

[0057] In the seventh embodiment of the present invention, the PMOS and NMOS transistors configured in the first to third semiconductor pillars 12a, 12b, and 12c all have symmetrical source and drain regions. In particular, the first NMOS (M1), the second NMOS (M3), the first PMOS (M2), and the second PMOS (M4) configure a flip-flop and serve as a region for storing one bit of data. By configuring this region with vertically stacked PMOS and NMOS transistors, the operating margin of the SRAM is increased.

[0058] The seventh embodiment has three semiconductor pillars, which is one less than the sixth embodiment.

[0059] [Eighth embodiment] 12 is a cross-sectional view showing one memory cell in an SRAM memory array as an integrated circuit 2 according to an eighth embodiment of the present invention. Similar to the fifth to seventh embodiments, the eighth embodiment of the present invention relates to one memory cell in an SRAM memory cell array as an integrated circuit 2. Two semiconductor pillars 12, a first semiconductor pillar 12a and a second semiconductor pillar 12b, are erected side by side on a substrate 11.

[0060] In the eighth embodiment, a first PMOS (M2) is configured at the bottom of the first semiconductor pillar 12a, and a second PMOS (M4) is configured at the top. A first NMOS (M1), a second NMOS (M3), a fourth NMOS (M6), and a third NMOS (M5) are configured in this order from bottom to top in the second semiconductor pillar 12b. The third NMOS (M5) and the fourth NMOS (M6) function as access transistors.

[0061] The drain electrode 31a of the first NMOS (M1) and the drain electrode 31b of the first PMOS (M2) are connected on the same plane at the same height. The gate electrode 32a of the first NMOS (M1) and the gate electrode 32b of the first PMOS (M2) are connected at the same height. As a result, the first NMOS (M1) and the first PMOS (M2) form a first CMOS circuit 41a.

[0062] The drain electrode 34a of the second NMOS (M3) and the drain electrode 34b of the second PMOS (M4) are connected on the same plane at the same height. The gate electrode 35a of the second NMOS (M3) and the gate electrode 35b of the second PMOS (M4) are connected at the same height. As a result, the second NMOS (M3) and the second PMOS (M4) form a second CMOS circuit 41b.

[0063] The drain electrodes 31a, 31b of the first CMOS circuit 41a extend to the opposite side of the second semiconductor pillar 12b to form a horizontal wiring portion 42a, and the gate electrodes 35a, 35b of the second CMOS circuit 41b extend to the opposite side of the second semiconductor pillar 12b across the first semiconductor pillar 12a to form a horizontal wiring portion 42c. The vertical wiring portion 42b of the first wiring portion 42 is provided along the erection direction of the semiconductor pillar 12 and connects the horizontal wiring portions 42a, 42c, so that the drain electrodes 31a, 31b of the first CMOS circuit 41a and the gate electrodes 35a, 35b of the second CMOS circuit 41b are connected vertically.

[0064] One of the source and drain electrodes 37a of the fourth NMOS (M6) is connected to the gate electrodes 32a and 32b of the first CMOS circuit 41a and the drain electrodes 34a and 34b of the second CMOS circuit 41b via the second wiring portion 43. The second wiring portion 43 is configured so that the first horizontal wiring portion 43a, which is an extension of the gate electrode 32a of the first CMOS circuit 41a, the second horizontal wiring portion 43d, which is an extension of the drain electrodes 34a and 34b of the second CMOS circuit 41b in the horizontal direction, and the third horizontal wiring portion 43c, which is an extension of either the source electrode or the drain electrode 37a of the fourth NMOS (M6), partially overlap each other in a plan view, and a vertical wiring portion 43b, which is provided in the extension direction of the semiconductor pillar 12, connects the first to third horizontal wiring portions 43a, 43c, and 43d. The vertical wiring portion 43b connects the horizontal wiring portions 43a, 43c, and 43d in the stacking direction. The horizontal wiring portion may also be called an extension portion.

[0065] Either the source electrode or the drain electrode 37b of the third NMOS (M5) extends laterally at the same height and is connected to the drain electrodes 31a and 31b of the first CMOS circuit 41a via a third wiring portion 44, part of which is on the same plane as the drain electrodes 31a and 31b of the first CMOS circuit 41a. The third wiring portion 44 is composed of a first horizontal wiring portion 44a extending laterally from the drain electrodes 31a and 31b of the first CMOS circuit 41a, a second horizontal wiring portion 44c along which either the source electrode or the drain electrode 37b of the third NMOS (M5) extends laterally, and a vertical wiring portion 44b that is provided along the extension direction of the semiconductor pillar 12 in a portion where the first horizontal wiring portion 44a and the second horizontal wiring portion 44c partially overlap in a plan view, connecting the two.

[0066] The gate electrode 38b of the third NMOS (M5) and the gate electrode 38a of the fourth NMOS (M6) are connected to the word line WL through electrode vias 28a and 28b via laterally extending extensions 38g and 38f, respectively. The other electrode 39b of the third NMOS (M5) either the source electrode or the drain electrode is connected to the bit line BL through an electrode via 29a from an extension 39g extending laterally, and the other electrode 39a of the fourth NMOS (M6) either the source electrode or the drain electrode is connected to the bit bar line BBL through an extension 39f extending laterally and the electrode via 29b. Here, the extension 38f extends in the opposite direction to the extension 38g, and the extension 39f extends in the opposite direction to the extension 39g.

[0067] In the eighth embodiment of the present invention, the PMOS and NMOS transistors configured in the first and second semiconductor pillars 12a and 12b each have a symmetrical source and drain region. In particular, the first NMOS (M1), the second NMOS (M3), the first PMOS (M2), and the second PMOS (M4) configure a flip-flop to store one bit of data. By configuring this region with vertically stacked PMOS and NMOS transistors, the operating margin of the SRAM is increased.

[0068] In the integrated circuit according to the eighth embodiment, one SRAM memory cell is configured by stacking two levels of PMOS and four levels of NMOS using two semiconductor pillars 12 (12a, 12b). Within the SRAM cell, two levels of PMOS are configured for the first semiconductor pillar 12a, and four levels of NMOS are configured for the second semiconductor pillar 12b.

[0069] In the illustrated embodiment, the first NMOS (M1) and the first PMOS (M2) have drain electrodes 31a and 31b at their bottoms and source electrodes 33a and 33b at their tops, and the second NMOS (M3) and the second PMOS (M4) have drain electrodes 34a and 34b at their bottoms and source electrodes 36a and 36b at their tops. However, each NMOS and PMOS may have a drain electrode at its top and a source electrode at its bottom.

[0070] The source electrodes 33a and 33b of the first NMOS (M1) and the first PMOS (M2) are insulated from the drain electrodes 34a and 34b of the second NMOS (M3) and the second PMOS (M4) by an isolation layer 23a. The source electrodes 36a and 36b of the second NMOS (M3) and the second PMOS (M4) are insulated from either the source electrode or the drain electrode 37a of the fourth NMOS (M6) by an isolation layer 23b. The other electrode 39a of the fourth NMOS (M6) is insulated from either the source electrode or the drain electrode 37b of the third NMOS (M5) by an isolation layer 23c.

[0071] In the fifth to eighth embodiments, in the memory cell array of the SRAM serving as the integrated circuit 2, for one memory cell, a PMOS or an NMOS of the same type is stacked in each of the multiple semiconductor pillars 12, and the electrical characteristics of the source and drain regions of each MOS are symmetrical. Therefore, for example, the threshold voltages of the PMOS and NMOS for each semiconductor pillar 12 are within the same range. In particular, the first NMOS (M1), the second NMOS (M3), the first PMOS (M2), and the second PMOS (M4) form a flip-flop and serve as a region for storing one bit of data. By configuring this region with PMOS and NMOS stacked vertically, the operating margin of the SRAM is increased.

[0072] In this way, since the source and drain regions of each PMOS and NMOS are symmetrical, there is no need to provide transistors other than the six transistors.

[0073] As explained in the fifth to eighth embodiments, the arrangement of the semiconductor pillars 12, the number of field-effect transistors including MOS in each semiconductor pillar 12, the wiring of the word lines, bit lines, and bit bar lines, and the relative positional relationship between the memory cells may be changed as appropriate. By including the semiconductor device 1 according to the first to third embodiments as a basic configuration, the design of the SRAM has a high degree of freedom. These features cannot be realized with an asymmetric vertical GAA transistor.

[0074] In the fifth to eighth embodiments, the semiconductor pillars 12 that form the channels of six transistors (GAA-MOSFETs) and the intra-cell wiring for connecting the source electrode, drain electrode, or gate electrode of one transistor to another transistor are preferably located on the same plane at the same height. The wiring portions, excluding the extension portions that extend laterally from each electrode to connect to both ends of the intra-cell wiring, are aligned along the direction in which the semiconductor pillars 12 extend, i.e., the stacking direction and channel direction.

[0075] Since the wiring portion extending in the direction in which the semiconductor pillar 12 extends is formed in the same plane as the semiconductor pillar 12 (the cross section shown in FIG. 12), there is no need to provide wiring on a plane intersecting that plane. This makes it possible to eliminate excess wiring as much as possible, suppressing the generation of Joule heat and Joule heat loss. Furthermore, the layout or footprint can be made smaller, allowing for higher integration.

[0076] [Ninth embodiment] In the fifth to eighth embodiments, the configuration of one memory cell has been described, but in each embodiment, the multiple semiconductor pillars 12 that make up the memory cell can be stacked vertically to form multiple memory cells in a multi-stage configuration. Alternatively, multiple semiconductor pillars 12 may be erected on the substrate 11 in the vertical and horizontal directions in a plan view, and the memory cells may be arranged in the vertical and horizontal directions. In the ninth embodiment, as one of these configurations, an SRAM will be described as an integrated circuit configured by stacking one memory cell according to the fifth embodiment vertically. Below, a case of three stages will be described, but two, four, or more stages may also be used.

[0077] FIG. 13 is a diagram schematically illustrating an integrated circuit 2 according to a ninth embodiment of the present invention. FIG. 14 is an enlarged diagram schematically illustrating a portion of an integrated circuit according to the ninth embodiment of the present invention. In the integrated circuit 2 according to the ninth embodiment of the present invention, first, second, and third semiconductor pillars 12a, 12b, and 12c are arranged in this order on a substrate 11 provided with a first isolation layer 13. Six-stage PMOS transistors are configured, each of which can form a channel in a portion of the second semiconductor pillar 12b. Six-stage NMOS transistors are configured, each of which can form a channel in a portion of the first semiconductor pillar 12a. Six-stage NMOS transistors are configured, each of which can form a channel in a portion of the third semiconductor pillar 12c. In comparison with the six-stage PMOS transistors formed above and below the second semiconductor pillar 12b, an NMOS transistor formed by the adjacent first semiconductor pillar 12a, an NMOS transistor formed by the third semiconductor pillar 12c, an NMOS transistor formed by the first semiconductor pillar 12a, an NMOS transistor formed by the third semiconductor pillar 12c, an NMOS transistor formed by the first semiconductor pillar 12a, and an NMOS transistor formed by the third semiconductor pillar 12c are arranged in this order from the substrate 11 upward to form a first CMOS circuit 41a, a second CMOS circuit 41b, a third CMOS circuit 41c, a fourth CMOS circuit 41d, a fifth CMOS circuit 41e, and a sixth CMOS circuit 41f. The first, second, third, fourth, fifth, and sixth NMOS transistors 45a, 45b, 45c, 45d, 45e, and 45f, which do not constitute the CMOS circuits from the substrate 11 upward, function as access transistors. The first cell 46a is configured by the first and second CMOS circuits 41a and 41b and the first and second NMOSs 45a and 45b, the second cell 46b is configured by the third and fourth CMOS circuits 41c and 41d and the third and fourth NMOSs 45c and 45d, and the third cell 46c is configured by the fifth and sixth CMOS circuits 41e and 41f and the fifth and sixth NMOSs 45e and 45f. The first cell 46a is operated under the control of a peripheral circuit (not shown) via a word line WL1. The second cell 46b is operated under the control of a peripheral circuit (not shown) via a word line WL2. The third cell 46c is operated under the control of a peripheral circuit (not shown) via a word line WL3.In this way, the first cell 46a, the second cell 46b, and the third cell 46c are controlled and operated independently from the peripheral circuits by the respective word lines WL1, WL2, and WL3.

[0078] Here, when vertically connecting the extension portions 42a, 43a of the gate electrodes of the first to sixth CMOS circuits 41a to 41f extending in at least one of the left and right, front and rear directions, and the extension portions 42b, 43b of the source electrodes or drain electrodes of the NMOS or PMOS access transistors adjacent to the extension portions 42a, 43a extending in one of the left and right directions, particularly when connecting vertically from the extension portions 42a, 43a, 42b, 43b, the connection is made by wiring portions 42c, 43c extending in the vertical direction from the plane on which the first to third semiconductor pillars 12a, 12b, 12c are provided, either front or rear, as shown in FIG. 14 . In this way, the wiring portions 42c, 43c may not be located on the plane on which the first to third semiconductor pillars 12a, 12b, 12c are provided, but may be located on a plane parallel to or intersecting this plane. This also applies to other embodiments.

[0079] [Tenth embodiment] 15 is a diagram schematically illustrating an integrated circuit 2 according to a tenth embodiment of the present invention. The integrated circuit 2 according to the tenth embodiment of the present invention is preferably configured by stacking individual SRAM memory cells, i.e., in multiple stages, and one memory cell is configured with four NMOSs and two PMOSs, each of which can form a channel in a portion of the first to sixth semiconductor pillars 12a, 12b, 12c, 12d, 12e, and 12f. The first to sixth semiconductor pillars 12a, 12b, 12c, 12d, 12e, and 12f are arranged in this order.

[0080] On the first isolation layer 13, a first PMOS (M2) in which a channel can be formed is configured in a part of the second semiconductor pillar 12b, a first NMOS (M1) in which a channel can be formed in a part of the third semiconductor pillar 12c, a second NMOS (M3) in which a channel can be formed in a part of the fourth semiconductor pillar 12d, a second PMOS (M4) in which a channel can be formed in a part of the fifth semiconductor pillar 12e, a third NMOS (M5) in which a channel can be formed in a part of the first semiconductor pillar 12a, and a fourth NMOS (M6) in which a channel can be formed in a part of the sixth semiconductor pillar 12f. Here, the third NMOS (M5) and the fourth NMOS (M6) are both access transistors.

[0081] The drain electrode 31a of the first NMOS (M1) and the drain electrode 31b of the first PMOS (M2) are connected, the gate electrode 32a of the first NMOS (M1) and the gate electrode 32b of the first PMOS (M2) are connected, and the first NMOS (M1) and the first PMOS (M2) form a first CMOS circuit 41a.

[0082] The drain electrode 34a of the second NMOS (M3) and the drain electrode 34b of the second PMOS (M4) are connected, the gate electrode 35a of the second NMOS (M3) and the gate electrode 35b of the second PMOS (M4) are connected, and the second NMOS (M3) and the second PMOS (M4) form a second CMOS circuit 41b.

[0083] Either the source electrode or the drain electrode 31c of the third NMOS (M5) extends laterally and is connected to the drain electrodes 34a and 34b of the first CMOS circuit 41a. Either the source electrode or the drain electrode 34c of the fourth NMOS (M6) extends laterally and is connected to the drain electrodes 34a and 34b of the second CMOS circuit 41b.

[0084] A gate electrode 32c of the third NMOS (M5) and a gate electrode 35c of the fourth NMOS (M6) are connected to a word line WL through electrode vias (not shown). The other of the source and drain electrodes 33c of the third NMOS (M5) is connected to a bit bar line BBL through an electrode via 39b, and the other of the source and drain electrodes 36c of the fourth NMOS (M6) is connected to a bit line BL through an electrode via 39a.

[0085] Six transistors that make up one SRAM cell are formed on the same surface of the first to sixth semiconductor pillars 12a to 12f, and the source and drain regions of each transistor have a symmetrical structure. That is, the resistances of the source and drain regions of each transistor are in the same range, resulting in a well-match.

[0086] Here, we will explain well-matching. The flip-flop that controls the memory in SRAM is configured by connecting the output line of a first CMOS circuit to the input line of a second CMOS circuit, and connecting the output line of the second CMOS circuit to the input line of the first CMOS circuit. The input line and output line can also be expressed as the input node and output node. When the first CMOS circuit and the second CMOS circuit have the same configuration and various parameters are evaluated to be equal, the relationship between the input voltage and the output voltage of the first CMOS will be equal to the relationship between the input voltage and the output voltage of the second CMOS. This relationship between two CMOS circuits is called well-matching (perfectly matched).

[0087] The wiring portion 47 connecting the gate electrodes 32a, 32b of the first CMOS circuit 41a to the drain electrodes 34a, 34b of the second CMOS circuit 41b and the wiring portion 48 connecting the drain electrodes 31a, 31b of the first CMOS circuit 41a to the gate electrodes 35a, 35b of the second CMOS circuit 41b are both provided between the third semiconductor pillar 12c and the fourth semiconductor pillar 12d and extend in the vertical direction. Therefore, the drain electrodes 31a, 31b of the first CMOS circuit 41a extend to the side opposite to one electrode 31c to form an extension portion, and the gate electrodes 35a, 35b of the second CMOS circuit 41b extend to overlap the extension portion in a plan view to form an extension portion, and both extension portions are connected by the wiring portion 48. The drain electrodes 34a and 34b of the second CMOS circuit 41b extend opposite to the one electrode 34c to form an extension portion, and the gate electrodes 32a and 32b of the first CMOS circuit 41a extend to overlap the extension portions in a plan view, forming an extension portion, and both extension portions are connected by a wiring portion 47. Both wiring portions 47 and 48 and the extension portions connected thereto can be provided in the gap between the third semiconductor pillar 12c and the fourth semiconductor pillar 12d. Therefore, the internal wiring of the flip-flop formed by the first CMOS circuit 41a and the second CMOS circuit 41b is extremely short. This reduces Joule heat generation and enables higher integration.

[0088] In the first CMOS circuit 41a, the PMOS (M2) whose channel may be formed in part of the second semiconductor pillar 12b may be laterally reversed from the NMOS (M1) whose channel may be formed in part of the third semiconductor pillar 12c. In the second CMOS circuit 41b, the NMOS (M3) whose channel may be formed in part of the fourth semiconductor pillar 12d may be laterally reversed from the PMOS (M4) whose channel may be formed in part of the fifth semiconductor pillar 12e.

[0089] 15, the upper portions of the first CMOS circuit 41a are drain electrodes 31a and 31b, and the lower portions of the second CMOS circuit 41b are drain electrodes 34a and 34b. However, the lower portions of the first CMOS circuit 41a may be drain electrodes, and the upper portions of the second CMOS circuit 41b may be drain electrodes. The upper portions of each PMOS and NMOS are provided so as to be in contact with the isolation layer 23, just like the lower portions. In a plan view, the PMOS and NMOS are provided in a straight line on a plane including the first to sixth semiconductor pillars 12a to 12f. These features make it extremely easy to configure multiple stacked cells in the vertical direction of one cell shown in FIG. 15 so that channels can be formed in parts of the first to sixth semiconductor pillars 12a to 12f.

[0090] 15, when the SRAM cells are configured in a single layer, the wiring portions 47, 48 may be provided on the same plane as the first to sixth semiconductor pillars 12a to 12f, or may be provided on a plane different from the plane on which the first to sixth semiconductor pillars 12a to 12f are provided, for example, so as to extend in the vertical direction in a plane different in the front-to-back direction from the plane on which the first to sixth semiconductor pillars 12a to 12f are provided. The gate electrode and drain electrode may also extend in the front-to-back direction and be connected by the wiring portions 47, 48 extending in the vertical direction. This is particularly effective when the cells are configured in a multi-layer stack.

[0091] [Eleventh embodiment] 16 to 19 are schematic diagrams illustrating an integrated circuit according to an eleventh embodiment of the present invention. FIGS. 16 and 17 are plan views showing different perspectives, and FIGS. 18 and 19 are cross-sectional views taken along lines I-I and II-II, respectively. Although FIGS. 16 and 17 are the same plan views, dotted lines indicate gate electrodes 35a and 35b, drain electrodes 31a, 31b, and 31c, and wiring portion 48 in FIG. 16. Dotted lines indicate gate electrodes 32a and 32b, drain electrodes 34a, 34b, and 34c, and wiring portion 47 in FIG. 17. The integrated circuit 2 according to the eleventh embodiment of the present invention is configured by stacking SRAM memory cells, and each memory cell is configured by four NMOS transistors and two PMOS transistors whose channels can be formed in portions of the first to sixth semiconductor pillars 12a to 12f, respectively. Unlike the tenth embodiment, in a plan view, the first to third semiconductor pillars 12a to 12c are arranged in a row, and the fourth to sixth semiconductor pillars 12d to 12f are arranged in a row in the same order at positions different from the row in the front-to-back direction.

[0092] On the same first isolation layer 13, for example, in the front row, a third NMOS (M5) whose channel may be formed in a part of the first semiconductor pillar 12a, a first PMOS (M2) whose channel may be formed in a part of the second semiconductor pillar 12b, and a first NMOS (M1) whose channel may be formed in a part of the third semiconductor pillar 12c are configured. In the rear row, a fourth NMOS (M6) whose channel may be formed in a part of the sixth semiconductor pillar 12f, a second NMOS (M3) whose channel may be formed in a part of the fifth semiconductor pillar 12e, and a second PMOS (M4) whose channel may be formed in a part of the fourth semiconductor pillar 12d are configured. Here, the third NMOS (M5) and the fourth NMOS (M6) are both access transistors.

[0093] The drain electrode 31a of the first NMOS (M1) and the drain electrode 31b of the first PMOS (M2) are connected, the gate electrode 32a of the first NMOS (M1) and the gate electrode 32b of the first PMOS (M2) are connected, and the first NMOS (M1) and the first PMOS (M2) form a first CMOS circuit 41a.

[0094] The drain electrode 34a of the second NMOS (M3) and the drain electrode 34b of the second PMOS (M4) are connected, the gate electrode 35a of the second NMOS (M3) and the gate electrode 35b of the second PMOS (M4) are connected, and the second NMOS (M3) and the second PMOS (M4) form a second CMOS circuit 41b.

[0095] Either the source electrode or the drain electrode 31c of the third NMOS (M5) extends laterally and is connected to the drain electrodes 31a and 31b of the first CMOS circuit 41a. Either the source electrode or the drain electrode 34c of the fourth NMOS (M6) extends laterally and is connected to the drain electrodes 34a and 34b of the second CMOS circuit 41b.

[0096] The gate electrode 32c of the third NMOS (M5) and the gate electrode 35c of the fourth NMOS (M6) are connected to a word line WL (not shown) through separate electrode vias (not shown). The other of the source electrode and drain electrode 33c of the third NMOS (M5) is connected to a bit bar line BBL through an electrode via (not shown), and the other of the source electrode and drain electrode 36c of the fourth NMOS (M6) is connected to a bit line BL through an electrode via (not shown).

[0097] Six transistors that make up one SRAM cell are formed on the same surface of the first to sixth semiconductor pillars 12a to 12f, and the source and drain regions of each transistor have a symmetrical structure. That is, the resistances of the source and drain regions of each transistor are in the same range, resulting in a well-match.

[0098] The wiring portion 47 connecting the gate electrodes 32a, 32b of the first CMOS circuit 41a to the drain electrodes 34a, 34b of the second CMOS circuit 41b and either the source electrode or the drain electrode 34c of the fourth NMOS (M6) is composed of a portion extending in a direction intersecting the erection direction of the third semiconductor pillar 12c and the sixth semiconductor pillar 12f, for example, in the front-to-back direction, and a portion extending parallel to the erection direction (i.e., up and down).

[0099] The wiring portion 48 connecting the gate electrodes 35a, 35b of the second CMOS circuit 41b to the drain electrodes 31a, 31b of the first CMOS circuit 41a and either the source electrode or the drain electrode 31c of the third NMOS (M5) is composed of a portion extending in a direction intersecting the erection direction of the first semiconductor pillar 12a and the fourth semiconductor pillar 12d, for example, in the front-to-back direction, and a portion extending parallel to the erection direction (i.e., up and down).

[0100] Therefore, the internal wiring of the flip-flop formed by the first CMOS circuit 41a and the second CMOS circuit 41b is shortened, which reduces the generation of Joule heat and allows for higher integration.

[0101] In both the tenth and eleventh embodiments, in the first CMOS circuit 41a, the PMOS (M2) having a channel in part of the second semiconductor pillar 12b may be laterally reversed from the NMOS (M1) having a channel in part of the third semiconductor pillar 12c. In the second CMOS circuit 41b, the NMOS (M3) having a channel in part of the fourth semiconductor pillar 12d may be laterally reversed from the PMOS (M4) having a channel in part of the fifth semiconductor pillar 12e.

[0102] 18 and 19, the upper portions of the first CMOS circuit 41a are drain electrodes 31a and 31b, and the lower portions of the second CMOS circuit 41b are drain electrodes 34a and 34b, but the lower portions of the first CMOS circuit 41a may be drain electrodes, and the upper portions of the second CMOS circuit 41b may be drain electrodes. The upper portions of each PMOS and NMOS are provided so as to be in contact with the isolation layer 23, just like the lower portions.

[0103] In a tenth embodiment of the present invention, the PMOSs and NMOSs are arranged in a straight line in a plan view as shown in Fig. 15. In an eleventh embodiment of the present invention, the PMOSs and NMOSs are arranged in a straight line in a front-to-back row in a plan view as shown in Figs.

[0104] 15 and 16 to 19 can be stacked vertically to form multiple cells so that channels can be formed in parts of the six semiconductor pillars 12. In this case, the threshold voltages of the MOSs that use parts of the semiconductor pillars 12 as channels are in the same range, eliminating the need to provide a separate MOS-FET for adjusting the threshold voltage.

[0105] The first to sixth semiconductor pillars 12a to 12f and the wiring portions 47, 48 can be arranged arbitrarily in a plan view, and among these, they may be provided on a straight line in a plan view as shown in Fig. 15, but are preferably arranged symmetrically around an arbitrary point in a plan view, for example, in an S-shape or Z-shape, because this allows the well-match described above to be achieved.

[0106] [Twelfth embodiment] The semiconductor device 1 shown in the first embodiment of the present invention can constitute a DRAM as an integrated circuit 3. In the DRAM as an integrated circuit 3 according to the twelfth embodiment of the present invention, one cell is constituted by a vertical GAA-MOSFET and a capacitor. FIG. 20 is a cross-sectional view showing the configuration of the DRAM as an integrated circuit 3 according to the twelfth embodiment of the present invention. FIG. 21 is a basic equivalent circuit diagram of the DRAM.

[0107] In the vertical GAA-MOSFET 1a, a gate insulating layer 17 is provided on a portion of a semiconductor pillar 12 provided on a substrate 11, the portion of which may serve as a channel. A gate electrode 18 is provided surrounding the gate insulating layer 17. A first electrode 14 and a second electrode 21, serving as a source electrode and a drain electrode (or vice versa), are provided above and below the gate insulating layer 17, with isolation layers 16 and 20 interposed between them, surrounding the semiconductor pillar 12. In the capacitor 50, a first capacitor electrode 51 is provided on the same plane as the first electrode 14 and with the same thickness. A second capacitor electrode 52 is provided opposite the first capacitor electrode 51 and separated along a channel that may be formed in the semiconductor pillar 12, so as to be unconnected to the second electrode 21. A connection electrode 53 is provided on the same plane as the first electrode 14 and the first capacitor electrode 51 and at the same height, connecting the first electrode 14 and the first capacitor electrode 51. It is also possible to connect the second electrode 21 and the second capacitor electrode 52 without connecting the first electrode 14 and the first capacitor electrode 51.

[0108] 20 , at least one semiconductor pillar 12 is erected on a substrate 11, a connection portion of the semiconductor pillar 12 with the substrate 11 is buried in a first isolation layer 13, and the semiconductor pillar 12 is disposed approximately perpendicular to the first isolation layer 13. A first electrode 14, serving as either a source electrode or a drain electrode, is disposed on the first isolation layer 13 so as to surround the semiconductor pillar 12, a first capacitor electrode 51 is disposed on the same surface as the first electrode 14 at the same height, and a connection electrode portion 53 on the first isolation layer 13 connects the first electrode 14 and the first capacitor electrode 51. A first insulating layer 15 is disposed on the first isolation layer 13 in a region where the first electrode 14 and the first capacitor electrode 51 are not provided, so as to have approximately the same thickness as those electrodes. A second isolation layer 16 is provided on the first electrode 14, the first capacitor electrode 51, and the first insulating layer 15. A gate insulating layer 17 is provided on the second isolation layer 16 to circumferentially surround a portion of the semiconductor pillar 12. A gate electrode 18 is provided to further circumferentially surround the gate insulating layer 17. The gate electrode 18 is connected to a word line WL via an electrode via 28 extending in the vertical direction of the semiconductor pillar 12 at a position different from the semiconductor pillar 12. The second insulating layer 19 is provided on the second isolation layer 16 so that the second insulating layer 19 has approximately the same thickness as the gate insulating layer 17 and the gate electrode 18. This makes the second insulating layer 19 approximately flush with an insulating layer formed on the gate electrode 18 at the same time as the gate insulating layer 17. A third isolation layer 20 is provided on the insulating layer and the second insulating layer 19. A second electrode 21, which serves as the other of the source and drain electrodes, is provided on the third isolation layer 20, facing the first electrode 14 and circumferentially surrounding a portion of the semiconductor pillar 12. The second electrode 21 is connected to the bit line BL by an electrode via 29 extending in the vertical direction. A second capacitor electrode 52 is provided facing the first capacitor electrode 51 at a predetermined distance. In the illustrated embodiment, the second capacitor electrode 52 is provided at the same height as the second electrode 21 and is provided on the opposite side of the first capacitor electrode 51 with the second isolation layer 16, the second insulating layer 19, and the third isolation layer 20 sandwiched therebetween.The second capacitor electrode 52 is connected to, for example, ground through a vertically extending electrode via 29. An isolation layer 54 of the same material as the second isolation layer 16, the insulating layer 19, and the third isolation layer 20 is provided on the upper side of the connection electrode 53.

[0109] In the DRAM as the integrated circuit 3 according to the twelfth embodiment, both the first capacitor electrode 51 and the second capacitor electrode 52 are provided in a stack including the source electrode and the drain electrode of the GAA-MOSFET 1a. The areas of the first capacitor electrode 51 and the second capacitor electrode 52 can be freely set with little variation, and the capacitance as a capacitor can be accurately realized.

[0110] [Thirteenth embodiment] FIG. 22 is a cross-sectional view schematically illustrating one cell of a DRAM as an integrated circuit 3 according to a thirteenth embodiment of the present invention. The DRAM as an integrated circuit 3 according to the thirteenth embodiment of the present invention differs from the twelfth embodiment in that the first capacitor electrode 51 and the second capacitor electrode 52 are thinner than the first electrode 14, the first capacitor electrode 51 is provided on the first isolation layer 13, a non-conductive layer 55 is provided on the first capacitor electrode 51, and the second capacitor electrode 52 is provided on the non-conductive layer 55. Compared to the twelfth embodiment, the distance between the first capacitor electrode 51 and the second capacitor electrode 52 is shorter, achieving a large capacitance even with a small electrode area. Furthermore, when such cells are stacked vertically, they are less susceptible to the influence of adjacent capacitors above and below than when the twelfth embodiment is similarly stacked. Furthermore, leakage current is small.

[0111] [Fourteenth embodiment] 23 is a cross-sectional view schematically showing one cell of a DRAM as an integrated circuit 3 according to the fourteenth embodiment of the present invention. The DRAM as an integrated circuit 3 according to the fourteenth embodiment of the present invention is as follows.

[0112] The first capacitor electrode 57a has its lower surface flush with the lower surface of the first electrode 14, which is either the source or drain electrode of the GAA-MOSFET 1a, and is thinner than the first electrode 14. A connection electrode 53 on the first isolation layer 13 connects the first capacitor electrode 57a to the first electrode 14. The third capacitor electrode 57c is provided opposite the first capacitor electrode 57a with a non-conductive layer 56a interposed therebetween, and has its upper surface at the same height as the upper surface of the first electrode 14.

[0113] The second capacitor electrode 57b is provided thinner than the second electrode 21, which is the other of the source and drain electrodes of the GAA-MOSFET 1a, so that its lower surface is flush with the lower surface of the second electrode 21. The fourth capacitor electrode 57d is provided opposite the second capacitor electrode 57b with a non-conductive layer 56b interposed therebetween so that its upper surface is at the same height as the upper surface of the second electrode 21.

[0114] The second capacitor electrode 57b and the third capacitor electrode 57c are arranged to substantially overlap each other in a plan view. The fifth capacitor electrode 57e is connected to one end of the second capacitor electrode 57b and one end of the third capacitor electrode 57c, and extends vertically in the stacking direction. The fourth capacitor electrode 57d is arranged to substantially overlap the first capacitor electrode 57a in a plan view. The sixth capacitor electrode 57f is connected to one end of the first capacitor electrode 57a and one end of the fourth capacitor electrode 57d, and extends vertically in the stacking direction. The fifth capacitor electrode 57e has a shorter vertical dimension than the sixth capacitor electrode 57f. The first capacitor electrode 57a overlaps with the fourth capacitor electrode 57d, but extends to connect to the connection electrode 53. The second capacitor electrode 57b extends partially toward the GAA-MOSFET 1a relative to the fourth capacitor electrode 57d, and is connected to, for example, ground during use via an electrode via 58 extending in the stacking direction. A non-conductive layer 56c is interposed between the fifth capacitor electrode 57e and the sixth capacitor electrode 57f, and the non-conductive layer 56c is integrated with the non-conductive layer 56a sandwiched between the pair of the first and third capacitor electrodes 57a and 57c and the non-conductive layer 56b sandwiched between the pair of the second and fourth capacitor electrodes 57b and 57d. An isolation layer 54, made of the same material as the second isolation layer 16, the second insulating layer 19, and the third isolation layer 20, is provided above the connection electrode 53 and between the third capacitor electrode 57c and the second capacitor electrode 57b.

[0115] As described above, in one cell constituting the DRAM as the integrated circuit 3 according to the fourteenth embodiment, the capacitor is formed with a U-shaped cross section as shown in the figure. As in the thirteenth embodiment, a large capacitance is realized even with a small electrode area, and by providing capacitor components at different heights, a large capacitance is realized even with a smaller electrode area, and the refresh timing period is extended. The cell footprint can be reduced, resulting in higher density.

[0116] [Fifteenth embodiment] An integrated circuit 3 according to the fifteenth embodiment of the present invention is configured by stacking individual memory cells of a DRAM. While a case where one cell described in the twelfth embodiment is stacked vertically will be described, this can also be applied to the integrated circuits 3 described in the thirteenth and fourteenth embodiments. Fig. 24 is a cross-sectional view schematically showing a cell of the integrated circuit 3 according to the fifteenth embodiment of the present invention, and Fig. 25 is a cross-sectional view taken along the line XX in Fig. 24.

[0117] 24, a first GAA MOSFET 61a and a second GAA MOSFET 61b are provided at different heights in positions that overlap in a plan view. Semiconductor pillars 12 are provided on a substrate 11 at different heights in positions that overlap in a plan view. Each semiconductor pillar 12 is provided, from bottom to top, with a first isolation layer 13, a first insulating layer 15 provided on the first isolation layer 13, a first electrode 14 which is either a source electrode or a drain electrode provided to surround the semiconductor pillar 12, a second isolation layer 16 provided on the first insulating layer 15 and the first electrode 14, a gate insulating layer 17 provided on the second isolation layer 16 to surround the semiconductor pillar 12, and a gate insulating layer 18 provided to surround the gate insulating layer 17. The first GAA MOSFET 61a is composed of electrode 18, second insulating layer 19, third isolation layer 20 (including an insulating layer formed on gate electrode 18 at the same time as gate insulating layer 17) provided on part of gate electrode 18 and second insulating layer 19, second electrode 21 (the other of the source electrode and drain electrode) provided on third isolation layer 20, and third insulating layer 22, and fourth isolation layer 23a provided on second electrode 21 and third insulating layer 22. Similarly, a second GAA MOSFET 61b is formed on fourth isolation layer 23a with a similar stacked structure.

[0118] A first capacitor electrode 51 is provided at the same height as the first electrode 14 of each of the first GAA-MOSFET 61a and the second GAA-MOSFET 61b, and a second capacitor electrode 52 is provided opposite the first capacitor electrode 51 with a non-conductive layer 70 sandwiched between them. The first capacitor electrode 51 is connected to the first electrode 14, which is located at the same height, by a connection electrode 53. The second capacitor electrode 52 is connected to, for example, ground during use via a common electrode via 29.

[0119] Each gate electrode 18 is connected to a corresponding word line WL via an electrode via 28. The second electrodes 21 described above are each drawn out in the front-rear direction and connected to a bit line via an electrode via 29, as shown in FIG.

[0120] In the fifteenth embodiment, a stack of a first GAA MOSFET 61a and a second GAA MOSFET 61b and a stack of two capacitors 50 are integrated into a single stack. By applying a voltage from the word line WL to the gate electrode 18 via the electrode via 28, the threshold voltages of the first GAA MOSFET 61a and the second GAA MOSFET 61b are brought into the same range, thereby reducing MOSFET variations and variations due to charging and discharging of the capacitor. Errors between "0" and "1" due to potential levels are not a problem even with miniaturization and increased integration. This is because the source and drain regions of each GAA MOSFET are symmetrical.

[0121] In the fifteenth embodiment of the present invention, die or wafer levels are not stacked, and a three-dimensional integrated circuit with an extremely high integration density is constructed. This also applies to the other embodiments described below.

[0122] Furthermore, the present invention is not limited to a two-layer structure having both a GAA-MOSFET and a capacitor on the top and bottom, but may also be a three-layer structure, a four-layer structure, or a structure with more layers.

[0123] In the embodiment shown in Fig. 25, the electrodes are connected to the respective bit lines BL via electrode vias 29, but in some cases, they may be connected to a single bit line BL. Fig. 26 is a cross-sectional view schematically showing an integrated circuit 3 according to a fifteenth embodiment different from that shown in Fig. 24. As shown in Fig. 26, the electrode 21 of either the source or drain electrode of the lower GAA MOSFET 61a that is not connected to the capacitor electrode and the electrode 21 of either the source or drain electrode of the upper GAA MOSFET 61b that is not connected to the capacitor electrode may be connected to a common bit line by a wiring portion 29a.

[0124] Fig. 27 is a cross-sectional view schematically showing an integrated circuit 3 according to a fifteenth embodiment of the present invention, which is different from Figs. 24 and 26, and Fig. 28 is a cross-sectional view taken along line XX in Fig. 27. As shown in Figs. 27 and 28, DRAMs each having a GAA-MOSFET and a capacitor arranged side by side may be stacked vertically. Each GAA-MOSFET 1 (1a, 1b, 1c, 1d) and a capacitor 50 are connected by a corresponding connection electrode 53.

[0125] [16th embodiment] An integrated circuit according to a sixteenth embodiment of the present invention relates to a ferroelectric random access memory (FeRAM), phase change memory (PCM), or resistance change memory (ReRAM) element, which is formed by interposing a ferroelectric layer, a phase change layer, or a resistance change layer between a pair of capacitor electrodes constituting the capacitor according to any one of the twelfth to fifteenth embodiments. The memory cells may be configured as a single layer, two layers, or three layers. This reduces variations even with increased integration density, thereby improving the characteristics of the integrated circuit. FIG. 29 is a cross-sectional view schematically illustrating an integrated circuit according to the sixteenth embodiment of the present invention. The integrated circuit can be configured by interposing a ferroelectric layer, a phase change layer, or a resistance change layer, indicated by the reference numeral 70, between a first capacitor electrode 51 and a second capacitor electrode 52.

[0126] [Seventeenth embodiment] In an integrated circuit according to an embodiment of the present invention, basic units constituting any one of CMOS, DRAM, and SRAM may be stacked in multiple stages, or at least two types of basic units constituting each of CMOS, DRAM, and SRAM may be stacked. That is, the integrated circuit may be configured by stacking multiple basic units constituting CMOS. The integrated circuit may be configured by stacking multiple basic units constituting DRAM. The integrated circuit may be configured by stacking multiple basic units constituting SRAM. The integrated circuit may be configured by stacking one or multiple basic units constituting CMOS, and then stacking one or multiple basic units constituting SRAM on top of that. The integrated circuit may be configured by stacking one or multiple basic units constituting SRAM, and then stacking one or multiple basic units constituting CMOS on top of that. The integrated circuit may be configured by stacking one or multiple basic units constituting CMOS, and then stacking one or multiple basic units constituting DRAM on top of that. The integrated circuit may be configured with one or multiple stacked basic units constituting DRAM, and one or multiple stacked basic units constituting CMOS on top of that. The integrated circuit may be configured with one or multiple stacked basic units constituting CMOS, and one or multiple stacked basic units constituting DRAM on top of that, and one or multiple stacked basic units constituting SRAM on top of that. In this case, the order of CMOS, SRAM, and DRAM can be set arbitrarily. Any of the above-mentioned embodiments may be selected for each of the CMOS, SRAM, and CMOS. Furthermore, by repeatedly providing each stage in the front-to-back direction in a plan view, a three-dimensional integrated circuit may be configured.

[0127] As an example, an integrated circuit for storing values ​​calculated by CMOS as cache memory will be described. However, a CMOS circuit may be combined with DRAM, or with SRAM, or with both SRAM and DRAM. In such cases, the number of CMOS, SRAM, and DRAM stages may be arbitrarily set. In this case, one or more CMOS circuits function as logic circuits. Figure 30 is a schematic diagram of an integrated circuit 4 according to a seventeenth embodiment of the present invention. The integrated circuit 4 according to the seventeenth embodiment of the present invention is configured with CMOS circuits 41a and 41b in the first and second stages, and an SRAM 46 above them. In the third and fourth stages, NMOS and CMOS are alternately arranged. This configuration is similar to the integrated circuit 2 shown in Figure 7. The transistors in the SRAM 46 are labeled M1 to M6, as in Figure 7. The integrated circuit 4 has first to third semiconductor pillars 12 (12a, 12b, 12c) standing on a substrate 11. Four PMOS transistors are provided at different heights relative to the second semiconductor pillar 12b. NMOS transistors are provided in second to fourth stages relative to the first semiconductor pillar 12a. NMOS transistors are provided in the first, third, and fourth stages relative to the third semiconductor pillar 12c. The PMOS transistors and NMOS transistors in the first stage form a first CMOS circuit 41a, and the PMOS transistors and NMOS transistors in the second stage form a second CMOS circuit 41b. The PMOS transistors and NMOS transistors in the third stage form a third CMOS circuit 41c, and the PMOS transistors and NMOS transistors in the fourth stage form a fourth CMOS circuit 41d. The NMOS transistors 45a and 45b in the third and fourth stages are both access transistors. The drain electrode of the first CMOS circuit 41a extends laterally, and this extension is connected to the gate electrode of the second CMOS circuit 41b by a wiring portion 42x extending vertically. The drain electrode of the first CMOS circuit 41a extends laterally, and the other of the source electrode and drain electrode of the third-stage NMOS transistor (M6) extends laterally, and these extension portions are connected to each other by a wiring portion 43x extending vertically.The gate electrode of the first CMOS circuit 41a extends laterally, and its extension is connected to the electrode via 29, through which the input signal Input is input. The drain electrode of the second CMOS circuit 41b extends laterally, and its extension is connected by a wiring portion 42y extending vertically, and is connected to an extension portion of the other of the source electrode or drain electrode of the NMOS transistor (M5) of the SRAM 46. The gate electrode of the third CMOS circuit 41c extends laterally, and is vertically connected to an extension portion of either the source electrode or the drain electrode of the third-stage NMOS 45a by a wiring portion 43y. The wiring portion 43 is connected to the drain electrode of the fourth CMOS circuit 41d. The gate electrode of the fourth CMOS circuit 41d extends laterally, and is vertically connected to an extension portion of either the source electrode or the drain electrode of the fourth-stage NMOS 45b by a wiring portion 42z. The wiring portion 42z is connected to the drain electrode of the third CMOS circuit 41c. The gate electrode of the NMOS transistor (M5) of the SRAM 46 extends laterally, and its extension is connected to the electrode via 28a and to the word line WL via the electrode via 28a. The gate electrode of the NMOS transistor (M6) of the SRAM extends laterally, and its extension is connected to the electrode via 28b and to the word line WL28b via the electrode via 28b.

[0128] The integrated circuit 4 according to the seventeenth embodiment of the present invention operates, for example, as follows: When an input "1" is input from the electrode via 29, a "0" is output via the gate electrode of the first CMOS circuit 41a. Then, a "0" is input to the gate electrode of the second CMOS circuit 41b and the wiring portion 43x, which is inverted by the second CMOS circuit 41b and a "1" is input to the wiring portion 42y. The wiring portion 43x corresponds to the bit line BL, and the wiring portion 42x corresponds to the bit bar line BBL.

[0129] When the word lines WL28a and WL28b are turned ON, the results of the calculations in the first CMOS circuit 41a and the second CMOS circuit 41b (in the above example, BL is "0" and BBL is "1") are input and stored in the first to fourth transistors (M1, M2, M3, M4). The data stored in this way is read by a peripheral circuit (not shown) using BL and BBL, just like a normal SRAM.

[0130] In the integrated circuit 4 shown in Figure 30, the second CMOS circuit 41b and the SRAM 46 are separated by the isolation layer 23b, so wiring is performed over a short distance by extending the wiring portions 43e and 42e vertically and connecting the various electrodes to the extension portions that are formed by extending horizontally and, in some cases, front and rear.

[0131] [Eighteenth embodiment] The 18th embodiment of the present invention relates to a basic manufacturing method used when manufacturing the semiconductor device or integrated circuit according to the first to seventeenth embodiments of the present invention. Figures 31A to 31P are cross-sectional views of each process in the manufacturing method of the semiconductor device according to the 18th embodiment of the present invention. The processes proceed in alphabetical order attached to the figure numbers.

[0132] A method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention will be described in detail. First, a substrate such as a Si substrate is prepared, and semiconductor pillars 101 are erected on the substrate (not shown). A substrate on which semiconductor pillars 101 are erected may be prepared.

[0133] 31A, an SiO film is deposited on the substrate as isolation layer 102, and an SiN film is deposited on isolation layer 102 as film 103, which will be one of a pair of first sacrificial layers. Then, photolithography patterning and selective etching techniques are used to form one of the pair of first sacrificial layers 104a. At this time, isolation layer 102 and one of the pair of first sacrificial layers 104a are formed so as to surround semiconductor pillar 101, respectively.

[0134] On the partially exposed first isolation layer 102, SiO2 is formed as a first insulating layer 105 having the same thickness as the sacrificial layer 104a that is paired with the first isolation layer 102. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0135] Next, an SiO film serving as the second isolation layer 106 is deposited on the first sacrificial layer 104a and the first insulating layer 105, and an SiN film serving as the second sacrificial layer is deposited on the second isolation layer 106. Then, the second sacrificial layer 107a is formed using photolithographic patterning and selective etching techniques. The second isolation layer 106 and the second sacrificial layer 107a are each formed to surround the semiconductor pillar 101. The film serving as the second sacrificial layer 107a is deposited so as to overlap the first sacrificial layer 104a and the semiconductor pillar 101 in a plan view, but not to overlap in other areas. This is also to provide the first through-hole 121 and the second through-hole 126 in separate positions, as will be described later.

[0136] On the partially exposed second isolation layer 106, SiO2 is formed as a second insulating layer 108 having the same thickness as the second sacrificial layer 107a. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0137] Next, an SiO2 film is deposited as the third isolation layer 109 on the second sacrificial layer 107a and the second insulating layer 108 (this stage is shown in FIG. 31B), and an SiN film is deposited as the film that will become the other pair of first sacrificial layer on the third isolation layer 109. Photolithographic patterning and selective etching techniques are used to form the other pair of first sacrificial layer 104b. At this time, the third isolation layer 109 and the other pair of first sacrificial layer 104b are each formed so as to surround the semiconductor pillar 101 (see FIG. 31C).

[0138] A third insulating layer of SiO2 having the same thickness as the other first sacrificial layer 104b is formed on the partially exposed third isolation layer 109. Needless to say, photolithographic patterning and selective etching techniques are used in this process.

[0139] Through this series of steps, the isolation layer 102, one first sacrificial layer 104a and insulating layer 105, the isolation layer 106, the second sacrificial layer 107a and insulating layer 108, the isolation layer 109, the other first sacrificial layer 104b and insulating layer are stacked in this order, and an SiO2 film is deposited as the top isolation layer to surround the semiconductor pillar 101, thereby preparing a stack for manufacturing one GAA-MOSFET.

[0140] To fabricate multiple GAA MOSFETs, simply stack the corresponding number of stacked bodies 100. After stacking, a SiO2 film is deposited as a top isolation layer. Note that the isolation layer separating the stacked bodies from each other in the integrated stacked body 100 can be thickened to structurally separate the upper and lower GAA MOSFETs. This state is shown in Figure 31C. The pair of first sacrificial layers 114a, 114b and the second sacrificial layer 117a in the second layer are formed in the same manner as the pair of first sacrificial layers 104a, 104b and the second sacrificial layer 107a in the first layer. Because the isolation layer and the insulating layer are both made of the same material, they are shown as layer 110 made of an insulating material in Figure 31C.

[0141] In the following explanation, a case where a two-layered laminate is constructed will be described, but it goes without saying that the same applies to a one-layered laminate and a three-layered or more laminated laminate.

[0142] Next, first through-holes 121 are formed in the layer 110 as first holes, reaching the first sacrificial layer 104a located closest to the substrate. For example, as shown in FIG. 31D, the first through-holes 121 are formed in the stack 100 so as to penetrate the paired first sacrificial layers 104a, 104b, 114a, and 114b. Next, as shown in FIG. 31E, the first sacrificial layers 104a, 104b, 114a, and 114b are removed by wet etching via the first through-holes 121, and the removed portions 104c, 104d, 114c, and 114d are connected to the first through-holes 121. As shown in FIG. 31F, a conductive layer 122, such as a metal layer, is formed on the paired removed portions 104c, 104d, 114c, and 114d of the first sacrificial layers and the first through-holes 121. At this time, an ALD (Atomic Layer Deposition) method or the like is used. As a result, a conductive layer 122, which will become the source electrode and the drain electrode, is simultaneously formed. Next, as shown in FIG. 31G, the conductive layer in the first through-hole is removed to open a hole 123, and as shown in FIG. 31H, the hole 123 is filled with an insulating film 125 to separate the source electrode and the drain electrode, which are indicated by reference numerals 124a, 124b, 124c, and 124d. Through this series of steps, the source electrode and the drain electrode are formed.

[0143] Next, a second through-hole 126 is formed in the layer 110 so as to reach the second sacrificial layer 107a located closest to the substrate. For example, as shown in FIG. 31I, the second through-hole 126 is formed in the stack 100 so as to penetrate the second sacrificial layers 107a and 117a. Next, as shown in FIG. 31J, the second sacrificial layers 107a and 117a are removed by wet etching via the second through-hole 126. As shown in FIG. 31K, a portion of the semiconductor pillar 101 is exposed in the portions 107c and 117c where the second sacrificial layers 107a and 117a have been removed. An insulating layer 127 that will serve as a gate insulating layer is then deposited on the exposed portion. For this purpose, an ALD method or the like is used, and the insulating layer 127 is formed to a thickness sufficiently thinner than the second sacrificial layers 107a and 117a. Next, as shown in FIG. 31L, a conductive layer 128, such as a metal layer, is formed on the insulating layer 127 to fill the second through-hole 126. This simultaneously forms portions that will become multiple gate electrodes. Next, as shown in FIG. 31M, the conductive layer 128 in the second through-hole 126 is removed to form a hole 129, and as shown in FIG. 31N, an insulator 130 is deposited in the hole 129 to separate the connection between the conductive layer 128a and the conductive layer 128b. Through this series of steps, a gate insulating layer 127 and conductive layers 128a and 128b are formed. The conductive layer 128a is used as the gate electrode 18a.

[0144] Next, for the conductive layers 128a and 128b that overlap in plan view, the conductive layer 128 is partially removed and an insulating layer such as SiO2 is deposited so that the distance from the semiconductor pillar 101 is shorter than that of the conductive layer 128b located above, thereby processing the conductive layer 128b into the gate electrode 18b. For example, this can be achieved by etching away the portion of a certain conductive layer 128b to be partially removed, as well as the portions of the isolation layer and insulating layer present above that portion, and then filling back in with an insulating layer such as SiO2.

[0145] Around the same time, among the multiple conductive layers that overlap in plan view and serve as source and drain electrodes, the upper conductive layers 124b, 124c, and 124d are processed by partially removing each of the conductive layers 124b, 124c, and 124d and depositing an insulating layer such as SiO2 so that the distance from the semiconductor pillar 121 is shorter. For example, this can be achieved by etching away the portion of a conductive layer to be partially removed and the portions of the isolation layer and insulating layer above that portion, and then filling in the remaining portions with an insulating layer such as SiO2. In this case, when removing the portions of the multiple conductive layers to be partially removed and the portions of the isolation layer and insulating layer above that portion, separate portions may be removed so that they form an L-shape in cross section, and then filled in with an insulating layer such as SiO2. Reference numeral 110a denotes a portion composed of substantially the same insulating material. Figure 31O shows the state after this series of processes.

[0146] 31P, wiring is performed by connecting either the source electrode or the drain electrode 14a, 21a, 14b, 21b to the gate electrode 18a, 18b through the corresponding electrode vias 24a, 25a, 24b, 25b, 26a, 26b. If the insulating film formed as the gate insulating layer partially remains at the connection portion between the gate electrode and the electrode via, this portion is also removed before connecting the electrode via.

[0147] By going through the above series of steps, the semiconductor device 1 according to the second embodiment shown in FIG. 2 can be fabricated as a plurality of GAA-MOSFETs. The fabrication of the source and drain electrodes and the fabrication of the gate insulating film and gate electrode may be reversed. Furthermore, although the stacked body 100 is formed by erecting the semiconductor pillars 101 on the substrate, it is also possible to form the stacked body on the substrate, and then drill holes in the formation regions for the semiconductor pillars 101, and then deposit the material for the semiconductor pillars in the holes.

[0148] [Basic form of the 18th embodiment] A method for manufacturing a semiconductor device according to the eighteenth embodiment of the present invention includes forming a stack 100 in which paired first sacrificial layers 104a, 104b, 114a, and 114b are provided in portions that will become source electrodes and portions that will become drain electrodes, and isolating layers are provided either above or below these first sacrificial layers; forming first holes in the stack 100 that reach the plurality of first sacrificial layers 104a, 104b, 114a, and 114b, for example, first through holes 121 that penetrate the plurality of first sacrificial layers 104a, 104b, 114a, and 114b; etching and removing the plurality of first sacrificial layers 104a, 104b, 114a, and 114b via the through holes 121; and then simultaneously depositing a conductive layer in the removed portions to form source electrodes and drain electrodes. Here, the first through holes 121 may be holes that reach the first sacrificial layers 104a, 104b, 114a, and 114b.

[0149] When the semiconductor device has a single-stage GAA MOSFET, the stack 100 may be provided with a pair of sacrificial layers, one above the other, to form the source electrode and the other below the drain electrode. The pair of sacrificial layers is simultaneously etched, and a conductive layer, such as a metal layer, is simultaneously deposited to simultaneously fabricate the source electrode and the drain electrode. This allows the source electrode and the drain electrode to be fabricated simultaneously using the same material. This results in the same structural configuration, including the shape and dimensions of the source electrode and the drain electrode, as well as the same effect on the source electrode and the drain electrode relative to the semiconductor pillar, compared to fabricating the source electrode and the drain electrode at different times. This allows the source region and the drain region formed in the semiconductor pillar to be identical.

[0150] Furthermore, the isolation layer provided on the portion that will become the source electrode (or drain electrode) has the same thickness as the isolation layer provided on the portion that will become the drain electrode (or source electrode). As a result, the portion of the semiconductor pillar surrounded by the source electrode and the portion surrounded by either the isolation layer above or below it become the source region, and the portion surrounded by the drain electrode and the portion surrounded by either the isolation layer above or below it become the drain region. As a result, the source region is identical to the drain region in terms of not only material but also shape and size. Therefore, the source region and the drain region are symmetrical.

[0151] In this regard, in conventional technology, a substrate on which semiconductor pillars are erected is prepared, and a metal layer that will become, for example, a lower source electrode is deposited and etched back to form the source electrode. Next, the portion of the semiconductor pillar above the source electrode is cleaned without fail to form an isolation layer between the source electrode and the portion that will become the gate region. Next, a gate insulating film is formed on the portion of the semiconductor pillar above the isolation layer, a metal layer is formed on the gate insulating film, and the metal layer is etched back to form a gate electrode. Next, the portion of the semiconductor pillar above the gate insulating film and gate electrode is cleaned without fail to form an isolation layer between the gate insulating film and gate electrode and the portion that will become the drain region. Next, a metal layer is formed on the portion of the semiconductor pillar above the isolation layer, and the metal layer is etched back to form the drain electrode. Finally, an isolation layer is formed in the region including the drain electrode, and vias are formed for the source electrode, drain electrode, and gate electrode, respectively.

[0152] In conventional techniques, the source electrode, isolation layer, gate insulating film, gate electrode, isolation layer, drain electrode, and isolation layer are formed in this order from bottom to top of the semiconductor pillar. Therefore, the source electrode and drain electrode are not formed simultaneously. After the source electrode is formed, the exposed portion of the semiconductor pillar is necessarily cleaned, which reduces the diameter of the semiconductor pillar and causes damage to the semiconductor pillar due to metal diffusion caused by the cleaning. Furthermore, after the gate insulating layer and gate electrode are formed, the exposed portion of the semiconductor pillar is necessarily cleaned, which further reduces the diameter of the semiconductor pillar and causes further damage to the semiconductor pillar due to metal diffusion caused by the cleaning. Therefore, the portion of the source region of the semiconductor pillar after the source electrode is formed cannot be the same as the portion of the drain region of the semiconductor pillar after the drain electrode is formed. Furthermore, the etching back of the metal layer cannot be precisely controlled. These problems also exist when the drain electrode, isolation layer, gate insulating film, gate electrode, isolation layer, source electrode, and isolation layer are formed in this order from bottom to top of the semiconductor pillar.

[0153] As mentioned above, etching a metal causes the metal to diffuse into semiconductors such as Si, which changes the electrical properties. Therefore, when etching a metal, it is necessary to also partially etch the surface of semiconductors such as Si to make it clean.

[0154] In contrast, in the method for fabricating a semiconductor device according to the eighteenth embodiment of the present invention, first, there is no process that adversely affects the formation of the source electrode and the drain electrode, and therefore there is no semiconductor pillar cleaning process as in the past. Therefore, the semiconductor pillar does not gradually or stepwise become thinner in the axial direction as it moves upward, and the diameters of the source electrode and the drain electrode do not differ. In other words, the inner diameters of the source region and the drain region do not differ. When forming the conductive layer that forms the source and drain electrodes, metal does not come into contact with regions other than the source and drain regions of the semiconductor pillar. In other words, openings are made only in the areas where conductive layers are required in the stack 100 itself, which includes multiple sacrificial layers and isolation layers, and conductive layers such as metal layers are deposited only in the openings.

[0155] Therefore, the semiconductor device manufacturing method according to the eighteenth embodiment of the present invention has the following advantages. Not only the structural configuration including the shape and dimensions of the source and drain electrodes, but also the influence of the formation of the source and drain electrodes on the semiconductor pillars is the same, and the source and drain regions formed in the semiconductor pillars can also be identical. Furthermore, with regard to manufacturing variations, since the source and drain electrodes are manufactured simultaneously, manufacturing variations of the source electrode match manufacturing variations of the drain electrode.

[0156] These effects are achieved not only in semiconductor devices with a single-stage GAA MOSFET but also in semiconductor devices with multiple stages of GAA MOSFETs. In the case of a single-stage GAA MOSFET, a pair of first sacrificial layers may be provided above and below the stack to form the source and drain electrodes. In the case of a semiconductor device with multiple stages of GAA MOSFETs, a pair of sacrificial layers may be provided above and below the stack to form the source and drain electrodes. Furthermore, in the case of multiple stages of GAA MOSFETs, even among multiple GAA MOSFETs formed vertically around a single semiconductor pillar, it is preferable that the source and drain electrodes of the lower GAA MOSFET be fabricated simultaneously with the source and drain electrodes of the upper GAA MOSFET. This is because variations in fabrication between GAA MOSFETs stacked vertically around a single semiconductor pillar also occur. Therefore, the performance of GAA MOSFETs stacked vertically around a single semiconductor pillar, particularly the threshold voltage and drive current, are evaluated to be identical.

[0157] According to the method for fabricating a semiconductor device of the eighteenth embodiment of the present invention, when fabricating a multi-layered GAA-MOSFET, the number of steps is not approximately proportional to the number of steps for fabricating a single-layer GAA-MOSFET, thereby enabling time reduction.

[0158] In a method for fabricating a semiconductor device according to an eighteenth embodiment of the present invention, the following stack (particularly referred to as a "single-layer stack") is formed on a substrate on which at least one semiconductor pillar is provided. A first isolation layer 102 is formed on the substrate as shown in FIG. 31A to eliminate the influence of uneven shapes at the bases of the semiconductor pillars. The stack includes a lower first sacrificial layer (e.g., reference numeral 104a), a second isolation layer (e.g., reference numeral 106) provided on the lower first sacrificial layer, a second sacrificial layer (e.g., reference numeral 107a) provided on the second isolation layer, a third isolation layer (e.g., reference numeral 109) provided on the second sacrificial layer, an upper first sacrificial layer (e.g., reference numeral 104b) provided on the third isolation layer, and a fourth isolation layer provided on the upper first sacrificial layer. Referring now to FIGS. 31B and 31C, the first sacrificial layers 104a and 104b are configured as a pair that surround the semiconductor pillar 101 and are spaced apart in the axial direction. The second sacrificial layer 107a surrounds the semiconductor pillar 101 and is provided so as not to overlap the first sacrificial layers 104a and 104b in a plan view. The second sacrificial layer 107 (107a) is sandwiched vertically between a second isolation layer 106 and a third isolation layer 109. As shown in FIG. 31B, the second isolation layer 106 contacts one first sacrificial layer 104a at the bottom and the second sacrificial layer 107a at the top. The isolation layer 109 contacts the second sacrificial layer 107a at the bottom and the other first sacrificial layer 104b at the top.

[0159] Next, first through-holes 121 are formed in the layer 110 to reach the first sacrificial layer 104a, which is located closest to the substrate. For example, as shown in FIG. 31D, first through-holes 121 are formed in the stack 100, penetrating the paired first sacrificial layers 104a, 104b, 114a, and 114b. As shown in FIG. 31E, the paired first sacrificial layers 104a, 104b, 114a, and 114b are etched and removed via the first through-holes 121. This exposes the portions of the semiconductor pillar 101 that were surrounded by the paired first sacrificial layers 104a, 104b, 114a, and 114b. As shown in FIG. 31F, conductive layers 122 for forming source and drain electrodes are simultaneously deposited to surround the exposed portions. The first through-holes 121 may be holes that reach the first sacrificial layers 104a, 104b, 114a, and 114b.

[0160] Around the same time, a second through-hole 126 is formed in the layer 110 as a second hole, reaching the second sacrificial layer 107a located closest to the substrate. For example, as shown in FIG. 31I, a second through-hole 126 is formed in the stack 100, penetrating the second sacrificial layers 107a and 117a. As shown in FIG. 31J, the second sacrificial layers 107a and 117a are etched and removed via the second through-hole 126. This exposes the portion of the semiconductor pillar 101 that was surrounded by the second sacrificial layers 107a and 117a. The second through-hole 126 may be any hole that reaches the second sacrificial layers 107a and 117a. As shown in FIG. 31K, an insulating layer is deposited to surround the exposed portion, forming a gate insulating layer 127. Next, a conductive layer 128 is deposited to surround the gate insulating layer 127, forming a gate electrode.

[0161] In this manner, the gate insulating layer 127 and the gate electrode are formed. Because the semiconductor pillar 101 has not been cleaned prior to this formation process, the diameter of the semiconductor pillar 101 does not vary along the axial direction of the semiconductor pillar 101. Therefore, the dimensions of the channel that can be formed in the semiconductor pillar 101 do not depend on the axial direction of the semiconductor pillar 101.

[0162] To fabricate multiple stacked GAA-MOSFETs, the aforementioned single-layer stack is stacked vertically in multiple layers, with the first and second through-holes formed so as to penetrate each layer of the stack vertically. This allows for the formation of multiple vertically stacked GAA-MOSFETs. Furthermore, when fabricating multiple stacked GAA-MOSFETs, multiple source and drain electrodes can be fabricated simultaneously without the need for additional processes for the number of layers. This not only reduces the number of fabrication steps, but also allows the source and drain electrodes of each GAA-MOSFET to be fabricated with the same shape and dimensions, and their characteristics do not differ between adjacent GAA-MOSFETs. For example, multiple PMOSs fabricated on a single semiconductor pillar can be evaluated as having the same threshold voltage. Multiple NMOSs fabricated on a single semiconductor pillar can also be evaluated as having the same threshold voltage.

[0163] Each first sacrificial layer is formed by depositing a selectively etchable material and then patterning it. The same applies to the second sacrificial layer. The first and second sacrificial layers can both be made of SiN nitride, and in this case, the first, second, and third isolation layers can be made of SiO2 oxide. Depending on the etching solution, the oxygen and nitrogen compositions of the oxide and nitride films, as well as the oxynitride film, can be adjusted. This allows the areas to be etched to be limited.

[0164] By employing the basic configuration of the eighteenth embodiment of the present invention, it is possible to fabricate the semiconductor devices and integrated circuits according to the first to seventeenth embodiments. In particular, by arranging vertical GAA-FETs in a matrix pattern in the front-to-back and left-to-right directions in a plan view and arranging vertical GAA-FETs at least above or below each of the vertical GAA-FETs, an integrated circuit having a three-dimensional structure in which FETs are arranged three-dimensionally can be formed.

[0165] [19th embodiment] A method for fabricating a DRAM as an integrated circuit according to a 19th embodiment of the present invention will be described. In a DRAM, one memory cell is configured by connecting a GAA-MOSFET as a field-effect transistor and a capacitor. The method for fabricating a GAA-MOSFET has already been described, and the method for fabricating a semiconductor device according to the 18th embodiment can be used. For a capacitor, in the method for fabricating a semiconductor device according to the 18th embodiment, the dimensions of the pair of first sacrificial layers in plan view are simply lengthened by the length of the capacitor electrode and the connection electrode. Several methods applicable to fabricating DRAMs will be described in detail below.

[0166] 32A to 32Q and 33A to 33M are cross-sectional views showing each process in a method for fabricating a DRAM as an integrated circuit according to the 19th embodiment of the present invention. The processes proceed in the order of the alphabet attached to the figure numbers. First, a substrate 131 on which semiconductor pillars 101 are provided is prepared. Then, a stacked body 151 having a basic configuration including a first isolation layer 132, one of a pair of a first sacrificial layer 133 and a first insulating layer 134, a second isolation layer 135, a second sacrificial layer 136 and a second insulating layer 137, a third isolation layer 138, and the other of the pair of a first sacrificial layer 139 and a third insulating layer 140 is formed on the substrate 131. 32A , a fourth isolation layer 141 is formed on the other first sacrificial layer 139 and third insulating layer 140 of the pair, and then the first sacrificial layer 142 and first insulating layer 143 of the pair, the fifth isolation layer 144, the second sacrificial layer 145 and second insulating layer 146, the sixth isolation layer 147, the other first sacrificial layer 148 and third insulating layer 149 of the pair, and the seventh isolation layer 150 are stacked on the fourth isolation layer 141 in this order to form a stacked body 151. The first sacrificial layers 133, 142 and first insulating layers 134, 143 of the pair, the second sacrificial layers 136, 145 and second insulating layers 137, 146, and the other first sacrificial layers 139, 148 and third insulating layers 140, 149 of the pair are patterned. In this way, a patterned multilayer is formed on the substrate 131 on which the semiconductor pillars 101 are provided (FIG. 32A). For a detailed description, refer to the 18th embodiment. Note that the semiconductor pillars 101 may be formed after the formation of the stack.

[0167] Next, through-holes 152 are formed as holes penetrating the paired first sacrificial layers 133, 139, 142, and 148 between the MOSFET formation region and the capacitor formation region to reach the surface of the substrate 131 (FIG. 32B), and insulating layers 153 are formed as separation layers in the through-holes 152 (FIG. 32C). Note that the through-holes 152 may be holes that reach the first sacrificial layers 133, 139, 142, and 148. Next, through-holes 154 are formed in the insulating layer 153 as separation layers to reach the substrate 131 adjacent to the paired first sacrificial layers 133, 139, 142, and 148 on the capacitor formation region side of the insulating layer 153 (FIG. 32D), and the paired first sacrificial layers 133, 139, 142, and 148 in the capacitor formation region are etched and removed using the through-holes 154 (FIG. 32E). It is sufficient that the through-holes 154 reach the first sacrificial layers 133, 139, 142, and 148. Next, a conductive layer 155 such as a metal layer is formed on the etched portions 133a, 139a, 142a, and 148a of the first sacrificial layer and on the through-holes 154 (FIG. 32F). Then, the portions of the conductive layer 155 that block the through-holes 154 are removed down to the portion that reaches the substrate 131 (FIG. 32G). An insulator is deposited on the removed portions, indicated by the reference numeral 154, and integrated with the insulating layer 153 of FIG. 32E to form an insulating layer 156, thereby forming a plurality of capacitor electrodes from the conductive layer 155 (FIG. 32H).

[0168] Next, as in the eighteenth embodiment, the source electrode 158 and the drain electrode 157 of the MOSFET are simultaneously formed, and the gate insulating layer 159 and the gate electrode 160 are also formed (FIG. 32I). The simultaneous formation of the source electrode 158 and the drain electrode 157 and the formation of the gate insulating layer 159 and the gate electrode 160 can be performed in any order.

[0169] Next, insulating layer 156 produced in the step of Fig. 32I is removed by etching, and hole 162 is opened so as to reach substrate 131. Thereafter, first isolation layer 161 is formed directly on substrate 131 (Fig. 32J). Then, conductive layer 163 such as a metal layer is deposited in hole 162 on first isolation layer 161 (Fig. 32K), and conductive layer 163 is etched to the same thickness as bottom-most source electrode (or drain electrode) 158 and conductive layer 155 to form connection electrode 165 (Fig. 32L).

[0170] Next, an insulating layer 166 is formed in the hole 164 above the connecting electrode 165 formed by the process shown in FIG. 32L to connect the capacitor formation region and the MOSFET formation region (FIG. 32M). The insulating layer 166 is then removed by etching down to the bottom end of the connecting electrode 170 to be formed next, forming a part of the isolation layer (lower part of the isolation layer) 168 (FIG. 32N). A conductive layer 169 such as a metal layer is then deposited on the part of the isolation layer 168 (FIG. 32O), and the conductive layer 169 is etched to the same thickness as the second-stage source electrode (or drain electrode) 158 and the conductive layer 155 to form the connecting electrode 170 (FIG. 32P). After that, an insulating layer 172 is formed in the hole 171 above the connecting electrode 170 to form a part of the isolation layer (upper part of the isolation layer) (FIG. 32Q).

[0171] Through the above series of processes, the MOSFET and capacitor are wired and connected within the cell.

[0172] Next, an electrode via is formed to ground one of the pair of capacitor electrodes. This process is, for example, as follows: In the state shown in Fig. 33A, a hole 180 is formed in the area where the electrode via is to be formed, leaving one first isolation layer 132 on the substrate 131 (Fig. 33B). An insulating layer 181 is deposited on the first isolation layer 132 (Fig. 33C), and the insulating layer 181 is etched to form a hole 183 so that it is flush with the first-stage drain electrode (or source electrode) 157 and conductive layer 155 that are not connected to the connecting electrode 165, thereby forming a base 182 of the via connecting wiring (Fig. 33D).

[0173] Next, a conductive layer 184 such as a metal layer is deposited on the base 182 formed by the process shown in Fig. 33D (Fig. 33E), and the conductive layer 184 is etched to the same thickness as the drain electrode (or source electrode) 157 and the conductive layer 155, thereby forming a via connection wiring 185 (Fig. 33F). An insulating layer 187 is deposited in a hole 186 on the via connection wiring 185 (Fig. 33G), and the insulating layer 187 is etched to form a hole 189 so that the insulating layer 187 is flush with the second-stage drain electrode (or source electrode) 157 and the conductive layer 155 that are not connected to the connection electrode 170, thereby forming a base 188 of the via connection wiring (Fig. 33H). A conductive layer such as a metal layer is deposited on the base 188 formed by the process shown in Figure 33H, and the conductive layer is etched to the same thickness as the drain electrode (or source electrode) 157 and the conductive layer 155 to form via connection wiring 190, and an insulating layer 191 is deposited in the hole above the via connection wiring 190 (Figure 33I).

[0174] Next, holes are made by etching so as to reach the first-stage via connection wiring 185, and electrode vias 193 are formed to connect to the via connection wirings 185 and 190. An insulating layer 192 is formed on the electrode vias 193 to insulate them from the surrounding area (FIG. 33J). The electrode vias 193 are connected to, for example, ground when in use.

[0175] The formation of electrode via wiring to the gate electrode will now be described. A hole 194 is drilled in the upper gate electrode layer, isolation layer, and insulating film so as to reach the lowest gate electrode 160 (FIG. 33K). An electrode via 195a is formed so as to reach the lowest gate electrode 160, and a necessary portion around the electrode via 195a is surrounded by an insulating layer 196 (FIG. 33L). Next, a hole is drilled in the isolation layer 147, insulating layer 149, and isolation layer 150 so as to reach the gate electrode 160 above the gate electrode 160 reached by the electrode via 195a, and an electrode via 195b is formed. The electrode via 195b is surrounded by an insulating layer as necessary (FIG. 33M).

[0176] The formation of electrode via wiring to the source electrode 158 and the drain electrode 157 will be described. FIGS. 34A to 34F are cross-sectional views along line XX in FIG. 33M for each step in a method for fabricating a DRAM as an integrated circuit according to the 19th embodiment of the present invention. The steps proceed in alphabetical order. In FIG. 34A, a hole 197 is drilled in the conductive layer, isolation layer, and insulating film so as to reach the lowest drain electrode (or source electrode) 157 that is not connected to the conductive layer 155 (FIG. 34B). Next, a hole 198 is drilled in the isolation layer 150 so as to reach the drain electrode (or source electrode) 157 in the upper layer that is not connected to the conductive layer 155 (FIG. 34C). At this time, the two holes may be integrated. Next, an insulating layer 199 is formed in the drilled holes 197 and 198 (FIG. 34D).

[0177] Holes 200 and 201 are formed separately in insulating layer 199 by etching to respective depths that reach conductive layer 157 to which the electrode vias are to be connected (FIG. 34E). Then, conductive layers 202 and 203 such as metal layers are formed in holes 200 and 201, thereby forming electrode vias (FIG. 34F).

[0178] By this series of steps, wiring to the memory cells of the DRAM is formed. The electrode vias to the gate electrode 160 and the electrode vias to the source electrode 158 may be formed by other methods.

[0179] Furthermore, electrode vias may be formed so as to share electrode vias connected to conductive layers 155 that serve as electrodes for a plurality of capacitors.

[0180] The method of forming electrode vias in the gate electrodes, source electrodes, and drain electrodes of a plurality of GAA-MOSFETs is not limited to the above-mentioned method, and can be applied not only to the fabrication of DRAM but also to the fabrication of SRAM.

[0181] [Twentieth embodiment] A method for fabricating a DRAM as an integrated circuit according to the 20th embodiment of the present invention will be described. The 20th embodiment will be described in particular for the case of manufacturing a DRAM like the 13th embodiment. Figures 35A to 35G are cross-sectional views of each process in the method for fabricating a DRAM as an integrated circuit according to the 20th embodiment of the present invention. The processes proceed in alphabetical order attached to the figure numbers.

[0182] First, a substrate 131 on which a semiconductor pillar 101 is erected is prepared, and a laminate having a basic structure consisting of a first isolation layer 132, one of a pair of a first sacrificial layer 133 and a first insulating layer 134, a second isolation layer 135, a second sacrificial layer 136 and a second insulating layer 137, a third isolation layer 138, and the other of the pair of a first sacrificial layer 139 and a third insulating layer 140 is formed on the substrate 131. 35A , a fourth isolation layer 141 is formed on the other first sacrificial layer 139 and third insulating layer 140 of the pair, and then the first sacrificial layer 142 and first insulating layer 143 of the pair, the fifth isolation layer 144, the second sacrificial layer 145 and second insulating layer 146, the sixth isolation layer 147, the other first sacrificial layer 148 and third insulating layer 149 of the pair, and a seventh isolation layer (not shown) are stacked in this order on the fourth isolation layer 141 to form a stacked body 151. The first sacrificial layers 133, 142 and first insulating layers 134, 143 of the pair, the second sacrificial layers 136, 145 and second insulating layers 137, 146, and the other first sacrificial layers 139, 148 and third insulating layers 140, 149 of the pair are patterned. At this time, the other (or one) of the pair of first sacrificial layers 139, 148 is provided only in the GAA-MOSFET formation region, not in the capacitor formation region, and third insulating layers 140, 149 are provided. Details of this process will be readily apparent to those skilled in the art if some of the processes described in this specification are reused. In this manner, a patterned multilayer is formed on the substrate 131 on which the semiconductor pillars 101 are provided (FIG. 35A). For a detailed description, see the 18th embodiment. Alternatively, the semiconductor pillars 101 may be formed after the formation of the stack.

[0183] Also, as shown in FIG. 35A, a first isolation layer 210 is provided to separate the GAA-MOSFET formation region from the capacitor formation region, and a second isolation layer 211 is provided at a position facing the first isolation layer 210 in the capacitor formation region in the cross-sectional view.

[0184] Next, as shown in Figure 35B, in the capacitor formation region, a hole 212 is opened near the second isolation layer 211 of the first isolation layer 210, penetrating the first isolation layer 132, one of the first sacrificial layers 133, the second isolation layer 135, the second insulating layer 137, the third isolation layer 138, the third insulating layer 140, the fourth isolation layer 141, one of the first sacrificial layers 142, the fifth isolation layer 144, the second insulating layer 146, the sixth isolation layer 147, and the third insulating layer 149. As shown in Figure 35C, the SiN serving as the first sacrificial layers 133 and 142 is etched, and the etched portion 213 is connected to the hole 212.

[0185] Next, as shown in Fig. 35D, a conductive layer such as a metal layer is deposited by ALD or the like on hole 212 and the upper surface of first isolation layer 132 exposed by etching, the lower surface of second isolation layer 135, the side surface of first isolation layer 210, the upper surface of fourth isolation layer 141, the lower surface of fifth isolation layer 144, and the like, to form a pair of upper and lower capacitor electrodes 214. Thereafter, as shown in Fig. 35E, layer 215 is formed to be sandwiched between the pair of upper and lower capacitor electrodes 214. At this time, a layer is also deposited in the through hole 212 as shown in Fig. 35B.

[0186] Next, the conductive layer formed on the side surface of the through hole 212 and the deposits therebetween are removed by etching, and the upper and lower insulating and isolating layers are also removed together with part of the second isolation layer 211, as shown in Fig. 35F. Then, the hole 216 formed by the removal is filled with an insulator 217, and as shown in Fig. 35G, a capacitor formation region and a GAA-MOSFET formation region are being formed separately.

[0187] Thereafter, the GAA-MOS is formed in the same manner as in the eighteenth embodiment, and one of the paired capacitor electrodes and the source electrode (or drain electrode) present on the same surface are wired in the cell using a connection electrode.

[0188] Then, a common electrode via may be provided for the other capacitor electrode of the pair.

[0189] [Twenty-first embodiment] The 21st embodiment of the present invention is similar to the 20th embodiment in that one of the paired first sacrificial layers in the 20th embodiment serves as a similar first sacrificial layer in the second isolation layer and the fifth isolation layer immediately above it. Figures 36A and 36B are diagrams showing part of a manufacturing process of a DRAM according to the 21st embodiment of the present invention.

[0190] One of the pair of first sacrificial layers 133, 142 shown in Figure 32A is patterned as shown in Figure 36A so that the second isolation layer 135 and fifth isolation layer 144 directly above it also become similar first sacrificial layers.

[0191] Then, by going through the process described in the 20th embodiment, a pair of capacitor electrodes 214 and a layer 215 sandwiched between them are provided in the capacitor formation region as shown in Figure 36B, and in cross-sectional view, both are sandwiched between a first separation layer 210 and a second separation layer 211 on the left and right.

[0192] In the 21st embodiment, unlike the 20th embodiment, the thickness of the capacitor electrodes 214 is thin, and the layer 215 sandwiched between the pair of capacitor electrodes 214 is not formed as part of the original laminate 151, thereby improving design freedom.

[0193] Using this method, a ferroelectric random access memory (FeRAM) element, a phase change memory (PCM) element, or a resistive random access memory (ReRAM) element can be fabricated by interposing a ferroelectric layer, a phase change layer, or a resistive random access memory (ReRAM) layer between a pair of capacitor electrodes 214 instead of layer 215. In this case, this method can be applied to integrated circuits in which memory cells are stacked in one, two, three, or more stages.

[0194] [Twenty-second embodiment] The method for fabricating a DRAM as an integrated circuit according to the 22nd embodiment of the present invention is a method for fabricating a DRAM (the 14th embodiment, FIG. 23) in which a capacitor electrode has a U-shaped cross section. Figures 37A to 37E are cross-sectional views of each process in the method for fabricating a DRAM according to the 22nd embodiment of the present invention. The processes proceed in alphabetical order attached to the figure numbers.

[0195] In the 22nd embodiment of the present invention, in the capacitor formation region of the 20th embodiment, the second isolation layer 135 and the fifth isolation layer 144 directly above the pair of first sacrificial layers 133 and 142 are similarly formed as first sacrificial layers, and the second insulating layers 137 and 146 directly above these layers are also similarly formed as first sacrificial layers. In other words, as shown in FIG. 37A , the first sacrificial layers 133 and 142 that replace the capacitor are thicker. Correspondingly, the other pair of first sacrificial layers 139 and 148 are provided only in the GAA-MOSFET formation region, not in the capacitor formation region. Those skilled in the art will readily understand this detail by partially utilizing the processes described in this specification.

[0196] As shown in FIG. 37A, a first isolation layer 210 is provided to separate the GAA-MOSFET formation region from the capacitor formation region, and a second isolation layer 211 is provided at a position facing the first isolation layer 210 in the capacitor formation region in the cross-sectional view.

[0197] Next, as shown in Figure 37B, in the capacitor formation region, a hole 220 is drilled in the first isolation layer 210 near the second isolation layer 211, down to the substrate 131, and as shown in Figure 37C, the SiN serving as the first sacrificial layers 133, 142 is etched to connect to the hole 220.

[0198] Next, as shown in FIG. 37D , a conductive layer 222 is deposited by ALD or the like on the through-hole 220 and the etched exposed portions of the top surface of the first isolation layer 132, the bottom surface of the third isolation layer 138, the top surface of the fourth isolation layer 141, the bottom surface of the sixth isolation layer 147, and the side surface of the second isolation layer 211, to form one of the pair of capacitor electrodes. In the region of the hole 220 and the exposed portions, an insulating layer 223 is formed either above or below the one of the pair of capacitor electrodes. Furthermore, a conductive layer 224, which will become the other of the pair of capacitor electrodes, is formed either above or below the insulating layer 223. Each of these layers is formed by adjusting the deposition time and supply amount using ALD or the like. Note that the insulating layer 223 can also be called a dielectric layer because it is sandwiched between the pair of capacitor electrodes.

[0199] Next, as shown in FIG. 37D, an insulating material is deposited in the remaining holes by ALD or the like to form isolation layer 225.

[0200] Then, holes are drilled to expose the side surfaces of first isolation layer 210 and insulating layer 223. As a result, one or more pairs of opposing capacitor electrodes and upper and lower isolation layers 226 sandwiched therebetween are formed by conductive layer 222 on the first isolation layer 132 side and conductive layer 222 on the third isolation layer 138 side, and conductive layer 222 on the fourth isolation layer 141 side and conductive layer 222 on the sixth isolation layer 147 side.

[0201] 37E, the holes are filled with an insulator to recreate first separation layer 227. Thereafter, as already described, the capacitor electrodes and source electrodes (or drain electrodes) are wired within the cell using connection electrodes, and vias for connection to the outside are provided.

[0202] [Twenty-third embodiment] A method for fabricating a DRAM as an integrated circuit according to the 23rd embodiment of the present invention is a method for fabricating a DRAM configured such that either one of the source and drain electrodes 21 of a lower GAA MOSFET 61a that is not connected to a capacitor electrode, and either one of the source and drain electrodes 21 of an upper GAA MOSFET 61b that is not connected to a capacitor electrode, are connected to a common bit line by a wiring portion 29a, as shown in Fig. 26. Figs. 38A to 38H are diagrams sequentially showing part of the manufacturing process of a DRAM as an integrated circuit 3 according to the 23rd embodiment of the present invention.

[0203] As shown in FIG. 38A, a GAA MOSFET 230 and a capacitor 231 are fabricated and separated by an isolation layer 232. Then, as shown in FIG. 38B, the isolation layer 232 is removed by etching, exposing only the first isolation layer 132 directly above the substrate 131. Next, as shown in FIG. 38C, a wiring electrode 233 is formed to connect the source electrode (or drain electrode) of the bottom-most GAA MOSFET to the capacitor electrode. Next, as shown in FIG. 38D, the drain electrode (or source electrode) of the first-stage GAA MOSFET and the source electrode (or drain electrode) of the second-stage GAA MOSFET are connected by a conductive layer 234 such as a metal layer, and an insulator is deposited on the remaining portion to form an isolation layer 235. This conductive layer 234 is connected to a bit line or bit bar line. Next, as shown in FIG. 38E, a connection electrode 236 is formed to connect the drain electrode (or source electrode) of the second-stage GAA MOSFET to the capacitor electrode located at the same height. Thereafter, as shown in Figures 38F and 38G, holes 237 are drilled and filled with insulator 238, and then holes are drilled to form electrode vias 239 for the gate electrodes, and as shown in Figure 38H, connection portions 240 of the electrode vias to the bit lines are formed at positions around the page.

[0204] By including these steps, memory cells of a DRAM are formed.

[0205] [Twenty-fourth embodiment] The 24th embodiment of the present invention relates to a basic manufacturing method used when manufacturing a semiconductor device or integrated circuit including a CMOS circuit according to the third to eleventh embodiments of the present invention. Figures 40A to 40W are cross-sectional views of each process in the manufacturing method of a CMOS circuit according to the 24th embodiment of the present invention. The processes progress in alphabetical order attached to the figure numbers.

[0206] A method for fabricating a CMOS circuit according to the 24th embodiment of the present invention will be described in detail. First, a substrate 400 such as a Si substrate is prepared, and semiconductor pillars 401a and 401b are erected on the substrate 400 (FIG. 40A). One corresponds to a P-type semiconductor pillar, and the other corresponds to an N-type semiconductor pillar. A substrate on which the semiconductor pillars 401a and 401b are erected may be prepared. As a result, the semiconductor pillars 401a and 401b are formed in the axial direction so that they are spaced apart in a plan view.

[0207] 40B, an SiO film is deposited on substrate 400 as isolation layer 402, and an SiN film is deposited on isolation layer 402 as film 403, which will be one of the pair of first sacrificial layers. Then, photolithography patterning and selective etching techniques are used to form one of the pair of first sacrificial layers 403a. At this time, isolation layer 402 and one of the pair of first sacrificial layers 403a are formed so as to surround semiconductor pillars 401a and 401b.

[0208] 40C, SiO2 is formed as a first insulating layer 403b having the same thickness as one of the sacrificial layers 403a on the partially exposed first isolation layer 402. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0209] Next, an SiO film serving as second isolation layer 404 is deposited on first sacrificial layer 403a and first insulating layer 403b (FIG. 40D), and an SiN film serving as the second sacrificial layer is deposited on second isolation layer 404. Photolithographic patterning and selective etching techniques are used to form second sacrificial layer 405. At this time, second sacrificial layer 405 is formed so as to surround semiconductor pillars 401a and 401b. The film serving as second sacrificial layer 405 is deposited so as to overlap first sacrificial layer 403a around semiconductor pillar 401a and first sacrificial layer 403a around semiconductor pillar 401b in a plan view, but not overlap with each other in other portions.

[0210] On the partially exposed second isolation layer 404, SiO2 is formed as a second insulating layer 406 having the same thickness as the second sacrificial layer 405. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0211] Next, an SiO2 film is deposited on the second sacrificial layer 405 and the second insulating layer 406 as a third isolation layer 407, and an SiN film is deposited on the third isolation layer 407 as a film that will become the other pair of first sacrificial layer, and photolithographic patterning and selective etching techniques are used to form the other pair of first sacrificial layer 408. At this time, the third isolation layer 407 and the other pair of first sacrificial layer 408 are formed so as to surround the semiconductor pillars 401a and 401b, respectively.

[0212] On the partially exposed third isolation layer 407, SiO2 is formed as a third insulating layer 409 having the same thickness as the other first sacrificial layer 408. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0213] Through this series of steps, isolation layer 402, one first sacrificial layer 403a and insulating layer 403b, isolation layer 404, second sacrificial layer 405 and insulating layer 406, isolation layer 407, the other first sacrificial layer 408 and insulating layer 409 are stacked in this order, and an SiO2 film is deposited as uppermost isolation layer 410 to surround semiconductor pillars 401a and 401b, thereby preparing a stacked body for manufacturing two GAA-MOSFETs using at least two semiconductor pillars 401a and 401b that are separated in plan view. This state is shown in Figure 40E.

[0214] To fabricate multiple GAA-MOSFETs by stacking multiple stacks, simply stack the corresponding number of stacks. After stacking, a SiO2 film is deposited as the top isolation layer. In the integrated stack, the isolation layer that vertically isolates the stacks can be made thicker to structurally separate the upper and lower GAA-MOSFETs. The following explanation focuses on a single-level stack, but stacks with two or more levels can be fabricated in a similar manner or with necessary modifications.

[0215] Next, as shown in FIG. 40F, two first through holes 411a and 411b are formed in the laminate as first holes, reaching the first sacrificial layer 403a. The first through holes 411a and 411b pass through the isolation layer 410, the insulating layer 409, the isolation layer 407, the insulating layer 406, and the isolation layer 404 to reach the first sacrificial layer 403a. Next, as shown in FIG. 40G, the first sacrificial layer 403a is removed by wet etching via the first through holes 411a and 411b, and the removed portions are connected to the corresponding first through holes 411a and 411b. Here, the first through holes 411a and 411b are not connected to each other due to the insulating layer 403b. As shown in FIG. 40H, a conductive layer 412 such as a metal layer is formed in the removed portion of the first sacrificial layer and in the first through-holes 411a and 411b. A CVD method or the like is used for this. This simultaneously forms adjacent source electrodes separated by an insulating layer 403b. Next, as shown in FIG. 40I, the conductive layer 412 in the first through-holes 411a and 411b is removed to form holes 413a and 413b. As shown in FIG. 40J, the holes 413a and 413b are filled with insulators 414a and 414b. Source electrodes 412a and 412b are provided separately on the same surface of the first isolation layer 402, separated by an insulating layer 403b.

[0216] Next, as shown in FIG. 40K, a second through-hole 415 is formed in the isolation layer 410 so as to reach the other pair of first sacrificial layers 408. The second through-hole 415 penetrates the isolation layer 410 and reaches the first sacrificial layer 408. Next, as shown in FIG. 40L, the other first sacrificial layer 408 is removed by wet etching via the second through-hole 415. As shown in FIG. 40M, a conductive layer 416 such as a metal layer is formed in the portion from which the other first sacrificial layer 408 has been removed and in the second through-hole 415. This may be achieved by a CVD method or the like. Next, as shown in FIG. 40N, the conductive layer in the second through-hole 415 is removed to form a hole 417, and as shown in FIG. 40O, the hole 417 is filled with an insulator 417a. In this manner, the conductive layer 416a is simultaneously formed, including the portion connecting the drain electrode to the semiconductor pillar 401a and the drain electrode to the semiconductor pillar 401b.

[0217] Next, as shown in FIG. 40P, a third through-hole 418 is formed in the isolation layer 410, the insulating layer 409, and the isolation layer 407, reaching the second sacrificial layer 405. The third through-hole 418 penetrates the isolation layer 410, the insulating layer 409, and the isolation layer 407 to reach the second sacrificial layer 405. Next, as shown in FIG. 40Q, the second sacrificial layer 405 is removed by wet etching via the third through-hole 418. This exposes portions of the semiconductor pillars 401a and 401b, and an insulating layer 419 that will serve as a gate insulating layer is deposited on the exposed portions. For this purpose, an ALD method or the like is used, and the insulating layer 419 is sufficiently thinner than the second sacrificial layer 405. Next, as shown in FIG. 40S, a conductive layer 420, such as a metal layer, is formed on the insulating layer 419 to fill the second through-hole 418. This simultaneously forms portions that will become gate electrodes for two semiconductor pillars 401a and 401b. Next, as shown in FIG. 40T, conductive layer 420 in third through-hole 418 is removed to form hole 421, and insulator 422 is deposited in hole 421 as shown in FIG. 40U. In this series of steps, two gate insulating layers formed from parts of insulating layer 419 and two gate electrodes 420a are simultaneously formed in order.

[0218] As shown in Fig. 40V, holes are drilled to reach source electrodes 412a and 412b, respectively, and wiring is achieved by connecting through electrode vias 423a and 423b corresponding to the holes. Around the same time, as shown in Fig. 40W, holes are drilled to reach conductive layer 416a, which will become the drain electrode, and gate electrode 420a, respectively, and wiring is achieved by connecting through electrode vias 424 and 425 corresponding to the holes.

[0219] By going through the above series of steps, a CMOS circuit can be fabricated in which PMOS and NMOS transistors arranged at the same height are connected. The order of fabricating the source electrode, drain electrode, gate insulating film, and gate electrode does not matter. Although the semiconductor pillars 401a and 401b are erected on the substrate 400 to form a stacked body, it is also possible to form the stacked body on the substrate, and then drill holes in the formation regions for the semiconductor pillars 401a and 401b, and then deposit the semiconductor pillar material in the holes. A substrate 400 is prepared having a laminate including semiconductor pillars 401a and 401b that can be formed in the axial direction so that the P-type semiconductor pillar 401a and the N-type semiconductor pillar 401b are spaced apart in a planar view, at least one pair of first sacrificial layers 403a and 408 that surround the semiconductor pillars 401a and 401b, respectively, and are spaced apart in the axial direction, and a second sacrificial layer 405 that is provided so as not to partially overlap the first sacrificial layers 403a and 408 in a planar view at a height between one first sacrificial layer 403a and the other first sacrificial layer 408 that can surround the semiconductor pillars 401a and 401b, respectively, and that constitute the pair. A through-hole 418 is formed in the stack as a hole reaching the second sacrificial layer 405, and the second sacrificial layer 405 is removed. An insulating layer 419 serving as a gate insulating layer is simultaneously formed so as to surround the respective regions of the semiconductor pillar 401a and the semiconductor pillar 401b thereby exposed. A conductive layer 420 serving as a gate electrode 420a is simultaneously deposited so as to surround the gate insulating layer. While the manufacturing method in which a source electrode is provided between the isolation layer 402 and the isolation layer 404 and a drain electrode is provided between the isolation layer 407 and the isolation layer 410 has been described above, it is possible to provide a drain electrode between the isolation layer 402 and the isolation layer 404 and a source electrode between the isolation layer 407 and the isolation layer 410 by patterning a film provided between the isolation layer 407 and the isolation layer 410 without patterning the film 403.

[0220] [Twenty-fifth embodiment] The 25th embodiment of the present invention relates to a basic manufacturing method used when manufacturing the semiconductor device or integrated circuit including a CMOS circuit according to the third to eleventh embodiments of the present invention. Figures 41A to 41V are cross-sectional views of each process in the manufacturing method of a CMOS circuit according to the 25th embodiment of the present invention. The processes proceed in alphabetical order attached to the figure numbers.

[0221] A method for fabricating a CMOS circuit according to the 25th embodiment of the present invention will be described in detail. First, a substrate 500 such as a Si substrate is prepared, and semiconductor pillars 501a and 501b are erected on the substrate 500 (FIG. 41A). One corresponds to a P-type semiconductor pillar, and the other corresponds to an N-type semiconductor pillar. A substrate on which the semiconductor pillars 501a and 501b are erected may be prepared. As a result, the semiconductor pillars 501a and 501b are formed in the axial direction so that they are spaced apart in a plan view.

[0222] 41B, an SiO film is deposited on the substrate 500 as a first isolation layer 502, and an SiN film is deposited on the isolation layer 502 as a film 503 that will become a pair of first sacrificial layers. Then, photolithography patterning and selective etching techniques are used to form a pair of first sacrificial layers 503a. At this time, the isolation layer 502 and the pair of first sacrificial layers 503a are formed so as to surround the semiconductor pillars 501a and 501b, respectively.

[0223] 41C, a first insulating layer 503b of SiO2 having the same thickness as the sacrificial layer 503a is formed on the partially exposed first isolation layer 502. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0224] Next, a SiO2 film serving as second isolation layer 504 is deposited on first sacrificial layer 503a and first insulating layer 503b (FIG. 41D), and a SiN film serving as the second sacrificial layer is deposited on second isolation layer 504. Photolithographic patterning and selective etching techniques are used to form a film serving as second sacrificial layer 505a. At this time, the film serving as second sacrificial layer 505a is formed so as to surround semiconductor pillars 501a and 501b. Furthermore, the film serving as second sacrificial layer 505a is deposited so as to overlap the first sacrificial layer 503a and the semiconductor pillar 501a around the first sacrificial layer 503a and the semiconductor pillar 501b ...

[0225] SiO2 is formed as a second insulating layer 506 having the same thickness as the film that will become the second sacrificial layer 505a on the partially exposed second isolation layer 504. It goes without saying that photolithographic patterning and selective etching techniques are used in this process as well.

[0226] Around the same time, an insulating layer 506a for separation is provided between the semiconductor pillars 501a and 501b in the film that will become the second isolation layer 504 and the second sacrificial layer 505a. At this time, portions of the film that will become the second sacrificial layer 505a and the second isolation layer 504 where the insulating layer 506a will be provided are removed. The second sacrificial layers 505a are provided on both sides of the insulating layer 506a. The upper and lower surfaces of the insulating layer 506a protrude from the upper and lower surfaces of the second insulating layer 506 and the second sacrificial layer 505a.

[0227] Next, an SiO2 film is deposited on the second sacrificial layer 505a, the second insulating layer 506, and the separating insulating layer 506a as a third isolation layer 507, and an SiN film is deposited on the third isolation layer 507 as a film to be the other pair of first sacrificial layer, and photolithographic patterning and selective etching techniques are used to form the other pair of first sacrificial layer 508. At this time, the third isolation layer 507 and the other pair of first sacrificial layer 508 are formed so as to surround the semiconductor pillars 501a and 501b, respectively.

[0228] On the partially exposed third isolation layer 507, SiO2 is formed as a third insulating layer 509 having the same thickness as the other first sacrificial layer 508. It goes without saying that photolithographic patterning and selective etching techniques are used in this process.

[0229] Through this series of steps, an isolation layer 502, one first sacrificial layer 503a and insulating layer 503b, isolation layer 504, second sacrificial layer 505a, insulating layer 506 and separating insulating layer 506a, isolation layer 507, and the other first sacrificial layer 508 and insulating layer 509 are stacked in this order, and an SiO2 film is deposited as an uppermost isolation layer 510 to surround semiconductor pillars 501a and 501b, thereby preparing a stacked body for manufacturing two GAA-MOSFETs using at least two semiconductor pillars 501a and 501b that are separated in plan view. This state is shown in Figure 41E.

[0230] To fabricate multiple GAA-MOSFETs by stacking multiple stacks, simply stack the corresponding number of stacks. After stacking, a SiO2 film is deposited as the top isolation layer. In the integrated stack, the isolation layer that vertically isolates the stacks can be made thicker to structurally separate the upper and lower GAA-MOSFETs. The following explanation focuses on a single-level stack, but stacks with two or more levels can be fabricated in a similar manner or with necessary modifications.

[0231] Next, as shown in FIG. 41F, two first through holes 511a and 511b are provided in the laminate as first holes to reach first sacrificial layer 503a. First through holes 511a and 511b as first holes penetrate isolation layer 510, insulating layer 509, isolation layer 507, insulating layer 506, and isolation layer 504 to reach first sacrificial layer 503a. Next, as shown in FIG. 41G, first sacrificial layer 503a is removed by wet etching via first through holes 511a and 511b, and the removed portions are connected to the corresponding first through holes 511a and 511b. Before removing the first sacrificial layer 503a, the insulating layer 503b is adjacent to the first sacrificial layer 503a and exists on the same plane as the first sacrificial layer 503a to separate the first through-holes 511a and 511b. As shown in FIG. 41H, conductive layers 512a and 512b, such as metal layers, are formed in the removed portions of the first sacrificial layer and in the first through-holes 511a and 511b. This process is performed using a CVD method or the like. This allows adjacent source electrodes to be formed simultaneously, separated by the insulating layer 503b. Next, as shown in FIG. 41I, the conductive layers 512a, 512b in the first through holes 511a, 511b are removed to open holes 514a, 514b, thereby simultaneously forming source electrodes 513a, 513b, and as shown in FIG. 41J, the holes 514a, 514b are filled with insulators 515a, 515b.

[0232] Next, as shown in FIG. 41K, two second through-holes 516a and 516b are formed in the isolation layer 510, the insulating layer 509, and the isolation layer 507 to reach the second sacrificial layer 505a. The second through-holes 516a and 516b penetrate the isolation layer 510, the insulating layer 509, and the isolation layer 507 to reach the second sacrificial layer 505a. Next, as shown in FIG. 41L, the second sacrificial layer 505a is removed by wet etching via the second through-holes 516a and 516b. This exposes portions of the semiconductor pillars 501a and 501b. As shown in FIG. 41M, insulating layers 517a and 517b, which will become gate insulating layers, are deposited on the exposed portions using an ALD method or the like, and the thickness of the insulating layers is sufficiently thinner than the thickness of the film that will become the second sacrificial layer 505a. Next, as shown in FIG. 41N, conductive layers 518a and 518b, such as metal layers, are formed on the insulating layers 517a and 517b to fill the second through-holes 516a and 516b. This simultaneously forms gate electrodes for the two semiconductor pillars 501a and 501b. Next, as shown in FIG. 41O, the conductive layers 518a and 518b in the second through-holes 516a and 516b are removed to form holes 520a and 520b. Insulators 521a and 521b are then deposited in the holes 520a and 520b as shown in FIG. 41P. In this series of steps, two gate insulating layers composed of parts of the insulating layers 517a and 517b and two gate electrodes 519a and 519b are simultaneously formed in sequence.

[0233] Around the same time, as shown in FIG. 41Q, a third through-hole 522 is formed in the isolation layer 510 to reach the other first sacrificial layer 508. The third through-hole 522 penetrates the isolation layer 510 and reaches the first sacrificial layer 508. Next, as shown in FIG. 41R, the other first sacrificial layer 508 is removed by wet etching via the third through-hole 522. As shown in FIG. 41S, a conductive layer 523 such as a metal layer is formed in the portion from which the other first sacrificial layer 508 was removed and in the third through-hole 522. This process uses a CVD method or the like. This simultaneously forms drain electrodes for the semiconductor pillars 501a and 501b and a portion connecting the drain electrodes. Next, as shown in FIG. 41T, the conductive layer 523 in the third through-hole 522 is removed to form a hole 524. As shown in FIG. 41U, the hole 524 is filled with an insulating film 525.

[0234] 41V, holes are drilled to reach source electrodes 513a and 513b, respectively, to form electrode vias 526a and 526b, and these are connected to source electrodes 513a and 513b, thereby completing wiring. Around the same time, holes are drilled to reach gate electrodes 519a and 519b, respectively, to form electrode vias 527a and 527b, and these are connected to gate electrodes 519a and 519b, thereby completing wiring. Furthermore, a hole is drilled to reach drain electrode 523a, to form electrode via 528, and this is connected to drain electrode 523a, thereby completing wiring. The order of forming electrode vias 526a and 526b, electrode vias 527a and 527b, and electrode via 528 can be set arbitrarily.

[0235] By going through the above series of steps, a CMOS circuit can be fabricated in which PMOS and NMOS transistors are connected at the same height. The order of fabricating the source electrode, drain electrode, gate insulating film, and gate electrode does not matter. Although the stack is formed by erecting the semiconductor pillars 401a and 401b on the substrate 400, it is also possible to form the stack on the substrate, and then drill holes in the formation regions for the semiconductor pillars 401a and 401b and deposit the semiconductor pillar material in the holes. The semiconductor pillars 501a and 501b can be formed in the axial direction so as to be spaced apart from each other in a planar view. A substrate 500 is prepared having a stack including at least one pair of first sacrificial layers 503a and 508 that surround the semiconductor pillars 501a and 501b, respectively, and are spaced apart from each other in the axial direction. A hole 522 is formed in the isolation layer 510 of the stack so as to reach the first sacrificial layer 508, the first sacrificial layer 508 is removed, and a conductive layer 523 that will become a drain electrode 523a is simultaneously deposited so as to surround the exposed regions of the semiconductor pillars 501a and 501b, thereby simultaneously forming the drain electrodes of the semiconductor pillars 501a and 501b and a portion connecting them. The above describes a manufacturing method in which a source electrode is provided between the isolation layer 502 and the isolation layer 504 and a drain electrode is provided between the isolation layer 507 and the isolation layer 510. However, by patterning a film provided between the isolation layer 507 and the isolation layer 510 without patterning the film 503, a drain electrode can be provided between the isolation layer 502 and the isolation layer 504 and a source electrode can be provided between the isolation layer 507 and the isolation layer 510.

[0236] [Twenty-sixth embodiment] The 26th embodiment of the present invention relates to a basic manufacturing method used when manufacturing the semiconductor device or integrated circuit including a CMOS circuit according to the third to eleventh embodiments of the present invention. Figures 42A to 42V are cross-sectional views of each process in the manufacturing method of a CMOS circuit according to the 26th embodiment of the present invention. The processes progress in alphabetical order attached to the figure numbers.

[0237] A method for fabricating a CMOS circuit according to the 26th embodiment of the present invention will be described in detail. First, a substrate 600 such as a Si substrate is prepared, and semiconductor pillars 601a and 601b are erected on the substrate 600. One corresponds to a P-type semiconductor pillar, and the other corresponds to an N-type semiconductor pillar. A substrate on which the semiconductor pillars 601a and 601b are erected may be prepared. As a result, the semiconductor pillars 601a and 601b are formed in the axial direction so that they are spaced apart in a plan view.

[0238] Next, an SiO2 film is deposited on the substrate 600 as a first isolation layer 602, and an SiN film is deposited on the first isolation layer 602 as a film 603 that will become a pair of first sacrificial layers. Then, using photolithographic patterning and selective etching techniques, a pair of first sacrificial layers 603 is formed. At this time, the first isolation layer 602 and the pair of first sacrificial layers 603 are formed so as to surround the semiconductor pillars 601a and 601b, respectively. Although not shown in FIG. 42A , a SiO2 film is formed as a first insulating layer having the same thickness as the pair of sacrificial layers 603 on the partially exposed first isolation layer 602. It goes without saying that photolithographic patterning and selective etching techniques are also used at this time.

[0239] Next, an SiO2 film serving as a second isolation layer 604 is deposited on the first sacrificial layer 603 and the first insulating layer, and an SiN film serving as a film to be the second sacrificial layer is deposited on the second isolation layer 604. Photolithographic patterning and selective etching techniques are used to form a film to be the second sacrificial layer 605. At this time, the film to be the second sacrificial layer 605 is formed so as to surround the semiconductor pillars 601a and 601b. The film to be the second sacrificial layer 605 is deposited so as to overlap the first sacrificial layer 603 around the semiconductor pillar 601a and the first sacrificial layer 603 around the semiconductor pillar 601b in a plan view, but not overlap each other in other portions.

[0240] On the partially exposed second isolation layer 604, SiO2 is formed as a second insulating layer 606 having the same thickness as the film that will become the second sacrificial layer 605. It goes without saying that photolithographic patterning and selective etching techniques are used in this process as well.

[0241] Next, an SiO2 film is deposited on the second sacrificial layer 605 and the second insulating layer 606 as a third isolation layer 607, and an SiN film is deposited on the third isolation layer 607 as a film to be the other pair of first sacrificial layer 608. The other pair of first sacrificial layer 608 is then formed using photolithographic patterning and selective etching techniques. At this time, the third isolation layer 607 and the other pair of first sacrificial layer 608 are formed so as to surround the semiconductor pillars 601a and 601b, respectively.

[0242] On the partially exposed third isolation layer 607, a third insulating layer 609 made of SiO2 is formed to the same thickness as the other first sacrificial layer 608. It goes without saying that in this case too, photolithographic patterning and selective etching techniques are used.

[0243] Through this series of steps, an isolation layer 602, one first sacrificial layer 603 and insulating layer, isolation layer 604, second sacrificial layer 605 and insulating layer 606, isolation layer 607, the other first sacrificial layer 608 and insulating layer 609 are stacked in this order, and an SiO2 film is deposited as an uppermost isolation layer 610 to surround semiconductor pillars 601a and 601b, thereby preparing a stacked body for manufacturing two GAA-MOSFETs using at least two semiconductor pillars 601a and 601b that are separated in plan view. This state is shown in Figure 42A.

[0244] To fabricate multiple GAA-MOSFETs by stacking multiple stacks, simply stack the corresponding number of stacks. After stacking, a SiO2 film is deposited as the top isolation layer. In the integrated stack, the isolation layer that vertically isolates the stacks can be made thicker to structurally separate the upper and lower GAA-MOSFETs. The following explanation focuses on a single-level stack, but stacks with two or more levels can be fabricated in a similar manner or with necessary modifications.

[0245] Next, as shown in FIG. 42B, two first through holes 611a and 611b are provided as first holes to reach the first sacrificial layer 603. The first through holes 611a and 611b as first holes penetrate the isolation layer 610, the insulating layer 609, the isolation layer 607, the insulating layer 606, and the isolation layer 604 to reach the first sacrificial layer 603. While only one of the first through holes 611a and 611b may be provided, providing two of them allows the first sacrificial layer 603 to be formed more efficiently and / or reliably by subsequent etching. Next, as shown in FIG. 42C, the first sacrificial layer 603 is removed by wet etching via the first through holes 611a and 611b, and the removed portions are connected to the corresponding first through holes 611a and 611b. As shown in FIG. 42D, a conductive layer 612 such as a metal layer is formed in the removed portion of the first sacrificial layer 603 and in the first through-holes 611a and 611b. A CVD method or the like is used for this. This simultaneously forms drain electrodes for the semiconductor pillars 601a and 601b and a portion connecting the drain electrodes. Next, as shown in FIG. 42E, the conductive layer 612 in the first through-holes 611a and 611b is removed to form holes 613a and 613b, thereby simultaneously forming a drain electrode 612a. As shown in FIG. 42F, the holes 613a and 613b are filled with insulators 614a and 614b.

[0246] Next, as shown in FIG. 42G, a second through-hole 615 is formed in the isolation layer 610, the insulating layer 609, and the isolation layer 607, reaching the second sacrificial layer 605. The second through-hole 615 penetrates the isolation layer 610, the insulating layer 609, and the isolation layer 607 to reach the second sacrificial layer 605. Next, as shown in FIG. 42H, the second sacrificial layer 605 is removed by wet etching via the second through-hole 615. This exposes portions of the semiconductor pillars 601a and 601b. As shown in FIG. 42I, an insulating layer 616 that will serve as a gate insulating layer is deposited on the exposed portions using an ALD method or the like, and is sufficiently thinner than the second sacrificial layer 605. Next, as shown in FIG. 42J, a conductive layer 617, such as a metal layer, is formed on the insulating layer 616 to fill the second through-hole 615. This simultaneously forms portions that will become gate electrodes for the two semiconductor pillars 601a and 601b. Next, as shown in FIG. 42K, the conductive layer 617 in the second through-hole 615 is removed to form a hole 618, and as shown in FIG. 42L, an insulator 619 is deposited in the hole 618. In this series of steps, two gate insulating layers formed of parts of the insulating layer 616 and two gate electrodes 617a are simultaneously formed in order.

[0247] Around the same time, as shown in FIG. 42M, a third through-hole 620 is formed in the isolation layer 610 to reach the other first sacrificial layer 608. The third through-hole 620 penetrates the isolation layer 610 and reaches the first sacrificial layer 608. Next, as shown in FIG. 42N, the other first sacrificial layer 608 is removed by wet etching via the third through-hole 620. As shown in FIG. 42O, a conductive layer 621 such as a metal layer is formed in the portion from which the other first sacrificial layer 608 has been removed and in the third through-hole 620. This is done using a CVD method or the like. Next, as shown in FIG. 42P, the conductive layer 621 in the third through-hole 620 is removed to form a hole 622, and a conductive layer 621a is formed. As shown in FIG. 42Q, the hole 622 is filled with an insulator 623.

[0248] Next, the conductive layer 621a is partially removed between the semiconductor pillars 601a and 610b, and in FIG. 42R, the isolation layer 610 and the conductive layer 621a are partially removed between the semiconductor pillars 601a and 610b to form holes 624. This forms source electrodes 621b and 621c that are separate from the semiconductor pillars 601a and 601b. As shown in FIG. 42S, the holes 624 are filled with an insulator 625.

[0249] As shown in Fig. 42T, holes are drilled to reach source electrodes 621b and 621c, respectively, to form electrode vias 626a and 626b, which are then connected to source electrodes 621b and 621c, thereby completing wiring. Around the same time, as shown in Fig. 42U, a hole is drilled to reach drain electrode 612a, to form electrode via 627, which is then connected to drain electrode 612a, thereby completing wiring. Furthermore, as shown in Fig. 42V, a hole is drilled to reach gate electrode 617a, to form electrode via 628, which is then connected to gate electrode 617a, thereby completing wiring. The order in which electrode vias 626a and 626b, electrode via 627, and electrode via 628 are formed can be set arbitrarily.

[0250] By going through the above series of steps, a CMOS circuit can be fabricated in which PMOS and NMOS transistors are connected at the same height. The order of fabricating the source electrode, drain electrode, gate insulating film, and gate electrode does not matter. Although the stack is formed by erecting the semiconductor pillars 601a and 601b on the substrate 600, it is also possible to form the stack on the substrate, and then drill holes in the formation regions for the semiconductor pillars 601a and 601b, and deposit the semiconductor pillar material in the holes. The semiconductor pillars 601a and 601b may be formed axially so as to be spaced apart from each other in a planar view. A substrate is prepared having a stack including the other first sacrificial layer 608 surrounding the semiconductor pillars 601a and 601b and spaced apart from each other in the axial direction. A hole 620 is formed in the stack so as to reach the other first sacrificial layer 608, and the other first sacrificial layer 608 is removed. A conductive layer 621 is deposited so as to surround the exposed regions of the semiconductor pillar 601a and the semiconductor pillar 601b, and then the conductive layer 621a between the semiconductor pillar 601a and the semiconductor pillar 601b is partially removed to separate it into two conductive layers, thereby forming a source electrode 621b for the semiconductor pillar 601a and a source electrode 621c for the semiconductor pillar 601c.

[0251] According to the 26th embodiment, as shown in FIGS. 42Q and 42R, the conductive layer 621a between the semiconductor pillars 601a and 601b is etched from above the isolation layer 610. However, by removing portions of the conductive layer 621a including the top and bottom surfaces from the front-to-back direction relative to the plane of the drawing showing the cross section, the source electrode 621b for the semiconductor pillar 601a may be formed separately from the source electrode 621c for the semiconductor pillar 601b. This is effective when forming a two-stage, three-stage, or more stage FET such as a MOS transistor for each semiconductor pillar. This allows a source electrode to be formed between the isolation layer 602 and the isolation layer 604 and a drain electrode to be formed between the isolation layer 607 and the isolation layer 610, instead of providing a drain electrode between the isolation layer 602 and the isolation layer 604 and a source electrode between the isolation layer 607 and the isolation layer 610.

[0252] In the 24th, 25th, and 26th embodiments of the present invention, the holes provided for etching the first, second, and third sacrificial layers need only reach the first, second, and third sacrificial layers, respectively, and do not need to penetrate through them. This also applies to the semiconductor device and integrated circuit manufacturing methods according to the embodiments of the present invention. Furthermore, in the case of integrated circuits including CMOS circuits, such as those shown in Figures 4, 7, 9, 10, 11, 12, 13, 14, 15, 16 to 19, and 30, the corresponding number and type of semiconductor pillars and a stack formed by patterning the first, second, and insulating layers according to each integrated circuit are prepared on a substrate, and then the corresponding process is carried out. The semiconductor pillars are protected during the process by such a stack, as described in the basic manufacturing method for a semiconductor device using a single semiconductor pillar.

[0253] [Other embodiments] Here, we will explain whether or not to form a junction between the channel forming portion of the semiconductor pillar and the source region / drain region. When the diameter of the semiconductor pillar is 60 nm or less, a junctionless structure is preferable. When the diameter of the semiconductor pillar is 5 nm or more, a junction is preferable. When the semiconductor pillar is 5 nm to 60 nm, either a junction or no junction is adopted depending on the manufacturing process and performance.

[0254] In particular, when the semiconductor pillar is made of Si (silicon), a junctionless structure is preferable when the diameter of the semiconductor pillar is 20 nm or less, and a junction is preferable when the diameter of the semiconductor pillar is 20 nm or more. Note that as the diameter of the semiconductor pillar becomes smaller, it becomes more difficult to form a concentration gradient, so a junctionless structure is preferable.

[0255] When the semiconductor pillar is made of Si (silicon), the impurity concentration of the semiconductor pillar in the junctionless case is 5×10 21atoms / cm 3 It is fine if it is less than 10 19 ~10 21 atoms / cm 3 When the semiconductor pillar is made of another semiconductor material, the impurity concentration of the semiconductor pillar in the junctionless case is higher than the channel concentration of that material when there is a junction, and the upper limit of the concentration is a value at which the material is not conductive.

[0256] In each embodiment of the present invention, in the semiconductor pillar, the source region and drain region formed above and below the part that becomes the channel have a very small diameter, for example, on the order of several tens of nm, and it is therefore not possible to precisely control the gradient of the impurity concentration. For this reason, there is a form in which the source region, drain region, and the part that becomes the channel between them are junctionless. In this form, the semiconductor pillar is p + ,n + is formed as

[0257] Furthermore, when the diameter of the semiconductor pillar is 5 nm or more, the impurity concentration is controlled to form a junction in the channel region and the source and drain regions above and below it, resulting in npn or pnp. This is achieved by protecting the channel region with, for example, SiO2 when forming the semiconductor pillar, and doping the source and drain regions.

[0258] The semiconductor pillar may have any structure as long as a gate insulating layer is provided around a portion of the semiconductor pillar, and a source region and a drain region are provided above and below the gate insulating layer. Such a semiconductor pillar may have a cylindrical shape as well as a columnar shape. This is because a cylindrical semiconductor pillar improves threshold voltage characteristics. When the semiconductor pillar has a cylindrical shape, the inside of the cylinder may be hollow, or the inside of the cylinder may be made of one or more insulators. For example, a core of a conductive material may be surrounded by an insulator, and the cylindrical semiconductor pillar may be provided on the outside of the insulator.

[0259] The various materials are as follows: The substrate can be a Si substrate, for example. The semiconductor pillars are made of Si, preferably either p+ or n+. The next layers that make up the stack are, for example, as follows: The first isolation layer, second isolation layer, and third isolation layer are made of SiO2 or similar. The first sacrificial layer pair and second sacrificial layer are made of SiN or similar. The first insulating layer and second insulating layer are made of SiO2 or similar. The gate insulating layer is made of SiO2 or a high-k material such as HfO2. The gate insulating layer can be a single layer or multiple layers. The source electrode, drain electrode, and gate electrode are made of polysilicon, metals such as Ni and W, graphene, carbon nanotubes, or similar. The via wiring is made of Cu, graphene, carbon nanotubes, or similar. Wet etching is used for etching. Low-k oxide films are used for the isolation and separation layers. The film deposition method, such as ALD or CVD, is used, depending on the situation. If the semiconductor pillars are made of a material other than Si, a suitable material will be selected.

[0260] 1, the inner diameter of either the source region or the drain region (e.g., source region) 6 and the other of the source region or the drain region (e.g., drain region) 7 is determined by the outer diameter of the semiconductor pillar 12, and their height (axial length) is preferably 100 nm or less, and particularly preferably 50 nm or less. The height (axial length) should be at least 2 nm or more.

[0261] In an embodiment of the present invention, multiple FETs are formed at different heights on a single semiconductor pillar. When multiple layers or stages are provided in the vertical direction, the gate length may be different for each FET. This is expected to be useful in applications such as sensor devices. In such cases, the thickness of the second sacrificial layer may be made different for each of the multiple layers or stages.

[0262] When multiple FETs are provided in the vertical direction, it is preferable that the portions surrounded by the source electrodes that define the source and drain regions and the portions surrounded by the drain electrodes are fabricated in multiple identical layers, as described above.

[0263] 7, for example, when fabricating an SRAM, the transistors M1, M2, and M6 may be fabricated, followed by the wiring portion 43, followed by the transistors M3, M4, and M5, followed by the wiring portion 42. When designing the shape of the pattern of the sacrificial layer, the order in which the FETs in each layer are fabricated can be arbitrarily set by ensuring that the holes do not interfere with each other in order to fabricate the FETs in each layer.

[0264] [Effects of the embodiment of the present invention] A semiconductor device according to an embodiment of the present invention includes a semiconductor pillar erected on a substrate, a gate insulating layer provided so as to surround a portion of the semiconductor pillar, a gate electrode provided so as to surround the gate insulating layer, a first electrode which serves as one of a source electrode and a drain electrode and which is provided so as to surround a portion of the semiconductor pillar, and a second electrode which serves as the other of the source electrode and the drain electrode and which is provided so as to surround a portion of the semiconductor pillar and is spaced apart from the first electrode in the vertical direction, sandwiching the gate insulating layer and the gate electrode therebetween.

[0265] The region of the semiconductor pillar between the lower end of the gate insulating layer and the portion surrounded by the first electrode is symmetrical to the region between the upper end of the gate insulating layer and the portion surrounded by the second electrode. In other words, the electrical characteristics of either the source region or the drain region between one end face of a channel that can be formed by being surrounded by the gate insulating layer and the portion surrounded by the first electrode are symmetrical to the electrical characteristics of the other region of the source region or the drain region between the other end face of the channel and the portion surrounded by the second electrode.

[0266] 39 is a diagram for explaining that the electrical characteristics of the semiconductor device according to the embodiment of the present invention are symmetrical. The horizontal axis represents the drain-source voltage VDS and the vertical axis is the drain current I D In the semiconductor device 1 shown in FIG. 1, a gate voltage is applied to the gate electrode 18 so that the gate is turned ON, and a drain-source voltage V DS For the drain current I D flows as shown in the figure. This means that the electrical characteristics of the semiconductor device 1 when the portion of the semiconductor pillar 12 surrounded by the first electrode 14 and the second isolation layer 16 is set as either the source region or the drain region (assuming the source region) and the portion surrounded by the second electrode 21 and the third isolation layer 20 is set as the other region of the source region or the drain region (assuming the drain region) are symmetrical to the electrical characteristics of the semiconductor device when the portion surrounded by the first electrode 14 and the second isolation layer 16 is set as the drain region and the portion surrounded by the second electrode 21 and the third isolation layer 20 is set as the source region. This symmetry is defined as follows. When a gate voltage is applied to the gate electrode 18 so that the gate is turned ON, the drain-source voltage V DS When the value of the first electrode 14 and the second isolation layer 16 is changed, a current I flows from the area surrounded by the first electrode 14 and the second isolation layer 16 to the area surrounded by the second electrode 21 and the third isolation layer 20. D flows, and the curve indicated by the reference numeral 301 in FIG. 39 is drawn, and a certain value of current I D With respect to a certain voltage V 01 At the same time, the same gate voltage is applied to the gate electrode 18, and the drain-source voltage V DS When the value of the second electrode 21 and the third isolation layer 20 is changed, a current I flows from the area surrounded by the second electrode 21 and the third isolation layer 20 to the area surrounded by the first electrode 14 and the second isolation layer 16. D flows, and the curve indicated by the reference numeral 302 in FIG. 39 is drawn, and a certain value of current I D With respect to a certain voltage V 02 is determined. Voltage V 01 and voltage V 02 The magnitude of the voltage V from the average value 01 The magnitude of the voltage V 02 If the deviations (deviations) in the magnitude of the current are within 10%, it is evaluated as "symmetrical" as mentioned above. D However, the gate length L gate / Channel width W x 10-7 The voltage that satisfies [A] is voltage V 01 , voltage V 02 The gate length L gate is the length from one end face to the other end face of a channel that can be formed in a part of the semiconductor pillar 12 facing the gate insulating layer 17 by applying a gate voltage to the gate electrode 18 (see FIG. 1), and the channel width W is defined as D×π using the diameter D of the semiconductor pillar 12 shown in FIG. 1, and corresponds to the circumferential length of the cylindrical channel.

[0267] Therefore, the phrase "either the source region or the drain region between one end face of the channel that can be formed along the gate insulating layer of the semiconductor pillar and the portion surrounded by the first electrode has symmetrical electrical characteristics to the other region of either the source region or the drain region between the other end face of the channel and the portion surrounded by the second electrode" can be rephrased as follows: When a gate voltage is applied to the gate electrode, a predetermined amount of current flows from either the source region or the drain region between one end face of the channel that can be formed along the gate insulating layer of the semiconductor pillar and the portion surrounded by the first electrode, and the first voltage value V 01 and a second voltage value V when a predetermined amount of current flows from either the source region or the drain region between the other end face of the channel formed along the gate insulating layer of the semiconductor pillar and the portion surrounded by the second electrode by applying a gate voltage to the gate electrode. 02 Then, the difference (deviation) between the magnitude of each of the first voltage value and the second voltage value and the average value of the magnitude of the first voltage value and the second voltage value is within 10% of the average value. That is, -0.1×(|V 01 |+|V 02 |) / 2≦|V 01 |―(|V 01 |+|V 02 |) / 2≦0.1×(|V 01 |+|V 02 |) / 2,-0.1×(|V 01 |+|V 02 |) / 2≦|V 02 |―(|V 01 |+|V 02 |) / 2≦0.1×(|V 01 |+|V02 Here, the predetermined amount of current is the gate length L gate / Channel width W x 10 -7 It can be found from [A]. Note that the symbol |x| in the formula indicates the absolute value of x.

[0268] Therefore, in a single FET formed on a semiconductor pillar, the electric field distribution in the source region and the drain region is vertically symmetrical, and therefore the electrical characteristics in the source region and the drain region are vertically symmetrical. Therefore, for example, the temperature rise due to Joule heat in the source region and the drain region is the same, and therefore the impact of the temperature rise due to use is the same. If the source region and the drain region were asymmetrical, the electrical characteristics would be different, and the temperature rise due to Joule heat would be different in both regions, causing the characteristics to change over time. For example, the threshold voltage would be different, which would affect the specifications of an integrated circuit incorporating the semiconductor device. However, according to an embodiment of the present invention, this does not occur, and the threshold voltage of each MOS is at the same level even when MOSs are stacked vertically.

[0269] By stacking such semiconductor devices one above the other, the characteristics of two or more field effect transistors on top of each other are made to be at the same level.

[0270] Because the integrated circuit according to the embodiment of the present invention is configured using such semiconductor devices, the source and drain regions of one MOS are symmetrical, resulting in equal SNM. Furthermore, by stacking either a PMOS or an NMOS on one semiconductor pillar, wiring can be shortened. Furthermore, the wiring between the first NMOS, first CMOS, and second CMOS can be arranged in a plane that includes the axial direction of the semiconductor pillar and the direction in which the first, second, and third semiconductor pillars are aligned, enabling extremely high integration.

[0271] The semiconductor pillars according to the embodiment of the present invention may be arranged on the same plane or in various shapes such as Z-shape, U-shape, S-shape, etc. in plan view.

[0272] The phrase "semiconductor pillars are provided upright on a substrate" includes any of the following cases: a case in which semiconductor pillars 12 are provided upright on a substrate 11, extending vertically as shown in Fig. 1; a case in which multiple GAA-MOSFETs are stacked in layers, i.e., when gate insulating layers 17 are provided at portions of the semiconductor pillars 12 at different heights, a case in which semiconductor pillars 12 are provided upright on a substrate 11, extending continuously upright in the vertical direction; a case in which multiple GAA-MOSFETs are stacked in layers, i.e., when gate insulating layers 17 are provided at portions of the semiconductor pillars 12 at different heights, as shown in Figs. 24, 26, 27, etc., a case in which semiconductor pillars 12 are provided upright on a substrate 11, extending intermittently upright in the vertical direction, i.e., when a portion of the semiconductor pillars 12 is processed so as not to have semiconductor properties. Therefore, "semiconductor pillars are provided upright on a substrate" means "a semiconductor pillar is provided extending continuously or intermittently from a substrate."

[0273] In the integrated circuit according to the embodiment of the present invention, at least one GAA-MOSFET and each electrode of the capacitor are formed on the same surface, which facilitates downsizing. Since the GAA-MOSFET and the capacitor are configured in a stacked configuration, memory cells can be stacked. Since the GAA-MOSFET and the capacitor can be configured in pairs side by side, the wiring can be made compact. Furthermore, flexible design is possible.

[0274] The manufacturing method according to the embodiment of the present invention allows the source electrode and the drain electrode to be formed simultaneously, which eliminates manufacturing variations compared to when the source electrode and the drain electrode are formed sequentially. During manufacturing, the semiconductor pillar is not exposed and is protected by the stack. The semiconductor pillar is not damaged by cleaning during the manufacturing process. The drain region of the semiconductor pillar can be made identical and symmetrical to the source region.

[0275] Furthermore, when gate electrodes are provided at different heights on one semiconductor pillar with gate insulating layers interposed therebetween, it becomes possible to form a plurality of gate electrodes simultaneously, eliminating manufacturing variations.

[0276] According to an embodiment of the present invention, a three-dimensional integrated circuit is configured by repeatedly providing stages in the front-to-back direction in a plan view. For example, by arranging vertical GAA-FETs in the front-to-back and left-to-right directions in a plan view and arranging vertical GAA-FETs at least above or below each of these vertical GAA-FETs, an integrated circuit having a three-dimensional structure in which FETs are arranged in three dimensions can be configured. The vertical GAA-FETs constitute one of CMOS, DRAM, and SRAM. [Explanation of symbols]

[0277] 1: Semiconductor devices 1a, 61a, 61b: GAA-MOSFET 2, 3, 4: Integrated circuits 5a, 5b: Inverter circuit 6: Either the source region or the drain region (e.g., the source region) 7: The other of the source region and the drain region (for example, the drain region) 11: Circuit board 12: Semiconductor pillar 13: First isolation layer 14: First electrode 15: First insulating layer 16: Second isolation layer 17: Gate insulating layer 18: Gate electrode 19: Second insulating layer 20: The third layer of isolation 21: Second electrode 22: Third insulating layer 23: The fourth isolation layer 24, 24a, 24b, 25, 25a, 25b, 26, 26a, 26b, 28a, 28b, 39a, 39b: electrode vias 27,: Field effect transistor 31a, 31b, 34a, 34b: drain electrodes 32a, 32b, 32c, 35a, 35b, 35c, 35d, 38a, 38b: gate electrodes 33a, 33b, 36a, 36b: source electrodes 31c, 34c, 37a, 37b: either a source electrode or a drain electrode 33c, 36c, 36d, 39a, 39b: the other of the source electrode and the drain electrode 41a: First CMOS circuit 41b: Second CMOS circuit 41c: Third CMOS circuit 41d: Fourth CMOS circuit 41e: Fifth CMOS circuit 41f: 6th CMOS circuit 42: First wiring section 43: Second wiring section 44: Third wiring section 42a, 43a, 43c, 43d: Horizontal wiring section 43b, 43b: vertical wiring section 42x, 42y, 42z, 43x, 43y, 47, 48: Wiring section 45a, 45b, 45c, 45d, 45e, 45f: NMOS 46:SRAM 46a, 46b, 46c: 1st, 2nd, 3rd cells 50: Capacitor 51: First capacitor electrode 52: Second capacitor electrode 53: Connection electrode 54: Separation layer 55: Non-conductive layer 56a, 56b, 56c: Non-conductive layer 57a: First capacitor electrode 57b: Second capacitor electrode 57c: Third capacitor electrode 57d: Fourth capacitor electrode 57e: Fifth capacitor electrode 57e: Fourth capacitor electrode 57f: Sixth capacitor electrode 70: Any of a ferroelectric layer, a phase change layer, and a resistance change layer

Claims

1. a semiconductor pillar erected on a substrate; a gate insulating layer provided so as to surround a portion of the semiconductor pillar; a gate electrode provided so as to surround the gate insulating layer; a first electrode that serves as either a source electrode or a drain electrode and that is provided so as to surround a portion of the semiconductor pillar; a second electrode serving as the other of a source electrode and a drain electrode, the second electrode being spaced apart from the first electrode in the upward direction with the gate insulating layer and the gate electrode sandwiched therebetween and surrounding a part of the semiconductor pillar; It is equipped with a region of the semiconductor pillar between a lower end of the gate insulating layer and a portion surrounded by the first electrode is symmetrical to a region of the semiconductor pillar between an upper end of the gate insulating layer and a portion surrounded by the second electrode.

2. a semiconductor pillar erected on a substrate; a gate insulating layer provided so as to surround a portion of the semiconductor pillar; a gate electrode provided so as to surround the gate insulating layer; a first electrode that serves as one of a source electrode and a drain electrode and that is provided so as to surround a part of the semiconductor pillar; a second electrode serving as the other of the source electrode and the drain electrode, the second electrode being spaced apart from the first electrode in the vertical direction with the gate insulating layer and the gate electrode sandwiched therebetween and surrounding a part of the semiconductor pillar; It is equipped with a semiconductor device, wherein one of a source region and a drain region between one end face of a channel of the semiconductor pillar that may be formed along the gate insulating layer and a portion surrounded by the first electrode has symmetrical electrical characteristics to the other of the source region and the drain region between the other end face of the channel and a portion surrounded by the second electrode.

3. a semiconductor pillar erected on a substrate; a plurality of gate insulating layers provided at different heights so as to surround a portion of the semiconductor pillar; a plurality of gate electrodes each provided to surround a corresponding one of the gate insulating layers; a plurality of first electrodes each of which is provided at a different height so as to surround a part of the semiconductor pillar and serves as either a source electrode or a drain electrode; a plurality of second electrodes, each of which is provided at a different height so as to surround a part of the semiconductor pillar and serves as the other of the source electrode and the drain electrode; It is equipped with a plurality of field effect transistors each of which is configured by the gate insulating layer, the gate electrode, the first electrode, the second electrode, and a portion of the semiconductor pillar; a semiconductor device in which, in the plurality of field effect transistors, one of the source region and the drain region between one end face of a channel that may be formed along the gate insulating layer of the semiconductor pillar and a portion surrounded by the first electrode has symmetrical electrical characteristics to the other of the source region and the drain region between the other end face of the channel and a portion surrounded by the second electrode.

4. The semiconductor device of claim 3 , wherein the plurality of field effect transistors are isolated from each other.

5. A semiconductor device according to claim 3 or 4, a first semiconductor pillar and a second semiconductor pillar are erected on the same substrate as the semiconductor pillars, In the first semiconductor pillar, first and second p-channel FETs are configured by the gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the semiconductor pillar, each of which corresponds to the other, In the second semiconductor pillar, first and second n-channel FETs are configured by the gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the semiconductor pillar, each of which corresponds to the other, the gate electrode of the first p-channel FET is connected to the gate electrode of the first n-channel FET, and the drain electrode of the first p-channel FET is connected to the drain electrode of the first n-channel FET; the gate electrode of the second p-channel FET is connected to the gate electrode of the second n-channel FET, and the drain electrode of the second p-channel FET is connected to the drain electrode of the second n-channel FET.

6. A semiconductor device according to claim 3 or 4, a first semiconductor pillar and a second semiconductor pillar are erected on the same substrate as the semiconductor pillars, 10. An integrated circuit, wherein the first semiconductor pillar has a different diameter than the second semiconductor pillar and / or is composed of a different material than the second semiconductor pillar.

7. A semiconductor device according to claim 3 or 4, the semiconductor pillars include a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar that are erected on the same substrate; in the second semiconductor pillar, a first FET capable of forming a channel of either a first p-channel FET or a first n-channel FET, and a second FET capable of forming a channel of either a second p-channel FET or a second n-channel FET are configured by the gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar, each of which corresponds to the other; In the first semiconductor pillar, a FET capable of forming a channel of the other of a first p-channel FET and a first n-channel FET is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar, In the third semiconductor pillar, a FET capable of forming the other channel of either a second p-channel FET or a second n-channel FET is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the third semiconductor pillar, the gate electrode of the first p-channel FET is connected to the gate electrode of the first n-channel FET, and the drain electrode of the first p-channel FET is connected to the drain electrode of the first n-channel FET; the gate electrode of the second p-channel FET is connected to the gate electrode of the second n-channel FET, and the drain electrode of the second p-channel FET is connected to the drain electrode of the second n-channel FET.

8. A semiconductor device according to claim 3 or 4, the semiconductor pillars include first, second, and third semiconductor pillars that are erected on the same substrate; a first NMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar, and a first PMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar, a first CMOS is configured; a second PMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the second semiconductor pillar, and a second NMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the third semiconductor pillar, a second CMOS is configured; a third NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar; a fourth NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the third semiconductor pillar.

9. the first, second, and third semiconductor pillars are arranged in this order; 9. The integrated circuit according to claim 8, wherein the drain electrode in the first CMOS partially faces the drain electrode in the second CMOS with an insulating layer interposed therebetween, and extends in opposite directions in a direction in which the first, second, and third semiconductor pillars are aligned.

10. the gate electrode of the first CMOS is connected to either a source electrode or a drain electrode of the fourth NMOS and a drain electrode of the second CMOS in a plane including the first, second, and third semiconductor pillars, a plane parallel to the plane, or a plane intersecting the plane; 10. The integrated circuit according to claim 8, wherein the gate electrode of the second CMOS is connected to either a source electrode or a drain electrode of the third NMOS and a drain electrode of the first CMOS in a plane including the first, second, and third semiconductor pillars, a plane parallel to the plane, or a plane intersecting the plane.

11. A semiconductor device according to claim 3 or 4, the semiconductor pillars include first, second, third, and fourth semiconductor pillars that are erected on the same substrate; a first CMOS including a first NMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the third semiconductor pillar, and a first PMOS configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the second semiconductor pillar; a second PMOS configured with the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the second semiconductor pillar, and a second NMOS configured with the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the third semiconductor pillar; a third NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a part of the first semiconductor pillar; a fourth NMOS is configured by the corresponding gate electrode, the gate insulating layer, the first electrode, the second electrode, and a portion of the fourth semiconductor pillar.

12. the first, second, third, and fourth semiconductor pillars are erected in this order on the same substrate, a drain electrode of the first CMOS partially faces a drain electrode of the second CMOS via an insulating layer, and extends in opposite directions in a direction in which the first, second, third, and fourth semiconductor pillars are arranged, the gate electrode of the first CMOS is connected to either a source electrode or a drain electrode of the fourth NMOS and the drain electrode of the second CMOS at the top and bottom in any one of a plane including the first, second, third, and fourth semiconductor pillars, a plane parallel to the plane, and a plane intersecting the plane; 12. The integrated circuit according to claim 11, wherein the gate electrode of the second CMOS is connected to either a source electrode or a drain electrode of the third NMOS and the drain electrode of the first CMOS above and below in any one of a plane including the first, second, third, and fourth semiconductor pillars, a plane parallel to said plane, and a plane intersecting with said plane.

13. first to sixth semiconductor pillars erected on a substrate; first to sixth gate insulating layers provided corresponding to the first to sixth semiconductor pillars, respectively; first to sixth gate electrodes provided corresponding to the first to sixth semiconductor pillars, with corresponding first to sixth gate insulating layers interposed therebetween; first to sixth source electrodes provided corresponding to the first to sixth semiconductor pillars, respectively; first to sixth drain electrodes provided corresponding to the first to sixth semiconductor pillars, respectively; Equipped with the first gate electrode and the second gate electrode at the same height as the first gate electrode are connected to the third drain electrode and the fourth drain electrode at the same height as the third drain electrode by a first wiring portion in a vertical direction, the third gate electrode and the fourth gate electrode at the same height as the third gate electrode are connected to the first drain electrode and the second drain electrode at the same height as the first drain electrode by a second wiring portion in the up-down direction, the fifth source electrode or the fifth drain electrode provided on the fifth semiconductor pillar arranged outside the first and second semiconductor pillars is connected at the same height as the first and second drain electrodes; the sixth source electrode or the sixth drain electrode provided on the sixth semiconductor pillar arranged outside the third and fourth semiconductor pillars is connected at the same height as the third and fourth drain electrodes; an integrated circuit, wherein a source region between one end surface of a channel that can be formed along a corresponding one of the first to sixth semiconductor pillars and a portion surrounded by the corresponding source electrode has symmetrical electrical characteristics to a drain region between the other end surface of the channel and a portion surrounded by the drain electrode.

14. The integrated circuit of claim 13 , wherein the first through sixth semiconductor pillars are disposed in the same plane.

15. 15. The integrated circuit according to claim 13, wherein either or both of the first wiring portion and the second wiring portion are provided on a surface including the first to sixth semiconductor pillars or on a surface different from the surface including the first to sixth semiconductor pillars.

16. the first, second, and fifth semiconductor pillars are provided on a first surface; the third, fourth, and sixth semiconductor pillars are provided on a second surface different from the first surface, The integrated circuit according to claim 13 , wherein the first wiring portion and the second wiring portion are provided on a plane intersecting the first plane and the second plane.

17. A semiconductor device according to any one of claims 1 to 4; a first capacitor electrode provided on the same surface as the first electrode; a second capacitor electrode provided so as to face the first capacitor electrode; 1. An integrated circuit comprising:

18. 18. The integrated circuit of claim 17, wherein the second capacitor electrode is on the same plane as the second electrode.

19. the first capacitor electrode and the second capacitor electrode are thinner than the first electrode; 18. The integrated circuit of claim 17, wherein the second capacitor electrode is spaced from the first capacitor electrode by a distance less than a thickness of the first electrode.

20. 18. The integrated circuit according to claim 17, further comprising a connection electrode that connects said first electrode and said first capacitor electrode, said connection electrode being located in the same plane.

21. A semiconductor device according to any one of claims 1 to 4; a first capacitor electrode provided on the same surface as the first electrode; a second capacitor electrode provided on the same surface as the second electrode; a third capacitor electrode provided opposite the first capacitor electrode and spaced apart by a distance shorter than the thickness of the first electrode; a fourth capacitor electrode provided opposite the second capacitor electrode and spaced apart by a distance shorter than the thickness of the second electrode; a fifth capacitor electrode that vertically connects the first capacitor electrode and the fourth capacitor electrode; a sixth capacitor electrode connecting the second capacitor electrode and the third capacitor electrode in the vertical direction; 1. An integrated circuit comprising:

22. The integrated circuit according to claim 17 , further comprising one of a phase change film, a dielectric film, and a resistance change film between the first capacitor electrode and the second capacitor electrode.

23. 23. The integrated circuit according to claim 5, wherein basic units constituting any one of CMOS, DRAM and SRAM are stacked in multiple stages, or at least two types of basic units out of three types of basic units constituting CMOS, DRAM and SRAM are stacked.

24. providing a substrate having a stack of layers on which at least one semiconductor pillar can be formed in an axial direction, the stack of layers including at least one pair of first sacrificial layers surrounding the semiconductor pillar and spaced apart in the axial direction; forming a first hole in the stack to reach the first sacrificial layer; removing the mating first sacrificial layer; a pair of conductive layers that will form a pair of source and drain electrodes is deposited to surround the region of the semiconductor pillar that is exposed by removing the first sacrificial layer.

25. the stacked body includes a second sacrificial layer that surrounds the semiconductor pillar and is provided so as not to overlap the first sacrificial layer in a plan view at a height between the pair of first sacrificial layers; moreover, forming a second hole different from the first hole in the stack to reach the second sacrificial layer; removing the second sacrificial layer; forming a gate insulating layer to surround the region of the semiconductor pillar exposed by removing the second sacrificial layer; The manufacturing method according to claim 24 , further comprising depositing a conductive layer that will become a gate electrode so as to surround the gate insulating layer.

26. The method of claim 24 , wherein the stack includes a plurality of pairs of the first sacrificial layers.

27. the stack includes a plurality of pairs of the first sacrificial layers and the same number of pairs of the second sacrificial layers as the number of pairs of the first sacrificial layers; 26. The method of claim 25, wherein each of the second sacrificial layers has the same thickness so that gate lengths contributed by each of the plurality of gate electrodes are equal, or some of the second sacrificial layers have a different thickness from others of the second sacrificial layers so that gate lengths contributed by some of the plurality of gate electrodes are different from gate lengths contributed by other of the plurality of gate electrodes.

28. forming a third hole in the stack to reach the mating first sacrificial layer; forming a separation layer in the third hole; forming a fourth hole in the separation layer adjacent to the pair of first sacrificial layers; removing a portion of the first sacrificial layer exposed by the fourth hole; 28. The manufacturing method according to claim 24, further comprising forming a conductive layer to be a capacitor electrode in each of the regions from which the first sacrificial layer has been removed.

29. 29. The manufacturing method according to claim 28, further comprising forming a conductive layer for connecting either the source electrode or the drain electrode to one of the capacitor electrodes.

30. the stacked body includes a second sacrificial layer that surrounds the semiconductor pillar and is provided so as not to overlap the first sacrificial layer in a plan view at a height between the pair of first sacrificial layers, and an insulating layer that is provided between the pair of first sacrificial layers, removing portions of the first sacrificial layer and the insulating layer that are sandwiched between the upper and lower capacitor electrodes; 30. The manufacturing method according to claim 28 or 29, further comprising depositing a material to become any one of a phase change film, a dielectric film, and a resistance change film in the area from which the first sacrificial layer and the insulating layer have been removed.

31. a substrate having a laminate including at least one pair of first sacrificial layers that surround the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and are spaced apart in the axial direction, and a second sacrificial layer that surrounds the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and is provided so as not to partially overlap the first sacrificial layer in a plan view at a height between one first sacrificial layer and the other first sacrificial layer that constitutes the pair; forming a hole in the stack to access the second sacrificial layer; removing the second sacrificial layer; simultaneously forming a gate insulating layer so as to surround the P-type semiconductor pillar and the N-type semiconductor regions exposed by removing the second sacrificial layer; A manufacturing method in which a conductive layer that will become a gate electrode is simultaneously deposited so as to surround the gate insulating layer.

32. a substrate having a stacked body including at least one pair of first sacrificial layers that can be formed in an axial direction so as to be spaced apart from the P-type semiconductor pillar and the N-type semiconductor pillar in a plan view, and that surrounds the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and are spaced apart from each other in the axial direction; forming a hole in the stack to access one of the pair of first sacrificial layers; removing one of the first sacrificial layers; a pair of conductive layers that become drain electrodes are simultaneously deposited so as to surround regions of the P-type semiconductor pillar and the N-type semiconductor pillar that are exposed by removing one of the first sacrificial layers, thereby simultaneously forming the drain electrodes of the P-type semiconductor pillar and the N-type semiconductor pillar, and a portion that connects the two.

33. a substrate having a stacked body including at least one pair of first sacrificial layers that can be formed in an axial direction so as to be spaced apart from the P-type semiconductor pillar and the N-type semiconductor pillar in a plan view, and that surrounds the P-type semiconductor pillar and the N-type semiconductor pillar, respectively, and are spaced apart from each other in the axial direction; forming a hole in the stack to access one of the pair of first sacrificial layers; removing one of the first sacrificial layers; a conductive layer is deposited to surround regions of the P-type semiconductor pillar and the N-type semiconductor pillar that are exposed by removing one of the first sacrificial layers, and then the conductive layer between the P-type semiconductor pillar and the N-type semiconductor pillar is partially removed to form a source electrode for the P-type semiconductor pillar and a source electrode for the N-type semiconductor pillar.

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