Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device which is structured to increase input capacity of IGBT and suppress a gate leak current.SOLUTION: An adjacent active trench 11y in an IGBT region 10 and an adjacent capacity adjustment trench 22x in a diode region 20 extend in a Y direction and are provided in a stripe shape in a planar view. A plurality of crossing trenches 23 extends in an X direction, which crosses the Y direction at the right angle, and is provided in a stripe shape in a planar view. The plurality of crossing trenches 23 is provided from the adjacent capacity adjustment trench 22x to the adjacent active trench 11y in the planar view. Therefore, a gate electrode 11a of the adjacent active trench 11y and a capacity adjustment electrode 22a of the adjacent capacity adjustment trench 22x are electrically connected via an electrode 23a for crossing trenches in the crossing trench 23.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device including an IGBT region and a diode region, and a method for manufacturing the same. [Background technology]

[0002] To improve the performance and reduce the cost of power semiconductor devices, devices such as reverse conducting insulated gate bipolar transistors (RC-IGBTs) have been developed. In the following explanation, reverse conducting insulated gate bipolar transistors will be referred to as "RC-IGBTs." RC-IGBTs are semiconductor devices that can conduct electricity in both directions, and some devices integrate an IGBT and a diode built into the same semiconductor substrate.

[0003] For example, Patent Document 1 proposes a structure for adjusting capacitance of an RC-IGBT using a trench provided in the diode region. An electrode material is buried in the trench via an insulating film. Patent Document 1 employs a gate connection structure in which the trench in the diode region is pulled up by a gate wiring portion formed on the semiconductor substrate and connected to the gate potential of the IGBT. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-43890 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the conventional gate connection structure disclosed in Patent Document 1 and the like, when the total number of trenches formed in the diode region is increased, it is necessary to provide a connection region with the gate pull-up portion in each of the trenches, and the number of connection regions with the gate pull-up portion also increases. The connection region of each of the trenches is usually provided at the end.

[0006] For this reason, conventional gate connection structures are prone to electric field concentration in the connection region with the upper gate lead. Therefore, conventional gate connection structures tend to increase gate leakage current, so increasing the number of trenches in the diode region to increase input capacitance results in an increased gate leakage current. Specifically, input capacitance refers to the sum of the gate-emitter capacitance Cge and gate-collector capacitance Cgc of the IGBT.

[0007] The present disclosure has been made to solve the above problems, and has an object to provide a semiconductor device having a structure that increases the input capacitance of an IGBT and suppresses gate leakage current. [Means for solving the problem]

[0008] A semiconductor device according to the present disclosure is a semiconductor device configured to include an IGBT region having an IGBT therein and a diode region having a diode therein, the semiconductor device including a semiconductor substrate having first and second main surfaces, a drift layer of a first conductivity type provided in the semiconductor substrate, a base layer of a second conductivity type provided in the semiconductor substrate and selectively disposed on the first main surface side of the drift layer, an anode layer of a second conductivity type provided in the semiconductor substrate and selectively disposed on the first main surface side of the drift layer, and and an emitter electrode provided on the first main surface, wherein the drift layer and the emitter electrode are shared between the IGBT region and the diode region, the base layer is used in the IGBT region, and the anode layer is used in the diode region, and the semiconductor device includes an active trench provided in a region that penetrates the base layer from the first main surface side and reaches a part of the drift layer, a diode trench provided in a region that penetrates the anode layer from the first main surface side and reaches a part of the drift layer, and the capacitance adjustment trench is embedded in the active trench via a gate insulating film; a diode electrode is embedded in the diode trench via a diode insulating film; a capacitance adjustment electrode is embedded in the capacitance adjustment trench via a capacitance adjustment insulating film; an intersection trench electrode is embedded in the intersection trench via an intersection trench insulating film; the diode electrode is electrically connected to the emitter electrode; the intersection trench is extended from the capacitance adjustment trench to the active trench in a plan view; and the gate electrode and the capacitance adjustment electrode are electrically connected via the intersection trench electrode. [Effects of the Invention]

[0009] In the semiconductor device of the present disclosure, the gate electrode provided in the IGBT region is electrically connected to the capacitance adjustment electrode provided in the diode region via the intersection trench electrode provided in the semiconductor substrate.

[0010] Therefore, the semiconductor device of the present disclosure can increase the input capacitance of the IGBT and suppress the gate leakage current without increasing the number of active trenches. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a planar structure of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view showing the structure of the cross section AA of FIG. [Figure 3] FIG. 2 is a cross-sectional view showing the cross-sectional structure of FIG. 1 taken along the line BB. [Figure 4] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present disclosure. [Figure 5] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present disclosure. [Figure 6] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 7] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 8] FIG. 13 is a plan view showing the planar structure of a semiconductor device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] <Introduction> Hereinafter, embodiments 1 to 6 will be described with reference to the drawings. The drawings are schematic illustrations, and the relative sizes and positions may be changed. In the following description, the same or corresponding components are given the same reference numerals, and repeated description may be omitted. In the following description, terms indicating specific positions and directions, such as "top," "bottom," "side," "bottom," "front," or "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not limit the directions when actually implemented. Regarding the conductivity types of semiconductors, the first conductivity type will be described as n-type and the second conductivity type as p-type. However, these may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. n + The concentration of donor impurities is higher in n-type than in n-type, - The p type means that the concentration of donor impurities is lower than that of n type. + The type has a higher concentration of acceptor impurities than the p-type, - means that the concentration of acceptor impurities is lower than that of p-type.

[0013] <First Embodiment> Fig. 1 is a plan view showing the planar structure of a semiconductor device 81 according to a first embodiment of the present disclosure, as viewed from above. Fig. 2 is a cross-sectional view showing the AA cross-sectional structure of Fig. 1, and Fig. 3 is a cross-sectional view showing the BB cross-sectional structure of Fig. 1. An XYZ Cartesian coordinate system is depicted in each of Figs. 1 to 3. Note that Fig. 1 omits the illustration of an interlayer insulating film 4 and an emitter electrode 6, which are structures on the upper surface of a semiconductor substrate 40.

[0014] 1 to 3, a semiconductor device 81 according to a first embodiment of the present disclosure includes a semiconductor substrate 40. The semiconductor device 81 according to the first embodiment includes an IGBT region 10 having an IGBT (Insulated Gate Bipolar Transistor) therein, and a diode region 20 having a diode therein.

[0015] The semiconductor substrate 40 has a first main surface S1 that is a first main surface on the +Z direction side and a second main surface S2 that is a second main surface on the −Z direction side opposite to the first main surface S1. Furthermore, the semiconductor substrate 40 is divided into an IGBT region 10 and a diode region 20.

[0016] The semiconductor substrate 40 is provided with a first conductivity type n - An n-type drift layer 1 and an n-type carrier accumulation layer 2 are provided. The carrier accumulation layer 2 is provided on the upper surface of the drift layer 1. That is, the carrier accumulation layer 2 is provided adjacent to the drift layer 1 on the first main surface S1 side. The combined structure of the drift layer 1 and the carrier accumulation layer 2 functions as a drift layer in a broad sense.

[0017] The semiconductor substrate 40 is further provided with a base layer 15 and a p-type anode layer 25 of the second conductivity type, ie, p-type.

[0018] The base layer 15 is formed on the upper surface of the carrier accumulation layer 2 in the IGBT region 10. That is, the base layer 15 is selectively disposed on the first main surface S1 side of the semiconductor substrate 40 with respect to the drift layer 1. The base layer 15 is provided in the IGBT region 10.

[0019] The anode layer 25 is formed on the upper surface of the carrier accumulation layer 2 in the diode region 20. That is, the anode layer 25 is selectively disposed on the first main surface S1 side of the semiconductor substrate 40 with respect to the drift layer 1. The anode layer 25 is provided in the diode region 20.

[0020] The upper surfaces of the base layer 15 and the anode layer 25 in the +Z direction form the first main surface S1 of the semiconductor substrate 40.

[0021] The IGBT region 10 extends from the first main surface S1 to the second main surface S2 of the semiconductor substrate 40. The diode region 20 also extends from the first main surface S1 to the second main surface S2 of the semiconductor substrate 40.

[0022] As shown in FIG. 2, the IGBT region 10 has n + type emitter layer 13, p +There are IGBT contact layers 14 and active trenches 11 .

[0023] As shown in FIGS. 1 and 2, the IGBT region 10 has a p + type IGBT contact layer 14 and n + A mold emitter layer 13 is optionally provided.

[0024] On the other hand, as shown in FIGS. 1 to 3, in the diode region 20, p + A type diode contact layer 24 is optionally provided.

[0025] 2, with respect to the IGBT region 10, a plurality of active trenches 11 are provided in a region where the emitter layer 13 is formed. Each of the plurality of active trenches 11 is provided in a region that extends from the first main surface S1 side of the semiconductor substrate 40, through the base layer 15 and the carrier accumulation layer 2, and reaches a part of the drift layer 1.

[0026] A gate electrode 11a is buried in each of the multiple active trenches 11 via a gate insulating film 11b. The gate insulating film 11b is formed on the inner wall of the active trench 11. Hereinafter, in the description of the device structure, the completed structure of the active trench 11, including the gate electrode 11a and the gate insulating film 11b, may be simply referred to as the "active trench 11."

[0027] As shown in FIG. 1, the active trenches 11 are each provided in a stripe shape extending in the Y direction in plan view.

[0028] 1 to 3, a diode trench 21 and a plurality of capacitance adjustment trenches 22 are provided in the diode region 20. Although only one diode trench 21 is shown in FIGS. 1 and 2, a plurality of diode trenches 21 may be provided in the diode region 20.

[0029] As shown in FIG. 2, the diode trench 21 is provided in a region that extends from the first main surface S1 side of the semiconductor substrate 40, through the anode layer 25 and the carrier accumulation layer 2, and reaches a part of the drift layer 1.

[0030] A diode electrode 21a is buried in the diode trench 21 via a diode insulating film 21b. The diode insulating film 21b is formed on the inner wall of the diode trench 21. Hereinafter, in describing the device structure, the completed structure of the diode trench 21, including the diode electrode 21a and the diode insulating film 21b, may be simply referred to as the "diode trench 21."

[0031] Furthermore, as shown in FIG. 2, the plurality of capacitance adjustment trenches 22 are provided in a region that extends from the first main surface S1 side of the semiconductor substrate 40 through the anode layer 25 and the carrier accumulation layer 2 to reach a part of the drift layer 1.

[0032] A capacitance adjustment electrode 22a is buried in each of the plurality of capacitance adjustment trenches 22 via a capacitance adjustment insulating film 22b. The capacitance adjustment insulating film 22b is formed on the inner wall of the capacitance adjustment trench 22. Hereinafter, in the description of the device structure, the completed structure including the capacitance adjustment electrode 22a and the capacitance adjustment insulating film 22b with respect to the capacitance adjustment trench 22 may be simply referred to as the "capacitance adjustment trench 22."

[0033] 1 and 2, one of the plurality of capacitance adjustment trenches 22 is provided near the boundary L12 between the IGBT region 10 and the diode region 20, and this capacitance adjustment trench 22 becomes the adjacent capacitance adjustment trench 22x. On the other hand, the active trench 11 provided at the position closest to the boundary L12 among the plurality of active trenches 11 becomes the adjacent active trench 11y.

[0034] 3 , in the diode region 20, the plurality of intersection trenches 23 are provided in a region that penetrates from the first main surface S1 side of the semiconductor substrate 40 through the anode layer 25 and the carrier accumulation layer 2 to reach a part of the drift layer 1. In the IGBT region 10, the plurality of intersection trenches 23 are provided in a region that penetrates from the first main surface S1 side of the semiconductor substrate 40 through the base layer 15 and the carrier accumulation layer 2 to reach a part of the drift layer 1.

[0035] An intersection trench electrode 23a is buried in each of the multiple intersection trenches 23 via an intersection trench insulating film 23b. The capacitance adjustment insulating film 22b is formed on the inner wall of the intersection trench 23. In the following description of the device structure, the completed structure of the intersection trench 23, including the intersection trench electrode 23a and the intersection trench insulating film 23b, may be simply referred to as the "intersection trench 23."

[0036] 1, the diode trenches 21 are provided in a stripe pattern extending in the Y direction in plan view. Similarly, the plurality of capacitance adjustment trenches 22 are provided in a stripe pattern extending in the Y direction in plan view.

[0037] On the other hand, the multiple intersection trenches 23 are each provided in a stripe shape extending in the X direction intersecting the Y direction at a right angle in plan view. Specifically, the multiple intersection trenches 23 are each provided from the adjacent capacitance adjustment trench 22x to the adjacent active trench 11y in plan view, and the intersection trench electrode 23a is in contact with the gate electrode 11a of the adjacent active trench 11y, and the intersection trench electrode 23a is in contact with the capacitance adjustment electrode 22a of the adjacent capacitance adjustment trench 22x.

[0038] Therefore, the gate electrode 11a of the adjacent active trench 11y and the capacitance adjustment electrode 22a of the adjacent capacitance adjustment trench 22x are electrically connected via the intersection trench electrode 23a in the intersection trench 23.

[0039] In addition, the intersection trench 23 is also provided between a pair of capacitance adjustment trenches 22, 22 that are adjacent to each other in plan view, and the intersection trench electrode 23 a contacts each of the pair of capacitance adjustment electrodes 22 a, 22 a. Therefore, the pair of capacitance adjustment electrodes 22 a are electrically connected via the intersection trench electrode 23 a.

[0040] Incidentally, even when three or more capacitance adjustment trenches 22 are formed, the capacitance adjustment trenches 22 can be electrically connected to each other via the intersection trench electrodes 23a by providing a plurality of intersection trenches 23 corresponding to a plurality of pairs of capacitance adjustment trenches 22, 22. However, a planar structure is required in which no diode trenches 21 are provided between the capacitance adjustment trenches 22.

[0041] In this way, the intersection trench 23 is provided between the plurality of capacitance adjustment trenches 22 in plan view, so that the plurality of capacitance adjustment electrodes 22a are electrically connected to each other via the intersection trench electrode 23a.

[0042] In the IGBT region 10, the surface structure formed on the surfaces of the IGBT contact layer 14, the emitter layer 13, and the gate electrode 11a includes, for example, the emitter electrode 6 and the interlayer insulating film 4 shown in Figures 2 and 3. The emitter electrode 6 is set to a reference potential such as a ground battery by an external terminal or the like (not shown).

[0043] 2, the interlayer insulating film 4 is formed to cover the upper part of the active trench 11, and the emitter electrode 6 is provided on the upper surface of the semiconductor substrate 40 including the interlayer insulating film 4. The presence of the interlayer insulating film 4 provides insulation between the gate electrode 11a and the emitter electrode 6. Since the emitter electrode 6 is formed on the upper surface of the semiconductor substrate 40 in an opening region 18 where the interlayer insulating film 4 is not formed, the emitter electrode 6 is electrically connected to the emitter layer 13 and the IGBT contact layer 14.

[0044] In the IGBT region 10, the rear surface structure formed on the rear surface of the drift layer 1 includes, for example, an n-type buffer layer 3, a p-type collector layer 16, and a collector electrode 7 shown in FIG.

[0045] In the IGBT region 10, the buffer layer 3 is provided on the −Z direction side of the drift layer 1, i.e., on the underside of the second main surface S2 side, and the collector layer 16 is provided on the underside of the buffer layer 3. Furthermore, the collector electrode 7 is provided on the underside of the collector layer 16.

[0046] An IGBT having the above-mentioned emitter electrode 6, IGBT contact layer 14, emitter layer 13, base layer 15, drift layer 1, buffer layer 3, collector layer 16, collector electrode 7, gate electrode 11a, and gate insulating film 11b as main components is provided in the IGBT region 10.

[0047] In this configuration, the IGBT operates by applying a positive voltage to the gate electrode 11a to form an n-type channel region in a part of the base layer 15, and applying a positive voltage to the collector electrode .

[0048] 1 to 3, the structure of the diode region 20 will be described. In the diode region 20, a drift layer 1, a carrier accumulation layer 2, an anode layer 25, a diode contact layer 24, a diode trench 21, a plurality of capacitance adjustment trenches 22, and a plurality of intersection trenches 23 are provided in a semiconductor substrate 40.

[0049] The drift layer 1 and the carrier accumulation layer 2 are shared between the diode region 20 and the IGBT region 10 .

[0050] In the diode region 20, the emitter electrode 6 and the interlayer insulating film 4 shown in Figures 2 and 3 are formed as a surface structure formed on the surface of the semiconductor substrate 40 including the diode contact layer 24, the anode layer 25, the diode trench 21, the capacitance adjustment trench 22, and the intersection trench 23.

[0051] 2 and 3, the interlayer insulating film 4 is formed to cover the upper portions of the diode trench 21, the plurality of capacitance adjustment trenches 22, and the plurality of intersection trenches 23, and the emitter electrode 6 is provided on the upper surface of the semiconductor substrate 40 including the interlayer insulating film 4. The presence of the interlayer insulating film 4 insulates the emitter electrode 6 from the diode electrode 21a, capacitance adjustment electrode 22a, and intersection trench electrode 23a.

[0052] The diode electrode 21a is electrically connected to the emitter electrode 6 in a region not shown in FIGS.

[0053] Since the emitter electrode 6 is formed on the upper surface of the semiconductor substrate 40 on the opening region 18 where the interlayer insulating film 4 is not formed, the emitter electrode 6 in the diode region 20 is electrically connected to the diode contact layer 24.

[0054] The emitter electrode 6 is an electrode that is shared by the IGBT region 10 and the diode region 20. The emitter electrode 6 may be made of, for example, an aluminum alloy.

[0055] In the diode region 20, the rear surface structure formed on the rear surface of the drift layer 1 includes the n-type buffer layer 3, n-type + A molded cathode layer 26 and collector electrode 7 are provided.

[0056] In the diode region 20, the buffer layer 3 is provided on the −Z direction side of the drift layer 1, i.e., on the underside of the second main surface S2 side, and the cathode layer is provided on the underside of the buffer layer 3. The collector electrode 7 is provided on the underside of the cathode layer .

[0057] The n-type buffer layer 3 and the collector electrode 7 can be shared between the IGBT region 10 and the diode region 20. The cathode layer 26 is used in the diode region 20.

[0058] A diode having as its main components the emitter electrode 6, anode layer 25, drift layer 1, carrier accumulation layer 2, buffer layer 3, cathode layer 26, and collector electrode 7 described above is provided in the diode region 20. In the diode region 20, the emitter electrode 6 functions as an anode electrode, and the collector electrode 7 functions as a cathode electrode.

[0059] In this way, the drift layer 1, carrier accumulation layer 2, buffer layer 3, emitter electrode 6, and collector electrode 7 are shared between the IGBT region 10 and the diode region 20. On the other hand, the base layer 15, emitter layer 13, IGBT contact layer 14, and collector layer 16 are used in the IGBT region 10, and the diode contact layer 24, anode layer 25, and cathode layer 26 are used in the diode region 20.

[0060] Furthermore, the intersection trench 23 is shared between the IGBT region 10 and the diode region 20, the active trench 11 is used in the IGBT region 10, and the diode trench 21 and the capacitance adjustment trench 22 are used in the diode region 20.

[0061] (effect) In the semiconductor device 81 of embodiment 1, the gate electrode 11a of the adjacent active trench 11y provided in the IGBT region 10 has a gate connection structure in which it is electrically connected to the capacitance adjustment electrode 22a of the adjacent capacitance adjustment trench 22x provided in the diode region 20 via the intersection trench electrode 23a provided in the semiconductor substrate 40.

[0062] For each of the plurality of capacitance adjustment trenches 22, the portion where the capacitance adjustment electrode 22a faces the anode layer 25 via the capacitance adjustment insulating film 22b contributes to the gate-emitter capacitance Cge of the IGBT, and the portion where the capacitance adjustment electrode 22a faces the carrier accumulation layer 2 or the drift layer 1 via the capacitance adjustment insulating film 22b contributes to the gate-collector capacitance Cgc of the IGBT. The input capacitance is the sum of the gate-emitter capacitance Cge and the gate-collector capacitance Cgc of the IGBT.

[0063] Therefore, the above-described gate connection structure of the semiconductor device 81 allows at least the capacitance adjustment electrode 22a of the adjacent capacitance adjustment trench 22x to be used as the input capacitance of the IGBT, thereby increasing the input capacitance of the IGBT formed in the IGBT region 10.

[0064] Therefore, the semiconductor device 81 of embodiment 1 can increase the input capacitance of the IGBT formed in the IGBT region 10 with the minimum number of active trenches 11 necessary, without increasing the number of active trenches 11, and can also suppress the gate leakage current in the IGBT.

[0065] This disclosure assumes that the current change indicated by di / dt is rate-limiting, and aims to obtain an IGBT with switching characteristics that enhances the voltage change indicated by dv / dt. To achieve this, the semiconductor device of this disclosure achieves the effect of increasing the input capacitance in order to increase the ratio of the input capacitance to the feedback capacitance in the IGBT. The "feedback capacitance" here refers to the gate-collector parasitic capacitance Cgc in the IGBT.

[0066] Next, the effect of suppressing gate leakage current will be described. In conventional semiconductor devices, electrical connection members such as gate lead electrodes are provided on the edge regions of the active trench and capacitance adjustment trench to electrically connect the gate electrode and capacitance adjustment electrode. Therefore, conventional semiconductor devices have a gate electrode structure that is prone to electric field concentration from the electrical connection members to the edge regions of the active trench and capacitance adjustment trench when a gate voltage is applied to the IGBT.

[0067] As a result, the conventional semiconductor device has a problem in that the electric field concentration causes an increase in gate leakage current.

[0068] On the other hand, the semiconductor device 81 of embodiment 1 uses the intersection trench electrode 23a provided in the semiconductor substrate 40 as an electrical connection member, so there is no possibility of the above-mentioned electric field concentration occurring, and it is possible to suppress gate leakage current.

[0069] In the semiconductor device 81 of the first embodiment, the plurality of capacitance adjustment electrodes 22a provided in the diode region 20 are electrically connected via the intersection trench electrode 23a.

[0070] Therefore, in the semiconductor device 81 of the first embodiment, the input capacitance of the IGBT formed in the IGBT region 10 can be further increased by the amount that the plurality of capacitance adjustment electrodes 22a can be used as the input capacitance of the IGBT.

[0071] Furthermore, an interlayer insulating film 4 is provided above the capacitance adjusting electrode 22a and the intersection trench electrode 23a, and neither the capacitance adjusting electrode 22a nor the intersection trench electrode 23a has any electrical connection with the emitter layer 13 or the emitter electrode 6.

[0072] Therefore, a parasitic nMOSFET is not formed in which the capacitance adjusting electrode 22a and the intersection trench electrode 23a serve as gate electrodes and the cathode layer 26 serves as an electrode region, and an increase in on-voltage during diode operation can be suppressed.

[0073] (Manufacturing method) The manufacturing method of the semiconductor device 81 of the first embodiment includes the following steps (a) to (d), and by performing steps (a) to (d), the unfinished active trench 11, the diode trench 21, the capacitance adjustment trench 22, and the intersection trench 23 are formed.

[0074] Step (a): forming the active trench 11; Step (b): forming the diode trench 21; Step (c): forming the capacitance adjusting trench 22; Step (d)...forming the intersection trench 23; The above steps (a) to (d) are performed simultaneously, so that the unfinished trenches 11, 21 to 23 are formed to approximately the same depth.

[0075] For example, steps (a) to (d) can be performed simultaneously using an existing manufacturing method, such as depositing an oxide film such as SiO2 on the semiconductor substrate 40, then forming openings in the oxide film at the portions where the unfinished trenches 11, 21 to 23 will be formed by mask processing, and etching the semiconductor substrate 40 using the openings as a mask.

[0076] The trenches 11, 21 to 23 can be completed, for example, through the following process: The semiconductor substrate 40 is heated in an atmosphere containing oxygen to form an oxide film on the inner walls of the trenches 11, 21 to 23 and on the first main surface S1 of the semiconductor substrate 40. In this example, an oxide film is used as the insulating film.

[0077] Of the oxide films formed on the inner walls of the trenches 11, 21-23, the oxide film in the active trench 11 becomes the gate insulating film 11b, and the oxide film formed in the diode trench 21 becomes the diode insulating film 21b. Similarly, the oxide film formed in the capacitance adjustment trench 22 becomes the capacitance adjustment insulating film 22b, and the oxide film formed in the intersection trench 23 becomes the intersection trench insulating film 23b. The oxide films formed on the first main surface S1 of the semiconductor substrate 40 will be removed in a later process.

[0078] Next, in the trenches 11, 21 to 23 with the oxide film formed on the inner walls, polysilicon doped with n-type or p-type impurities is deposited using a CVD (chemical vapor deposition) method or the like to form the gate electrode 11a, the diode electrode 21a, the capacitance adjustment electrode 22a, and the intersection trench electrode 23a.

[0079] The method for manufacturing the semiconductor device 81 of the first embodiment can manufacture the semiconductor device 81 including the active trench 11, the diode trench 21, the capacitance adjustment trench 22, and the intersection trench 23 without increasing the number of manufacturing steps by simultaneously performing the above-mentioned steps (a) to (d).

[0080] <Embodiment 2> Fig. 4 is a cross-sectional view showing the cross-sectional structure of a semiconductor device 82 according to the second embodiment of the present disclosure. Fig. 4 corresponds to the cross-sectional structure taken along the line AA in Fig. 1 shown in the first embodiment. An XYZ orthogonal coordinate system is depicted in Fig. 4.

[0081] Hereinafter, structures similar to those of the semiconductor device 81 of the first embodiment shown in FIGS. 1 to 3 will be given the same reference numerals and explanations thereof will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 82 of the second embodiment.

[0082] As shown in FIG. 4, the semiconductor device 82 has a structure in which the carrier accumulation layer 2 and the anode layer 25 in the diode region 20 are replaced with an anode layer 25B.

[0083] The anode layer 25B is provided adjacent to the first main surface S1 side of the drift layer 1. That is, the lower surface of the anode layer 25B coincides with the upper surface of the drift layer 1. In this manner, the anode layer 25B has a formation depth corresponding to the combined structure of the anode layer 25 and the carrier accumulation layer 2 of the first embodiment.

[0084] As shown in FIG. 4, the diode trench 21 and the plurality of capacitance adjustment trenches 22 are provided in regions that extend from the first main surface S1 through the anode layer 25B and reach a part of the drift layer 1.

[0085] Furthermore, the anode layer 25B provided in the diode region 20 is formed deeper toward the second main surface S2 than the base layer 15. That is, the anode layer 25B is formed deeper than the base layer 15 by the thickness of the carrier accumulation layer 2 of the first embodiment.

[0086] In the semiconductor device 82 of the second embodiment, the anode layer 25B provided in the diode region 20 has a structure formed to a greater depth than the base layer 15 provided in the IGBT region 10. Therefore, the semiconductor device 82 of the second embodiment can increase the input capacitance of the IGBT.

[0087] The reason why the input capacitance of the IGBT can be increased will be explained below. The gate-emitter parasitic capacitance Cge, which is part of the input capacitance, is proportional to the contact area between the anode layer 25B and the capacitance adjustment trench 22. Therefore, by increasing the depth of the anode layer 25B relative to the base layer 15, the contact area increases, and as a result, the input capacitance of the IGBT increases.

[0088] The method for manufacturing the semiconductor device 82 of the second embodiment can simultaneously perform steps (a) to (d) similar to those of the first embodiment, and can achieve the same effects as those of the first embodiment.

[0089] <Third Embodiment> Fig. 5 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 83 according to a third embodiment of the present disclosure. Fig. 5 corresponds to the cross-sectional structure taken along line AA in Fig. 1 shown in the first embodiment. An XYZ orthogonal coordinate system is depicted in Fig. 5.

[0090] Hereinafter, structures similar to those of the semiconductor device 81 of embodiment 1 shown in Figures 1 to 3 or the semiconductor device 82 of embodiment 2 shown in Figure 4 will be given the same reference symbols and explanations will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 83 of embodiment 3.

[0091] 5, in the semiconductor device 83 of the third embodiment, the plurality of capacitance adjustment trenches are classified into adjacent capacitance adjustment trenches 22x and capacitance adjustment trenches 32. The adjacent capacitance adjustment trenches 22x are trenches provided at positions closest to the active trench 11. The capacitance adjustment trenches 32 function as intermediate capacitance adjustment trenches other than the capacitance adjustment trenches 22.

[0092] A capacitance adjustment electrode 32a is buried in the capacitance adjustment trench 32 via a capacitance adjustment insulating film 32b. Hereinafter, in the description of the device structure, with regard to the capacitance adjustment trench 32, the completed structure including the capacitance adjustment electrode 32a and the capacitance adjustment insulating film 32b may be simply referred to as the "capacitance adjustment trench 32."

[0093] The intersection trench 23 is provided between the adjacent capacitance adjustment trench 22x and the capacitance adjustment trench 32 in plan view, and the capacitance adjustment electrode 22a of the adjacent capacitance adjustment trench 22x and the capacitance adjustment electrode 32a of the capacitance adjustment trench 32 are electrically connected via the intersection trench electrode 23a.

[0094] The adjacent capacitance adjustment trench 22x has a first depth that penetrates from the first main surface S1 side through the anode layer 25B and reaches a part of the drift layer 1.

[0095] On the other hand, the capacitance adjustment trench 32, which is an intermediate capacitance adjustment trench, has a second depth such that its bottom surface is provided within the anode layer 25B. That is, the second depth of the capacitance adjustment trench 32 is shallower than the first depth of the capacitance adjustment trench 22. Therefore, the capacitance adjustment trenches 22 and 32 in the semiconductor device 83 of the third embodiment are provided from the first main surface S1 side to at least a part of the anode layer 25B.

[0096] In the semiconductor device 83 of the third embodiment, the formation depth of the capacitance adjustment trench 32, which is the middle capacitance adjustment trench among the plurality of capacitance adjustment trenches, is set to the second depth, thereby making it possible to reduce the feedback capacitance value due to the plurality of capacitance adjustment electrodes in the IGBT. Note that the plurality of capacitance adjustment electrodes include the capacitance adjustment electrode 22a of the adjacent capacitance adjustment trench 22x and the capacitance adjustment electrode 32a of the capacitance adjustment trench 32.

[0097] Since the bottom of the capacitance adjusting trench 32 shown in FIG. 5 exists in the anode layer 25B, the feedback capacitance in the capacitance adjusting trench 32 is substantially "0".

[0098] As a result, the semiconductor device 82 of the third embodiment can reduce the feedback capacitance in the IGBT, thereby shortening the turn-on rise time, the turn-off fall time, and reducing power loss.

[0099] Furthermore, since the adjacent capacitance adjustment trenches 22x have a first depth that penetrates the anode layer 25B and reaches a part of the drift layer 1, a decrease in the breakdown voltage of the semiconductor device 83 can be suppressed.

[0100] That is, by depleting the region sandwiched between the adjacent active trench 11y and the adjacent capacitance adjustment trench 22x, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 83. Specifically, the sandwiched region corresponds to the carrier accumulation layer 2 and the base layer 15.

[0101] 5 shows only one capacitance adjustment trench 32 as the intermediate capacitance adjustment trench, a plurality of intermediate capacitance adjustment trenches may be formed. In this case, at least one of the plurality of intermediate capacitance adjustment trenches may be formed to the second depth like the capacitance adjustment trench 32, and the other intermediate capacitance adjustment trenches may be formed to the first depth like the capacitance adjustment trench 22.

[0102] The method for manufacturing the semiconductor device 83 of the third embodiment can simultaneously perform steps (a) to (d) similar to those of the first embodiment, and can achieve the same effects as those of the first embodiment.

[0103] However, since the formation depth of the capacitance adjustment trench 32 is different from that of the trenches 11, 21 to 23, it is desirable to form the capacitance adjustment trench 32 at a timing different from that of steps (a) to (d). Note that the active trench 11, the diode trench 21, and the intersection trench 23 are formed to a first depth.

[0104] <Fourth Embodiment> Fig. 6 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 84 according to embodiment 4 of the present disclosure. Fig. 6 corresponds to the cross-sectional structure taken along line AA in Fig. 1 shown in embodiment 1. An XYZ orthogonal coordinate system is depicted in Fig. 6.

[0105] Hereinafter, structures similar to those of the semiconductor device 81 of embodiment 1 shown in Figures 1 to 3 or the semiconductor device 82 of embodiment 2 shown in Figure 4 will be given the same reference symbols and explanations will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 84 of embodiment 4.

[0106] 6, adjacent active trenches 11, 11 among the multiple active trenches 11 are evenly arranged with an active trench pitch P1, which is a first interval, between them. That is, the multiple active trenches 11 are arranged discretely at equal intervals along the X direction.

[0107] 6, adjacent capacitance adjustment trenches 22, 22 among the plurality of capacitance adjustment trenches 22 are spaced apart by a capacitance adjustment trench pitch P2, which is a second interval. That is, the plurality of capacitance adjustment trenches 22 are spaced apart at equal intervals along the X direction. The capacitance adjustment trench pitch P2, which is the second interval, is narrower than the active trench pitch P1, which is the first interval.

[0108] In the semiconductor device 84 of the fourth embodiment, adjacent capacitance adjustment trenches 22, 22 among the plurality of capacitance adjustment trenches 22 are spaced apart by a capacitance adjustment trench pitch P2 that is narrower than the active trench pitch P1 between adjacent active trenches 11, 11.

[0109] Therefore, in the semiconductor device 84 of the fourth embodiment, a larger total number of capacitance adjustment trenches 22 than the total number of active trenches 11 can be provided in a formation region of the same area.

[0110] As a result, in the semiconductor device 54 of the fourth embodiment, the total number of the capacitance adjustment trenches 22 is increased, and accordingly the input capacitance of the IGBT can be increased.

[0111] The method for manufacturing the semiconductor device 84 of the fourth embodiment can simultaneously perform steps (a) to (d) similar to those of the first embodiment, and can achieve the same effects as those of the first embodiment.

[0112] However, steps (a) and (c) must be performed by setting the pattern of the openings so that the active trench pitch P1 between adjacent active trenches 11, 11 and the capacitance adjustment trench pitch P2 between adjacent capacitance adjustment trenches 22, 22 are different.

[0113] <Fifth Embodiment> Fig. 7 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 85 according to a fifth embodiment of the present disclosure. Fig. 7 corresponds to the cross-sectional structure taken along line AA in Fig. 1 shown in the first embodiment. An XYZ orthogonal coordinate system is depicted in Fig. 7.

[0114] Hereinafter, structures similar to those of the semiconductor device 81 of embodiment 1 shown in Figures 1 to 3 or the semiconductor device 82 of embodiment 2 shown in Figure 4 will be given the same reference symbols and explanations will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 85 of embodiment 5.

[0115] 7, a semiconductor device 85 of the fifth embodiment is characterized in that the plurality of capacitance adjustment trenches 22 are replaced with a plurality of capacitance adjustment trenches 42. Note that the adjacent capacitance adjustment trench 42x corresponds to the adjacent capacitance adjustment trench 22x, and is provided at a position closest to the boundary L12.

[0116] Similar to the capacitance adjustment trenches 22 of the second embodiment, each of the capacitance adjustment trenches 42 is provided in a region that extends from the first main surface S1 side of the semiconductor substrate 40 through the anode layer 25 and reaches a part of the drift layer 1.

[0117] A capacitance adjustment electrode 42a is buried in the capacitance adjustment trench 42 via a capacitance adjustment insulating film 42b. Hereinafter, in the description of the device structure, with regard to the capacitance adjustment trench 42, the completed structure including the capacitance adjustment electrode 42a and the capacitance adjustment insulating film 42b may be simply referred to as the "capacitance adjustment trench 42."

[0118] As in the first embodiment, the multiple intersection trenches 23 are each provided from the adjacent capacitance adjustment trench 42x to the adjacent active trench 11y in a planar view, and the gate electrode 11a of the adjacent active trench 11y and the capacitance adjustment electrode 42a of the adjacent capacitance adjustment trench 42x are electrically connected via the intersection trench electrode 23a in the intersection trench 23.

[0119] Additionally, similarly to the first embodiment, the intersection trench 23 is provided between the plurality of capacitance adjustment trenches 42 in plan view, and the plurality of capacitance adjustment electrodes 42a are electrically connected to each other via the intersection trench electrode 23a.

[0120] The gate insulating film 11b of the active trench 11 has a first thickness. Similarly, the diode insulating film 21b of the diode trench 21 has a first thickness.

[0121] On the other hand, the capacitance adjustment insulating film 42b of the capacitance adjustment trench 42 has a second film thickness that is thinner than the first film thickness. Similarly, the intersection trench insulating film 23b of the intersection trench 23 (not shown in FIG. 7) also has the second film thickness.

[0122] In the semiconductor device 85 of the fifth embodiment, the capacitance adjusting insulating film 42b and the intersection trench insulating film 23b have a second film thickness that is thinner than the first film thickness of the diode insulating film 21b, thereby increasing the input capacitance of the IGBT.

[0123] This is because the capacitance component contributing to the input capacitance of the IGBT increases as the thickness of the capacitance adjustment insulating film 42b is made thinner in each of the plurality of capacitance adjustment trenches 42. Similarly, the capacitance component contributing to the input capacitance of the IGBT increases as the thickness of the intersection trench insulating film 23b is made thinner in each of the plurality of intersection trenches 23.

[0124] The method for manufacturing the semiconductor device 85 of the fifth embodiment can simultaneously perform steps (a) to (d) similar to those of the first embodiment, and can achieve the same effects as those of the first embodiment.

[0125] However, in step (c), capacitance adjustment trenches 42 are formed instead of the capacitance adjustment trenches 22, and the film thickness of the intersection trench insulating film 23b in the intersection trenches 23 is set to the second film thickness.

[0126] The trenches 11, 21, 42, and 23 are completed, for example, through the steps shown below. Here, an oxide film is used as the insulating film.

[0127] The semiconductor substrate 40 is heated in an atmosphere containing oxygen to form oxide films on the inner walls of the trenches 11, 21, 42, and 23 and on the first main surface S1 of the semiconductor substrate 40. The oxide film in the capacitance adjustment trench 42 becomes the capacitance adjustment insulating film 42b, and the oxide film in the intersection trench 23 becomes the intersection trench insulating film 23b. The capacitance adjustment insulating film 42b and the intersection trench insulating film 23b are manufactured to have the second film thickness described above.

[0128] As described above, in the fifth embodiment, the intersection trench insulating film 23b is formed to have the second film thickness, which is the same as the capacitance adjusting insulating film 42b.

[0129] Next, in the trenches 11, 21, 42, 23 with the oxide film formed on the inner walls thereof, polysilicon doped with n-type or p-type impurities is deposited by a CVD method or the like to form a capacitance adjustment electrode 42a in the capacitance adjustment trench 42 and an intersection trench electrode 23a in the intersection trench 23. At this time, the electrode material is also buried inside the active trench 11 and the diode trench 21.

[0130] Thereafter, the upper surfaces of the capacitance adjusting trenches 42 and the intersection trenches 23 are coated with resist by photolithography, and then the oxide film and electrode material formed inside the active trenches 11 and the diode trenches 21 are removed.

[0131] After removing the resist, the above-described oxide film formation method and CVD method are used to form the gate insulating film 11b and gate electrode 11a in the active trench 11, and the diode insulating film 21b and diode electrode 21a in the diode trench 21. At this time, the gate insulating film 11b and diode insulating film 21b are manufactured to have the above-described first film thickness.

[0132] As another method for manufacturing the trench structure of the fifth embodiment, a method can be considered in which the first trench group is the active trenches 11 and the diode trenches 21, the second trench group is the capacitance adjustment trenches 42 and the intersection trenches 23, and the first trench group and the second trench group are manufactured in separate processes.

[0133] <Sixth Embodiment> 8 is a plan view showing the planar structure of a semiconductor device 86 according to a sixth embodiment of the present disclosure, as viewed from above. An XYZ Cartesian coordinate system is depicted in Fig. 8. Note that Fig. 8 does not show the interlayer insulating film 4 and the emitter electrode 6, which are structures on the upper surface of the semiconductor substrate 40.

[0134] Hereinafter, structures similar to those of the semiconductor device 81 of the first embodiment shown in Figures 1 to 3 will be given the same reference numerals and explanations thereof will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 86 of the sixth embodiment.

[0135] As shown in FIG. 8, compared to the semiconductor device 81 of the first embodiment, the semiconductor device 86 of the sixth embodiment is characterized in that the diode trench 21 is replaced with a diode trench 31, the capacitance adjustment trench 22 is replaced with a capacitance adjustment trench 52, and the intersection trench 23 is replaced with an intersection trench 33.

[0136] Similar to the diode trenches 21 of the first embodiment, each of the plurality of diode trenches 31 is provided in a region that extends from the first main surface S1 side of the semiconductor substrate 40 through the anode layer 25 and the carrier accumulation layer 2 to reach a part of the drift layer 1.

[0137] A diode electrode 31a is buried in each of the plurality of diode trenches 31 via a diode insulating film 31b. The diode insulating film 31b is formed on the inner wall of the diode trench 31. Hereinafter, in the description of the device structure, the completed structure including the diode electrode 31a and the diode insulating film 31b of the diode trench 31 may be simply referred to as the "diode trench 31."

[0138] 8 shows only one capacitance adjustment trench 52, but in reality, a plurality of capacitance adjustment trenches 52 are provided in the diode region 20. In the following description, it is assumed that a plurality of capacitance adjustment trenches 52 are formed in the diode region 20.

[0139] Similar to the plurality of capacitance adjustment trenches 22 of the first embodiment, each of the plurality of capacitance adjustment trenches 52 is provided in a region extending from the first main surface S1 side of the semiconductor substrate 40 through the anode layer 25 and the carrier accumulation layer 2 to reach a part of the drift layer 1.

[0140] A capacitance adjustment electrode 52a is buried via a capacitance adjustment insulating film 52b in each of the plurality of capacitance adjustment trenches 52. In the following description of the device structure, with regard to the capacitance adjustment trench 52, the completed structure including the capacitance adjustment electrode 52a and the capacitance adjustment insulating film 52b may be simply referred to as the "capacitance adjustment trench 52."

[0141] Similar to the intersection trenches 23 of the first embodiment, each of the multiple intersection trenches 33 is provided in a region that extends from the first main surface S1 side of the semiconductor substrate 40 through the base layer 15 or the anode layer 25 and the carrier accumulation layer 2 to reach a part of the drift layer 1.

[0142] An intersection trench electrode 33a is buried in each of the multiple intersection trenches 33 via an intersection trench insulating film 33b. The capacitance adjustment insulating film 22b is formed on the inner wall of the intersection trench 33. In the following description of the device structure, the completed structure of the intersection trench 33, including the intersection trench electrode 33a and the intersection trench insulating film 33b, may be simply referred to as the "intersection trench 33."

[0143] As shown in FIG. 8, among the plurality of diode trenches 31 and the plurality of capacitance adjustment trenches 52, the diode trench 31 is provided at a position closest to the active trench 11.

[0144] That is, the plurality of diode trenches 31 have an adjacent diode trench 31x provided at a position closest to the adjacent active trench 11y, and the plurality of capacitance adjustment trenches 52 have an adjacent capacitance adjustment trench 52x adjacent to the adjacent diode trench 31x in a direction away from the adjacent active trench 11y.

[0145] As described above, the semiconductor device 86 of the sixth embodiment has a planar structure in which the adjacent diode trench 31x is adjacent to the adjacent active trench 11y, but the adjacent capacitance adjustment trench 52x is not adjacent to the adjacent active trench 11y.

[0146] 8, the plurality of diode trenches 31 are provided in a stripe pattern, each extending in the Y direction in plan view. Similarly, the plurality of capacitance adjustment trenches 52 are provided in a stripe pattern, each extending in the Y direction in plan view.

[0147] Furthermore, as shown in FIG. 8, each of the plurality of diode trenches 31 includes partial trenches 311 to 313 as a plurality of partial trenches that are provided separately with trench non-formation regions 300 interposed therebetween.

[0148] On the other hand, the multiple intersection trenches 33 are each provided in a stripe pattern extending in the X direction that intersects the Y direction at a right angle in plan view. Specifically, the multiple intersection trenches 33 are each provided from the adjacent capacitance adjustment trench 52x to the adjacent active trench 11y in plan view, and the gate electrode 11a of the adjacent active trench 11y and the capacitance adjustment electrode 52a of the adjacent capacitance adjustment trench 52x are electrically connected to each other via the intersection trench electrode 33a in the intersection trench 33.

[0149] Furthermore, the intersection trench 33 is provided so as to intersect the trench non-formation region 300 of the adjacent diode trench 31x in plan view. That is, the intersection trench 33 is provided so as to extend from the adjacent capacitance adjustment trench 52x to the adjacent active trench 11y, intersecting the trench non-formation region 300 in plan view.

[0150] In this way, the intersection trench 33 is provided so as to intersect the trench-free region 300, and therefore there is no electrical connection between the intersection trench electrode 33a and the diode electrode 31a of the adjacent diode trench 31x.

[0151] Therefore, the intersection trench 33 is provided from the adjacent capacitance adjustment trench 52x to the adjacent active trench 11y in a planar view, and the capacitance adjustment electrode 52a of the adjacent capacitance adjustment trench 52x and the gate electrode 11a of the adjacent active trench 11y are electrically connected via the intersection trench electrode 33a, and there is no electrical connection between the diode electrode 31a of the adjacent diode trench 31x and the intersection trench electrode 33a.

[0152] In addition, similar to the first embodiment, the multiple intersection trenches 33 are each provided between the multiple capacitance adjustment trenches 52, 52 in a planar view, and the capacitance adjustment electrodes 52a between the capacitance adjustment trenches 52, 52 adjacent to each other in the X direction are electrically connected to each other via the intersection trench electrodes 33a in the intersection trenches 33.

[0153] Specifically, the intersection trench 33 is formed between a pair of adjacent capacitance adjustment trenches 52, 52, and is provided so as to intersect the trench non-formation region 300 of the diode trench 31 in plan view.

[0154] In the semiconductor device 86 of the sixth embodiment, an adjacent diode trench 31x is provided at a position closest to the active trench 11 among the plurality of diode trenches 31 and the plurality of capacitance adjustment trenches 52.

[0155] Therefore, in the semiconductor device 86 of the sixth embodiment, a plurality of capacitance adjustment trenches 52 can be formed in the central region of the diode region 20, and therefore the capacitance balance within the diode region 20 can be equalized.

[0156] By equalizing the capacitance balance within the diode region 20, it is possible to suppress the current imbalance phenomenon in which current is locally concentrated within the diode region 20.

[0157] The multiple intersection trenches 33 in the semiconductor device 86 of embodiment 6 are arranged to intersect with the trench non-formation region 300 in a planar view, and therefore the intersection trenches 33 do not intersect with any of the multiple partial trenches, i.e., the partial trenches 311 to 313, in a planar view.

[0158] Therefore, in the semiconductor device 86 of the sixth embodiment, the plurality of intersection trenches 33 can be formed relatively easily so that the intersection trench electrodes 33a and the diode electrodes 31a are not electrically connected to each other.

[0159] In this way, even if an adjacent diode trench 31x exists between the adjacent active trench 11y and the adjacent capacitance adjustment trench 52x in a planar view, the diode electrode 31a of the adjacent diode trench 31x does not have an electrical connection relationship with the intersection trench electrode 33a or the capacitance adjustment electrode 52a.

[0160] As an arrangement relationship between the plurality of diode trenches 31 and the plurality of capacitance adjustment trenches 52 in the diode region 20, for example, a planar structure in which the diode trenches 31 and the capacitance adjustment trenches 52 are alternately formed for every i (i = 1 to N (> 1)) trenches can be considered.

[0161] The method for manufacturing the semiconductor device 86 of the sixth embodiment can simultaneously carry out steps (a) to (d) similar to those of the first embodiment, and can achieve the same effects as those of the first embodiment.

[0162] However, in step (b), diode trench 31 is formed instead of diode trench 21. Similarly, in step (c), capacitance adjustment trench 52 is formed instead of capacitance adjustment trench 22, and in step (d), intersection trench 33 is formed instead of intersection trench 23.

[0163] <Other> It should be noted that, within the scope of the present disclosure, it is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0164] For example, the semiconductor substrate 40 may be a substrate with a set breakdown voltage class, a FZ (Float Zone) resistant substrate, an MCZ (Magnetic field applied CZ (Czochralski)) substrate, an epitaxial substrate, etc. However, the semiconductor substrate 40 is not limited to the above-mentioned substrates and can be applied. Features of each embodiment may also be partially applied to other embodiments.

[0165] Furthermore, the structures shown in the third to fifth embodiments may be provided in the diode region 20 of the first embodiment having the anode layer 25 and the carrier accumulation layer 2 .

[0166] In the above-described embodiment, the planar structures of the active trenches 11 and 21, the diode trenches 21 and 31, and the capacitance adjustment trenches 22, 32, 42, and 52 are formed in a stripe shape. However, the planar structure is not limited to this, and for example, the planar structures of the trenches 11, 21, 21, 31, 22, 32, 42, and 52 described above may be formed in an island shape.

[0167] Various aspects of the present disclosure are summarized below as appendices.

[0168] (Appendix 1) A semiconductor device including an IGBT region having an IGBT therein and a diode region having a diode therein, a semiconductor substrate having first and second main surfaces; a first conductivity type drift layer provided in the semiconductor substrate; a second conductivity type base layer provided in the semiconductor substrate and selectively disposed on the first main surface side of the drift layer; a second conductivity type anode layer provided on the semiconductor substrate and selectively disposed on the first main surface side of the drift layer; an emitter electrode provided on the first main surface of the semiconductor substrate, the drift layer and the emitter electrode are shared between the IGBT region and the diode region, the base layer is used in the IGBT region, and the anode layer is used in the diode region; The semiconductor device includes: an active trench provided in a region that penetrates the base layer from the first main surface side and reaches a part of the drift layer; a diode trench provided in a region that penetrates the anode layer from the first principal surface side and reaches a part of the drift layer; a capacitance adjusting trench provided from the first principal surface side to at least a part of the anode layer; an intersection trench provided in a region that penetrates the base layer or the anode layer from the first main surface side and reaches a part of the drift layer, the intersection trench is shared between the IGBT region and the diode region, the active trench is used in the IGBT region, and the diode trench and the capacitance adjustment trench are used in the diode region; a gate electrode is embedded in the active trench via a gate insulating film; a diode electrode is buried in the diode trench via a diode insulating film; a capacitance adjustment electrode is buried in the capacitance adjustment trench via a capacitance adjustment insulating film; an intersection trench electrode is buried in the intersection trench via an intersection trench insulating film; the diode electrode is electrically connected to the emitter electrode; the intersection trench is provided from the capacitance adjustment trench to the active trench in a plan view, and the gate electrode and the capacitance adjustment electrode are electrically connected via the intersection trench electrode. Semiconductor device.

[0169] (Appendix 2) 10. The semiconductor device according to claim 1, the capacitance adjustment trenches include a plurality of capacitance adjustment trenches, and the capacitance adjustment electrodes include a plurality of capacitance adjustment electrodes corresponding to the plurality of capacitance adjustment trenches; the intersection trench is provided between the plurality of capacitance adjustment trenches in plan view, and the plurality of capacitance adjustment electrodes are electrically connected to each other via the intersection trench electrode; Semiconductor device.

[0170] (Appendix 3) 3. The semiconductor device according to claim 2, the capacitance adjustment trench is provided in a region that penetrates the anode layer from the first main surface side and reaches a part of the drift layer, the anode layer is formed deeper toward the second main surface than the base layer; Semiconductor device.

[0171] (Appendix 4) The semiconductor device according to claim 2 or 3, the plurality of capacitance adjustment trenches include an adjacent capacitance adjustment trench provided at a position closest to the active trench and an intermediate capacitance adjustment trench other than the adjacent capacitance adjustment trench; the adjacent capacitance adjustment trench has a first depth, the first depth being a depth that penetrates the anode layer from the first main surface side and reaches a part of the drift layer; the intermediate capacitance adjusting trench has a second depth with a bottom surface disposed within the anode layer; Semiconductor device.

[0172] (Appendix 5) The semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 4, the active trenches include a plurality of active trenches, and the gate electrodes include a plurality of gate electrodes corresponding to the plurality of active trenches; Adjacent active trenches among the plurality of active trenches are arranged with a first interval therebetween, Adjacent capacitance adjustment trenches among the plurality of capacitance adjustment trenches are arranged at a second interval that is narrower than the first interval. Semiconductor device.

[0173] (Appendix 6) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, the gate insulating film has a first thickness; the capacitance adjusting insulating film has a second film thickness that is thinner than the first film thickness; Semiconductor device.

[0174] (Appendix 7) A semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, the diode trenches include an adjacent diode trench provided at a position closest to the active trench; the capacitance adjustment trenches include adjacent capacitance adjustment trenches adjacent to the adjacent diode trenches in a direction away from the active trench; the intersection trench is provided from the adjacent capacitance adjustment trench to the active trench in plan view, the capacitance adjustment electrode of the adjacent capacitance adjustment trench is electrically connected to the gate electrode via the intersection trench electrode, and the diode electrode of the adjacent diode trench is not electrically connected to the intersection trench electrode; Semiconductor device.

[0175] (Appendix 8) 8. The semiconductor device according to claim 7, the adjacent diode trenches include a plurality of partial trenches that are spaced apart from each other with a trench-free region interposed therebetween, The intersection trench is provided so as to intersect the trench non-formation region in a plan view. Semiconductor device.

[0176] (Appendix 9) A method for manufacturing a semiconductor device, comprising the steps of: manufacturing a semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 8; (a) forming the active trench; (b) forming the diode trench; (c) forming the capacitance adjustment trench; (d) forming the intersection trenches; The steps (a) to (d) are performed simultaneously. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0177] 1 drift layer, 2 carrier accumulation layer, 3 buffer layer, 4 interlayer insulating film, 6 emitter electrode, 7 collector electrode, 15 base layer, 10 IGBT region, 11 active trench, 11a gate electrode, 11b gate insulating film, 16 collector layer, 20 diode region, 21, 31 diode trench, 21a, 31a diode electrode, 21b, 31b diode insulating film, 22, 32, 42, 52 capacitance adjustment trench, 22a, 32a, 42a, 52a capacitance adjustment electrode, 22b, 32b, 42b, 52b capacitance adjustment insulating film, 23, 33 intersection trench, 23a, 33a intersection trench electrode, 23b, 33b intersection trench insulating film, 25, 25B anode layer, 26 cathode layer, 40 semiconductor substrate, 81 to 86 semiconductor device, S1 First principal surface, S2 second principal surface.

Claims

1. A semiconductor device including an IGBT region having an IGBT therein and a diode region having a diode therein, a semiconductor substrate having first and second main surfaces; a first conductivity type drift layer provided in the semiconductor substrate; a second conductivity type base layer provided in the semiconductor substrate and selectively disposed on the first main surface side of the drift layer; a second conductivity type anode layer provided on the semiconductor substrate and selectively disposed on the first main surface side of the drift layer; an emitter electrode provided on the first main surface of the semiconductor substrate, the drift layer and the emitter electrode are shared between the IGBT region and the diode region, the base layer is used in the IGBT region, and the anode layer is used in the diode region; The semiconductor device includes: an active trench provided in a region that penetrates the base layer from the first main surface side and reaches a part of the drift layer; a diode trench provided in a region that penetrates the anode layer from the first principal surface side and reaches a part of the drift layer; a capacitance adjusting trench provided from the first principal surface side to at least a part of the anode layer; an intersection trench provided in a region that penetrates the base layer or the anode layer from the first main surface side and reaches a part of the drift layer, the intersection trench is shared between the IGBT region and the diode region, the active trench is used in the IGBT region, and the diode trench and the capacitance adjustment trench are used in the diode region; the capacitance adjusting trench is provided only between the active trench and the diode trench; a gate electrode is embedded in the active trench via a gate insulating film; a diode electrode is buried in the diode trench via a diode insulating film; a capacitance adjustment electrode is buried in the capacitance adjustment trench via a capacitance adjustment insulating film; an intersection trench electrode is buried in the intersection trench via an intersection trench insulating film; the diode electrode is electrically connected to the emitter electrode; the intersection trench is provided from the capacitance adjustment trench to the active trench in plan view, and the gate electrode and the capacitance adjustment electrode are electrically connected via the intersection trench electrode. Semiconductor device.

2. 2. The semiconductor device according to claim 1, the capacitance adjustment trenches include a plurality of capacitance adjustment trenches, and the capacitance adjustment electrodes include a plurality of capacitance adjustment electrodes corresponding to the plurality of capacitance adjustment trenches; the intersection trench is provided between the plurality of capacitance adjustment trenches in plan view, and the plurality of capacitance adjustment electrodes are electrically connected to each other via the intersection trench electrode; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the capacitance adjustment trench is provided in a region that penetrates the anode layer from the first main surface side and reaches a part of the drift layer, the anode layer is formed deeper toward the second main surface than the base layer; Semiconductor device.

4. 4. The semiconductor device according to claim 2, wherein: the plurality of capacitance adjustment trenches include an adjacent capacitance adjustment trench provided at a position closest to the active trench and an intermediate capacitance adjustment trench other than the adjacent capacitance adjustment trench; the adjacent capacitance adjustment trench has a first depth, the first depth being a depth that penetrates the anode layer from the first main surface side and reaches a part of the drift layer; the intermediate capacitance adjusting trench has a second depth with a bottom surface disposed within the anode layer; Semiconductor device.

5. 4. The semiconductor device according to claim 2, wherein: the active trenches include a plurality of active trenches, and the gate electrodes include a plurality of gate electrodes corresponding to the plurality of active trenches; Adjacent active trenches among the plurality of active trenches are arranged with a first interval therebetween, Adjacent capacitance adjustment trenches among the plurality of capacitance adjustment trenches are disposed at a second interval that is narrower than the first interval. Semiconductor device.

6. 4. The semiconductor device according to claim 1, the gate insulating film has a first thickness; the capacitance adjusting insulating film has a second film thickness that is thinner than the first film thickness; Semiconductor device.

7. A semiconductor device comprising an IGBT region having an IGBT therein and a diode region having a diode therein, a semiconductor substrate having first and second main surfaces; a first conductivity type drift layer provided in the semiconductor substrate; a second conductivity type base layer provided in the semiconductor substrate and selectively disposed on the first main surface side of the drift layer; a second conductivity type anode layer provided on the semiconductor substrate and selectively disposed on the first main surface side of the drift layer; an emitter electrode provided on the first main surface of the semiconductor substrate, the drift layer and the emitter electrode are shared between the IGBT region and the diode region, the base layer is used in the IGBT region, and the anode layer is used in the diode region; The semiconductor device includes: an active trench provided in a region that penetrates the base layer from the first main surface side and reaches a part of the drift layer; a diode trench provided in a region that penetrates the anode layer from the first principal surface side and reaches a part of the drift layer; a capacitance adjusting trench provided from the first principal surface side to at least a part of the anode layer; an intersection trench provided in a region that penetrates the base layer or the anode layer from the first main surface side and reaches a part of the drift layer, the intersection trench is shared between the IGBT region and the diode region, the active trench is used in the IGBT region, and the diode trench and the capacitance adjustment trench are used in the diode region; a gate electrode is embedded in the active trench via a gate insulating film; a diode electrode is buried in the diode trench via a diode insulating film; a capacitance adjustment electrode is buried in the capacitance adjustment trench via a capacitance adjustment insulating film; an intersection trench electrode is buried in the intersection trench via an intersection trench insulating film; the diode electrode is electrically connected to the emitter electrode; the intersection trench is provided from the capacitance adjustment trench to the active trench in a plan view, and the gate electrode and the capacitance adjustment electrode are electrically connected via the intersection trench electrode; the diode trenches include an adjacent diode trench provided at a position closest to the active trench; the capacitance adjustment trenches include adjacent capacitance adjustment trenches adjacent to the adjacent diode trenches in a direction away from the active trench; the intersection trench is provided from the adjacent capacitance adjustment trench to the active trench in plan view, the capacitance adjustment electrode of the adjacent capacitance adjustment trench is electrically connected to the gate electrode via the intersection trench electrode, and the diode electrode of the adjacent diode trench is not electrically connected to the intersection trench electrode; the adjacent diode trenches include a plurality of partial trenches that are spaced apart from each other with a trench-free region interposed therebetween, The intersection trench is provided so as to intersect the trench non-formation region in a plan view. Semiconductor device.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, comprising the steps of: (a) forming the active trench; (b) forming the diode trench; (c) forming the capacitance adjustment trench; (d) forming the intersection trenches; The steps (a) to (d) are performed simultaneously. A method for manufacturing a semiconductor device.

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