Power Module

Abstract

To reduce wiring inductance.SOLUTION: A power module comprises: a power substrate in which a switching element constituting at least six arms is mounted on one circuit board; and a driver substrate provided with drivers each driving each of the at least six arms. The power substrate and the driver substrate are disposed away from each other in the thickness direction of the substrates. If the power module is virtually divided into an upper arm side and a lower arm side, and the upper arm side is further virtually divided so that each of the substrates is divided into four blocks, then the corresponding blocks of each of the substrates overlap each other in the thickness direction of the substrates.SELECTED DRAWING: Figure 33

Description

[Technical Field]

[0001] The present invention relates to a power module. [Background technology]

[0002] Conventionally, there is a three-phase bridge inverter circuit in which six diodes are bridge-connected (see Patent Document 1). Also known is a power module in which power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) are mounted on a substrate, and the necessary circuits are configured using wiring conductors and bonding wires formed on the substrate. In such a power module, it is important to optimize the layout of the power semiconductor elements in order to reduce wiring inductance, which causes noise (see Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 7-40790 [Patent Document 2] JP 2017-55610 A Summary of the Invention [Problem to be solved by the invention]

[0004] In silicon (hereinafter referred to as Si)-based power semiconductor elements, increasing the switching speed increases the ON voltage of the power semiconductor element, resulting in greater losses in the steady ON state. For this reason, new power semiconductor elements are being developed that use silicon carbide (hereinafter referred to as SiC) or gallium nitride (GaN), materials that are less likely to increase the ON voltage even when the switching speed is fast, instead of Si.

[0005] Unlike IGBTs and power MOS (Metal-Oxide-Semiconductor) FETs used in conventional power modules, GaN-FETs (GaN Field-Effect Transistors) have all three electrodes (drain electrode, source electrode, and gate electrode) on one surface. If the surface of this GaN-FET with the three electrodes is called the front surface and the opposite surface is called the back surface, then when the GaN-FET is placed on a substrate, the back surface is oriented toward the substrate (bottom).

[0006] Therefore, even if the layout within a power module optimized for IGBTs or power MOSFETs, which have electrodes on the backside, is used as is, it is difficult to sufficiently reduce the wiring inductance that causes noise when a large current flows through the wiring pattern within the power module.In other words, it cannot be said that the chip layout on the power board has been fully optimized in power modules equipped with GaN-FETs.

[0007] Therefore, this disclosure proposes a power module equipped with GaN-based power semiconductor elements that can reduce noise generation by optimizing the arrangement of elements on a power board and reducing wiring inductance. [Means for solving the problem]

[0008] A power module according to one embodiment of the present disclosure comprises a power board on which switching elements constituting at least six arms are mounted on a single circuit board, and a driver board equipped with drivers for driving each of the at least six arms, and the power board and driver board are arranged at a distance in the thickness direction of the board, and when the board is virtually divided into an upper arm side and a lower arm side, and the upper arm side is further virtually divided so that each board is divided into four blocks, the corresponding blocks of each board overlap in the thickness direction of the board. [Effects of the Invention]

[0009] According to the present disclosure, wiring inductance can be reduced. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of a GaN-FET circuit. [Figure 2] FIG. 2 is a diagram showing an example of a circuit of a cascade type GaN-FET. [Figure 3] FIG. 3 is a diagram showing an example of a GaN-FET chip. [Figure 4] FIG. 4 is a diagram showing an example of a Si-FET chip. [Figure 5] FIG. 5 is a diagram showing an example of mounting a cascade type GaN-FET. [Figure 6] FIG. 6 is a diagram showing a circuit that receives DC as input and outputs three-phase AC. [Figure 7] FIG. 7 is a diagram showing a circuit that receives DC as input, boosts the input current while improving the power factor, and outputs single-phase AC. [Figure 8] FIG. 8 is a diagram (1) for explaining points to be noted in order to reduce the wiring inductance in the power module according to the first embodiment. [Figure 9] FIG. 9 is a diagram (2) for explaining points to be noted in order to reduce the wiring inductance in the power module according to the first embodiment. [Figure 10] FIG. 10 is a diagram for explaining the optimum arrangement of the first to sixth switching elements Q1 to Q6 and the capacitor C1 in the power module according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing an optimum layout when GaN-FETs are used instead of cascade-type GaN-FETs. [Figure 12] FIG. 12 is a diagram showing an example of the circuit of the circuit block A. As shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view and a top view showing the configuration of the power module according to the first embodiment. [Figure 14]FIG. 14 is a diagram for explaining that the power module according to the first embodiment achieves an optimal arrangement. [Figure 15] FIG. 15 is a diagram for explaining circuit loops 1-1 to 1-6 in the power module according to the first embodiment. [Figure 16] FIG. 16 is a diagram for explaining a circuit loop 2-1 in the power module according to the first embodiment. [Figure 17] FIG. 17 is a diagram for explaining circuit loops 3-1, 3-2, and 3-3 in the power module according to the first embodiment. [Figure 18] FIG. 18 is a diagram for explaining the common impedance in the power module according to the first embodiment. [Figure 19] FIG. 19 is a top view showing the configuration of a power module in a reference example. [Figure 20] FIG. 20 is a diagram for explaining circuit loops 1-1 to 1-6 in the power module in the reference example. [Figure 21] FIG. 21 is a diagram for explaining a circuit loop 2-1 in a power module in a reference example. [Figure 22] FIG. 22 is a diagram for explaining the circuit loop 3-1 in the power module in the reference example. [Figure 23] FIG. 23 is a diagram for explaining the common impedance in the power module in the reference example. [Figure 24] FIG. 24 is a diagram showing a first modification in which three capacitors are arranged. [Figure 25] FIG. 25 is a diagram showing a modification of the circuit shown in FIG. [Figure 26] FIG. 26 is a diagram showing a power board of the circuit shown in FIG. 25 as a second modified example. [Figure 27] FIG. 27 is a diagram for explaining the common impedance in the power module in the second modification. [Figure 28]FIG. 28 is a diagram showing a circuit configuration of a power module according to the second embodiment. [Figure 29] FIG. 29 is a cross-sectional view and a top view showing the configuration of the power module according to the second embodiment. [Figure 30] FIG. 30 is a diagram in which the power module according to the second embodiment is virtually divided into blocks for each circuit with high affinity. [Figure 31] FIG. 31 is a diagram in which the power board of the power module according to the second embodiment is divided into blocks in the manner shown in FIG. [Figure 32] FIG. 32 is a diagram in which the driver board of the power module according to the second embodiment is divided into blocks in the manner shown in FIG. [Figure 33] FIG. 33 is a diagram in which blocks on a power board and blocks on a driver board of the power module according to the second embodiment are superimposed. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the power module disclosed herein will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to the embodiments described below. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of elements may differ from the actual situation. Furthermore, the dimensional relationships and ratios may differ between the drawings.

[0012] Conventionally, power modules have been known in which power semiconductor elements such as IGBTs are mounted on a power substrate and wired with bonding wires to form the necessary circuits. In such power modules, it is important to optimize the layout of the power semiconductor elements in order to reduce wiring inductance, which causes noise.

[0013] On the other hand, GaN-FETs, a power semiconductor element that has been developed in recent years, differ from IGBTs and power MOSFETs used in conventional power modules in that all three electrodes (drain electrode, source electrode, and gate electrode) are provided on the front surface.

[0014] Therefore, even if the layout optimized for IGBTs and power MOSFETs, which have electrodes on the backside, is used as is, it is difficult to sufficiently reduce wiring inductance. In other words, it cannot be said that the chip layout on the circuit board is optimized for power modules equipped with GaN-FETs.

[0015] This is because, in conventional power semiconductor elements where the collector electrode and drain electrode are provided on the back surface, wiring is formed to the electrodes on the back surface using the circuit pattern on the power board, whereas in GaN-FETs where the drain electrode is provided on the front surface, wiring is formed to the drain electrode using a bonding wire.

[0016] Therefore, there is a need for technology that can reduce wiring inductance in power modules equipped with GaN-FETs.

[0017] <Configuration of switching element> The present disclosure relates to a power module using a switching element that is a GaN-FET or a cascade GaN-FET. To facilitate understanding of each embodiment of the present disclosure, GaN-FETs and cascade GaN-FETs applicable to each embodiment will be described with reference to FIGS.

[0018] Figure 1 shows an example of a GaN-FET circuit. In a GaN-FET, the current flowing from the drain to the source is controlled by controlling the voltage applied to the gate.

[0019] Fig. 2 is a diagram showing an example of a circuit of a cascade GaN-FET. As shown in Fig. 2, inside the cascade GaN-FET, the source terminal of the GaN-FET and the drain terminal of the Si-FET are electrically connected, and the source terminal of the Si-FET and the gate terminal of the GaN-FET are electrically connected.

[0020] The drain terminal of the GaN-FET becomes the drain electrode of the cascade GaN-FET, the source terminal of the Si-FET becomes the source electrode of the cascade GaN-FET, and the gate terminal of the Si-FET becomes the gate electrode of the cascade GaN-FET.

[0021] In a cascade GaN-FET with such a circuit configuration, a normally-on GaN-FET can be driven as a normally-off switching element. That is, in a cascade GaN-FET, the element can be turned off by inputting a low-level signal to the gate electrode (i.e., the gate terminal of the Si-FET). In addition, in a cascade GaN-FET, the element can be turned on by inputting a high-level signal to the gate electrode.

[0022] The cascade GaN-FET has high breakdown voltage characteristics because it can utilize the breakdown voltage characteristics of the GaN-FET. Furthermore, the cascade GaN-FET can utilize the characteristics of the low-voltage Si-FET to drive the gate, so it can be driven at high voltage without sacrificing the high speed of the GaN-FET.

[0023] FIG. 3 is a diagram showing an example of a GaN-FET. This GaN-FET is a bare chip without a package, and FIG. 3 is a top view of it. The GaN-FET has a rectangular outer shape with long and short sides. A drain pad is provided on the front surface of the GaN-FET near one of the long sides. This drain pad is provided along one of the long sides. A source pad is provided near the other long side. This source pad is provided along the other long side. In addition, a pair of gate pads are provided on the front surface of the GaN-FET along the other long side, sandwiching the source pad.

[0024] Fig. 4 is a diagram showing an example of a Si-FET. This Si-FET is a bare chip without a package, and Fig. 4 is a top view of the Si-FET. As shown in Fig. 4, the Si-FET has a source pad and a gate pad on the front surface and a drain pad on the back surface.

[0025] FIG. 5 shows an example of a cascade GaN-FET. (a) in FIG. 5 shows the cascade GaN-FET before resin encapsulation, and (b) in FIG. 5 shows the cascade GaN-FET after resin encapsulation. As shown in (a) in FIG. 5, the cascade GaN-FET is configured by stacking a rectangular GaN-FET and a rectangular Si-FET that is smaller than the GaN-FET. A source pad provided on the front surface of the GaN-FET and a drain pad provided on the back surface of the Si-FET are electrically and mechanically connected by a conductive bonding material such as solder or a conductive adhesive. As a result, the drain of the GaN-FET corresponds to the drain of the cascade GaN-FET, the source of the Si-FET corresponds to the source of the cascade GaN-FET, and the gate of the Si-FET corresponds to the gate of the cascade GaN-FET.

[0026] Furthermore, one drain lead frame of the GaN-FET is provided along the long side along which the drain pad of the cascade GaN-FET is located, a source lead frame is provided along the other long side of the GaN-FET, and a gate lead frame is provided along the short side of the GaN-FET on the side where the gate pad of the cascade GaN-FET is located. The drain pad and drain lead frame are connected with bonding wire such as AL (Aluminum) wire, the source pad and source lead frame are connected with bonding wire such as AL wire, and the gate pad and gate lead frame are connected with AL wire or the like. Furthermore, the two gate pads of the GaN-FET are connected with AL wire or the like to the source lead frame.

[0027] Furthermore, as shown in FIG. 5(b), after resin sealing, the drain pad, source pad, and gate pad are sealed with resin, and only parts of the drain, source, and gate lead frames are connected to the outside.

[0028] In addition to stacking a GaN-FET chip and a Si-FET chip (Chip on Chip), there are also cases where the cascade GaN-FET has two chips arranged in parallel and connected by wires, patterns, lead frames, etc.

[0029] <Circuit configuration of power module (first embodiment)> Next, the circuit configuration of the power module according to the first embodiment will be described with reference to FIGS. 6 to 12. FIGS. 6 and 7 are diagrams showing examples of circuits that can be realized using the power module according to the first embodiment. FIG. 6 is a diagram showing a circuit that inputs DC and outputs three-phase AC. In FIG. 6, a three-phase motor is shown as an example of an application of the output. Hereinafter, the circuit in FIG. 6 may be referred to as a motor control circuit. FIG. 7 shows a circuit that inputs DC, boosts the input current while improving the power factor, and outputs single-phase AC. Hereinafter, the circuit in FIG. 7 may be referred to as a boost-type single-phase inverter output circuit.

[0030] As shown in FIGS. 6 and 7, circuit block A includes six switching elements, namely, a first switching element Q1 to a sixth switching element Q6. Circuit block B includes circuit block A and six drive circuits, namely, a Q1-GaN-FET drive circuit to a Q6-GaN-FET drive circuit. Circuit block A and circuit block B can be applied to power conversion devices having various circuit configurations. An example of a power conversion device is an inverter. The power module 1 according to the first embodiment corresponds to a circuit block obtained by adding a capacitor C1 to circuit block A.

[0031] The first to sixth switching elements Q1 to Q6 are all configured with switching elements Q that are cascade type GaN-FETs and have approximately the same withstand voltage characteristics and switching characteristics. Note that the first to sixth switching elements Q1 to Q6 may all be GaN-FETs.

[0032] The drain terminal of the first switching element Q1 is connected to the positive terminal P, the source terminal of the first switching element Q1 is connected to the drain terminal of the second switching element Q2, the gate terminal of the first switching element Q1 is connected to the gate terminal Q1-G, and the source terminal of the first switching element Q1 is connected to the source terminal Q1-S.

[0033] The drain terminal of the second switching element Q2 is connected to the source terminal of the first switching element Q1, and the source terminal of the second switching element Q2 is connected to the negative terminal N. In addition, the gate terminal of the second switching element Q2 is connected to the gate terminal Q2-G, and the source terminal of the second switching element Q2 is connected to the source terminal Q2-S.

[0034] The drain terminal of the third switching element Q3 is connected to the positive terminal P, and the source terminal of the third switching element Q3 is connected to the drain terminal of the fourth switching element Q4. The gate terminal of the third switching element Q3 is connected to the gate terminal Q3-G, and the source terminal of the third switching element Q3 is connected to the source terminal Q3-S. Note that the gate terminal Q3-G and the source terminal Q3-S are omitted from FIGS. 6 and 7.

[0035] The drain terminal of the fourth switching element Q4 is connected to the source terminal of the third switching element Q3, and the source terminal of the fourth switching element Q4 is connected to the negative terminal N. The gate terminal of the fourth switching element Q4 is connected to the gate terminal Q4-G, and the source terminal of the fourth switching element Q4 is connected to the source terminal Q4-S. Note that the gate terminal Q4-G and the source terminal Q4-S are omitted from FIGS. 6 and 7.

[0036] The drain terminal of the fifth switching element Q5 is connected to the positive terminal P, and the source terminal of the fifth switching element Q5 is connected to the drain terminal of the sixth switching element Q6. The gate terminal of the fifth switching element Q5 is connected to the gate terminal Q5-G, and the source terminal of the fifth switching element Q5 is connected to the source terminal Q5-S. Note that the gate terminal Q5-G and the source terminal Q5-S are omitted from FIGS. 6 and 7.

[0037] The drain terminal of the sixth switching element Q6 is connected to the source terminal of the fifth switching element Q5, and the source terminal of the sixth switching element Q6 is connected to the negative terminal N. The gate terminal of the sixth switching element Q6 is connected to the gate terminal Q6-G, and the source terminal of the sixth switching element Q6 is connected to the source terminal Q6-S. Note that the gate terminal Q6-G and the source terminal Q6-S are omitted from FIGS. 6 and 7.

[0038] The capacitor C1 is a noise removal capacitor connected between the positive terminal P and the negative terminal N. The circuit block A also has output terminals OUT1, OUT2, and OUT3.

[0039] 6, the output terminal OUT1 of the power module 1 is connected between the source terminal of the first switching element Q1 and the drain terminal of the second switching element Q2. The output terminal OUT2 is connected between the source terminal of the third switching element Q3 and the drain terminal of the fourth switching element Q4. The output terminal OUT3 is connected between the source terminal of the fifth switching element Q5 and the drain terminal of the sixth switching element Q6.

[0040] The Q1-GaN-FET drive circuit drives the first switching element Q1, and the Q2-GaN-FET drive circuit drives the second switching element Q2. Although not shown in Figures 6 and 7, the Q3-GaN-FET drive circuit drives the third switching element Q3, the Q4-GaN-FET drive circuit drives the fourth switching element Q4, the Q5-GaN-FET drive circuit drives the fifth switching element Q5, and the Q6-GaN-FET drive circuit drives the sixth switching element Q6. The overall control block controls the Q1-GaN-FET drive circuit through the Q6-GaN-FET drive circuit.

[0041] 6 and 7, in order to reduce noise generated by large currents that are intermittently switched on and off by switching elements and to achieve more efficient power conversion, it is important to reduce the wiring inductance within circuit block A. Therefore, points to note in reducing the wiring inductance within circuit block A will be described with reference to FIGS. 8 and 9.

[0042] 8 is a diagram (1) for explaining points to be noted in order to reduce wiring inductance in the power module 1 according to the first embodiment. As shown in Fig. 8, inside the power module 1, circuit loops of various paths are formed by the current flows indicated by arrows.

[0043] For example, within the power module 1, a circuit loop 1-1 is formed in which the current output from the Q1-GaN-FET drive circuit that drives the first switching element Q1 returns in the following order: the gate terminal of the first switching element Q1, the source terminal of the first switching element Q1, and the Q1-GaN-FET drive circuit.

[0044] Furthermore, within the power module 1, a circuit loop 1-2 is formed in which the current output from the Q2-GaN-FET drive circuit that drives the second switching element Q2 returns in the following order: the gate terminal of the second switching element Q2, the source terminal of the second switching element Q2, and the Q2-GaN-FET drive circuit.

[0045] Similarly, within the power module 1, a circuit loop 1-3 is formed for the third switching element Q3, a circuit loop 1-4 is formed for the fourth switching element Q4, a circuit loop 1-5 is formed for the fifth switching element Q5, and a circuit loop 1-6 is formed for the sixth switching element Q6.

[0046] Furthermore, within the power module 1, a circuit loop 2-1 is formed in which a current flows in order from the positive terminal P to the first switching element Q1, the second switching element Q2, the negative terminal N, the fourth switching element Q4, the third switching element Q3, and the positive terminal P.

[0047] Furthermore, within the power module 1, a circuit loop 2-2 is formed in which a current flows in order from the positive terminal P to the third switching element Q3, the fourth switching element Q4, the negative terminal N, the sixth switching element Q6, the fifth switching element Q5, and the positive terminal P.

[0048] Also, within the power module 1, a circuit loop 3-1 is formed of a current that flows in order from the capacitor C1 to the positive terminal P, the first switching element Q1, the second switching element Q2, the negative terminal N, and the capacitor C1.

[0049] Also, within the power module 1, a circuit loop 3-2 is formed of a current that flows in order from the capacitor C1 to the positive terminal P, the third switching element Q3, the fourth switching element Q4, the negative terminal N, and the capacitor C1.

[0050] Also, within the power module 1, a circuit loop 3-3 is formed of a current that flows in order from the capacitor C1 to the positive terminal P, the fifth switching element Q5, the sixth switching element Q6, the negative terminal N, and the capacitor C1.

[0051] Furthermore, the power module 1 according to the first embodiment can reduce the noise generated from the circuit loops (hereinafter also referred to as generated noise) (reduce wiring inductance) by shortening the lengths of the above-mentioned circuit loops 1-1 to 1-6, circuit loops 2-1 and 2-2, and circuit loops 3-1 to 3-3 as much as possible, and by minimizing the areas (loop areas) contained within such circuit loops as much as possible.

[0052] 9 is a diagram (2) for explaining points to be noted in order to reduce the wiring inductance in the power module 1 according to the first embodiment. As shown in Fig. 9, a large current line IL is formed in the first switching element Q1 in the power module 1, through which a large current flows from the drain terminal to the source terminal.

[0053] Furthermore, the first switching element Q1 in the power module 1 is provided with a small current line IS for passing a control signal from the gate terminal to the source terminal.

[0054] In the power module 1 according to the first embodiment, the common impedance CI at the portion where the currents flowing through the above-mentioned large current line IL and small current line IS flow in common is made as small as possible, thereby making it possible to reduce the wiring inductance.

[0055] Although the example in FIG. 9 shows the first switching element Q1, the wiring inductance can be reduced in the same way for the second switching element Q2 to the sixth switching element Q6 by making this common impedance CI as small as possible.

[0056] The circuits shown in Figures 8 and 9 are included in common with the circuits in Figures 6 and 7. That is, the points explained using Figures 8 and 9 are valid for the circuits in Figures 6 and 7, and are also valid for a wide variety of circuits that have circuit block A and circuit block B shown in Figures 6 and 7. Note that although cascade GaN-FETs are used as switching elements in Figures 8 and 9, all switching elements may be GaN-FETs.

[0057] Next, based on the points to be noted above, specific means for reducing the wiring inductance within the power module 1 will be described with reference to FIGS.

[0058] Fig. 10 is a diagram for explaining the optimum arrangement of the first to sixth switching elements Q1 to Q6 and the capacitor C1 in the power module 1 according to the first embodiment. Fig. 10(a) shows the circuit, and Fig. 10(b) shows the optimum arrangement. In the present disclosure, as shown in Fig. 10(a), the wiring formed inside the power module 1 is virtually divided into several groups (hereinafter also referred to as wiring sections).

[0059] Specifically, the wiring section from capacitor C1 via positive terminal P to the drain terminal of first switching element Q1, the drain terminal of third switching element Q3, or the drain terminal of fifth switching element Q5 is defined as network P-NET. Also, the wiring section from gate terminal Q1G to the gate terminal of first switching element Q1, from said gate terminal via the inside of the Si-FET to the source terminal of first switching element Q1, and from said source terminal to source terminal Q1S is defined as network Q1G-NET.

[0060] The wiring section from the output terminal OUT1 to the source terminal of the first switching element Q1 and the drain terminal of the second switching element Q2 is designated as a network OUT1-NET. The wiring section from the gate terminal Q2G to the gate terminal of the second switching element Q2, from that gate terminal via the inside of the Si-FET to the source terminal of the second switching element Q2, and from that source terminal to the source terminal Q2S is designated as a network Q2G-NET.

[0061] The wiring section from the gate terminal Q3G to the gate terminal of the third switching element Q3, from this gate terminal through the inside of the Si-FET to the source terminal of the third switching element Q3, and via this source terminal to the source terminal Q3S is referred to as a network Q3G-NET.The wiring section from the output terminal OUT2 to the source terminal of the third switching element Q3 and the drain terminal of the fourth switching element Q4 is referred to as a network OUT2-NET.

[0062] The wiring section from the gate terminal Q4G to the gate terminal of the fourth switching element Q4, from that gate terminal through the inside of the Si-FET to the source terminal of the fourth switching element Q4, and via that source terminal to the source terminal Q4S is referred to as network Q4G-NET. The wiring section from the gate terminal Q5G to the gate terminal of the fifth switching element Q5, from that gate terminal through the inside of the Si-FET to the source terminal of the fifth switching element Q5, and via that source terminal to the source terminal Q5S is referred to as network Q5G-NET. The wiring section from the output terminal OUT3 to the source terminal of the fifth switching element Q5 and the drain terminal of the sixth switching element Q6 is referred to as network OUT3-NET.

[0063] The wiring section from the gate terminal Q6G to the gate terminal of the sixth switching element Q6, from the gate terminal to the source terminal of the sixth switching element Q6 via the inside of the Si-FET, and to the source terminal Q6S via the source terminal is defined as a network Q6G-NET. The wiring section from the capacitor C1 to the source terminal of the second switching element Q2, the source terminal of the fourth switching element Q4, or the source terminal of the sixth switching element Q6 via the negative terminal N is defined as a network N-NET.

[0064] The P-NET AREA, Q-NET AREA, OUT1-NET AREA, OUT2-NET AREA, OUT3-NET AREA, Q1G-NET AREA, Q2G-NET AREA, Q3G-NET AREA, Q4G-NET AREA, Q5G-NET AREA, and Q6G-NET AREA shown in (b) of Figure 10 are patterning areas corresponding to the P-NET, Q-NET, OUT1-NET, OUT2-NET, OUT3-NET, Q1G-NET, Q2G-NET, Q3G-NET, Q4G-NET, Q5G-NET, and Q6G-NET, respectively, shown in (a) of Figure 10.

[0065] As shown in FIG. 10(b), in the power module 1 according to the first embodiment, the upper-arm switching elements (Q1, Q3, Q5) are arranged so that the gates of the Si-FETs are located above the central portion 4 of the power module 1 where the capacitor C1 is located. A P-NET is located on the drain side of each GaN-FET, and OUT1-NET to OUT3-NET are located on the source side of each GaN-FET. The lower-arm switching elements (Q2, Q4, Q6) are arranged so that the gates of the Si-FETs are located below the central portion 4. An N-NET is located on the source side of each GaN-FET, and OUT1-NET to OUT3-NET are located on the drain side of each GaN-FET. The P-NET and N-NET are arranged parallel to each other between the upper-arm and lower-arm switching elements. The capacitor C1 is located between the third switching element Q3 and the fourth switching element Q4, i.e., in the central portion 4 of the power board where the first to sixth switching elements Q1 to Q6 are located.

[0066] The intersections of OUT2-NET to OUT3-NET with P-NET and N-NET are wired on a separate layer if it is a multi-layer board, and connected with jumper wires etc. if it is a single-phase board. In Figure 10(b), the OUT2-NET AREA and OUT3-NET AREA are cut at the top and bottom, and the cut points are connected by wire bonding.

[0067] By arranging the first to sixth switching elements Q1 to Q6 and the capacitor C1 in this manner, noise generated among the six switching elements is not unbalanced, and the wiring length can be shortened, thereby reducing noise generated. This prevents an increase in noise generated by an extremely long wiring pattern, and ensures a good current path for large currents to flow. Note that in each embodiment of the present invention, an example is described in which the switching elements and the capacitor C1 are arranged based on the central portion 4.

[0068] The first to sixth switching elements Q1 to Q6 are arranged such that the first switching element Q1, the third switching element Q3, and the fifth switching element Q5 are aligned on a single straight line (a virtual straight line (not shown)). The second switching element Q2, the fourth switching element Q4, and the sixth switching element Q6 are aligned on a single straight line (a virtual straight line (not shown)). The virtual straight lines are substantially parallel to each other. The line (not shown) connecting the first switching element Q1 and the second switching element Q2, the line (not shown) connecting the third switching element Q3 and the fourth switching element Q4, and the line (not shown) connecting the fifth switching element Q5 and the sixth switching element Q6 are substantially parallel to each other.

[0069] Fig. 11 is a diagram showing the optimum layout when GaN-FETs are used instead of the cascade GaN-FETs. In Fig. 11, the cascade GaN-FETs in Fig. 10 are replaced with GaN-FETs.

[0070] <Configuration of Power Module (First Embodiment)> Next, the configuration of the power module 1 to which the optimal layout shown in FIG. 10 is applied will be described with reference to FIGS. 12 and 13. FIG. 12 is a diagram showing an example of a circuit of a circuit block A. Compared to the circuit block A shown in FIGS. 6 and 7, the circuit block A in FIG. 12 is provided with a thermistor. Two terminals TH1 and TH2 are connected to the thermistor. The thermistor is provided to detect the temperature of the substrate.

[0071] FIG. 13 shows a cross-sectional view and a top view illustrating the configuration of a power module 1 according to the first embodiment. (a) of FIG. 13 shows the cross-sectional view, and (b) of FIG. 13 shows the top view. The cross-sectional portion shown in the cross-sectional view is shown in the top view. (a) of FIG. 13 is a schematic view viewed in the direction of the arrow from the cross-sectional line in the top view shown in (b) of FIG. 13. As shown in (a) of FIG. 13, the power module 1 according to the first embodiment includes a power board 10, a case 11, a lid 12, and a silicone gel 13 as a resin sealant. The power board 10 is an example of a circuit board.

[0072] The power board 10 is configured with a circuit board having high heat resistance and high heat dissipation properties, such as a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazing) board. On the front surface of the power board 10, first to sixth switching elements Q1 to Q6, a capacitor C1, etc. are mounted.

[0073] Case 11 has a frame shape and is provided so as to surround the front surface of power board 10. Case 11 houses each element mounted on power board 10. Case 11 also has mounting holes formed therein that are used to fix power module 1 inside a power conversion device.

[0074] The case 11 is formed of, for example, polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, or the like.

[0075] The lid 12 covers the front surface of the power board 10 housed in the case 11 and is provided to close the upper part of the frame-shaped case 11. The lid 12 is formed, for example, from the same resin as the case 11. Silicon gel 13 is filled inside the case 11 and seals the various elements mounted on the front surface of the power board 10. An external output PIN is provided upright on the power board 10. For example, FIG. 13(b) shows a diagram in which the external output PIN provided upright on the negative terminal N is viewed from above (top view) and from the side (side view).

[0076] The power board 10 and the case 11, and the case 11 and the lid 12 are joined together with an adhesive (not shown).

[0077] 13(b), a capacitor C1 and first to sixth switching elements Q1 to Q6 are mounted on the front surface of the power board 10. The capacitor C1 is disposed in a central portion 4 of the power board 10. The upper arm switching elements (Q1, Q3, Q5) are disposed so that the gates of the Si-FETs are located above the central portion 4 of the power board 10. The lower arm switching elements (Q2, Q4, Q6) are disposed so that the gates of the Si-FETs are located below the central portion 4 of the power board 10.

[0078] Circuit patterns 21 to 43 constituting a wiring portion are provided on the front surface of the power board 10. The circuit patterns 21 to 43 are provided independently of one another on an insulating layer included in the power board 10, and therefore the circuit patterns 21 to 43 are not electrically connected to one another.

[0079] The circuit patterns 21 to 43 will be described with reference to Fig. 14. Fig. 14 is a diagram for explaining that the power module 1 according to the first embodiment achieves an optimal arrangement. Fig. 14(a) is a diagram showing the front surface of the power board 10 shown in Fig. 13, and Fig. 14(b) is a diagram showing the correspondence between the circuit patterns and the parts shown in Fig. 10.

[0080] As shown in FIG. 14(a), the size of the power board 10 is 37.50 mm×28.50 mm.

[0081] When the first switching element Q1 and the second switching element Q2 are used as references, a circuit pattern 21 is formed in an area on the opposite side of the first switching element Q1 and the second switching element Q2 from the area in which the capacitor C1 is disposed. Most of this circuit pattern 21 corresponds to the network OUT1-NET.

[0082] A circuit pattern 22 is formed in the region on the drain terminal side of the first switching element Q1, the region on the drain terminal side of the third switching element Q3, the region on the drain terminal side of the fifth switching element Q5, and the region connecting these three regions on the lower arm side. This circuit pattern 22 corresponds to the network P-NET.

[0083] A circuit pattern 23 is formed in the region on the source terminal side of the second switching element Q2, the region on the source terminal side of the fourth switching element Q4, the region on the source terminal side of the sixth switching element Q6, and the region connecting these three regions on the upper arm side. Most of this circuit pattern 23 corresponds to the network N-NET.

[0084] When the first switching element Q1 is used as a reference, circuit patterns 24 and 25 are arranged in an area on the opposite side of the first switching element Q1 from the area in which the second switching element Q2 is arranged. These circuit patterns 24 and 25 correspond to a part of the network Q1G-NET.

[0085] When the second switching element Q2 is used as a reference, circuit patterns 26 and 27 are arranged in an area on the opposite side of the second switching element Q2 from the area in which the second switching element Q1 is arranged. These circuit patterns 26 and 27 correspond to a part of the network Q2G-NET.

[0086] When the third switching element Q3 is used as a reference, circuit patterns 28, 29, and 30 are arranged in an area on the opposite side of the third switching element Q3 from the area where the fourth switching element Q4 is arranged. Circuit pattern 28 extends to an area on the source side of the third switching element Q3. Circuit pattern 28 corresponds to a part of network OUT2-NET. Circuit patterns 29 and 30 correspond to a part of network Q3G-NET.

[0087] A circuit pattern 31 is arranged in an area on the drain side of the fourth switching element Q4. Furthermore, when the fourth switching element Q4 is used as a reference, circuit patterns 32 and 33 are arranged in an area on the opposite side of the fourth switching element Q4 from the area in which the third switching element Q3 is arranged. The circuit pattern 31 corresponds to a part of the network OUT2-NET. Furthermore, the circuit patterns 32 and 33 correspond to a part of the network Q4G-NET.

[0088] When the fifth switching element Q5 is used as a reference, circuit patterns 34, 35, and 36 are arranged in an area on the opposite side of the fifth switching element Q5 from the area where the sixth switching element Q6 is arranged. Circuit pattern 34 includes an area on the source side of the fifth switching element Q5. Circuit pattern 34 corresponds to a part of network OUT3-NET. Furthermore, circuit patterns 35 and 36 correspond to a part of network Q5G-NET.

[0089] A circuit pattern 37 is arranged in an area on the drain side of the sixth switching element Q6. Furthermore, when the sixth switching element Q6 is used as a reference, circuit patterns 38 and 39 are arranged in an area on the opposite side of the sixth switching element Q6 from the area in which the fifth switching element Q5 is arranged. The circuit pattern 37 corresponds to a part of the network OUT3-NET. Furthermore, the circuit patterns 38 and 39 correspond to a part of the network Q6G-NET.

[0090] When the portion of circuit pattern 21 adjacent to the second switching element Q2 is used as a reference, circuit patterns 40 and 41 are arranged in a region on the opposite side of the second switching element Q2 from the portion adjacent to the second switching element Q2. Circuit patterns 42 and 43 are arranged in a region sandwiched between the first switching element Q1 and the second switching element Q2.

[0091] As described above, in the power module 1 according to the first embodiment, the capacitor C1, the first to sixth switching elements Q1 to Q6, and the respective wiring portions are optimally arranged as shown in FIG. 11(b).

[0092] The specific wiring configuration for these circuit patterns 21 to 43 is as follows: In circuit pattern 21, the source electrode (source pad) of the first switching element Q1, the gate electrode (gate pad) of the GaN-FET of first switching element Q1, and the drain electrode (drain pad) of the second switching element Q2 are electrically connected via bonding wires W. In addition, a source terminal Q1-S is provided in a portion of circuit pattern 21 adjacent to circuit pattern 24, and when source terminal Q1-S is used as a reference, an output terminal OUT1 is provided in circuit pattern 21 on the opposite side of source terminal Q1-S from the region in which circuit pattern 24 is arranged.

[0093] The drain electrode of the first switching element Q1, the drain electrode of the third switching element Q3, and the drain electrode of the fifth switching element Q5 are electrically connected to the circuit pattern 22 via bonding wires W. In addition, a positive terminal P is provided on the circuit pattern 22 near the fifth switching element Q5.

[0094] A capacitor C1 is provided between the circuit pattern 22 and the circuit pattern 23, and the circuit pattern 22 and the circuit pattern 23 are electrically connected via the capacitor C1.

[0095] The circuit pattern 23 is electrically connected via bonding wires W to the source electrode of the second switching element Q2, the gate electrode of the GaN-FET of the second switching element Q2, the source electrode of the fourth switching element Q4, the gate electrode of the GaN-FET of the fourth switching element Q4, the source electrode of the sixth switching element Q6, and the gate electrode of the GaN-FET of the sixth switching element Q6.

[0096] Furthermore, a negative terminal N is provided near the sixth switching element Q6 on the circuit pattern 23. Furthermore, a source terminal Q2-S is provided at a portion of the circuit pattern 23 adjacent to the circuit pattern 26, a source terminal Q4-S is provided at a portion of the circuit pattern 23 adjacent to the circuit pattern 32, and a source terminal Q6-S is provided at a portion of the circuit pattern 23 adjacent to the circuit pattern 38.

[0097] A gate terminal Q1-G is provided on the circuit pattern 24. A resistor R1-1 is provided between the circuit pattern 24 and the circuit pattern 25, and the circuit pattern 24 and the circuit pattern 25 are electrically connected via the resistor R1-1.

[0098] The gate electrode of the first switching element Q1 is electrically connected to the circuit pattern 25 via a bonding wire W. A resistor R1-2 is provided between the circuit pattern 25 and the circuit pattern 21, and the circuit pattern 25 and the circuit pattern 21 are electrically connected to each other via the resistor R1-2.

[0099] A gate terminal Q2-G is provided on the circuit pattern 26. A resistor R2-1 is provided between the circuit pattern 26 and the circuit pattern 27, and the circuit pattern 26 and the circuit pattern 27 are electrically connected via the resistor R2-1.

[0100] The gate electrode of the second switching element Q2 is electrically connected to the circuit pattern 27 via a bonding wire W. A resistor R2-2 is provided between the circuit pattern 27 and the circuit pattern 23, and the circuit pattern 27 and the circuit pattern 23 are electrically connected via the resistor R2-2.

[0101] The source electrode of the third switching element Q3 and the gate electrode of the GaN-FET of the third switching element Q3 are electrically connected to circuit pattern 28 via bonding wire W. In addition, circuit pattern 31 is electrically connected to circuit pattern 28 via bonding wire W. In addition, a source terminal Q3-S is provided in a portion of circuit pattern 28 adjacent to circuit pattern 29, and an output terminal OUT2 is provided in circuit pattern 28 on the side opposite circuit pattern 29 when source terminal Q3-S is used as a reference.

[0102] A gate terminal Q3-G is provided on the circuit pattern 29. A resistor R3-1 is provided between the circuit pattern 29 and the circuit pattern 30, and the circuit pattern 29 and the circuit pattern 30 are electrically connected via the resistor R3-1.

[0103] The gate electrode of the third switching element Q3 is electrically connected to the circuit pattern 30 via a bonding wire W. A resistor R3-2 is provided between the circuit pattern 30 and the circuit pattern 28, and the circuit pattern 30 and the circuit pattern 28 are electrically connected via the resistor R3-2.

[0104] The drain electrode of the fourth switching element Q4 is electrically connected to the circuit pattern 31 via a bonding wire W.

[0105] A gate terminal Q4-G is provided on the circuit pattern 32. A resistor R4-1 is provided between the circuit pattern 32 and the circuit pattern 33, and the circuit pattern 32 and the circuit pattern 33 are electrically connected via the resistor R4-1.

[0106] The source electrode of the fourth switching element Q4 is electrically connected to the circuit pattern 33 via a bonding wire W. A resistor R4-2 is provided between the circuit pattern 33 and the circuit pattern 23, and the circuit pattern 33 and the circuit pattern 23 are electrically connected via the resistor R4-2.

[0107] The source electrode of the fifth switching element Q5 and the gate electrode of the GaN-FET of the fifth switching element Q5 are electrically connected to the circuit pattern 34 via a bonding wire W. Furthermore, the circuit pattern 37 is electrically connected to the circuit pattern 34 via a bonding wire W. The capacitor C1 is disposed in a region sandwiched between wires connecting the drain electrode of the GaN-based switching element of the upper arm and the source electrode of the GaN-based switching element of the lower arm. Specifically, the capacitor C1 is disposed in a region sandwiched between the bonding wire W connecting the circuit pattern 28 and the circuit pattern 31 and the bonding wire W connecting the circuit pattern 34 and the circuit pattern 37. Furthermore, a source terminal Q5-S is provided in a portion of the circuit pattern 34 adjacent to the circuit pattern 35. When the source terminal Q5-S is used as a reference, an output terminal OUT3 is provided in the circuit pattern 34 on the opposite side of the source terminal Q5-S from the region where the circuit pattern 35 is disposed.

[0108] A gate terminal Q5-G is provided on the circuit pattern 35. A resistor R5-1 is provided between the circuit pattern 35 and the circuit pattern 36, and the circuit pattern 35 and the circuit pattern 36 are electrically connected via the resistor R5-1.

[0109] The gate electrode of the fifth switching element Q5 is electrically connected to the circuit pattern 36 via a bonding wire W. A resistor R5-2 is provided between the circuit pattern 36 and the circuit pattern 34, and the circuit pattern 36 and the circuit pattern 34 are electrically connected via the resistor R5-2.

[0110] The drain electrode of the sixth switching element Q6 is electrically connected to the circuit pattern 37 via a bonding wire W.

[0111] A gate terminal Q6-G is provided on the circuit pattern 38. A resistor R6-1 is provided between the circuit pattern 38 and the circuit pattern 39, and the circuit pattern 38 and the circuit pattern 39 are electrically connected via the resistor R6-1.

[0112] The source electrode of the sixth switching element Q6 is electrically connected to the circuit pattern 39 via a bonding wire W. A resistor R6-2 is provided between the circuit pattern 39 and the circuit pattern 23, and the circuit pattern 39 and the circuit pattern 23 are electrically connected via the resistor R6-2.

[0113] A terminal TH1 connected to one electrode of the thermistor is provided on the circuit pattern 40. A circuit pattern 42 is electrically connected to the circuit pattern 40 via a bonding wire W. A terminal TH2 connected to the other electrode of the thermistor is provided on the circuit pattern 41. A circuit pattern 43 is electrically connected to the circuit pattern 41 via a bonding wire W.

[0114] In addition, the positive terminal P, the negative terminal N, the output terminals OUT1 to OUT3, the gate terminals Q1-G to Q6-G, the source terminals Q1-S to Q6-S, and the terminals TH1 and TH2 are all made of a conductive material such as metal, and are electrically and mechanically connected to each circuit pattern by a conductive bonding material such as solder or a conductive adhesive.

[0115] Fig. 15 is a diagram for explaining the circuit loops 1-1 to 1-6 in the power module 1 according to the first embodiment. As shown in Fig. 15, in the power module 1 according to the first embodiment, the lengths of the circuit loops 1-1 to 1-6 are made as short as possible, and the loop areas of the circuit loops 1-1 to 1-6 are made as small as possible.

[0116] Fig. 16 is a diagram for explaining a circuit loop 2-1 in a power module 1 according to the first embodiment. As shown in Fig. 16(a), in the power module 1 according to the first embodiment, the length of the circuit loop 2-1 is made as short as possible, and the loop area of ​​the circuit loop 2-1 is made as small as possible. Furthermore, as shown in Fig. 16(b), the length of the circuit loop 2-2 is made as short as possible, and the loop area of ​​the circuit loop 2-2 is made as small as possible.

[0117] As described above, the length and area of ​​each of the circuit loops 1-1 to 1-6 and the circuit loops 2-1 and 2-2 in the power module 1 are minimized. This reduces the noise generated in each of the circuit loops. Furthermore, because the circuit loops 1-1 to 1-6 and the circuit loops 2-1 and 2-2 do not pass through the capacitor C1, the wiring inductance in each of the circuit loops can be reduced even if the capacitor C1 is not installed.

[0118] Fig. 17 is a diagram for explaining the circuit loops 3-1, 3-2, and 3-3 in the power module 1 according to the first embodiment. As shown in Fig. 17, in the power module 1 according to the first embodiment, the lengths of the circuit loops 3-1, 3-2, and 3-3 passing through the capacitor C1 are made as short as possible, and the loop areas of the circuit loops 3-1, 3-2, and 3-3 are made as small as possible. Therefore, the power module 1 equipped with the capacitor C1 can further reduce the wiring inductance in the circuit loops in addition to the above effects.

[0119] Fig. 18 is a diagram for explaining the common impedance CI in the power module 1 according to the first embodiment. (a) of Fig. 18 is a diagram for explaining the periphery of the first switching element Q1, and (b) of Fig. 18 is a diagram for explaining the periphery of the second switching element Q2.

[0120] As shown in (a) of Figure 18, in the first switching element Q1, the location where the bonding wire W extending from the source electrode of the Si-FET (i.e., the source electrode of the first switching element Q1) is connected to the circuit pattern 21 is defined as a first connection portion 51.

[0121] In addition, in the first switching element Q1, a portion where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 21 is defined as a second connection portion 52.

[0122] In the first embodiment, the first connection portion 51 is closer to the short side (the left side in FIG. 18) of the power board 10 than the second connection portion 52. In other words, the first connection portion 51 is disposed farther away from the first switching element Q1 to which they are connected than the second connection portion 52. This makes it possible to minimize the overlapping portion (i.e., common impedance CI) between the large current line IL flowing from the drain terminal to the source terminal of the first switching element Q1 and the small current line IS flowing from the gate electrode to the source terminal of the first switching element Q1.

[0123] Therefore, according to the first embodiment, the common impedance CI can be reduced, and the influence of noise generated in the large current line IL on the small current line IS can be reduced.

[0124] Although FIG. 18(a) shows the first switching element Q1, the common impedance CI can be minimized by similarly providing the first connection portion 51 and the second connection portion 52 in the circuit patterns 28 and 34 for the third switching element Q3 and the fifth switching element Q5.

[0125] Also, as shown in (b) of Figure 18, in the second switching element Q2, the point where the bonding wire W extending from the source electrode of the Si-FET (i.e., the source electrode of the second switching element Q2) is connected to the circuit pattern 23 is defined as a third connection portion 53.

[0126] In addition, in the second switching element Q2, a location where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 23 is defined as a fourth connection portion 54.

[0127] In the first embodiment, the third connection portion 53 is closer to the center of the power board 10 than the fourth connection portion 54. In other words, the third connection portion 53 is disposed farther from the second switching element Q2 to which they are connected than the fourth connection portion 54. This makes it possible to minimize the overlapping portion (i.e., common impedance CI) between the large current line IL flowing from the drain terminal to the source terminal of the second switching element Q2 and the small current line IS flowing from the gate electrode to the source terminal of the second switching element Q2.

[0128] Therefore, according to the first embodiment, the common impedance CI can be reduced, and the influence of noise generated in the large current line IL on the small current line IS can be reduced.

[0129] Although FIG. 18(b) shows the second switching element Q2, the common impedance CI can be minimized by similarly providing the third connection portion 53 and the fourth connection portion 54 in the circuit pattern 23 for the fourth switching element Q4 and the sixth switching element Q6.

[0130] Next, the wiring inductance will be compared between the power module 1 according to the first embodiment described above and a power module 100 according to a reference example, which is arranged based on a different concept from that of the first embodiment. Fig. 19 is a top view showing the configuration of the power module 100 according to the reference example. This reference example uses a component arrangement and patterning method that is generally adopted in power modules using Si-FETs and Si-IGBTs.

[0131] As shown in Fig. 19, the size of the power board of the power module 100 is 58.00 mm x 29.00 mm. Compared to (a) of Fig. 14, the size of the power board of the power module 100 is larger, even though the same elements are used to form the same circuit.

[0132] Fig. 20 is a diagram for explaining circuit loops 1-1 to 1-6 in a power module 100 of a reference example. Comparing Fig. 15 with Fig. 20, there is no difference in merit between the power module 1 according to the first embodiment and the power module 100 of the reference example.

[0133] Fig. 21 is a diagram for explaining the circuit loop 2-1 in the power module 100 of the reference example. Comparing Fig. 16 with Fig. 21, in the power module 100 of the reference example, the length of the circuit loop 2-1 is longer and the loop area of ​​the circuit loop 2-1 is larger than in the first embodiment.

[0134] Fig. 22 is a diagram for explaining the circuit loop 3-1 in the power module 100 of the reference example. Comparing Fig. 17 with Fig. 22, in the power module 100 of the reference example, the length of the circuit loop 3-1 is longer and the loop area of ​​the circuit loop 3-1 is larger than in the first embodiment.

[0135] That is, in the power module 1 according to the first embodiment, the lengths of the circuit loops 2-1 and 3-1 are shorter and the loop areas of these circuit loops are smaller than those of the power module 100 of the reference example, which allows the wiring inductance of the power module 1 to be reduced in the first embodiment.

[0136] Fig. 23 is a diagram for explaining the common impedance CI in the power module 100 of the reference example. Comparing Fig. 18(a) with Fig. 23, there is no difference in merit between the power module 1 according to the first embodiment and the power module 100 of the reference example.

[0137] <Modification of the first embodiment> So far, we have described the case where only one capacitor C1 is arranged, but more capacitors may be arranged in the power module 1. Fig. 24 is a diagram showing Modification 1 in which three capacitors are arranged. Fig. 24(a) shows the arrangement of the capacitors, and Fig. 24(b) shows circuit loops 3-1 to 3-3.

[0138] 24(a), capacitor C1 is placed in a region sandwiched between a bonding wire W connected to the drain electrode of the third switching element Q3 and a bonding wire W connected to the source electrode of the fourth switching element Q4. Capacitor C2 is placed in a region sandwiched between a bonding wire W connected to the drain electrode of the first switching element Q1 and a bonding wire W connected to the source electrode of the second switching element Q2. Capacitor C3 is placed in a region sandwiched between the source electrode of the fifth switching element Q5 and the source electrode of the sixth switching element Q6.

[0139] The area where capacitor C1 is arranged and the area where capacitor C2 is arranged are separated by a bonding wire W that connects circuit pattern 28 and circuit pattern 31. The area where capacitor C1 is arranged and the area where capacitor C3 is arranged are separated by a bonding wire W that connects circuit pattern 34 and circuit pattern 37.

[0140] As shown in Fig. 24(b), in Modification 1, a circuit loop 3-1 including a capacitor C2 is formed, a circuit loop 3-2 including a capacitor C1 is formed, and a circuit loop 3-3 including a capacitor C3 is formed. Compared with the circuit loops 3-1 to 3-3 shown in Fig. 17, the lengths of the circuit loops 3-1 to 3-3 shown in Fig. 24(b) are shorter, and the loop areas of the circuit loops 3-1 to 3-3 are smaller.

[0141] Fig. 25 is a diagram showing a modified example of the motor control circuit shown in Fig. 6. Compared to Fig. 6, the circuit shown in Fig. 25 has negative terminals N1 to N3 instead of the negative terminal N. Furthermore, current detection circuits are provided between the negative terminal N1 and the negative DC input terminal, between the negative terminal N2 and the negative DC input terminal, and between the negative terminal N3 and the negative DC input terminal.

[0142] Fig. 26 is a diagram showing a power board 10 of the circuit shown in Fig. 25 as a modified example 2. Compared to Fig. 14, a negative terminal N1 is provided in a portion of the circuit pattern 23 adjacent to the source terminal Q2-S, a negative terminal N2 is provided in a portion of the circuit pattern 23 adjacent to the source terminal Q4-S, and a negative terminal N3 is provided in a portion of the circuit pattern 23 adjacent to the source terminal Q6-S.

[0143] In the power board 10 shown in FIG. 26, similarly to the power board 10 shown in FIG. 14, the length of each of the circuit loops 1-1 to 1-6, 2-1, 2-2, 3-1 to 3-3 within the power module 1 is made as short as possible, and the loop area of ​​each is made as small as possible.

[0144] Fig. 27 is a diagram for explaining the common impedance CI in the power module 1 in Modification 2. Fig. 27 shows the area around Q2. As in the explanation in Fig. 18(b), in Modification 2 as well, the common impedance CI in the power module 1 can be made as small as possible.

[0145] Second Embodiment Next, a power module 1 according to a second embodiment will be described with reference to Fig. 28 to Fig. 33. Fig. 28 is a diagram showing the circuit configuration of the power module 1 according to the second embodiment.

[0146] 28, the power module 1 of the second embodiment includes a power board 10 and a driver board 3. The circuit configuration of the power board 10 is the same as that of the first embodiment, and therefore detailed description thereof will be omitted.

[0147] The driver board 3 has GaN-FET drive circuits DR1 to DR6 and an interface circuit IF.

[0148] The GaN-FET drive circuit DR1 is connected to the source terminal A (Q1-S) and the gate terminal B (Q1-G), and drives the first switching element Q1 via the source terminal Q1-S and the gate terminal Q1-G. A predetermined control signal is input to the GaN-FET drive circuit DR1 from the interface circuit IF, and a predetermined control voltage is input from the upper arm power supply input terminal VU1.

[0149] The GaN-FET drive circuit DR2 is connected to the gate terminal G (Q2-G) and the source terminal H (Q2-S), and drives the second switching element Q2 via the gate terminal Q2-G and the source terminal Q2-S. A predetermined control signal and a predetermined control voltage are input to the GaN-FET drive circuit DR2 from the interface circuit IF.

[0150] The GaN-FET drive circuit DR3 is connected to the source terminal C (Q3-S) and the gate terminal D (Q3-G), and drives the third switching element Q3 via the source terminal Q3-S and the gate terminal Q3-G. A predetermined control signal is input to the GaN-FET drive circuit DR3 from the interface circuit IF, and a predetermined control voltage is input from the upper arm power supply input terminal VU2.

[0151] The GaN-FET drive circuit DR4 is connected to the gate terminal I (Q4-G) and the source terminal J (Q4-S), and drives the fourth switching element Q4 via the gate terminal Q4-G and the source terminal Q4-S. A predetermined control signal and a predetermined control voltage are input to the GaN-FET drive circuit DR4 from the interface circuit IF.

[0152] The GaN-FET drive circuit DR5 is connected to the source terminal C (Q5-S) and the gate terminal D (Q5-G), and drives the fifth switching element Q5 via the source terminal Q5-S and the gate terminal Q5-G. A predetermined control signal is input to the GaN-FET drive circuit DR5 from the interface circuit IF, and a predetermined control voltage is input from the upper arm power supply input terminal VU3.

[0153] The GaN-FET drive circuit DR6 is connected to the gate terminal K (Q6-G) and the source terminal L (Q6-S), and drives the sixth switching element Q6 via the gate terminal Q6-G and the source terminal Q6-S. A predetermined control signal and a predetermined control voltage are input to the GaN-FET drive circuit DR6 from the interface circuit IF.

[0154] Predetermined control signals are input to the interface circuit IF from the outside via interface terminals IF1 to IFn. Predetermined control voltages are also input to the interface circuit IF from the lower arm power supply input terminals VL1 to VL3. Note that the predetermined control voltages input from the lower arm power supply input terminals VL1 to VL3 are voltages for driving the GaN-FET drive circuits DR2, DR4, and DR6, respectively.

[0155] Fig. 29 is a cross-sectional view and a top view showing the configuration of a power module 1 according to the second embodiment. Fig. 29(a) shows the cross-sectional view, and Fig. 29(b) shows the top view. Note that the configuration of the power board 10 is the same as that of the first embodiment described above, so illustrations and detailed description will be omitted.

[0156] 29(a), in the power module 1 according to the second embodiment, a driver board 3 is disposed between a power board 10 and a lid 12, and is arranged substantially parallel to the power board 10 and the lid 12. The driver board 3 is received by a driver board receiver 11a of a case 11. The inside of the case 11, including the driver board 3, is filled with silicone gel 13.

[0157] 29(b), GaN-FET drive circuits DR1 to DR6, interface terminals IF1 to IFn, upper arm power supply input terminals VU1 to VU3, and lower arm power supply input terminals VL1 to VL3 are provided on the driver board 3. Although not shown in FIG. 29, the driver board 3 is also provided with an interface circuit IF.

[0158] In the second embodiment, in plan view, a GaN-FET drive circuit DR1 is provided near the first switching element Q1, and a GaN-FET drive circuit DR2 is provided near the second switching element Q2. Furthermore, a GaN-FET drive circuit DR3 is provided near the third switching element Q3, and a GaN-FET drive circuit DR4 is provided near the fourth switching element Q4. Furthermore, a GaN-FET drive circuit DR5 is provided near the fifth switching element Q5, and a GaN-FET drive circuit DR6 is provided near the sixth switching element Q6.

[0159] Moreover, in the second embodiment, in plan view, an upper arm power supply input terminal VU1 is provided near the GaN-FET drive circuit DR1, an upper arm power supply input terminal VU2 is provided near the GaN-FET drive circuit DR3, and an upper arm power supply input terminal VU3 is provided near the GaN-FET drive circuit DR5.

[0160] Fig. 30 is a diagram showing a virtual division into blocks according to circuits with high affinity in the power module 1 according to the second embodiment. As shown in Fig. 30, the circuits formed in the power module 1 according to the second embodiment are divided into four blocks A, B, C, and D according to circuits with high affinity.

[0161] Here, "circuits with high affinity" are circuits that are grouped together at similar potentials, and within these circuits with high affinity, malfunctions due to noise, etc. are unlikely to occur even if the parts are placed close to each other. On the other hand, if circuits belonging to different blocks are placed close to each other, they are more likely to malfunction due to noise, etc., due to the influence of different potentials.

[0162] As shown in FIG. 30, block A includes a first switching element Q1, a GaN-FET drive circuit DR1, a gate terminal B, a source terminal A, an output terminal OUT1, and an upper arm power supply input terminal VU1.

[0163] This block A corresponds to one of the upper arms in the power module 1. Therefore, in this block A, the potential swings greatly between a high voltage (for example, 400 V) and a low voltage (for example, 0 V) ​​every time the first switching element Q1 is turned on or off.

[0164] Block B includes a third switching element Q3, a GaN-FET drive circuit DR3, a gate terminal D, a source terminal C, an output terminal OUT2, and an upper arm power supply input terminal VU2.

[0165] This block B corresponds to one of the upper arms in the power module 1. Therefore, in this block B, the potential swings greatly between a high voltage (for example, 400 V) and a low voltage (for example, 0 V) ​​every time the third switching element Q3 is turned on or off.

[0166] Block C includes a fifth switching element Q5, a GaN-FET drive circuit DR5, a gate terminal F, a source terminal E, an output terminal OUT3, and an upper arm power supply input terminal VU3.

[0167] This block C corresponds to one of the upper arms in the power module 1. Therefore, in this block C, the potential swings greatly between a high voltage (for example, 400 V) and a low voltage (for example, 0 V) ​​every time the fifth switching element Q5 is turned on or off.

[0168] Block D includes a second switching element Q2, a fourth switching element Q4, a sixth switching element Q6, GaN-FET drive circuits DR2, DR4, DR6, an interface circuit IF, gate terminals G, I, K, source terminals H, J, L, interface terminals IF1 to IFn, and lower arm power supply input terminals VL1 to VL3.

[0169] Such block D corresponds to the three lower arms of the power module 1. Therefore, in such block D, even when the second switching element Q2, the fourth switching element Q4, or the sixth switching element Q6 is turned on or off, the potential does not swing greatly between high and low voltages, and the potential is maintained near a low voltage (for example, 0 V).

[0170] Fig. 31 is a diagram showing the power board 10 of the power module 1 according to the second embodiment divided into blocks in the manner shown in Fig. 30. As shown in Fig. 31, in the power board 10, most of block A is arranged along the upper portion of the left short side and the left portion of the upper long side. In addition, in the power board 10, most of block C is arranged along the upper portion of the right short side and the right portion of the upper long side. In addition, in the power board 10, most of block B is arranged so as to be sandwiched between block A and block C. Furthermore, in the power board 10, block D is arranged in roughly the lower half.

[0171] Fig. 32 is a diagram showing the driver board 3 of the power module 1 according to the second embodiment divided into blocks using the method shown in Fig. 30. As shown in Fig. 32, on the driver board 3, block A is arranged in a rectangular shape along the upper part of the left short side and the left part of the upper long side. On the driver board 3, block C is arranged in a rectangular shape along the upper part of the right short side and the right part of the upper long side. On the driver board 3, block B is arranged so as to be sandwiched between blocks A and C. On the driver board 3, block D is arranged in a rectangular shape in the lower half.

[0172] Fig. 33 is a diagram showing an overlap of blocks on the power board 10 and blocks on the driver board 3 of the power module 1 according to the second embodiment. In Fig. 33, the hatched areas indicate areas where different blocks overlap. As shown in Fig. 33, in the power module 1 of the second embodiment, block A corresponding to one of the upper arms, block B corresponding to one of the upper arms, block C corresponding to one of the upper arms, and block D corresponding to three lower arms are each designed to overlap as much as possible in the thickness direction. There are areas where block A and block D partially overlap, areas where block A and block D partially overlap, and areas where block C and block D partially overlap.

[0173] This makes it possible to prevent circuits belonging to different blocks from being placed close to each other, and therefore, according to the second embodiment, malfunctions due to noise or the like can be prevented.

[0174] 29(b), in the second embodiment, gate terminal B and source terminal A belonging to block A, gate terminal D and source terminal C belonging to block B, and gate terminal F and source terminal E belonging to block C are arranged in an area away from block D. Furthermore, gate terminals G, I, K and source terminals H, J, L belonging to block D are arranged in an area away from blocks A, B, and C.

[0175] This makes it possible to prevent noise from different blocks from being input to the gate terminals B, D, F, G, I, and K and the source terminals A, C, E, H, J, and L. Therefore, according to the second embodiment, it is possible to prevent the first to sixth switching elements Q1 to Q6 from malfunctioning due to noise or the like.

[0176] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

[0177] For example, in each of the above-described embodiments, the capacitor C1 is configured with a single capacitor, but the capacitor C1 does not have to be configured with a single capacitor. The capacitor C1 may be configured with a plurality of capacitors connected in series, or a plurality of capacitors connected in parallel. Furthermore, the capacitor C1 may be configured with a capacitor and a resistor connected in series.

[0178] Furthermore, in each of the above-described embodiments, an example has been shown in which the electrodes of the first to sixth switching elements Q1 to Q6 are connected to the corresponding circuit patterns by bonding wires W, but the members connecting the electrodes of the first to sixth switching elements Q1 to Q6 to the circuit patterns are not limited to bonding wires W. For example, the electrodes of the first to sixth switching elements Q1 to Q6 may be electrically connected to the circuit patterns by a lead frame or the like.

[0179] In addition, although the above-described embodiments have been described with respect to GaN-FETs, the GaN-FETs may be other GaN-based switching elements. In addition, in the above-described embodiments, the Si-FETs have been described with respect to Si-FETs, but the Si-FETs may be other Si-based switching elements.

[0180] Furthermore, in the above-described second embodiment, an example has been shown in which the capacitor C1 is mounted on the power board 10, but the capacitor C1 may also be mounted on the driver board 3, or on a separately provided printed circuit board 2. In this case, the capacitor C1 only needs to be provided in the central portion 4 of the power board 10 in a plan view.

[0181] As described above, the power module 1 according to each embodiment includes a power board 10 and includes three upper arms, namely, the first switching element Q1, the third switching element Q3, and the fifth switching element Q5, and three lower arms, namely, the second switching element Q2, the fourth switching element Q4, and the sixth switching element Q6. The power module 1 according to each embodiment also includes a capacitor C1 in the center of the power board 10. The three upper arm switching elements and the three lower arm switching elements are arranged to sandwich the capacitor C1. Each switching element has a rectangular shape with long and short sides, with a drain electrode provided on one long side and a gate electrode provided on the other long side. The three upper arm switching elements and the three lower arm switching elements are arranged so that the drain electrode and gate electrode are oriented in opposite directions. This allows the circuit loops 1-1 to 1-6, circuit loops 2-1 to 2-2, and circuit loops 3-1 to 3-3 to be as short as possible, and further, the loop areas of these circuit loops to be minimized. This allows the wiring inductance of the power module 1 to be reduced.

[0182] In the power module 1 according to each embodiment, a drain electrode is provided along one long side of the switching element, and a source electrode is provided along the other long side. Each switching element is arranged so that its short side faces the long side of the power board 10. This reduces the wiring inductance of the power module 1.

[0183] Furthermore, in the power module 1 according to each embodiment, the location where the bonding wire W extending from the source electrode of the Si-FET is connected to the circuit pattern 21 is defined as a first connection portion 51, and the location where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 21 is defined as a second connection portion 52. The first connection portion 51 is located closer to the short side of the power substrate 10 than the second connection portion 52. This reduces the overlap between the large current line including the first connection portion 51 and the small current line including the second connection portion 52. This allows the common impedance CI of the power module 1 to be minimized.

[0184] Furthermore, in the power module 1 according to each embodiment, the point where the bonding wire W extending from the source electrode of the Si-FET in the second switching element Q2 is connected to the circuit pattern 23 is designated as a third connection 53, and the point where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 23 is designated as a fourth connection 54. The third connection 53 is located closer to the center of the power substrate 10 than the fourth connection 54. This reduces the overlap between the large current line IL flowing from the drain terminal to the source terminal of the second switching element Q2 and the small current line IS flowing from the gate electrode to the source terminal of the GaN-FET included in the second switching element Q2. This minimizes the common impedance CI of the power module 1.

[0185] Furthermore, in the power module 1 according to each embodiment, the capacitor C1 is disposed in a region sandwiched between the bonding wire W connecting the circuit pattern 28 and the circuit pattern 31 and the bonding wire W connecting the circuit pattern 34 and the circuit pattern 37. This allows the power module 1 to be made smaller.

[0186] In the power module 1 according to the first modification of the first embodiment, the capacitor C1 is disposed in a region sandwiched between a bonding wire W connected to the drain electrode of the third switching element Q3 and a bonding wire W connected to the source electrode of the fourth switching element Q4. The capacitor C2 is disposed in a region sandwiched between a bonding wire W connected to the drain electrode of the first switching element Q1 and a bonding wire W connected to the source electrode of the second switching element Q2. The capacitor C3 is disposed in a region sandwiched between a source electrode of the fifth switching element Q5 and a source electrode of the sixth switching element Q6. This shortens the circuit loops 3-1 to 3-3, and further reduces the loop areas of these circuit loops. This allows the wiring inductance of the power module 1 to be reduced.

[0187] The power module 1 according to the second embodiment includes a power board 10 having six arms, namely, a first switching element Q1 to a sixth switching element Q6, and a driver board 3 having GaN-FET drive circuits DR1 to DR6 that drive the first switching element Q1 to the sixth switching element Q6, respectively. The driver board 3 is disposed between the power board 10 and the lid 12 and substantially parallel to the power board 10 and the lid 12. The power board 10 and the driver board 3 are divided into four blocks A, B, C, and D, each corresponding to a circuit with a high affinity. Blocks A to D of the power board 10 are disposed so as to overlap with blocks A to D of the driver board 3, respectively. This prevents the first switching element Q1 to the sixth switching element Q6 from malfunctioning due to noise or the like.

[0188] Furthermore, in the power module 1 according to each embodiment, the capacitor C1 is mounted in the central portion 4 on the power board 10. This eliminates the need to provide a separate printed circuit board 2 for mounting the capacitor C1, thereby reducing the manufacturing cost of the power module 1.

[0189] In the power module 1 according to each embodiment, the first to sixth switching elements Q1 to Q6 are cascade GaN-FETs in which the source electrodes arranged on the front surface of the GaN-FETs are electrically and mechanically connected to the drain electrodes arranged on the back surface of the Si-FETs, thereby enabling the normally-on GaN-FETs to be driven as normally-off switching elements.

[0190] It should be noted that the embodiments disclosed herein are illustrative in all respects and should not be considered limiting. Indeed, the above-described embodiments may be embodied in various forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended claims. [Explanation of symbols]

[0191] 1 Power Module 2 Printed circuit board 3 Driver Board 4 Central part 10 Power Board 21~43 Circuit Pattern 51 First connection part 52 Second connection part P positive terminal N negative terminal C1~C3 capacitors Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element Q5 Fifth switching element Q6 6th switching element W Bonding Wire

Claims

1. a power board on which switching elements constituting the three upper arms and three lower arms are mounted on a single circuit board; a driver board including drivers for driving the three upper arms and the three lower arms, A power module in which the power board and the driver board are arranged to be spaced apart in a thickness direction of the boards, an area included in the power board and the driver board, the area including three blocks each including a circuit that operates using a potential of the source electrode of the switching elements that configure the three upper arms as a reference potential; and a block including a circuit that operates using a potential of a common source electrode of the three switching elements that configure the three lower arms as a reference potential; the three blocks corresponding to the upper arm on the power board and the three blocks corresponding to the upper arm on the driver board are arranged at positions where blocks having the same reference potential substantially overlap each other in a thickness direction of the board; the block corresponding to the lower arm on the power board and the block corresponding to the lower arm on the driver board are disposed at positions that substantially overlap each other in a thickness direction of the boards, the three blocks corresponding to the upper arms on the power board each include an area for inter-arm wiring connecting the upper arms and the lower arms; The three blocks corresponding to the upper arm on the power board and the block corresponding to the lower arm on the driver board do not overlap in the thickness direction of the board in an area other than the area of ​​the inter-arm wiring. Power module.

2. 2. The power module according to claim 1, wherein wiring for supplying power to the three upper arms is arranged near a boundary between the three blocks on the power board corresponding to the upper arms and the block on the power board corresponding to the lower arm.

3. 3. The power module according to claim 2, wherein wiring for supplying power to the three lower arms is arranged substantially parallel to wiring for supplying power to the three upper arms.

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