Multiplexer

Abstract

To improve an attenuation characteristic in a non-passage band including a high-frequency band while improving a loss against a signal in a passage band.SOLUTION: In a multiplexer 7B, a first inductor via VH1, a second inductor via VH2, and a third inductor via VH3 form a first inductor LH1, a second inductor LH2, and a third inductor LH3, respectively. A fourth inductor via VH4 forms a fourth inductor LH4. A fifth inductor via VH5 forms a fifth inductor LH5. A sixth inductor via VH6 forms a sixth inductor LH6. At least one of the fourth inductor via VH4, the fifth inductor via VH5, and the sixth inductor via VH6 is arranged in a boundary region 74 of a first filter 71B and a second filter 72B.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] The present invention relates generally to multiplexers. [Background technology]

[0002] Patent Document 1 describes an LC filter. The LC filter described in Patent Document 1 includes a laminate, flat plate-shaped first and second electrodes, and a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode. The laminate is formed by stacking a plurality of dielectric layers. The first capacitor electrode, the second capacitor electrode, and the third capacitor electrode form a capacitor between the second electrode and the laminate. The LC filter described in Patent Document 1 further includes capacitor electrodes facing the first capacitor electrode and the third capacitor electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 241104 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional LC filter described in Patent Document 1, since capacitor electrodes facing the first capacitor electrode and the third capacitor electrode are provided, there are cases in which sufficient attenuation in the high frequency band cannot be obtained.

[0005] The present invention has been made in view of the above points, and has as its object to provide a multiplexer that can improve loss for signals in the passband and also improve attenuation characteristics in non-passbands including high frequency bands. [Means for solving the problem]

[0006] An LC filter according to one aspect of the present invention includes a laminate, a first input / output port, a second input / output port, a first electrode, a second electrode, a first capacitor electrode, a second capacitor electrode, a third capacitor electrode, a first inductor via, a second inductor via, a third inductor via, and a first inductor pattern portion. The laminate is formed by stacking a plurality of dielectric layers. The first input / output port is provided on the laminate. The second input / output port is provided on the laminate and is different from the first input / output port. The first electrode is a flat-plate-shaped electrode provided on a first dielectric layer of the plurality of dielectric layers. The second electrode is a flat-plate-shaped electrode provided on a second dielectric layer of the plurality of dielectric layers that is different from the first dielectric layer. The first capacitor electrode forms a first capacitor with the second electrode. The second capacitor electrode forms a second capacitor with the second electrode. The third capacitor electrode forms a third capacitor with the second electrode. The first inductor via has a first end connected to the first capacitor electrode and a second end connected to the first electrode, forming a first inductor. The second inductor via has a third end connected to the second capacitor electrode and a fourth end connected to the first electrode, forming a second inductor. The third inductor via has a fifth end connected to the third capacitor electrode and a sixth end connected to the first electrode, forming a third inductor. The first inductor pattern portion forms a fourth inductor. The first capacitor electrode and the second capacitor electrode form a fourth capacitor. The second capacitor electrode and the third capacitor electrode form a fifth capacitor. The first inductor pattern portion has a first end connected to at least one of the first electrode, the first inductor via, and the first capacitor electrode, and a second end connected to the first input / output port. The first capacitor electrode and the third capacitor electrode do not face each other.

[0007] A multiplexer according to one aspect of the present invention includes a first filter including the LC filter, and a second filter, wherein the second filter passes signals in a frequency band higher than the pass band of the first filter.

[0008] A high-frequency module according to one aspect of the present invention includes a filter including the LC filter and an amplifier.

[0009] A communication device according to one aspect of the present invention includes the high-frequency module and a signal processing circuit.

[0010] A multiplexer according to one aspect of the present invention includes a first filter, a second filter, and a laminate. The first filter is a low-pass filter. The second filter passes signals in a frequency band higher than the pass band of the first filter. The laminate includes a plurality of dielectric layers stacked one upon the other. The first filter includes a first electrode, a second electrode, a first capacitor electrode, a second capacitor electrode, a third capacitor electrode, a first inductor via, a second inductor via, a third inductor via, and a first inductor pattern portion. The first electrode is provided on a first dielectric layer of the plurality of dielectric layers. The second electrode is provided on a second dielectric layer of the plurality of dielectric layers different from the first dielectric layer and is a ground electrode. The first capacitor electrode forms a first capacitor with the second electrode. The second capacitor electrode forms a second capacitor with the second electrode. The third capacitor electrode forms a third capacitor with the second electrode. The first inductor via has a first end connected to the first capacitor electrode and a second end connected to the first electrode, forming a first inductor. The second inductor via has a third end connected to the second capacitor electrode and a fourth end connected to the first electrode, forming a second inductor. The third inductor via has a fifth end connected to the third capacitor electrode and a sixth end connected to the first electrode, forming a third inductor. The first inductor pattern portion forms a fourth inductor. The second filter includes a second filter first electrode, a second filter second electrode, a second filter first capacitor electrode, a second filter second capacitor electrode, a second filter third capacitor electrode, a second filter first inductor via, a second filter second inductor via, a second filter third inductor via, a second filter fourth inductor via, a second filter fifth inductor via, and a second filter sixth inductor via. The first electrode for the second filter is provided on the first dielectric layer of the plurality of dielectric layers, and the second electrode for the second filter is provided on a second dielectric layer of the plurality of dielectric layers that is different from the first dielectric layer and is a ground electrode.The second filter first capacitor electrode forms a second filter first capacitor between itself and the second filter second electrode. The second filter second capacitor electrode forms a second filter second capacitor between itself and the second filter second electrode. The second filter third capacitor electrode forms a second filter third capacitor between itself and the second filter second electrode. The second filter first inductor via is connected between the second filter first capacitor electrode and the second filter first electrode to form a second filter first inductor. The second filter second inductor via is connected between the second filter second capacitor electrode and the second filter first electrode to form a second filter second inductor. The second filter third inductor via is connected between the second filter third capacitor electrode and the second filter first electrode to form a second filter third inductor. The second filter fourth inductor via is connected between the second filter first electrode and the second filter second electrode to form a second filter fourth inductor connected in series with the second filter first inductor. The second filter fifth inductor via is connected between the second filter first electrode and the second filter second electrode to form a second filter fifth inductor connected in series with the second filter second inductor. The second filter sixth inductor via is connected between the second filter first electrode and the second filter second electrode to form a second filter sixth inductor connected in series with the second filter third inductor. At least one of the second filter fourth inductor via, the second filter fifth inductor via, and the second filter sixth inductor via is arranged in a boundary region between the first filter and the second filter. [Effects of the Invention]

[0011] The LC filter, multiplexer, high-frequency module, and communication device according to the above aspects of the present invention can improve loss for passband signals and also improve attenuation characteristics in non-passbands including high-frequency bands. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view of an LC filter according to a first embodiment. [Figure 2] FIG. 2 is a perspective view of the LC filter. [Figure 3] FIG. 3 is a perspective plan view of the LC filter. [Figure 4] FIG. 4 is a circuit diagram of the LC filter of the same. [Figure 5] FIG. 5 is a characteristic diagram of the LC filter of the same. [Figure 6] FIG. 6 is a perspective view of the LC filter according to the second embodiment. [Figure 7] FIG. 7 is a perspective view of the LC filter. [Figure 8] FIG. 8 is a perspective plan view of the LC filter. [Figure 9] FIG. 9 is a circuit diagram of the LC filter of the same. [Figure 10] FIG. 10 is a perspective view of the LC filter according to the third embodiment. [Figure 11] FIG. 11 is a perspective view of the LC filter. [Figure 12] FIG. 12 is a perspective plan view of the LC filter. [Figure 13] FIG. 13 is a circuit diagram of the LC filter of the same. [Figure 14] FIG. 14 is a characteristic diagram of the LC filter of the same. [Figure 15] FIG. 15 is a perspective view of the LC filter according to the fourth embodiment. [Figure 16] FIG. 16 is a perspective view of the LC filter. [Figure 17]FIG. 17 is a perspective plan view of the LC filter. [Figure 18] FIG. 18 is a circuit diagram of the LC filter of the above embodiment. [Figure 19] FIG. 19 is a schematic diagram of a multiplexer according to the fifth embodiment. [Figure 20] FIG. 20 is a schematic diagram of a multiplexer according to a modification of the fifth embodiment. [Figure 21] FIG. 21 is a schematic diagram of a high-frequency module and a communication device according to the sixth embodiment. [Figure 22] FIG. 22 is a perspective view of a multiplexer according to the seventh embodiment. [Figure 23] FIG. 23 is a perspective view of the multiplexer. [Figure 24] FIG. 24 is a perspective plan view of the multiplexer. [Figure 25] FIG. 25 is a circuit diagram of the multiplexer of the above embodiment. [Figure 26] FIG. 26 is a perspective view of a multiplexer according to the eighth embodiment. [Figure 27] FIG. 27 is a perspective view of the multiplexer. [Figure 28] FIG. 28 is a characteristic diagram of the multiplexer according to the ninth embodiment. [Figure 29] FIG. 29 is a perspective view of a main part of a multiplexer according to the tenth embodiment. [Figure 30] FIG. 30 is a plan view of a main part of a multiplexer according to a modification of the tenth embodiment. [Figure 31] FIG. 31 is a circuit diagram of a multiplexer according to the twelfth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, LC filters according to embodiments 1 to 4, multiplexers according to embodiments 5 and 7 to 12, and a high-frequency module and a communication device according to embodiment 6 will be described with reference to the drawings. The drawings referred to in the following embodiments are schematic diagrams, and the ratios of sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensional ratios.

[0014] In the following description, the stacking direction of the laminate 2 described below (the stacking direction of multiple dielectric layers in the laminate 2) will be referred to as the "first direction D1", the direction perpendicular to the first direction D1 and along one side of the laminate 2 will be referred to as the "second direction D2", and the direction along the other side of the laminate 2 will be referred to as the "third direction D3".

[0015] In Figures 1 to 3, 6 to 8, 10 to 12, 15 to 17, 22 to 24, 26, 27, 29 and 30, the dielectric layers of the laminate 2 are omitted, and only the wiring pattern portions, vias and terminal conductors formed inside the dielectric layers are shown.

[0016] (Embodiment 1) (1) Overall structure of the LC filter The structure of the LC filter 1 according to embodiment 1 will be described with reference to the drawings. The LC filter 1 according to embodiment 1 is a low-pass filter that passes signals in a frequency band lower than a specific frequency.

[0017] (2) Components of the LC filter Hereinafter, each component of the LC filter 1 according to the first embodiment will be described with reference to the drawings.

[0018] As shown in FIGS. 1 to 3, the LC filter 1 includes a laminate 2, a plurality of terminals 3, a first electrode P1, a second electrode P2, a plurality of capacitor electrodes PC0, and a plurality of inductor vias V0.

[0019] (2.1) Laminate As shown in FIGS. 1 to 3, the laminate 2 is a rectangular parallelepiped or approximately rectangular parallelepiped, and is formed by stacking a plurality of dielectric layers (not shown) in the stacking direction. In other words, the laminate 2 is a structure in which a plurality of dielectric layers are stacked. Each of the plurality of dielectric layers of the laminate 2 is formed of, for example, ceramic. Inside the laminate 2, inductors and capacitors are formed by a plurality of wiring pattern portions, a plurality of electrodes, and a plurality of vias (via conductors) formed on each dielectric layer. Note that the laminate 2 is not limited to a rectangular parallelepiped or approximately rectangular parallelepiped, and may be a solid of another shape.

[0020] The laminate 2 has a first main surface 201 and a second main surface 202. A second electrode P2 is formed on a second dielectric layer (not shown) adjacent to the second main surface 202 of the laminate 2. A first electrode P1 is formed on a first dielectric layer (not shown) adjacent to the first main surface 201 of the laminate 2. In FIGS. 1 to 3, the first electrode P1 is indicated by a two-dot chain line.

[0021] (2.2) Terminals The multiple terminals 3 (input terminal T1, output terminal T2, and ground terminal GND) are flat electrodes and are provided on the laminate 2. More specifically, the multiple terminals 3 are arranged on the second main surface 202 of the laminate 2. The multiple terminals 3 are LGA (Land Grid Array) terminals regularly arranged on the second main surface 202 of the laminate 2. The multiple terminals 3 are external terminals for connecting the LC filter 1 to an external device (not shown).

[0022] The multiple terminals 3 include an input terminal T1 (first input / output port) and an output terminal T2 (second input / output port). The input terminal T1 is connected to a first capacitor electrode PC1. The output terminal T2 is connected to a third capacitor electrode PC3. The multiple terminals 3 also include a ground terminal GND. The ground terminal GND has a ground potential.

[0023] (2.3) First electrode, second electrode 1 to 3, the first electrode P1 is provided on a first dielectric layer (not shown) of the plurality of dielectric layers of the laminate 2. The first electrode P1 is a flat plate electrode having a rectangular shape when viewed from above in the stacking direction (first direction D1) of the laminate 2.

[0024] The second electrode P2 is provided on a second dielectric layer (not shown) different from the first dielectric layer among the multiple dielectric layers of the laminate 2. The second electrode P2 is a flat plate electrode having a flat plate shape. The second electrode P2 is connected to the ground terminal GND. More specifically, the second electrode P2 is connected to the ground terminal GND disposed on the second main surface 202 of the laminate 2 through a via (not shown).

[0025] (2.4) Capacitor electrodes As shown in FIGS. 1 to 3, the LC filter 1 includes a first capacitor electrode PC1, a second capacitor electrode PC2, and a third capacitor electrode PC3 as a plurality of capacitor electrodes PC0.

[0026] The first capacitor electrode PC1 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P1 and the second electrode P2 in the first direction D1. The first capacitor electrode PC1 is disposed apart from the second electrode P2 and forms a first capacitor C1 (see FIG. 4) between the first capacitor electrode PC1 and the second electrode P2. The first capacitor electrode PC1 is connected to the first inductor pattern portion PL1.

[0027] The second capacitor electrode PC2 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P1 and the second electrode P2 in the first direction D1. More specifically, the second capacitor electrode PC2 has a first portion PC21 and a second portion PC22. The second capacitor electrode PC2 is disposed apart from the second electrode P2 and forms a second capacitor C2 (see FIG. 4) between itself and the second electrode P2.

[0028] The third capacitor electrode PC3 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P1 and the second electrode P2 in the first direction D1. The third capacitor electrode PC3 is disposed apart from the second electrode P2 and forms a third capacitor C3 (see FIG. 4) between the third capacitor electrode PC3 and the second electrode P2. The third capacitor electrode PC3 is connected to the output terminal T2 through a via conductor V33.

[0029] The first capacitor electrode PC1 and the second capacitor electrode PC2 form a fourth capacitor C4 (see FIG. 4). The second capacitor electrode PC2 and the third capacitor electrode PC3 form a fifth capacitor C5 (see FIG. 4). More specifically, the first portion PC21 of the second capacitor electrode PC2 and the first capacitor electrode PC1 form the fourth capacitor C4. The second portion PC22 of the second capacitor electrode PC2 and the third capacitor electrode PC3 form the fifth capacitor C5.

[0030] The first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 are provided between the first electrode P1 and the second electrode P2 in the stacking direction (first direction D1) of the laminate 2. The first capacitor electrode PC1 may partially overlap the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the first capacitor electrode PC1 is provided between the first electrode P1 and the second electrode P2 such that at least a portion of the first capacitor electrode PC1 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Furthermore, the second capacitor electrode PC2 may partially overlap with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the second capacitor electrode PC2 is provided between the first electrode P1 and the second electrode P2 so that at least a portion of the second capacitor electrode PC2 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Furthermore, the third capacitor electrode PC3 may partially overlap with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2, or may entirely overlap with the first electrode P1 and the second electrode P2. In other words, the third capacitor electrode PC3 is provided between the first electrode P1 and the second electrode P2 so that at least a portion of the third capacitor electrode PC3 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2.

[0031] (2.5) Inductor via As shown in FIGS. 1 to 3, the LC filter 1 includes a first inductor via V1, a second inductor via V2, and a third inductor via V3 as the multiple inductor vias V0.

[0032] The first inductor via V1 is connected between the first capacitor electrode PC1 and the first electrode P1. More specifically, the first inductor via V1 has a first end 11 and a second end 12. The first end 11 of the first inductor via V1 is connected to the first capacitor electrode PC1. The second end 12 of the first inductor via V1 is connected to the first electrode P1. The first inductor via V1 forms a first inductor L1 (see FIG. 4).

[0033] The second inductor via V2 is connected between the second capacitor electrode PC2 and the first electrode P1. More specifically, the second inductor via V2 has a third end 21 and a fourth end 22. The third end 21 of the second inductor via V2 is connected to the second capacitor electrode PC2. The fourth end 22 of the second inductor via V2 is connected to the first electrode P1. The second inductor via V2 forms a second inductor L2 (see FIG. 4). The second inductor via V2 includes a plurality of via conductors V21, V22 (two in the illustrated example) extending in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V21, V22 are connected in parallel between the second capacitor electrode PC2 and the first electrode P1. The plurality of via conductors V21, V22 are also arranged side by side along the second direction D2.

[0034] The third inductor via V3 is connected between the third capacitor electrode PC3 and the first electrode P1. More specifically, the third inductor via V3 has a fifth end 31 and a sixth end 32. The fifth end 31 of the third inductor via V3 is connected to the third capacitor electrode PC3. The sixth end 32 of the third inductor via V3 is connected to the first electrode P1. The third inductor via V3 forms a third inductor L3 (see FIG. 4). The third inductor via V3 includes a plurality of via conductors V31, V32 (two in the illustrated example) extending in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V31, V32 are connected in parallel between the third capacitor electrode PC3 and the first electrode P1. The plurality of via conductors V31, V32 are also arranged side by side along the second direction D2.

[0035] Each of the first inductor via V1, the second inductor via V2, and the third inductor via V3 includes at least one via conductor.

[0036] The number of via conductors in each of the second inductor vias V2 and the third inductor vias V3 is greater than the number of via conductors in the first inductor vias V1.

[0037] (2.6) Inductor pattern 1 to 3, the first inductor pattern portion PL1 has a first end connected to at least one of the first electrode P1, the first inductor via V1, and the first capacitor electrode PC1, and a second end connected to the input terminal T1. The first inductor pattern portion PL1 forms a fourth inductor L4 (see FIG. 4).

[0038] More specifically, the first inductor pattern portion PL1 includes a plurality of (two in the illustrated example) pattern portions P41 and P42 and a plurality of (three in the illustrated example) via conductors V41 to V43. The pattern portion P42 is connected to the first capacitor electrode PC1 through the via conductor V41. The pattern portion P41 is connected to the input terminal T1 through the via conductor V42. The pattern portions P41 and P42 are connected by the via conductor V43 and are arranged side by side in the first direction D1. The via conductor V41 corresponds to a first end of the first inductor pattern portion PL1, and the via conductor V42 corresponds to a second end of the first inductor pattern portion PL1. The pattern portion P41 is provided in a wound state on a plane in one dielectric layer (not illustrated) of the plurality of dielectric layers of the laminate 2. The pattern portion P42 is provided in a state of being wound on a plane on one of the plurality of dielectric layers of the laminate 2 (not shown) that is different from the dielectric layer on which the pattern portion P41 is provided.

[0039] 1 to 3, the first capacitor electrode PC1 and the third capacitor electrode PC3 of the LC filter 1 do not face each other. Specifically, the LC filter 1 does not include a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3. This allows the fourth inductor L4 (see FIG. 4) formed in the first inductor pattern portion PL1 to reduce loss for signals in the pass band and improve attenuation characteristics in non-pass bands including high-frequency bands.

[0040] The inductance of the first inductor pattern portion PL1 is greater than the inductance of each of the first inductor via V1, the second inductor via V2, and the third inductor via V3. This allows the fourth inductor L4 (see FIG. 4) formed by the first inductor pattern portion PL1 to reduce high-frequency components, thereby further increasing the attenuation in the high-frequency band.

[0041] As described above, the first inductor pattern portion PL1 (pattern portions P41, P42) is provided in a wound state on a plane on at least one of the plurality of dielectric layers (not shown) of the laminate 2. This makes it possible to easily increase the inductance of the fourth inductor L4 compared to the inductors (first inductor L1, second inductor L2, third inductor L3) formed by inductor vias.

[0042] More specifically, the first inductor pattern portion PL1 of the first embodiment is provided in a laminated and wound state on at least two of the multiple dielectric layers. This allows the inductance of the fourth inductor L4 to be further increased without increasing the planar area of ​​the first inductor pattern portion PL1. In other words, compared to an inductor without a laminated structure, the inductance of the fourth inductor L4 can be increased even if its area in plan view from the stacking direction (first direction D1) of the laminate 2 is smaller. The planar area of ​​the first inductor pattern portion PL1 refers to the area of ​​the region surrounded by the periphery of the first inductor pattern portion PL1 in plan view from the stacking direction (first direction D1) of the laminate 2. The periphery of the first inductor pattern portion PL1 refers to a line connecting the outermost edges of the first inductor pattern portion PL1 in plan view from the stacking direction of the laminate 2.

[0043] The first inductor pattern portion PL1 is provided between the first electrode P1 and the second electrode P2 in the stacking direction (first direction D1) of the multiple dielectric layers in the laminate 2. The first inductor pattern portion PL1 may partially overlap with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the first inductor pattern portion PL1 is provided between the first electrode P1 and the second electrode P2 so that at least a portion of the first inductor pattern portion PL1 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2.

[0044] In particular, the first inductor pattern portion PL1 is provided between the first electrode P1 and the first capacitor electrode PC1 in the stacking direction (first direction D1) of the laminate 2. The first inductor pattern portion PL1 may partially overlap with the first electrode P1 and the first capacitor electrode PC1, or may entirely overlap with the first electrode P1 and the first capacitor electrode PC1, in a plan view from the stacking direction of the laminate 2. In other words, the first inductor pattern portion PL1 is provided between the first electrode P1 and the first capacitor electrode PC1 so that at least a portion of the first inductor pattern portion PL1 overlaps with the first electrode P1 and the first capacitor electrode PC1 in a plan view from the stacking direction of the laminate 2.

[0045] The second capacitor electrode PC2 has a first portion PC21 and a second portion PC22. The first portion PC21 faces the first capacitor electrode PC1 in the stacking direction (first direction D1) of the laminate 2. The second portion PC22 faces the third capacitor electrode PC3 in the stacking direction (first direction D1) of the laminate 2.

[0046] The first inductor pattern portion PL1 is provided between the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2 in the stacking direction (first direction D1) of the laminate 2. The first inductor pattern portion PL1 may partially overlap with the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2, or may entirely overlap with the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2, in a plan view from the stacking direction of the laminate 2. In other words, the first inductor pattern portion PL1 is provided between the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2 such that at least a portion of the first inductor pattern portion PL1 overlaps with the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2, in a plan view from the stacking direction of the laminate 2.

[0047] (3) LC filter circuit configuration Next, the circuit configuration of the LC filter 1 will be described with reference to Fig. 4. In Fig. 4, the connection portions indicated by dashed lines correspond to the first electrode P1, the second electrode P2, the first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 in Figs.

[0048] As shown in FIG. 4, the LC filter 1 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4.

[0049] (3.1) First capacitor, first inductor The first capacitor C1 is formed between the first capacitor electrode PC1 and the second electrode P2. The first capacitor C1 is formed by capacitive coupling between the first capacitor electrode PC1 and the second electrode P2. The second electrode P2 is connected to the ground terminal GND. The first inductor L1 is connected between the first capacitor electrode PC1 and the first electrode P1. The first inductor L1 corresponds to the first inductor via V1.

[0050] (3.2) Second capacitor, second inductor The second capacitor C2 is formed between the second capacitor electrode PC2 and the second electrode P2. The second capacitor C2 is formed by capacitive coupling between the second capacitor electrode PC2 and the second electrode P2. The second inductor L2 is connected between the second capacitor electrode PC2 and the first electrode P1. The second inductor L2 corresponds to the second inductor via V2 (via conductors V21, V22, see FIG. 1).

[0051] (3.3) Third capacitor, third inductor The third capacitor C3 is formed between the third capacitor electrode PC3 and the second electrode P2. The third capacitor C3 is formed by capacitive coupling between the third capacitor electrode PC3 and the second electrode P2. The third capacitor C3 is connected to the output terminal T2. The third inductor L3 is connected between the third capacitor electrode PC3 and the first electrode P1. The third inductor L3 corresponds to the third inductor via V3 (via conductors V31, V32, see FIG. 1).

[0052] (3.4) Fourth Capacitor The fourth capacitor C4 is formed between the first capacitor electrode PC1 and the second capacitor electrode PC2 by capacitive coupling between the first capacitor electrode PC1 and the second capacitor electrode PC2.

[0053] (3.5) Fifth Capacitor The fifth capacitor C5 is formed between the second capacitor electrode PC2 and the third capacitor electrode PC3 by capacitive coupling between the second capacitor electrode PC2 and the third capacitor electrode PC3.

[0054] (3.6) Fourth inductor The fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1. The fourth inductor L4 corresponds to the first inductor pattern portion PL1.

[0055] In the LC filter 1, no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. In other words, in the LC filter 1, there is no capacitor formed by capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3.

[0056] (4) Filter characteristics Next, simulation results of the pass characteristics of the LC filter 1 according to the first embodiment will be described with reference to Fig. 5. Fig. 5 shows the pass characteristics of the LC filter 1 according to the first embodiment (solid lines S1 and S2) and the pass characteristics of an LC filter according to a comparative example (dashed lines S3 and S4). In Fig. 5, the horizontal axis represents frequency, and the vertical axis represents the insertion loss (solid lines S1 and S3) and return loss (solid lines S2 and S4) of the LC filter 1.

[0057] First, the LC filter of the comparative example will be described. In the LC filter of the comparative example, the fourth inductor L4 is not connected between the input terminal T1 and the first capacitor electrode PC1. Furthermore, in the LC filter of the comparative example, the first capacitor electrode PC1 and the third capacitor electrode PC3 face each other. Specifically, the LC filter of the comparative example has a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3. The insertion loss (dashed line S3) is approximately 10 dB at the high-frequency end of the pass band. On the other hand, in the non-pass band, which is a frequency band higher than the cutoff frequency, there is a band with an attenuation amount of less than 10 dB, and sufficient attenuation cannot be ensured. Furthermore, the reflection characteristic (dashed line S4) is lower than 12 dB across the entire pass band.

[0058] Next, the LC filter 1 according to the first embodiment will be described. As described above, in the LC filter 1 according to the first embodiment, a fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1 (see FIG. 4). In addition, in the LC filter 1 according to the first embodiment, the first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other (see FIGS. 1 to 3). Specifically, the LC filter 1 according to the first embodiment does not include a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3. As a result, an insertion loss (solid line S1) of approximately 10 dB is achieved at the high-frequency end of the pass band. Furthermore, in the non-pass band, which is higher in frequency than the pass band, an attenuation characteristic of 10 dB or more is obtained. Furthermore, the reflection characteristic (solid line S2) is lower than 12 dB across the entire pass band, similar to the reflection characteristic (dashed line S4) of the comparative example.

[0059] As described above, by applying a configuration in which the fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1 and there is no capacitor between the first capacitor electrode PC1 and the third capacitor electrode PC3 to the LC filter (low-pass filter) 1, it is possible to improve the attenuation characteristics in the non-pass band while maintaining the same level of loss for signals in the pass band.

[0060] (5) Effects The LC filter 1 according to the first embodiment includes a fourth inductor L4 connected to at least one of the first electrode P1, the first inductor via V1, and the first capacitor electrode PC1 and the input terminal T1 (first input / output port). The first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other. This allows the fourth inductor L4 formed in the first inductor pattern portion PL1 to improve (maintain) loss for signals in the pass band and improve attenuation characteristics in non-pass bands, including high-frequency bands.

[0061] In the LC filter 1 according to the first embodiment, the inductance of the first inductor pattern portion PL1 that forms the fourth inductor L4 is greater than the inductance of each of the first inductor via V1 that forms the first inductor L1, the second inductor via V2 that forms the second inductor L2, and the third inductor via V3 that forms the third inductor L3. This allows the fourth inductor L4 to reduce high-frequency components, thereby further increasing the amount of attenuation in the high-frequency band.

[0062] In the LC filter 1 according to the first embodiment, the first inductor pattern portion PL1 forming the fourth inductor L4 is provided in a wound state on a plane on at least one of the dielectric layers, which makes it easy to increase the inductance of the fourth inductor L4 compared to the inductors formed by inductor vias (the first inductor L1, the second inductor L2, and the third inductor L3).

[0063] In the LC filter 1 according to the first embodiment, the first inductor pattern portion PL1 forming the fourth inductor L4 is provided in a wound state by being laminated on at least two of the multiple dielectric layers. This allows the inductance of the fourth inductor L4 to be further increased without increasing the planar area of ​​the first inductor pattern portion PL1. The planar area of ​​the first inductor pattern portion PL1 refers to the area of ​​the region surrounded by the periphery of the first inductor pattern portion PL1 in a planar view from the stacking direction (first direction D1) of the laminate 2. The periphery of the first inductor pattern portion PL1 refers to a line connecting the outermost edges of the first inductor pattern portion PL1 in a planar view from the stacking direction of the laminate 2.

[0064] (6) Variations A modification of the first embodiment will be described below.

[0065] (6.1) Variation 1 As a first modification of the first embodiment, the first inductor via V1 may be formed of a plurality of via conductors, in other words, it is sufficient that the first inductor via V1 has at least one via conductor.

[0066] (6.2) Variation 2 As a second modification of the first embodiment, the second inductor via V2 may be formed of one via conductor, similar to the first inductor via V1. Alternatively, the second inductor via V2 may be formed of three or more via conductors. In other words, the second inductor via V2 only needs to have at least one via conductor.

[0067] (6.3) Variation 3 As a third modification of the first embodiment, the third inductor via V3 may be formed of one via conductor, similar to the first inductor via V1. Alternatively, the third inductor via V3 may be formed of three or more via conductors. In other words, the third inductor via V3 only needs to have at least one via conductor.

[0068] (6.4) Variation 4 As a fourth modification of the first embodiment, the first inductor pattern portion PL1 may be provided in a state of being wound on a plane on one of the plurality of dielectric layers (not shown) of the laminate 2. Moreover, the first inductor pattern portion PL1 may be provided in a state of being stacked and wound on three or more of the plurality of dielectric layers of the laminate 2. In other words, it is sufficient that the first inductor pattern portion PL1 is provided in a state of being wound on a plane on at least one of the plurality of dielectric layers of the laminate 2.

[0069] The LC filter 1 according to each of the above modifications also provides the same effects as the LC filter 1 according to the first embodiment.

[0070] (Embodiment 2) 6 to 8, the LC filter 1A according to the second embodiment differs from the LC filter 1 according to the first embodiment (see FIG. 1) in that the first inductor via V1 has a plurality of (two in the illustrated example) via conductors V11, V12. Note that, in the LC filter 1A according to the second embodiment, the same components as those in the LC filter 1 according to the first embodiment are denoted by the same reference numerals and will not be described.

[0071] (1) Composition As shown in Figs. 6 to 8, the first inductor via V1 of the second embodiment has a via conductor V11 (first partial via) and a via conductor V12 (second partial via). The via conductor V11 is connected to the first electrode P1 and the first inductor pattern portion PL1. The via conductor V12 is connected to the first capacitor electrode PC1 and the first inductor pattern portion PL1. Note that, with regard to the first inductor via V1 of the second embodiment, descriptions of the same configurations and functions as those of the first inductor via V1 of the first embodiment (see Fig. 1) will be omitted.

[0072] 6 to 8, the first inductor pattern portion PL1 of the second embodiment has a first end connected to at least one of the first electrode P1, the first inductor via V1, and the first capacitor electrode PC1, and a second end connected to the input terminal T1. The first inductor pattern portion PL1 forms a fourth inductor L4 (see FIG. 9).

[0073] More specifically, the first inductor pattern portion PL1 includes a plurality of pattern portions P41, P42 (two in the illustrated example), a connection portion P43, and a plurality of via conductors V42, V43 (two in the illustrated example). The pattern portion P42 is connected to the first inductor via V1 through the connection portion P43. The pattern portion P41 is connected to the input terminal T1 through the via conductor V42. The pattern portion P41 and the pattern portion P42 are connected by the via conductor V43 and are arranged side by side in the first direction D1. The connection portion P43 corresponds to a first end of the first inductor pattern portion PL1, and the via conductor V42 corresponds to a second end of the first inductor pattern portion PL1. Note that, with regard to the first inductor pattern portion PL1 of the second embodiment, a description of the same configuration and function as those of the first inductor pattern portion PL1 of the first embodiment (see FIG. 1) will be omitted.

[0074] As shown in FIG. 9, the first inductor L1 of the second embodiment has two inductors L11 and L12. The inductor L11 is formed by a via conductor V11. The inductor L12 is formed by a via conductor V12. The inductor L11 is connected to the second inductor L2, the third inductor L3, and the fourth inductor L4. The inductor L12 is connected to the first capacitor C1, the fourth capacitor C4, and the fourth inductor L4. Note that, with regard to the first inductor L1 of the second embodiment, a description of the same configuration and function as the first inductor L1 of the first embodiment (see FIG. 4) will be omitted.

[0075] In the LC filter 1A according to the second embodiment, similarly to the LC filter 1 (see FIG. 4) according to the first embodiment, no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, in the LC filter 1A, there is no capacitor formed by capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3.

[0076] (2) Effects In the LC filter 1A of embodiment 2, as in the LC filter 1 of embodiment 1, the fourth inductor L4 formed in the first inductor pattern portion PL1 can improve loss for signals in the pass band and also improve attenuation characteristics in non-pass bands including high-frequency bands.

[0077] (3) Variations As a modification of the second embodiment, the first inductor via V1 is not limited to being formed by two via conductors, and may be formed by three or more via conductors.

[0078] The LC filter 1A according to the above-described modified example also provides the same effects as the LC filter 1A according to the second preferred embodiment.

[0079] (Embodiment 3) 10 to 12, the LC filter 1B according to the third embodiment differs from the LC filter 1 according to the first embodiment (see FIG. 1) in that it includes a second inductor pattern portion PL2. Note that, with respect to the LC filter 1B according to the third embodiment, the same components as those of the LC filter 1 according to the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0080] (1) Composition As shown in FIGS. 10 to 12, the LC filter 1B according to the third embodiment includes a second inductor pattern portion PL2.

[0081] The second inductor pattern portion PL2 has a third end connected to at least one of the first electrode P1, the third inductor via V3, and the third capacitor electrode PC3, and a fourth end connected to the output terminal T2. The second inductor pattern portion PL2 forms a fifth inductor L5 (see FIG. 13).

[0082] More specifically, the second inductor pattern portion PL2 includes a plurality of (two in the illustrated example) pattern portions P51 and P52 and a plurality of (three in the illustrated example) via conductors V51 to V53. The pattern portion P51 is connected to the third capacitor electrode PC3 via the via conductor V51. The pattern portion P51 is connected to the output terminal T2 via the via conductor V52, the pattern portion P52, and the via conductor V53. The via conductor V51 corresponds to the third end of the second inductor pattern portion PL2, and the via conductor V53 corresponds to the second end of the second inductor pattern portion PL2.

[0083] Next, the circuit configuration of an LC filter 1B according to the third embodiment will be described with reference to Fig. 13. In Fig. 13, the connection portions indicated by dashed lines correspond to the first electrode P1, the second electrode P2, the first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 in Figs.

[0084] As shown in FIG. 13, the LC filter 1B includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, and a fifth inductor L5.

[0085] The fifth inductor L5 is connected between the output terminal T2 and the third capacitor electrode PC3. The fifth inductor L5 corresponds to the second inductor pattern portion PL2.

[0086] The inductance of the second inductor pattern portion PL2 is greater than the inductance of each of the first inductor via V1, the second inductor via V2, and the third inductor via V3. This allows the fifth inductor L5 (see FIG. 13) formed by the second inductor pattern portion PL2 to reduce high-frequency components, thereby further increasing the attenuation in the high-frequency band.

[0087] The second inductor pattern portion PL2 is provided in a wound state on a plane in at least one of the plurality of dielectric layers (not shown) of the laminate 2. This makes it possible to easily increase the inductance of the fifth inductor L5 compared to the inductors formed by inductor vias (the first inductor L1, the second inductor L2, and the third inductor L3).

[0088] In the LC filter 1B according to the third embodiment, no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, in the LC filter 1B, there is no capacitor formed by capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3.

[0089] (2) Filter characteristics Next, simulation results of the pass characteristics of the LC filter 1B according to the third embodiment will be described with reference to Fig. 14. Fig. 14 shows the pass characteristics of the LC filter 1B according to the third embodiment (solid lines S5 and S6) and the pass characteristics of an LC filter of a comparative example (dashed lines S7 and S8). In Fig. 14, the horizontal axis represents frequency, and the vertical axis represents the insertion loss (solid lines S5 and S7) and return loss (solid lines S6 and S8) of the LC filter 1B.

[0090] First, the LC filter of the comparative example will be described. In the LC filter of the comparative example, the fourth inductor L4 is not connected between the input terminal T1 and the first capacitor electrode PC1, and the fifth inductor L5 is not connected between the output terminal T2 and the third capacitor electrode PC3. Furthermore, in the LC filter of the comparative example, the first capacitor electrode PC1 and the third capacitor electrode PC3 face each other. Specifically, the LC filter of the comparative example includes a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3. The insertion loss (dashed line S7) is approximately 10 dB at the high-frequency end of the pass band. On the other hand, in the non-pass band, which is a frequency band higher than the cutoff frequency, there is a band with an attenuation amount of less than 10 dB, and sufficient attenuation cannot be ensured. The reflection characteristic (dashed line S8) is lower than 12 dB across the entire pass band.

[0091] Next, an LC filter 1B according to the third embodiment will be described. As described above, in the LC filter 1B according to the third embodiment, a fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1 (see FIG. 13), and a fifth inductor L5 is connected between the output terminal T2 and the third capacitor electrode PC3 (see FIG. 13). In addition, in the LC filter 1B according to the third embodiment, the first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other (see FIGS. 10 to 12). Specifically, the LC filter 1B according to the third embodiment does not include a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3. As a result, an insertion loss (solid line S5) of approximately 10 dB is achieved at the high-frequency end of the pass band. Furthermore, in a non-pass band that is higher in frequency than the pass band, an attenuation characteristic of 20 dB or more is obtained. Furthermore, the reflection characteristic (solid line S6) is lower than 16 dB throughout the entire pass band.

[0092] As described above, by applying a configuration to the LC filter (low-pass filter) 1B in which the fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1, the fifth inductor L5 is connected between the output terminal T2 and the third capacitor electrode PC3, and there is no capacitor between the first capacitor electrode PC1 and the third capacitor electrode PC3, it is possible to improve the attenuation characteristics in the non-pass band while maintaining the same level of loss for signals in the pass band.

[0093] (3) Effects The LC filter 1B according to the third embodiment includes a fifth inductor L5 connected to at least one of the first electrode P1, the third inductor via V3, and the third capacitor electrode PC3 and the output terminal T2 (second input / output port). This allows the fifth inductor L5 to reduce high-frequency components, thereby further increasing the attenuation in the high-frequency band.

[0094] In the LC filter 1B according to the third embodiment, the inductance of the second inductor pattern portion PL2 that forms the fifth inductor L5 is greater than the inductance of each of the first inductor via V1 that forms the first inductor L1, the second inductor via V2 that forms the second inductor L2, and the third inductor via V3 that forms the third inductor L3. This allows the fifth inductor L5 to reduce high-frequency components, thereby further increasing the attenuation in the high-frequency band.

[0095] In the LC filter 1B according to the third embodiment, the second inductor pattern portion PL2 forming the fifth inductor L5 is provided in a wound state on a plane in at least one of the dielectric layers, which makes it easy to increase the inductance of the fifth inductor L5 compared to the inductors formed by inductor vias (the first inductor L1, the second inductor L2, and the third inductor L3).

[0096] (4) Variations As a modification of the third embodiment, the second inductor pattern portion PL2 may be provided in a laminated and wound state on at least two of the plurality of dielectric layers (not shown) of the laminate 2. In other words, it is sufficient that the second inductor pattern portion PL2 is provided in a planar wound state on at least one of the plurality of dielectric layers of the laminate 2.

[0097] In the LC filter 1B according to the modification of the third embodiment, the second inductor pattern portion PL2 forming the fifth inductor L5 is provided in a wound state by being laminated on at least two of the dielectric layers, thereby making it possible to further increase the inductance of the fifth inductor L5 without increasing the planar area of ​​the second inductor pattern portion PL2.

[0098] The LC filter 1B according to the above-described modification also provides the same effects as the LC filter 1B according to the third preferred embodiment.

[0099] (Embodiment 4) 15 to 17, the LC filter 1C according to the fourth embodiment differs from the LC filter 1B according to the third embodiment (see FIG. 10) in that the third inductor via V3 has a plurality of (two in the illustrated example) via conductors V33, V34. Note that, in the LC filter 1C according to the fourth embodiment, the same components as those in the LC filter 1B according to the third embodiment are denoted by the same reference numerals and will not be described.

[0100] (1) Composition As shown in FIGS. 15 to 17, the third inductor via V3 of the fourth embodiment has a via conductor V33 (first partial via) and a via conductor V34 (second partial via). More specifically, the via conductor V32 in the third inductor via V3 has a via conductor V33 and a via conductor V34. The via conductor V33 is connected to the first electrode P1 and the second inductor pattern portion PL2. The via conductor V34 is connected to the third capacitor electrode PC3 and the second inductor pattern portion PL2. Note that, with regard to the third inductor via V3 of the fourth embodiment, descriptions of the same configurations and functions as those of the third inductor via V3 of the third embodiment (see FIG. 10) will be omitted.

[0101] As shown in FIG. 18, the third inductor L3 of the fourth embodiment has two inductors L31 and L32. The inductor L31 is formed by a via conductor V33. The inductor L32 is formed by a via conductor V34. The inductor L31 is connected to the first inductor L1, the second inductor L2, and the fifth inductor L5. The inductor L32 is connected to the third capacitor C3, the fifth capacitor C5, and the fifth inductor L5. Regarding the first inductor L1 of the second embodiment, a description of the same configuration and function as the first inductor L1 of the first embodiment (see FIG. 4) will be omitted.

[0102] In the LC filter 1C according to the fourth embodiment, similarly to the LC filter 1B according to the third embodiment (see FIG. 13), no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, in the LC filter 1C, there is no capacitor formed by capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3.

[0103] (2) Effects In the LC filter 1C according to the fourth embodiment, similarly to the LC filter 1B according to the third embodiment, the fifth inductor L5 can reduce high-frequency components, thereby further increasing the amount of attenuation in the high-frequency band.

[0104] (3) Variations As a modification of the fourth embodiment, the third inductor via V3 (via conductor V32) is not limited to being formed by two via conductors V33, V34 (partial vias), but may be formed by three or more via conductors (partial vias).

[0105] The LC filter 1C according to the above-described modification also provides the same effects as the LC filter 1C according to the fourth preferred embodiment.

[0106] (Embodiment 5) In the fifth embodiment, a configuration will be described in which the LC filters 1, 1A to 1C according to the first to fourth embodiments and their modifications are applied to a multiplexer 7 (see FIG. 19). Below, a case in which the LC filter 1 according to the first embodiment is applied to the multiplexer 7 will be described.

[0107] (1) Composition As shown in FIG. 19, the multiplexer 7 of embodiment 5 includes an input terminal T31, two output terminals T32 and T33, a first filter 71, a second filter 72, a plurality of (two in the illustrated example) inductors L10 and L20, and a plurality of (two in the illustrated example) capacitors C10 and C20.

[0108] The first filter 71 is connected between the input terminal T31 and the output terminal T32. The first filter 71 is a low-pass filter (LPF) that passes signals in a frequency band lower than a predetermined frequency, and includes an LC filter 1.

[0109] The inductor L10 has one end (first end) connected to the input terminal T31 and the other end (second end) connected to the first filter 71. The capacitor C10 is connected between the ground and a connection node between the inductor L10 and the first filter 71. The inductor L10 and the capacitor C10 form a low-pass filter, and function as a branching circuit for a high-frequency signal input to the input terminal T31.

[0110] The second filter 72 is connected between the input terminal T31 and the output terminal T33. The second filter 72 is a band-pass filter (BPF) or a high-pass filter (HPF) that passes signals in a frequency band higher than the pass band of the first filter 71.

[0111] The capacitor C20 has one end (first end) connected to the input terminal T31 and the other end (second end) connected to the second filter 72. The inductor L20 is connected between the ground and a connection node between the capacitor C20 and the second filter 72. The inductor L20 and the capacitor C20 form a high-pass filter, and function as a branching circuit for a high-frequency signal received at the input terminal T31.

[0112] (2) Effects By applying the LC filter 1 according to the first embodiment as the first filter 71 (low-pass filter) in the multiplexer 7 according to the fifth embodiment, it is possible to realize a multiplexer 7 having low loss and high attenuation characteristics. Note that, even when any of the LC filters 1A to 1C according to the second to fourth embodiments is applied as the first filter 71, the same effect can be achieved.

[0113] (3) Variations As a modification of the fifth embodiment, any of the LC filters 1, 1A to 1C according to the first to fourth embodiments and their modifications may be applied to a multiplexer 7A made up of three or more filters.

[0114] As shown in FIG. 20, the multiplexer 7A includes an input terminal T34, three output terminals T35 to T37, a first filter 71A, a second filter 72A, a third filter 73A, a plurality of inductors L10 and L30 (two in the illustrated example), and a plurality of capacitors C10 and C30 (two in the illustrated example).

[0115] The first filter 71A is connected between the input terminal T34 and the output terminal T35. The first filter 71A is a low-pass filter (LPF) that passes signals in a frequency band lower than a predetermined frequency, and may have a configuration similar to any of the LC filters 1, 1A to 1C according to the first to fourth embodiments and their respective modifications.

[0116] The inductor L10 has one end (first end) connected to the input terminal T34 and the other end (second end) connected to the first filter 71A. The capacitor C10 is connected between the connection node between the inductor L10 and the first filter 71A and ground. The inductor L10 and the capacitor C10 form a low-pass filter and function as a branching circuit for the high-frequency signal input to the input terminal T34.

[0117] The second filter 72A is connected between the input terminal T34 and the output terminal T36. The second filter 72A is a band-pass filter (BPF) that passes signals in a frequency band higher than the pass band of the first filter 71A.

[0118] The third filter 73A is connected between the input terminal T34 and the output terminal T37. The third filter 73A is a high-pass filter (HPF) or a band-pass filter (BPF) that passes signals in a frequency band higher than the pass band of the second filter 72A.

[0119] One end (first end) of the capacitor C30 is connected to the input terminal T34, and the other end (second end) is connected to the third filter 73A. The inductor L30 is connected between the connection node between the capacitor C30 and the third filter 73A and ground. The inductor L30 and the capacitor C30 form a high-pass filter, and function as a branching circuit for the high-frequency signal input to the input terminal T34.

[0120] In the multiplexer 7A according to the modification, by applying any one of the LC filters 1, 1A to 1C according to the first to fourth embodiments and the modifications as a low-pass filter provided in the pass path of the lowest frequency band signal, it is possible to realize a multiplexer 7A with low loss and high attenuation characteristics. In other words, in the multiplexer 7A, it is possible to improve the attenuation characteristics in the non-pass bands while maintaining the same level of loss for signals in the pass band.

[0121] The multiplexer 7A according to the above modification also provides the same effects as the multiplexer 7 according to the fifth embodiment.

[0122] (Embodiment 6) In the sixth embodiment, a high-frequency module 8 including any of the LC filters 1, 1A to 1C according to the first to fourth embodiments and their modifications, and a communication device 9 including the high-frequency module 8 will be described with reference to the drawings. The following describes a case where the LC filter 1 according to the first embodiment is used.

[0123] (1) High-frequency module As shown in Fig. 21, the high-frequency module 8 according to the sixth embodiment includes a filter 81 and an amplifier 82. The filter 81 includes the LC filter 1 (see Fig. 1).

[0124] The high-frequency module 8 is a module that is compatible with, for example, the 4G (fourth generation mobile communication) standard and the 5G (fifth generation mobile communication) standard. The 4G standard is, for example, the 3GPP (Third Generation Partnership Project, registered trademark) LTE (Long Term Evolution, registered trademark) standard. The 5G standard is, for example, the 5G NR (New Radio). The high-frequency module 8 is a module that is compatible with carrier aggregation and dual connectivity.

[0125] The high-frequency module 8 is configured to amplify a reception signal (high-frequency signal) received by an antenna 91 (described later) and output the amplified signal to a signal processing circuit 92 (described later). The high-frequency module 8 is also configured to amplify a transmission signal from the signal processing circuit 92 and output the amplified signal to the antenna 91. The high-frequency module 8 is controlled by the signal processing circuit 92, for example.

[0126] (2) Communications equipment 21, a communication device 9 according to the sixth embodiment includes a high-frequency module 8, at least one antenna 91 (one in the illustrated example), and a signal processing circuit 92. The communication device 9 is, for example, a mobile terminal (e.g., a smartphone), but is not limited to a mobile terminal and may be, for example, a wearable terminal (e.g., a smart watch).

[0127] The signal processing circuit 92 processes high-frequency signals (transmission signals and reception signals) passing through the high-frequency module 8. More specifically, the signal processing circuit 92 is configured to process reception signals received from the high-frequency module 8. The signal processing circuit 92 is also configured to process transmission signals to be output to the high-frequency module 8. The signal processing circuit 92 includes an RF signal processing circuit 93 and a baseband signal processing circuit 94.

[0128] The RF signal processing circuit 93 is, for example, an RFIC (Radio Frequency Integrated Circuit), and performs signal processing on a high-frequency signal (received signal). The RF signal processing circuit 93 performs signal processing such as down-conversion on the received signal received from the high-frequency module 8, and outputs the result to the baseband signal processing circuit 94. The RF signal processing circuit 93 also performs signal processing such as up-conversion on the transmission signal output from the baseband signal processing circuit 94, and outputs the result to the high-frequency module 8.

[0129] The baseband signal processing circuit 94 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 94 outputs the received signal received from the RF signal processing circuit 93 to the outside. This output signal (received signal) is used, for example, as an image signal for image display or as an audio signal for communication. The baseband signal processing circuit 94 also generates a transmission signal from a baseband signal (for example, an audio signal and an image signal) input from the outside, and outputs the generated transmission signal to the RF signal processing circuit 93.

[0130] (3) Effects By applying the LC filter 1 according to the first embodiment as the filter 81 (low-pass filter) in the high-frequency module 8 and communication device 9 according to the sixth embodiment, it is possible to realize a high-frequency module 8 and communication device 9 with low loss and high attenuation characteristics. That is, in the high-frequency module 8 and communication device 9, it is possible to improve the attenuation characteristics in the non-pass bands while maintaining the same level of loss for signals in the pass band. Note that the same effect can be achieved even when any of the LC filters 1A to 1C according to the second to fourth embodiments is applied as the filter 81.

[0131] (Embodiment 7) In the seventh embodiment, a multiplexer 7B as shown in FIGS. 22 to 25 will be described.

[0132] (1) Multiplexer structure 22 to 24, the multiplexer 7B includes a laminate 2, a plurality of terminals 3, a plurality of (two in the illustrated example) first electrodes P1, a second electrode P2, a plurality of capacitor electrodes PC0, PCH0, and a plurality of inductor vias V0, VH0. Also, the multiplexer 7B according to the seventh embodiment includes a first filter 71B and a second filter 72B as shown in FIG.

[0133] (1.1) Laminate The laminate 2 shown in FIGS. 22 to 24 has a rectangular parallelepiped or approximately rectangular parallelepiped shape and is formed by stacking a plurality of dielectric layers (not shown) in the stacking direction. In other words, the laminate 2 is a structure in which a plurality of dielectric layers are stacked. Each of the plurality of dielectric layers of the laminate 2 is formed of, for example, ceramic. Inside the laminate 2, inductors and capacitors are formed by a plurality of wiring pattern portions, a plurality of electrodes, and a plurality of vias (via conductors) formed on each dielectric layer. Note that the laminate 2 is not limited to a rectangular parallelepiped or approximately rectangular parallelepiped, and may be a solid having another shape.

[0134] The laminate 2 has a first main surface 201 and a second main surface 202. A second electrode P2 is formed on a second dielectric layer (not shown) adjacent to the second main surface 202 of the laminate 2. A plurality of first electrodes P1 are formed on the first dielectric layer (not shown) adjacent to the first main surface 201 of the laminate 2. In FIGS. 22 to 24, the plurality of first electrodes P1 are indicated by two-dot chain lines.

[0135] (1.2) Terminal The multiple terminals 3 (common terminal T40, first terminal T41, second terminal T42, and ground terminal GND) are flat electrodes and are provided on the laminate 2. More specifically, the multiple terminals 3 are arranged on the second main surface 202 of the laminate 2. The multiple terminals 3 are LGA terminals regularly arranged on the second main surface 202 of the laminate 2. The multiple terminals 3 are external terminals for connecting the multiplexer 7B to an external device (not shown).

[0136] The plurality of terminals 3 include a common terminal T40, a first terminal T41, and a second terminal T42. The plurality of terminals 3 are external terminals for connecting the multiplexer 7B to an external device (not shown).

[0137] (1.3) First electrode, second electrode As shown in FIGS. 22 to 24, the multiple first electrodes P1 are provided on a first dielectric layer (not shown) of the multiple dielectric layers of the laminate 2. Each of the multiple first electrodes P1 is a flat plate electrode. When viewed from a plane in the stacking direction (first direction D1) of the laminate 2, each first electrode P1 has a rectangular shape. As shown in FIG. 25, of the multiple first electrodes P1, the first electrode P11 is an electrode for the first filter 71B, and the first electrode P12 is an electrode for the second filter 72B.

[0138] The second electrode P2 is provided on a second dielectric layer (not shown) different from the first dielectric layer among the multiple dielectric layers of the laminate 2. The second electrode P2 is a flat plate electrode having a flat plate shape. The second electrode P2 is connected to the ground terminal GND. More specifically, the second electrode P2 is connected to the ground terminal GND disposed on the second main surface 202 of the laminate 2 through a via (not shown).

[0139] As described above, the first filter 71B and the second filter 72B are connected to the common ground terminal GND via the second electrode P2.

[0140] (1.4) Capacitor electrode of the first filter As shown in FIGS. 22 to 24, the first filter 71B includes a first capacitor electrode PC1, a second capacitor electrode PC2, and a third capacitor electrode PC3 as the plurality of capacitor electrodes PC0.

[0141] The first capacitor electrode PC1 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P11 and the second electrode P2 in the first direction D1. The first capacitor electrode PC1 is disposed apart from the second electrode P2 and forms a first capacitor C1 (see FIG. 25) between the first capacitor electrode PC1 and the second electrode P2. The first capacitor electrode PC1 is connected to the first inductor pattern portion PL1.

[0142] The second capacitor electrode PC2 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P11 and the second electrode P2 in the first direction D1. More specifically, the second capacitor electrode PC2 has a first portion PC21 and a second portion PC22. The second capacitor electrode PC2 is disposed apart from the second electrode P2 and forms a second capacitor C2 (see FIG. 25) between itself and the second electrode P2.

[0143] The third capacitor electrode PC3 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P11 and the second electrode P2 in the first direction D1. The third capacitor electrode PC3 is disposed apart from the second electrode P2 and forms a third capacitor C3 (see FIG. 25) between the third capacitor electrode PC3 and the second electrode P2. The third capacitor electrode PC3 is connected to the first terminal T41 through a via conductor V33.

[0144] The first capacitor electrode PC1 and the second capacitor electrode PC2 form a fourth capacitor C4 (see FIG. 25). The second capacitor electrode PC2 and the third capacitor electrode PC3 form a fifth capacitor C5 (see FIG. 25). More specifically, the first portion PC21 of the second capacitor electrode PC2 and the first capacitor electrode PC1 form the fourth capacitor C4. The second portion PC22 of the second capacitor electrode PC2 and the third capacitor electrode PC3 form the fifth capacitor C5.

[0145] The first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 are provided between the first electrode P11 and the second electrode P2 in the stacking direction (first direction D1) of the laminate 2. The first capacitor electrode PC1 may partially overlap the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the first capacitor electrode PC1 is provided between the first electrode P11 and the second electrode P2 such that at least a portion of the first capacitor electrode PC1 overlaps with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Furthermore, the second capacitor electrode PC2 may partially overlap with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the second capacitor electrode PC2 is provided between the first electrode P11 and the second electrode P2 so that at least a portion of the second capacitor electrode PC2 overlaps with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Furthermore, the third capacitor electrode PC3 may partially overlap with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2, or may entirely overlap with the first electrode P11 and the second electrode P2. In other words, the third capacitor electrode PC3 is provided between the first electrode P11 and the second electrode P2 so that at least a portion of the third capacitor electrode PC3 overlaps with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2.

[0146] (1.5) Inductor vias of the first filter As shown in FIGS. 22 to 24, the first filter 71B includes a first inductor via V1, a second inductor via V2, and a third inductor via V3 as the multiple inductor vias V0.

[0147] The first inductor via V1 is connected between the first capacitor electrode PC1 and the first electrode P11. More specifically, the first inductor via V1 has a first end 11 and a second end 12. The first end 11 of the first inductor via V1 is connected to the first capacitor electrode PC1. The second end 12 of the first inductor via V1 is connected to the first electrode P11. The first inductor via V1 forms a first inductor L1 (see FIG. 25).

[0148] The second inductor via V2 is connected between the second capacitor electrode PC2 and the first electrode P11. More specifically, the second inductor via V2 has a third end 21 and a fourth end 22. The third end 21 of the second inductor via V2 is connected to the second capacitor electrode PC2. The fourth end 22 of the second inductor via V2 is connected to the first electrode P11. The second inductor via V2 forms a second inductor L2 (see FIG. 25). The second inductor via V2 includes a plurality of via conductors V21, V22 (two in the illustrated example) extending in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V21, V22 are connected in parallel between the second capacitor electrode PC2 and the first electrode P11. The plurality of via conductors V21, V22 are also arranged side by side along the second direction D2.

[0149] The third inductor via V3 is connected between the third capacitor electrode PC3 and the first electrode P11. More specifically, the third inductor via V3 has a fifth end 31 and a sixth end 32. The fifth end 31 of the third inductor via V3 is connected to the third capacitor electrode PC3. The sixth end 32 of the third inductor via V3 is connected to the first electrode P11. The third inductor via V3 forms a third inductor L3 (see FIG. 25). The third inductor via V3 includes a plurality of via conductors V31, V32 (two in the illustrated example) extending in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V31, V32 are connected in parallel between the third capacitor electrode PC3 and the first electrode P11. The plurality of via conductors V31, V32 are also arranged side by side along the second direction D2.

[0150] (1.6) Inductor pattern part of the first filter 22 to 24, the first inductor pattern portion PL1 has a first end connected to the first capacitor electrode PC1 and a second end connected to the common terminal T40. The first inductor pattern portion PL1 forms a fourth inductor L4 (see FIG. 25).

[0151] More specifically, the first inductor pattern portion PL1 includes a plurality of (two in the illustrated example) pattern portions P41 and P42 and a plurality of (three in the illustrated example) via conductors V41 to V43. The pattern portion P42 is connected to the first capacitor electrode PC1 through the via conductor V41. The pattern portion P41 is connected to the common terminal T40 through the via conductor V42. The pattern portions P41 and P42 are connected by the via conductor V43 and are arranged side by side in the first direction D1. The via conductor V41 corresponds to a first end of the first inductor pattern portion PL1, and the via conductor V42 corresponds to a second end of the first inductor pattern portion PL1. The pattern portion P41 is provided in a wound state on a plane in one dielectric layer (not illustrated) of the plurality of dielectric layers of the laminate 2. The pattern portion P42 is provided in a state of being wound on a plane on one of the plurality of dielectric layers of the laminate 2 (not shown) different from the dielectric layer on which the pattern portion P41 is provided.

[0152] The first inductor pattern portion PL1 forms a helical coil. The helical coil is a coil of one turn or more. More preferably, the helical coil is a coil of two turns or more. In the first inductor pattern portion PL1, the distance between the pattern portion P41 and the pattern portion P42, i.e., the interlayer distance of the helical coil, is, for example, 50 μm or more.

[0153] (1.7) Capacitor electrode of the second filter As shown in Figures 22 to 24, the second filter 72B has a plurality of capacitor electrodes PCH0, including a first capacitor electrode PCH1, a second capacitor electrode PCH2, a third capacitor electrode PCH3, a fourth capacitor electrode PCH4, a fifth capacitor electrode PCH5, a sixth capacitor electrode PCH6, and a seventh capacitor electrode PCH7.

[0154] The first capacitor electrode PCH1 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The first capacitor electrode PCH1 is disposed apart from the second electrode P2 and forms a first capacitor CH1 (see FIG. 25) between the first capacitor electrode PCH1 and the second electrode P2. The first capacitor electrode PCH1 is connected to the first inductor via VH1.

[0155] The second capacitor electrode PCH2 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The second capacitor electrode PCH2 is disposed apart from the second electrode P2 and forms a second capacitor CH2 (see FIG. 25) between itself and the second electrode P2. The second capacitor electrode PCH2 is connected to the second inductor via VH2.

[0156] The third capacitor electrode PCH3 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The third capacitor electrode PCH3 is disposed apart from the second electrode P2 and forms a third capacitor CH3 (see FIG. 25) between the third capacitor electrode PCH3 and the second electrode P2. The third capacitor electrode PCH3 is connected to the second terminal T42 through a via conductor VH31.

[0157] The fourth capacitor electrode PCH4 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The fourth capacitor electrode PCH4 is disposed apart from the second capacitor electrode PCH2 and forms a fourth capacitor CH4 (see FIG. 25) between the fourth capacitor electrode PCH4 and the second capacitor electrode PCH2.

[0158] The fifth capacitor electrode PCH5 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The fifth capacitor electrode PCH5 is disposed apart from the second capacitor electrode PCH2 and forms a fifth capacitor CH5 (see FIG. 25) between the fifth capacitor electrode PCH5 and the second capacitor electrode PCH2.

[0159] The sixth capacitor electrode PCH6 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The sixth capacitor electrode PCH6 is disposed apart from the fourth capacitor electrode PCH4 and forms a sixth capacitor CH6 (see FIG. 25) between the sixth capacitor electrode PCH6 and the fourth capacitor electrode PCH4.

[0160] The seventh capacitor electrode PCH7 has a flat plate shape and is formed on a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The seventh capacitor electrode PCH7 is disposed apart from the first capacitor electrode PCH1 and forms a seventh capacitor CH7 (see FIG. 25) between itself and the first capacitor electrode PCH1. The seventh capacitor electrode PCH7 is connected to the via conductor VH71.

[0161] (1.8) Second filter inductor via As shown in FIGS. 22 to 24, the second filter 72B includes a first inductor via VH1, a second inductor via VH2, a third inductor via VH3, a fourth inductor via VH4, a fifth inductor via VH5, and a sixth inductor via VH6 as the multiple inductor vias VH0.

[0162] The first inductor via VH1 is connected between the first capacitor electrode PCH1 and the first electrode P12. The first inductor via VH1 forms the first inductor LH1 (see FIG. 25).

[0163] The second inductor via VH2 is connected between the second capacitor electrode PCH2 and the first electrode P12. The second inductor via VH2 forms the second inductor LH2 (see FIG. 25).

[0164] The third inductor via VH3 is connected between the third capacitor electrode PCH3 and the first electrode P12. The third inductor via VH3 forms the third inductor LH3 (see FIG. 25).

[0165] The fourth inductor via VH4 is connected between the first electrode P12 and the second electrode P2. The fourth inductor via VH4 forms the fourth inductor LH4 (see FIG. 25).

[0166] The fifth inductor via VH5 is connected between the first electrode P12 and the second electrode P2. The fifth inductor via VH5 forms a fifth inductor LH5 (see FIG. 25).

[0167] The sixth inductor via VH6 is connected between the first electrode P12 and the second electrode P2. The sixth inductor via VH6 forms a sixth inductor LH6 (see FIG. 25).

[0168] (1.9) Inductor pattern of the second filter 22 to 24, the inductor pattern portion PLH1 has a first end connected to the seventh capacitor electrode PCH7 and a second end connected to the common terminal T40. The inductor pattern portion PLH1 forms a seventh inductor LH7 (see FIG. 25).

[0169] More specifically, the inductor pattern portion PLH1 includes a plurality of (two in the illustrated example) pattern portions PLH11 and PLH12 and a plurality of (two in the illustrated example) via conductors VH71 and VH72. The pattern portion PLH11 is connected to the common terminal T40 via the via conductor V42. The pattern portion PLH12 is connected to the seventh capacitor electrode PCH7 via the via conductor VH71. The pattern portions PLH11 and PLH12 are connected by the via conductor VH72 and are arranged side by side in the first direction D1. The via conductor VH71 corresponds to a first end of the inductor pattern portion PLH1, and the via conductor V42 corresponds to a second end of the inductor pattern portion PLH1. The pattern portion PLH11 is provided in a wound state on a plane in one dielectric layer (not illustrated) of the plurality of dielectric layers of the laminate 2. The pattern portion PLH12 is provided in a state of being wound on a plane on one of the plurality of dielectric layers of the laminate 2 (not shown) that is different from the dielectric layer on which the pattern portion PLH11 is provided.

[0170] The inductor pattern portion PLH1 forms a helical coil. The helical coil is a coil of one turn or more. More preferably, the helical coil is a coil of two turns or more. In the inductor pattern portion PLH1, the distance between the pattern portion PLH11 and the pattern portion PLH12, i.e., the interlayer distance of the helical coil, is, for example, 50 μm or more.

[0171] (1.10) Arrangement of multiple inductor vias in the second filter As shown in FIGS. 22 to 24, in the second filter 72B, the first inductor via VH1 to the third inductor via VH3 are not directly connected to the second electrode P2, which is at ground potential. The first inductor via VH1 is connected to the first capacitor electrode PCH1, the second inductor via VH2 is connected to the second capacitor electrode PCH2, and the third inductor via VH3 is connected to the third capacitor electrode PCH3. The first capacitor electrode PCH1 to the third capacitor electrode PCH3 face the second electrode P2. These first inductor vias VH1 to VH3 are called open-end vias. The first inductor LH1 to the third inductor LH3 are called open-end coils. On the other hand, the fourth inductor via VH4 to the sixth inductor via VH6 are directly connected to the second electrode P2, which is at ground potential. These fourth inductor vias VH4 to VH6 are called short-circuit end vias. The fourth inductor LH4 to the sixth inductor LH6 are called short-circuit end coils.

[0172] The fourth inductor via VH4 to the sixth inductor via VH6 are arranged in a boundary region 74 between the first filter 71B and the second filter 72B. More specifically, the fourth inductor via VH4 to the sixth inductor via VH6 are arranged closer to the first filter 71B than the first inductor via VH1 to the third inductor via VH3. The fourth inductor via VH4 to the sixth inductor via VH6 are arranged to line up along the third direction D3. Here, the boundary region 74 is a region that overlaps with the first electrode P12 in a plan view from the stacking direction (first direction D1) of the multilayer body 2, and that is close to a boundary 75 between the first electrode P11 and the first electrode P12 in the second direction D2.

[0173] Current flows from the first capacitor CH1 to the third capacitor CH3 through the first inductor LH1 (first inductor via VH1) to the third inductor LH3 (third inductor via VH3) and through the fourth inductor LH4 (fourth inductor via VH4) to the sixth inductor LH6 (sixth inductor via VH6). That is, current flows from the open-end coil (open-end via) to the short-end coil (short-end via). As a result, the current flowing through the fourth inductor via VH4 to the sixth inductor via VH6 and the current flowing through the first inductor via V1 to the third inductor via V3 of the first filter 71B are opposite in direction, thereby reducing degradation of isolation between the first filter 71B and the second filter 72B.

[0174] (2) Multiplexer circuit configuration As shown in FIG. 25, the multiplexer 7B according to the seventh embodiment includes a common terminal T40, a first terminal T41, a second terminal T42, a first filter 71B, and a second filter 72B.

[0175] (2.1) Circuit configuration of the first filter The first filter 71B is connected between the common terminal T40 and the first terminal T41. The first filter 71B is a low-pass filter (LPF) that passes signals in a frequency band lower than a predetermined frequency.

[0176] The first filter 71B includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. Note that a description of the same configuration as the LC filter 1 according to the first embodiment will be omitted.

[0177] (2.2) Circuit configuration of the second filter The second filter 72B is connected between the common terminal T40 and the second terminal T42. The second filter 72B is a band-pass filter or a high-pass filter that passes signals in a frequency band higher than the pass band of the first filter 71B.

[0178] The second filter 72B includes a first capacitor CH1 (first capacitor for the second filter), a second capacitor CH2 (second capacitor for the second filter), a third capacitor CH3 (third capacitor for the second filter), a fourth capacitor CH4, a fifth capacitor CH5, and a sixth capacitor CH6. The second filter 72B also includes a first inductor LH1 (first inductor for the second filter), a second inductor LH2 (second inductor for the second filter), a third inductor LH3 (third inductor for the second filter), a fourth inductor LH4, a fifth inductor LH5, and a sixth inductor LH6. The second filter 72B also includes a seventh inductor LH7 (seventh inductor for the second filter) and a seventh capacitor CH7 (series capacitor for the second filter).

[0179] (2.2.1) First capacitor, first inductor, fourth inductor The first capacitor CH1 is formed between the first capacitor electrode PCH1 and the second electrode P2. The first capacitor CH1 is formed by capacitive coupling between the first capacitor electrode PCH1 and the second electrode P2. The first inductor LH1 is connected between the first capacitor electrode PCH1 and the first electrode P12. The first inductor LH1 corresponds to the first inductor via VH1. The fourth inductor LH4 is connected between the first electrode P12 and the second electrode P2. The fourth inductor LH4 corresponds to the fourth inductor via VH4.

[0180] (2.2.2) Second capacitor, second inductor, fifth inductor The second capacitor CH2 is formed between the second capacitor electrode PCH2 and the second electrode P2. The second capacitor CH2 is formed by capacitive coupling between the second capacitor electrode PCH2 and the second electrode P2. The second inductor LH2 is connected between the second capacitor electrode PCH2 and the first electrode P12. The second inductor LH2 corresponds to the second inductor via VH2. The fifth inductor LH5 is connected between the first electrode P12 and the second electrode P2. The fifth inductor LH5 corresponds to the fifth inductor via VH5.

[0181] (2.2.3) 3rd capacitor, 3rd inductor, 6th inductor The third capacitor CH3 is formed between the third capacitor electrode PCH3 and the second electrode P2. The third capacitor CH3 is formed by capacitive coupling between the third capacitor electrode PCH3 and the second electrode P2. The third capacitor CH3 is connected to the second terminal T42. The third inductor LH3 is connected between the third capacitor electrode PCH3 and the first electrode P12. The third inductor LH3 corresponds to the third inductor via VH3. The sixth inductor LH6 is connected between the first electrode P12 and the second electrode P2. The sixth inductor LH6 corresponds to the sixth inductor via VH6.

[0182] (2.2.4) 4th capacitor, 5th capacitor, 6th capacitor The fourth capacitor CH4 is formed between the second capacitor electrode PCH2 and the fourth capacitor electrode PCH4 by capacitive coupling between the second capacitor electrode PCH2 and the fourth capacitor electrode PCH4.

[0183] The fifth capacitor CH5 is formed between the second capacitor electrode PCH2 and the fifth capacitor electrode PCH5, and is formed by capacitive coupling between the second capacitor electrode PCH2 and the fifth capacitor electrode PCH5.

[0184] The sixth capacitor CH6 is formed between the fourth capacitor electrode PCH4 and the sixth capacitor electrode PCH6 by capacitive coupling between the fourth capacitor electrode PCH4 and the sixth capacitor electrode PCH6.

[0185] (2.2.5) 7th inductor, 7th capacitor The seventh inductor LH7 is connected between the common terminal T40 and the seventh capacitor CH7. The seventh inductor LH7 corresponds to the inductor pattern portion PLH1.

[0186] The seventh capacitor CH7 is connected between the seventh capacitor electrode PCH7 and the first capacitor electrode PCH1. The seventh capacitor CH7 is formed by capacitive coupling between the seventh capacitor electrode PCH7 and the first capacitor electrode PCH1. The seventh capacitor CH7 is connected in series with the seventh inductor LH7.

[0187] (3) Effects In the multiplexer 7B according to the seventh embodiment, the fourth inductor via VH4 to the sixth inductor via VH6 of the second filter 72B are arranged in the boundary region 74 between the first filter 71B and the second filter 72B. This reduces the degradation of isolation between the first filter 71B and the second filter 72B.

[0188] (Embodiment 8) The multiplexer 7C according to the eighth embodiment differs from the multiplexer 7B according to the seventh embodiment (see FIGS. 22 to 24) in that a plurality of inductor vias VH0 are arranged as shown in FIGS. 26 and 27. Note that, with respect to the multiplexer 7C according to the eighth embodiment, the same components as those of the multiplexer 7B according to the seventh embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0189] (1) Multiplexer structure Similar to the multiplexer 7B according to the seventh embodiment, the multiplexer 7C according to the eighth embodiment includes a laminate 2, a plurality of terminals 3, a plurality of first electrodes P11, P12, a plurality of capacitor electrodes PC0, and a plurality of inductor vias VH0, as shown in Fig. 26 and Fig. 27. Similarly to the multiplexer 7B according to the seventh embodiment, the multiplexer 7C according to the eighth embodiment also includes a first filter 71C and a second filter 72C, as shown in Fig. 26 and Fig. 27.

[0190] (1.1) Second filter inductor via Similar to the multiplexer 7B of the seventh embodiment (see Figures 22 to 24), the second filter 72C of the eighth embodiment has a first inductor via VH1, a second inductor via VH2, a third inductor via VH3, a fourth inductor via VH4, a fifth inductor via VH5, and a sixth inductor via VH6 as multiple inductor vias VH0, as shown in Figures 26 and 27.

[0191] (1.2) Arrangement of multiple inductor vias in the second filter 26 and 27, in a second filter 72C of the eighth embodiment, similarly to the seventh embodiment, the first to third inductor vias VH1 to VH3 are not directly connected to the second electrode P2, which is at ground potential, but are connected to the first to third capacitor electrodes PCH1 to PCH3, and the first to third capacitor electrodes PCH1 to PCH3 face the second electrode P2. On the other hand, the fourth to sixth inductor vias VH4 to VH6 are directly connected to the second electrode P2, which is at ground potential.

[0192] In the eighth embodiment, the first inductor vias VH1 to VH3 are arranged in a staggered pattern. Furthermore, the fourth inductor vias VH4 to VH6 are arranged in a staggered pattern. More specifically, the fourth inductor vias VH4 and VH6, and the second inductor vias VH2 are arranged in the boundary region 74 between the first filter 71C and the second filter 72C. More specifically, the fourth inductor vias VH4, VH6, and VH2 are arranged closer to the first filter 71C than the first inductor vias VH1, VH3, and VH5. Furthermore, the fourth inductor vias VH4, VH2, and VH6 are arranged side by side along the third direction D3.

[0193] (2) Effects In the multiplexer 7C according to the eighth embodiment, there are also more short-circuited vias (fourth inductor via VH4, sixth inductor via VH6) than open-circuited vias (second inductor via VH2) in the boundary region 74 between the first filter 71C and the second filter 72C. This causes the current flowing through the fourth inductor via VH4 and the sixth inductor via VH6 to be opposite to the current flowing through the first inductor via V1 to the third inductor via V3 of the first filter 71C, thereby reducing degradation of isolation between the first filter 71C and the second filter 72C.

[0194] (Embodiment 9) A multiplexer 7B according to the ninth embodiment (see FIG. 25) differs from the multiplexer 7B according to the seventh embodiment in that the inductance of the fourth inductor L4 of the first filter 71B and the inductance of the seventh inductor LH7 of the second filter 72B are large. Note that, with respect to the multiplexer 7B according to the ninth embodiment, components similar to those of the multiplexer 7B according to the seventh embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0195] (1) Multiplexer circuit configuration Similar to the multiplexer 7B according to the seventh embodiment, the multiplexer 7B according to the ninth embodiment includes a first filter 71B and a second filter 72B.

[0196] The first filter 71B of the 9th embodiment includes a first capacitor C1 to a fifth capacitor C5 and a first inductor L1 to a fourth inductor L4, similar to the first filter 71B of the 7th embodiment. Note that a description of the same configuration as the first filter 71B of the 7th embodiment will be omitted.

[0197] The second filter 72B of the 9th embodiment includes a first capacitor CH1 to a seventh capacitor CH7 and a first inductor LH1 to a seventh inductor LH7, similar to the second filter 72B of the 7th embodiment. Note that a description of the same configuration as the second filter 72B of the 7th embodiment will be omitted.

[0198] In the first filter 71B of the ninth embodiment, the inductance of the fourth inductor L4 is larger than the inductance of each of the first inductor L1 to the third inductor L3. Since the fourth inductor L4 is formed by the first inductor pattern portion PL1, the inductance can be made larger than when the fourth inductor L4 is formed by an inductor via.

[0199] In the second filter 72B of the ninth embodiment, the inductance of the seventh inductor LH7 is larger than the inductance of each of the first inductor LH1 to sixth inductor LH6. Since the seventh inductor LH7 is formed by the inductor pattern portion PLH1, it is possible to increase the inductance compared to when the seventh inductor LH7 is formed by an inductor via.

[0200] The multiplexer 7B according to the ninth embodiment can obtain bandpass characteristics as shown in Fig. 28. Fig. 28 shows the bandpass characteristics of the first filter 71B (solid line S9) and the bandpass characteristics of the second filter 72B (dashed line S10).

[0201] In the first filter 71B, attenuation is obtained in a non-pass band that is higher in frequency than the pass band of the first filter 71B, while in the second filter 72B, attenuation is obtained in a non-pass band that is lower in frequency than the pass band of the second filter 72B.

[0202] (2) Effects In the multiplexer 7B according to the ninth embodiment, the inductance of the fourth inductor L4 of the first filter 71B is greater than the inductance of each of the first inductor L1 to third inductor L3. Also, the inductance of the seventh inductor LH7 of the second filter 72B is greater than the inductance of each of the first inductor LH1 to sixth inductor LH6. This improves the characteristics of the multiplexer 7B.

[0203] (3) Variations As a modification of the ninth embodiment, the inductance of the fourth inductor L4 of the first filter 71B and the inductance of the seventh inductor LH7 of the second filter 72B are not necessarily both large, and only the inductance of the fourth inductor L4 of the first filter 71B may be large. More specifically, the inductance of the fourth inductor L4 is larger than the inductance of each of the first inductor L1 to the third inductor L3. Alternatively, only the inductance of the seventh inductor LH7 of the second filter 72B may be large. More specifically, the inductance of the seventh inductor LH7 is larger than the inductance of each of the first inductor LH1 to the sixth inductor LH6. In short, it is sufficient that the inductance of at least one of the fourth inductor L4 of the first filter 71B and the seventh inductor LH7 of the second filter 72B is large.

[0204] (Embodiment 10) The multiplexer 7B according to the tenth embodiment differs from the multiplexer 7B according to the seventh embodiment in that the seventh inductor LH7 of the second filter 72B is a coil with multiple turns (four turns in the illustrated example) as shown in Fig. 29. Note that, with respect to the multiplexer 7B according to the tenth embodiment, components similar to those of the multiplexer 7B according to the seventh embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0205] (1) Composition In the multiplexer 7B according to the tenth embodiment, the seventh inductor LH7 of the second filter 72B is a multi-turn coil as shown in Fig. 29. The seventh inductor LH7 has a plurality of (eight in the illustrated example) inductor pattern portions PLH21 and a plurality of (eight in the illustrated example) inductor vias VH73.

[0206] Half of the multiple inductor pattern portions PLH21 are provided on one dielectric layer (not shown) of the multiple dielectric layers of the laminate 2. The remaining inductor pattern portions PLH21 are provided on one dielectric layer (not shown) of the multiple dielectric layers of the laminate 2 that is different from the above-mentioned dielectric layer.

[0207] The multiple inductor vias VH73 are provided between two dielectric layers on which multiple inductor pattern portions PLH21 are provided in the stacking direction of the laminate 2. Each inductor via VH73 is connected to two inductor pattern portions PLH21.

[0208] (2) Effects According to the multiplexer 7B of the tenth embodiment, it is easy to increase the inductance of the seventh inductor LH7.

[0209] As a modification of the tenth embodiment, the seventh inductor LH7 of the second filter 72B is not limited to being a multi-turn coil, but may be a one-turn coil. In other words, the seventh inductor LH7 may be a coil of one or more turns. This allows the inductance of the seventh inductor LH7 to be larger than when it is configured using an inductor via.

[0210] The fifth inductor L5 of the first filter 71B may be a multi-turn coil as shown in Fig. 29, or may be a one-turn coil. In short, the fifth inductor L5 of the first filter 71B may be a coil of one or more turns. This allows the inductance of the fifth inductor L5 to be larger than when it is configured using an inductor via.

[0211] As another modification of the tenth embodiment, the seventh inductor LH7 of the second filter 72B may be a spiral coil as shown in Fig. 30. The seventh inductor LH7 has an inductor pattern portion PLH31. This allows the inductance of the seventh inductor LH7 to be larger than when it is configured with an inductor via.

[0212] The fifth inductor L5 of the first filter 71B may be a spiral coil as shown in Fig. 30. This allows the inductance of the fifth inductor L5 to be larger than when it is configured with an inductor via.

[0213] (Embodiment 11) A multiplexer 7B according to the eleventh embodiment (see FIG. 25) differs from the multiplexer 7B according to the seventh embodiment in that the ratio of inductance to capacitance in a second filter 72B is greater than the ratio of inductance to capacitance in a first filter 71B. Note that, with respect to the multiplexer 7B according to the eleventh embodiment, components similar to those of the multiplexer 7B according to the seventh embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0214] In the multiplexer 7B according to the eleventh embodiment, the ratio of the inductance of the seventh inductor LH7 to the capacitance of the seventh capacitor CH7 in the second filter 72B is greater than the ratio of the inductance of the fourth inductor L4 to the capacitance of the first capacitor C1 in the first filter 71B, thereby enabling successful branching between the first filter 71B and the second filter 72B.

[0215] (Embodiment 12) 31, the multiplexer 7D according to the twelfth embodiment differs from the multiplexer 7B according to the ninth embodiment (see FIG. 25) in that it includes an inductor LA1 and a capacitor CA1. Note that, with respect to the multiplexer 7D according to the twelfth embodiment, the same components as those of the multiplexer 7B according to the ninth embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0216] (1) Multiplexer circuit configuration 31, the multiplexer 7D according to the twelfth embodiment includes an inductor LA1 and a capacitor CA1. Similarly to the multiplexer 7B according to the seventh embodiment, the multiplexer 7D also includes a first filter 71D and a second filter 72D.

[0217] The inductor LA1 is connected between the common terminal T40 and the branch point T43. The branch point T43 is the branch point between the first filter 71D and the second filter 72D. The inductor LA1 is formed of, for example, an inductor via.

[0218] The capacitor CA1 is connected between the path between the common terminal T40 and the branch point T43 and ground. More specifically, the capacitor CA1 is connected between the path between the inductor LA1 and the branch point T43 and ground. The capacitor CA1 is formed, for example, by two capacitor electrodes.

[0219] (2) Effects The multiplexer 7D according to the twelfth embodiment can also achieve a steep attenuation characteristic, similar to the multiplexer 7B according to the 9th embodiment, thereby improving the characteristics of the multiplexer 7B.

[0220] (3) Variations As a modification of the twelfth embodiment, the multiplexer 7D may include only the inductor LA1, rather than both the inductor LA1 and the capacitor CA1. Alternatively, the multiplexer 7D may include only the capacitor CA1. In short, the multiplexer 7D may include at least one of an inductor and a capacitor.

[0221] The above-described embodiments and modifications are merely a part of the various embodiments and modifications of the present invention. Furthermore, the embodiments and modifications can be modified in various ways depending on the design, etc., as long as the object of the present invention can be achieved.

[0222] (Aspect) The present specification discloses the following aspects.

[0223] An LC filter (1; 1A; 1B; 1C) according to a first aspect includes a laminate (2), a first input / output port (input terminal T1), a second input / output port (output terminal T2), a first electrode (P1), a second electrode (P2), a first capacitor electrode (PC1), a second capacitor electrode (PC2), a third capacitor electrode (PC3), a first inductor via (V1), a second inductor via (V2), a third inductor via (V3), and a first inductor pattern portion (PL1). The laminate (2) is formed by stacking a plurality of dielectric layers. The first input / output port is provided in the laminate (2). The second input / output port is provided in the laminate (2) and is different from the first input / output port. The first electrode (P1) is a flat-plate-shaped electrode provided in a first dielectric layer of the plurality of dielectric layers. The second electrode (P2) is a flat-plate-shaped electrode provided on a second dielectric layer different from the first dielectric layer among the multiple dielectric layers. The first capacitor electrode (PC1) forms a first capacitor (C1) together with the second electrode (P2). The second capacitor electrode (PC2) forms a second capacitor (C2) together with the second electrode (P2). The third capacitor electrode (PC3) forms a third capacitor (C3) together with the second electrode (P2). The first inductor via (V1) has a first end (11) connected to the first capacitor electrode (PC1) and a second end (12) connected to the first electrode (P1), thereby forming a first inductor (L1). The second inductor via (V2) has a third end (21) connected to the second capacitor electrode (PC2) and a fourth end (22) connected to the first electrode (P1), thereby forming a second inductor (L2). The third inductor via (V3) has a fifth end (31) connected to the third capacitor electrode (PC3) and a sixth end (32) connected to the first electrode (P1), forming a third inductor (L3). The first inductor pattern portion (PL1) forms a fourth inductor (L4). The first capacitor electrode (PC1) and the second capacitor electrode (PC2) form a fourth capacitor (C4). The second capacitor electrode (PC2) and the third capacitor electrode (PC3) form a fifth capacitor (C5).The first inductor pattern portion (PL1) has a first end (via conductor V41) connected to at least one of the first electrode (P1), the first inductor via (V1), and the first capacitor electrode (PC1), and a second end (via conductor V42) connected to the first input / output port. The first capacitor electrode (PC1) and the third capacitor electrode (PC3) do not face each other.

[0224] According to the LC filter (1; 1A; 1B; 1C) of the first aspect, the fourth inductor (L4) formed by the first inductor pattern portion (PL1) can improve loss for signals in the pass band and also improve attenuation characteristics in non-pass bands including high frequency bands.

[0225] In the LC filter (1; 1A; 1B; 1C) according to the second aspect, in the first aspect, the inductance of the first inductor pattern portion (PL1) is greater than the inductance of each of the first inductor via (V1), the second inductor via (V2), and the third inductor via (V3).

[0226] According to the LC filter (1; 1A; 1B; 1C) of the second aspect, the fourth inductor (L4) can reduce high frequency components, so that the attenuation in the high frequency band can be further increased.

[0227] In the LC filter (1; 1A; 1B; 1C) according to the third aspect, in the first or second aspect, the first inductor pattern portion (PL1) is provided in a wound state on a plane in at least one of the plurality of dielectric layers.

[0228] According to the LC filter (1; 1A; 1B; 1C) of the third aspect, the inductance of the fourth inductor (L4) can be easily increased compared to the inductors (first inductor L1, second inductor L2, third inductor L3) formed by inductor vias (first inductor via V1, second inductor via V2, third inductor via V3).

[0229] In the LC filter (1; 1A; 1B; 1C) according to the fourth aspect, in the third aspect, the first inductor pattern portion (PL1) is arranged in a stacked and wound state on at least two of the plurality of dielectric layers.

[0230] According to the LC filter (1; 1A; 1B; 1C) of the fourth aspect, the inductance of the fourth inductor (L4) can be further increased without increasing the planar area of ​​the first inductor pattern portion (PL1).

[0231] An LC filter (1B; 1C) according to a fifth aspect is the same as any one of the first to fourth aspects, and further includes a second inductor pattern portion (PL2). The second inductor pattern portion (PL2) forms a fifth inductor (L5). The second inductor pattern portion (PL2) has a third end (via conductor V51) connected to at least one of the first electrode (P1), the third inductor via (V3), and the third capacitor electrode (PC3), and a fourth end (via conductor V53) connected to the second input / output port (output terminal T2).

[0232] According to the LC filter (1B; 1C) of the fifth aspect, the fifth inductor (L5) can reduce high frequency components, so that the amount of attenuation in the high frequency band can be further increased.

[0233] In the LC filter (1B; 1C) according to the sixth aspect, in the fifth aspect, the inductance of the second inductor pattern portion (PL2) is greater than the inductance of each of the first inductor via (V1), the second inductor via (V2), and the third inductor via (V3).

[0234] According to the LC filter (1B; 1C) of the sixth aspect, the fifth inductor (L5) can reduce high frequency components, so that the amount of attenuation in the high frequency band can be further increased.

[0235] In the LC filter (1B; 1C) according to the seventh aspect, in the fifth or sixth aspect, the second inductor pattern portion (PL2) is provided in a wound state on a plane in at least one of the plurality of dielectric layers.

[0236] According to the LC filter (1B; 1C) of the seventh aspect, the inductance of the fifth inductor (L5) can be easily increased compared to the inductors (first inductor L1, second inductor L2, third inductor L3) formed by the inductor vias (first inductor via V1, second inductor via V2, third inductor via V3).

[0237] In the LC filter (1B; 1C) according to the eighth aspect, in the seventh aspect, the second inductor pattern portion (PL2) is provided in a laminated and wound state on at least two of the plurality of dielectric layers.

[0238] According to the LC filter (1B; 1C) of the eighth aspect, the inductance of the fifth inductor (L5) can be further increased without increasing the planar area of ​​the second inductor pattern portion (PL2).

[0239] In an LC filter (1C) according to a ninth aspect, in any one of the fifth to eighth aspects, the third inductor via (V3) has a first partial via (via conductor V33) and a second partial via (via conductor V34). The first partial via (via conductor V33) is connected to the first electrode (P1) and the second inductor pattern portion (PL2). The second partial via (via conductor V34) is connected to the third capacitor electrode (PC3) and the second inductor pattern portion (PL2).

[0240] In the LC filter (1; 1A; 1B; 1C) according to the tenth aspect, in any one of the first to ninth aspects, the first inductor pattern portion (PL1) is arranged between the first electrode (P1) and the second electrode (P2) in the stacking direction of the multiple dielectric layers in the laminate (2).

[0241] In the LC filter (1; 1A; 1B; 1C) according to the eleventh aspect, in the tenth aspect, the first inductor pattern portion (PL1) is arranged between the first electrode (P1) and the first capacitor electrode (PC1) in the stacking direction (first direction D1) of the laminate (2).

[0242] In an LC filter (1; 1A; 1B; 1C) according to a twelfth aspect, in the eleventh aspect, the second capacitor electrode (PC2) has a first portion (PC21) and a second portion (PC22). The first portion (PC21) faces the first capacitor electrode (PC1). The second portion (PC22) faces the third capacitor electrode (PC3). The first inductor pattern portion (PL1) is provided between the first electrode (P1) and the first portion (PC21) of the second capacitor electrode (PC2) in the stacking direction (first direction D1) of the laminate (2).

[0243] In an LC filter (1A) according to a thirteenth aspect, in any one of the first to twelfth aspects, the first inductor via (V1) has a first partial via (via conductor V11) and a second partial via (via conductor V12). The first partial via is connected to the first electrode (P1) and the first inductor pattern portion (PL1). The second partial via is connected to the first capacitor electrode (PC1) and the first inductor pattern portion (PL1).

[0244] In the LC filter (1; 1A; 1B; 1C) according to the fourteenth aspect, in any one of the first to thirteenth aspects, the first capacitor electrode (PC1), the second capacitor electrode (PC2) and the third capacitor electrode (PC3) are arranged between the first electrode (P1) and the second electrode (P2) in the stacking direction (first direction D1) of the multiple dielectric layers in the laminate (2).

[0245] In an LC filter (1; 1A; 1B; 1C) according to a fifteenth aspect, in any one of the first to fourteenth aspects, each of the first inductor via (V1), the second inductor via (V2), and the third inductor via (V3) includes at least one via conductor, and the number of via conductors in each of the second inductor via (V2) and the third inductor via (V3) is greater than the number of via conductors in the first inductor via (V1).

[0246] In an LC filter (1; 1A; 1B; 1C) according to a sixteenth aspect, in any one of the first to fifteenth aspects, the plurality of dielectric layers are made of ceramic.

[0247] The LC filter (1; 1A; 1B; 1C) according to the seventeenth aspect functions as a low-pass filter that passes signals in a frequency band lower than a specific frequency in any one of the first to sixteenth aspects.

[0248] A multiplexer (7; 7A; 7B; 7C; 7D) according to an eighteenth aspect includes a first filter (71; 71A; 71B; 71C; 71D) and a second filter (72; 72A; 72B; 72C; 72D). The first filter (71; 71A; 71b; 71C; 71D) includes an LC filter (1; 1A; 1B; 1C) according to any one of the first to seventeenth aspects. The second filter (72; 72A; 72B; 72C; 72D) passes signals in a frequency band higher than the pass band of the first filter (71; 71A; 71b; 71C; 71D).

[0249] A high-frequency module (8) according to a nineteenth aspect includes a filter (81) including the LC filter (1; 1A; 1B; 1C) according to any one of the first to seventeenth aspects, and an amplifier (82).

[0250] A communication device (9) according to a twentieth aspect includes the high-frequency module (8) according to the nineteenth aspect and a signal processing circuit (92).

[0251] A multiplexer (7B; 7C; 7D) according to a twenty-first aspect includes a first filter (71B; 71C; 71D), a second filter (72B; 72C; 72D), and a laminate (2). The first filters (71B; 71C; 71D) are low-pass filters. The second filters (72B; 72C; 72D) pass signals in a frequency band higher than the pass band of the first filters (71B; 71C; 71D). The laminate (2) is formed by stacking a plurality of dielectric layers. The first filter (71B; 71C; 71D) includes a first electrode (P11), a second electrode (P2), a first capacitor electrode (PC1), a second capacitor electrode (PC2), a third capacitor electrode (PC3), a first inductor via (V1), a second inductor via (V2), a third inductor via (V3), and a first inductor pattern portion (PL1). The first electrode (P11) is provided on a first dielectric layer of the plurality of dielectric layers. The second electrode (P2) is provided on a second dielectric layer different from the first dielectric layer of the plurality of dielectric layers and is a ground electrode. The first capacitor electrode (PCH1) forms a first capacitor (CH1) together with the second electrode (P2). The second capacitor electrode (PCH2) forms a second capacitor (CH2) together with the second electrode (P2). The third capacitor electrode (PCH3) forms a third capacitor (CH3) between itself and the second electrode (P2). The first inductor via (V1) has a first end connected to the first capacitor electrode (PC1) and a second end connected to the first electrode (P11), forming a first inductor (L1). The second inductor via (V2) has a third end connected to the second capacitor electrode (PC2) and a fourth end connected to the first electrode (P11), forming a second inductor (L2). The third inductor via (V3) has a fifth end connected to the third capacitor electrode (PC3) and a sixth end connected to the first electrode (P11), forming a third inductor (L3). The first inductor pattern portion (PL1) forms a fourth inductor (L4).The second filter (72B; 72C; 72D) includes a first electrode for the second filter (first electrode P12), a second electrode for the second filter (second electrode P2), a first capacitor electrode for the second filter (first capacitor electrode PCH1), a second capacitor electrode for the second filter (second capacitor electrode PCH2), a third capacitor electrode for the second filter (third capacitor electrode PCH3), a first inductor via for the second filter (first inductor via VH1), a second inductor via for the second filter (second inductor via VH2), a third inductor via for the second filter (third inductor via VH3), a fourth inductor via for the second filter (fourth inductor via VH4), a fifth inductor via for the second filter (fifth inductor via VH5), and a sixth inductor via for the second filter (sixth inductor via VH6). The first electrode for the second filter is provided in a first dielectric layer of the plurality of dielectric layers. The second filter second electrode is provided on a second dielectric layer different from the first dielectric layer among the multiple dielectric layers and serves as a ground electrode. The second filter first capacitor electrode forms a second filter first capacitor (first capacitor CH1) together with the second filter second electrode. The second filter second capacitor electrode forms a second filter second capacitor (second capacitor CH2) together with the second filter second electrode. The second filter third capacitor electrode forms a second filter third capacitor (third capacitor CH3) together with the second filter second electrode. The second filter first inductor via is connected between the second filter first capacitor electrode and the second filter first electrode to form a second filter first inductor (first inductor LH1). The second filter second inductor via is connected between the second filter second capacitor electrode and the second filter first electrode to form a second filter second inductor (second inductor LH2). The second filter third inductor via is connected between the second filter third capacitor electrode and the second filter first electrode, and forms a second filter third inductor (third inductor LH3).The second filter fourth inductor via is connected between the second filter first electrode and the second filter second electrode to form a second filter fourth inductor (fourth inductor LH4) connected in series with the second filter first inductor. The second filter fifth inductor via is connected between the second filter first electrode and the second filter second electrode to form a second filter fifth inductor (fifth inductor LH5) connected in series with the second filter second inductor. The second filter sixth inductor via is connected between the second filter first electrode and the second filter second electrode to form a second filter sixth inductor (sixth inductor LH6) connected in series with the second filter third inductor. At least one of the second filter fourth inductor via, the second filter fifth inductor via, and the second filter sixth inductor via is arranged in a boundary region (74) between the first filter (71B; 71C; 71D) and the second filter (72B; 72C; 72D).

[0252] In a multiplexer (7B; 7D) according to the 22nd aspect, in the 21st aspect, the fourth inductor via for the second filter (fourth inductor via VH4), the fifth inductor via for the second filter (fifth inductor via VH5), and the sixth inductor via for the second filter (sixth inductor via VH6) are all arranged in the boundary region (74).

[0253] A multiplexer (7C) according to a 23rd aspect is the same as in the 21st aspect, but the plurality of open-end vias are arranged in a staggered pattern. The plurality of open-end vias include a first inductor via for the second filter (first inductor via VH1), a second inductor via for the second filter (second inductor via VH2), and a third inductor via for the second filter (third inductor via VH3). The plurality of short-end vias are arranged in a staggered pattern. The plurality of short-end vias include a fourth inductor via for the second filter (fourth inductor via VH4), a fifth inductor via for the second filter (fifth inductor via VH5), and a sixth inductor via for the second filter (sixth inductor via VH6). In the boundary region (74), there are more short-end vias than open-end vias.

[0254] In a multiplexer (7B; 7C; 7D) according to a 24th aspect, in any one of the 21st to 23rd aspects, the first filter (71B; 71C; 71D) and the second filter (72B; 72C; 72D) are connected to a common ground terminal (GND).

[0255] A multiplexer (7B; 7C; 7D) according to a 25th aspect is any one of the 21st to 24th aspects, further comprising a common port (common terminal T40). The common port is provided in the laminate (2). The second filter (72B; 72C; 72D) has a seventh inductor for the second filter (seventh inductor LH7). The seventh inductor for the second filter is connected between the common port and a first capacitor for the second filter (first capacitor CH1). The inductance of the fourth inductor (L4) of the first filter (71B; 71C; 71D) is greater than the inductance of each of the first inductor (L1), the second inductor (L2), and the third inductor (L3). The inductance of the seventh inductor for the second filter (seventh inductor LH7) of the second filter (72B; 72C; 72D) is greater than the inductance of each of the first inductor for the second filter (first inductor LH1), the second inductor for the second filter (second inductor LH2), the third inductor for the second filter (third inductor LH3), the fourth inductor for the second filter (fourth inductor LH4), the fifth inductor for the second filter (fifth inductor LH5), and the sixth inductor for the second filter (sixth inductor LH6).

[0256] In a multiplexer (7B; 7C; 7D) according to a 26th aspect, in the 25th aspect, the second filter (72B; 72C; 72D) further includes a second filter series capacitor (seventh capacitor CH7), which is connected between the second filter seventh inductor (seventh inductor LH7) and the second filter first capacitor (first capacitor CH1).

[0257] In a multiplexer (7B; 7C; 7D) according to a 27th aspect, in the 25th or 26th aspect, at least one of the fourth inductor (L4) of the first filter (71B; 71C; 71D) and the seventh inductor for the second filter (72B; 72C; 72D) (seventh inductor LH7) is formed of a helical coil with one or more turns, and the inter-layer distance of the helical coil is 50 μm or more.

[0258] In a multiplexer (7B; 7C; 7D) according to the 28th aspect, in the 25th or 26th aspect, at least one of the fourth inductor (L4) of the first filter (71B; 71C; 71D) and the seventh inductor for the second filter (72B; 72C; 72D) (seventh inductor LH7) is formed by a coil having an inductor via and a pattern portion, or a spiral coil.

[0259] A multiplexer (7B; 7C; 7D) according to a 29th aspect is any one of the 25th to 28th aspects, wherein the second filter (72B; 72C; 72D) further includes a second filter series capacitor (seventh capacitor CH7). The second filter series capacitor is connected between a second filter seventh inductor (seventh inductor LH7) and a second filter first capacitor (first capacitor CH1). The ratio of the inductance of the second filter seventh inductor to the capacitance of the second filter series capacitor in the second filter (72B; 72C; 72D) is greater than the ratio of the inductance of the fourth inductor (L4) to the capacitance of the first capacitor (C1) in the first filter (71B; 71C; 71D).

[0260] A multiplexer (7D) according to a 30th aspect is any one of the 25th to 29th aspects, and further includes at least one of an inductor (LA1) and a capacitor (CA1). At least one of the inductor (LA1) and the capacitor (CA1) is connected to a path between a branch point (T43) and a common port (common terminal T40). The branch point (T43) is a branch point between the first filter (71D) and the second filter (72D). [Explanation of symbols]

[0261] 1,1A,1B,1C LC filter 2. Laminate 201 First main surface 202 Second main surface 3 terminals 7,7A,7B,7C,7D Multiplexer 71, 71A, 71B, 71C, 71D First filter 72, 72A, 72B, 72C, 72D Second filter 73A 3rd filter 74 Boundary area 75 Boundary 8 High-frequency module 81 filters 82 Amplifier 9. Communications equipment 91 Antenna 92 Signal Processing Circuit 93 RF signal processing circuit 94 Baseband signal processing circuit PC0 capacitor electrode PC1 First capacitor electrode PC2 Second capacitor electrode PC21 Part 1 PC22 2nd part PC3 Third capacitor electrode PCH0 capacitor electrode PCH1 1st capacitor electrode (1st capacitor electrode for 2nd filter) PCH2 2nd capacitor electrode (2nd capacitor electrode for 2nd filter) PCH3 3rd capacitor electrode (3rd capacitor electrode for 2nd filter) PCH4 4th capacitor electrode PCH5 5th capacitor electrode PCH6 6th capacitor electrode PCH7 7th capacitor electrode V0 inductor via V1 First inductor via V11 via conductor (first partial via) V12 via conductor (second partial via) 11 1st end 12 2nd end V2 Second inductor via V21, V22 via conductor 21 3rd end 22 4th end V3 3rd inductor via V31, V32 via conductor V33 via conductor (first partial via) V34 via conductor (second partial via) 31 5th end 32 6th end PL1 First inductor pattern P41, P42 pattern section P43 Connection part (first end of first inductor pattern part) V41 via conductor (first end of first inductor pattern) V42 via conductor (second end of first inductor pattern) V43 via conductor PL2 Second inductor pattern P51, P52 pattern section V51 via conductor (third end of second inductor pattern) V52 via conductor V53 via conductor (fourth end of second inductor pattern) VH0 inductor via VH1 1st inductor via (1st inductor via for 2nd filter) VH2 2nd inductor via (2nd inductor via for 2nd filter) VH3 3rd inductor via (3rd inductor via for 2nd filter) VH4 4th inductor via (4th inductor via for 2nd filter) VH5 5th inductor via (5th inductor via for 2nd filter) VH6 6th inductor via (6th inductor via for 2nd filter) PLH1 Inductor pattern PLH11, PLH12 pattern part VH71, VH72 via conductor PLH21, PLH31 inductor pattern C1 First capacitor C2 Second capacitor C3 Third capacitor C4 Fourth capacitor C5 Fifth capacitor CH1 1st capacitor (1st capacitor for 2nd filter) CH2 2nd capacitor (2nd capacitor for 2nd filter) CH3 3rd capacitor (3rd capacitor for 2nd filter) CH4 4th capacitor CH5 5th capacitor CH6 6th capacitor CH7 7th capacitor (series capacitor for 2nd filter) CA1 capacitor L1 First inductor L11, L12 inductors L2 Second inductor L3 Third inductor L31, L32 inductors L4 Fourth inductor L5 Fifth inductor LH1 1st inductor (1st inductor for 2nd filter) LH2 Second inductor (Second inductor for second filter) LH3 3rd inductor (3rd inductor for 2nd filter) LH4 4th inductor (4th inductor for 2nd filter) LH5 5th inductor (5th inductor for 2nd filter) LH6 6th inductor (6th inductor for 2nd filter) LH7 7th inductor (7th inductor for 2nd filter) LA1 inductor C10, C20, C30 capacitors L10, L20, L30 inductors P1 1st electrode P11 1st electrode P12 1st electrode (2nd electrode for 2nd filter) P2 Second electrode (Second electrode for second filter) T1 input terminal (first input / output port) T2 output terminal (second input / output port) T31, T34 input terminals T32, T33, T35, T36, T37 output terminals T40 Common terminal (common port) T41 1st terminal T42 2nd terminal T43 Junction GND Ground terminal D1 First direction (stacking direction) D2 2nd direction D3 Third direction S1, S2, S5, S6, S9 solid line S3, S4, S7, S8, S10 dashed lines

Claims

1. a first filter that is a low-pass filter; a second filter that passes signals in a frequency band higher than the pass band of the first filter; a laminate in which a plurality of dielectric layers are stacked, The first filter is a first electrode provided on a first dielectric layer of the plurality of dielectric layers; a second electrode that is a ground electrode and is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers; a first capacitor electrode forming a first capacitor between itself and the second electrode; a second capacitor electrode forming a second capacitor between the second electrode and the second capacitor electrode; a third capacitor electrode forming a third capacitor between the second electrode and the third capacitor electrode; a first inductor via having a first end connected to the first capacitor electrode and a second end connected to the first electrode, forming a first inductor; a second inductor via having a third end connected to the second capacitor electrode and a fourth end connected to the first electrode, forming a second inductor; a third inductor via having a fifth terminal connected to the third capacitor electrode and a sixth terminal connected to the first electrode, forming a third inductor; a first inductor pattern portion that forms a fourth inductor, The second filter is a first electrode for a second filter provided on the first dielectric layer of the plurality of dielectric layers; a second filter second electrode that is a ground electrode and is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers; a second filter first capacitor electrode that forms a second filter first capacitor between itself and the second filter second electrode; a second filter second capacitor electrode that forms a second filter second capacitor between itself and the second filter second electrode; a second filter third capacitor electrode that forms a second filter third capacitor between itself and the second filter second electrode; a second filter first inductor via connected between the second filter first capacitor electrode and the second filter first electrode, forming a second filter first inductor; a second filter second inductor via connected between the second filter second capacitor electrode and the second filter first electrode, forming a second filter second inductor; a second filter third inductor via connected between the second filter third capacitor electrode and the second filter first electrode, forming a second filter third inductor; a second filter fourth inductor via connected between the second filter first electrode and the second filter second electrode, forming a second filter fourth inductor connected in series with the second filter first inductor; a second filter fifth inductor via connected between the second filter first electrode and the second filter second electrode, forming a second filter fifth inductor connected in series with the second filter second inductor; a second filter sixth inductor via connected between the second filter first electrode and the second filter second electrode, forming a second filter sixth inductor connected in series with the second filter third inductor; At least one of the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter is disposed in a boundary region between the first filter and the second filter. Multiplexer.

2. the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter are all disposed in the boundary region; 2. The multiplexer of claim 1.

3. the plurality of open-ended vias including the second filter first inductor via, the second filter second inductor via, and the second filter third inductor via are arranged in a staggered pattern; a plurality of short-circuit end vias including the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter are arranged in a staggered pattern; In the boundary region, there are more short-circuited vias than open-circuited vias.

2. The multiplexer of claim 1.

4. the first filter and the second filter are connected to a common ground terminal. The multiplexer according to any one of claims 1 to 3.

5. a common port provided in the stack; the second filter includes a second filter seventh inductor connected between the common port and the second filter first capacitor; an inductance of the fourth inductor of the first filter being greater than an inductance of each of the first inductor, the second inductor, and the third inductor; an inductance of the second filter seventh inductor of the second filter is greater than an inductance of each of the second filter first inductor, the second filter second inductor, the second filter third inductor, the second filter fourth inductor, the second filter fifth inductor, and the second filter sixth inductor; 2. The multiplexer of claim 1.

6. the second filter further includes a second filter series capacitor connected between the second filter seventh inductor and the second filter first capacitor.

6. The multiplexer of claim 5.

7. at least one of the fourth inductor of the first filter and the second filter seventh inductor of the second filter is formed by a helical coil of one or more turns, The interlayer distance of the helical coil is 50 μm or more.

7. A multiplexer according to claim 5 or 6.

8. At least one of the fourth inductor of the first filter and the second filter seventh inductor of the second filter is formed by a coil having an inductor via and a pattern portion, or a spiral coil.

7. A multiplexer according to claim 5 or 6.

9. the second filter further includes a second filter series capacitor connected between the second filter seventh inductor and the second filter first capacitor, a ratio of the inductance of the seventh inductor for the second filter to the capacitance of the second filter series capacitor in the second filter is greater than a ratio of the inductance of the fourth inductor to the capacitance of the first capacitor in the first filter; 7. A multiplexer according to claim 5 or 6.

10. further comprising at least one of an inductor and a capacitor connected to a path between a branch point of the first filter and the second filter and the common port; 7. A multiplexer according to claim 5 or 6.

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