Package Structure

Abstract

To provide a package structure that can effectively reduce the probability of the product failure while achieving the thinness of product performance.SOLUTION: A package structure 100 includes a first layer 110, a second layer 120 and a third layer 130. The second layer includes an outer frame 121, a resonator 122 and a chip 123. The second layer is arranged between the first layer and third layer. The outer frame, first layer and third layer constitute a rectangular storage part 10. The resonator and chip are located in the rectangular accommodation part. The chip is located on one side of the resonator and electrically connected to the third layer and resonator through a plurality of conductive components 123C on the chip. The chip further may be located below the resonator.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a package structure. [Background technology]

[0002] With the trend toward high stability, miniaturization, and thinning of quartz crystal frequency devices, as well as the development of wafer-level package (WLP) technology, component placement is becoming increasingly important. For example, when placing a chip on the outer surface of a WLP structure, underfill is often used to cover conductive components (such as gold balls). However, the above-mentioned method cannot effectively protect the conductive components (e.g., defects caused by insufficient coverage) and may result in product defects during subsequent processes. Summary of the Invention [Problem to be solved by the invention]

[0003] The conductive parts cannot be effectively protected (eg, defects caused by inability to reliably cover them) and this can lead to product defects during subsequent processes. [Means for solving the problem]

[0004] The present invention provides a package structure that can effectively reduce the probability of product defects and simultaneously achieve thinner product performance.

[0005] The package structure of the present invention includes a first layer, a second layer, and a third layer. The second layer includes an outer frame, a resonator, and a chip. The second layer is disposed between the first and third layers. The outer frame, the first layer, and the third layer form a rectangular housing. The resonator and the chip are located within the rectangular housing. The chip is located on one side of the resonator, and the chip is electrically connected to the third layer and the resonator via a plurality of conductive components thereon.

[0006] The package structure of the present invention includes a first layer, a second layer, and a third layer. The second layer includes an outer frame, a resonator, and a chip. The second layer is disposed between the first and third layers. The outer frame, the first layer, and the third layer form a rectangular housing. The resonator and the chip are located within the rectangular housing. The chip is located below the resonator, and the chip is electrically connected to the third layer and the resonator via multiple conductive components thereon. [Effects of the Invention]

[0007] As described above, by using a laminated structure and a rectangular housing design, the present invention can reliably seal the resonator and the chip, ensuring that the conductive components on the chip are fully protected, thereby effectively reducing the probability of product defects and simultaneously achieving a thinner product.

[0008] In order to make the above features and advantages of the present invention easier to understand, the following detailed description of embodiments accompanied with drawings is provided. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic external view of a package structure according to one embodiment of the present invention; [Figure 2] FIG. 2 is a schematic exploded view of FIG. 1. [Figure 3] FIG. 2 is a schematic side view of the interior of FIG. 1. [Figure 4A] FIG. 3 is a schematic top view of the bottom of the third layer of FIG. 2. [Figure 4B] FIG. 3 is a schematic top view of the upper portion of the third layer of FIG. 2. [Figure 4C] FIG. 3 is a schematic top view of the bottom of the second layer of FIG. 2. [Figure 4D] FIG. 3 is a schematic top view of the upper portion of the second layer of FIG. 2. [Figure 4E] FIG. 3 is a schematic top view of the bottom of the first layer of FIG. 2. [Figure 4F] FIG. 3 is a schematic top view of the upper portion of the first layer of FIG. 2. [Figure 5]FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line AA' after stacking FIGS. 4A to 4F. [Figure 6] FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line BB' after stacking FIGS. 4A to 4F. [Figure 7] FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line CC' after stacking FIGS. 4A to 4F. [Figure 8] FIG. 10 is a schematic external view of a package structure according to another embodiment of the present invention. [Figure 9] FIG. 9 is a schematic exploded view of FIG. 8. [Figure 10] FIG. 9 is a schematic side view of the interior of FIG. 8. [Figure 11] FIG. 9 is a schematic top view of the upper portion of the third layer of FIG. 8. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following detailed description, for purposes of explanation and not limitation, exemplary embodiments disclosing specific details are set forth in order to provide a thorough understanding of various principles of the present invention. However, it will be apparent to one skilled in the art having the benefit of this invention that the present invention may be practiced in other embodiments that deviate from the specific details disclosed herein. Moreover, descriptions of well-known devices, methods, and materials may be omitted so as not to obscure the description of various principles of the present invention.

[0011]

[0023] Exemplary embodiments of the present invention will be fully described below with reference to the drawings. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described herein. For clarity, in the drawings, the sizes and thicknesses of regions, components, and layers are not drawn to scale. For ease of understanding, the same elements will be referred to by the same symbols in the following description.

[0012] Directional terms used herein (e.g., up, down, right, left, front, back, upper, and lower) are used solely with reference to the drawings and do not imply absolute orientation.

[0013] It should be understood that terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, but these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0015] FIG. 1 is a schematic external view of a package structure according to one embodiment of the present invention. FIG. 2 is a schematic exploded view of FIG. 1. FIG. 3 is a schematic side view of the interior of FIG. 1. FIGS. 4A, 4B, 4C, 4D, 4E, and 4F are schematic top views from the bottom of the third layer to the top of the first layer in FIG. 2, respectively. FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line A-A' after stacking FIGS. 4A to 4F. FIG. 6 is a schematic cross-sectional view taken along the cross-sectional line B-B' after stacking FIGS. 4A to 4F. FIG. 7 is a schematic cross-sectional view taken along the cross-sectional line C-C' after stacking FIGS. 4A to 4F. Here, FIG. 3 shows a side portion seen from direction D after assembly in FIG. 2.

[0016] 1 to 3, in this embodiment, the package structure 100 includes a first layer 110, a second layer 120, and a third layer 130, and the second layer 120 is disposed between the first layer 110 and the third layer 130, and the second layer 120 includes an outer frame 121, a resonator 122, and a chip 123. It should be noted that FIG. 2 merely shows the bonding position of the chip 123 in an exploded view, but does not show that the chip 123 is included in the third layer 130. As shown in FIG. 3, after assembly, the chip 123 is included in the second layer 120.

[0017] In some embodiments, chip 123 is an integrated circuit (IC), types of which include, but are not limited to, application specific integrated circuits (ASICs) and integrated circuits (ICs) fabricated using semiconductor technology.

[0018] Furthermore, the outer frame 121, the first layer 110, and the third layer 130 form a rectangular housing 10. The resonator 122 and the chip 123 are located within the rectangular housing 10, with the chip 123 located on one side of the resonator 122. The chip 123 is electrically connected to the third layer 130 and the resonator 122 via a plurality of conductive components 123C on the chip 123. Therefore, by using the laminated structure and the design of the rectangular housing 10, the present invention can reliably seal the resonator 122 and the chip 123 and ensure that the conductive components 123C on the chip 123 are fully protected, thereby effectively reducing the probability of product defects and achieving a slimmer product. The conductive components 123C may be gold balls, etc., and the conductive components 123C in the structure of this embodiment do not come into contact with air, so there is no underfill. Furthermore, as shown in FIG. 3, the rectangular housing 10 described above has a square structure, rather than an L-shape or convex shape.

[0019] Furthermore, when facing subsequent processes such as a molding process, the rectangular accommodating portion 10 comprehensively protects the conductive component 123C, thereby reducing the probability of product defects caused by deformation or interface damage to the conductive component 123C due to stress generated during the process, and since the chip does not protrude above the outer surface of the package structure, the thickness of the package structure 100 can be reduced to meet the requirement for thinness, but the present invention is not limited thereto.

[0020] In this embodiment, as shown in FIG. 2, the first layer 110 and the third layer 130 are both rectangular solid structures (not U-shaped, inverted U-shaped, or similar). That is, the first layer 110 and the third layer 130 do not have grooves, which reduces the difficulty of joining the laminated structures. At the same time, the etching step for forming the grooves can be omitted, which simplifies the process, but the present invention is not limited to this.

[0021] In some embodiments, the materials of the first layer 110, the outer frame 121, the resonator 122, and the third layer 130 are made of quartz crystal, so that the package structure 100 may be a wafer-level packaged crystal oscillator. For example, the first layer 110 and the third layer 130 may all be circuit boards, while the resonator 122 and the outer frame 121 may be an integrated structure. That is, as shown in FIGS. 4C and 4D , the outer frame 121 is directly and physically connected to the resonator 122. There is no bonding interface between the outer frame 121 and the resonator 122. This eliminates the need for adhesives such as bonding adhesives, thereby saving manufacturing costs and processes, but the present invention is not limited thereto. Here, in Figures 4C and 4D, the resonator 122 is physically connected to only one side of the outer frame 121, but in embodiments not shown, the resonator may be physically connected to at least two or more (e.g., three or four) sides of the outer frame depending on actual design requirements.

[0022] In some embodiments, the package structure 100 can be formed by the following steps: First, circuits and components required for each layer are formed on three quartz wafers through an appropriate process (e.g., a photolithography process), and multiple chips 123 are arranged on the wafer to serve as the third layer 130. Next, the three quartz wafers are bonded together using a bonding material (e.g., an appropriate adhesive material, such as the bonding parts 20 in FIG. 5), and then a singulation or dicing process is performed to separate the multiple package structures 100. Here, gaps between adjacent wafers are created by the bonding parts 20.

[0023] In some embodiments, the mutually facing top surface 121t and bottom surface 121b of the outer frame 121 directly contact the first layer 110 and the third layer 130, respectively. Since the thickness of the resonator 122 and the thickness of the chip 123 do not exceed the thickness of the outer frame 121, the resonator 122 and the chip 123 do not directly contact the first layer 110, but the present invention is not limited thereto.

[0024] In some embodiments, the packaging structure 100 is composed of only the first layer 110, the second layer 120, and the third layer 130, although the present invention is not limited thereto.

[0025] In order to make the circuit layout in the above-mentioned package structure 100 clearer and easier to understand, it will be described in detail below using Figures 4A to 4F and Figures 5 to 7, but this is not intended to limit the circuit layout of the present invention, and any circuit layout in which the chip 123 is electrically connected to the third layer 130 and the resonator 122 via the conductive component 123C thereon is within the scope of the present invention.

[0026] Here, Figure 4A corresponds to the circuit layout of the bottom 130b of the third layer 130, Figure 4B corresponds to the circuit layout of the top 130t of the third layer 130, Figure 4C corresponds to the circuit layout of the bottom 120b of the second layer 120, Figure 4D corresponds to the circuit layout of the top 120t of the second layer 120, Figure 4E corresponds to the circuit layout of the bottom 110b of the first layer 110, Figure 4F corresponds to the circuit layout of the top 110t of the first layer 110, and Figures 5 to 7 are drawings obtained by stacking these drawings vertically and taking cross sections.

[0027] 4A, 4B, and 7, the first layer 110, the second layer 120, and the third layer 130 are electrically connected to each other through a plurality of vias, and conductive components (not shown) of a chip 123 disposed on the surface of the upper portion 130t of the third layer 130 via a flip chip can be bonded to bonding pads C1, C2, C3, C4, C5, and C6, which are located on the surface of the upper portion 130t of the third layer 130. Here, bonding pads C1, C2, C3, and C4 are in physical contact with and electrically connected to vias V1, V2, V3, and V4 penetrating the third layer 130, respectively. Vias V1, V2, V3, and V4 then make downward physical contact and electrical connection to the circuitry on the bottom 130b of the third layer 130.

[0028] 4B to 4D and 5 to 7, bonding pads C5 and C6 are electrically connected to vias V5 and V6, respectively, which penetrate the second layer 120 through a circuit in the upper part 130t of the third layer 130. The vias V5 and V6 are in physical contact with and electrically connected to a circuit in the upper part 120t of the second layer 120. Here, the vias V5 and V6 are electrically connected to the second electrode E2 of the resonator 122 located in the bottom part 120b of the second layer 120 and the first electrode E1 of the resonator 122 located in the upper part 120t of the second layer 120 through another circuit.

[0029] 4E-4F and 5-7, the circuitry on the upper portion 120t of the second layer 120 is electrically connected to vias V7 and V8 that penetrate the first layer 110. Vias V7 and V8 are in physical contact with and electrically connected to the circuitry on the upper portion 110t of the first layer 110, completing a series connection path of the internal circuitry of the package structure 100. Here, bonding pads C1, C2, C3, C4, C5, C6, and vias V1, V2, V3, V4, V5, V6, V7, and V8 can be formed of an appropriate conductive material (e.g., copper).

[0030] It should be mentioned that the circuit areas not shown are merely illustrated for illustrative purposes, and these circuits can be added, deleted, or adjusted according to actual design requirements, and therefore these circuits are not used to limit the present invention.

[0031] In this embodiment, the resonator 122 and the chip 123 are located on the same horizontal plane. That is, the orthogonal projection of the resonator 122 on the third layer 130 does not overlap with the orthogonal projection of the chip 123 on the third layer 130. This allows the thickness of the second layer 120 to be reduced, which has the advantage of further reducing the thickness, although the present invention is not limited thereto. In other embodiments, a different configuration relationship may exist between the resonator 122 and the chip 123. Other configuration relationships will be further described below.

[0032] It should be noted that the reference numerals and some contents of the above-described embodiments are used in the following embodiments, and the same or similar reference numerals are used to indicate the same or similar components, and the same technical contents will not be described in detail in the following embodiments, as the omitted details can be referred to in the above-described embodiments.

[0033] Figure 8 is a schematic external view of a package structure according to another embodiment of the present invention. Figure 9 is a schematic exploded view of Figure 8. Figure 10 is a schematic side view of the interior of Figure 8. Figure 11 is a schematic top view of the upper part of the third layer of Figure 8.

[0034] 8 to 11 , compared with the package structure 100 of the above-described embodiment, in this embodiment, the chip 223 of the second layer 220 of the package structure 200 is located below the resonator 122. That is, the orthogonal projection of the resonator 122 on the third layer 130 partially overlaps with the orthogonal projection of the chip 223 on the third layer 130. Therefore, the thickness of the second layer 220 of the package structure 200 is greater than the thickness of the second layer 120 of the package structure 100. Furthermore, compared with the package structure 100, the package structure 200 of this embodiment can use a relatively large chip 223, as shown in FIG. 11 , providing additional design flexibility, although the present invention is not limited thereto. It should be noted that FIG. 9 merely illustrates the bonding position of the chip 223 in an exploded view and does not illustrate that the chip 223 is included in the third layer 130. As shown in FIG. 10 , after assembly, the chip 223 is included in the second layer 220.

[0035] In this embodiment, the corresponding connection relationships between bonding pads C1, C2, C3, C4, C5, and C6 and vias V1, V2, V3, V4, V5, and V6 are similar to those in Figure 4B, and other parts not shown can also be designed with circuit configurations similar to those in Figure 4A and Figures 4C to 4F, so their explanations are omitted here.

[0036] It should be noted that the above two embodiments are merely exemplary. The present invention does not limit the structural relationship between the resonator and the chip. It is only necessary that the chip is arranged in a stacked structure to achieve a complete protection effect within the scope of the present invention.

[0037] As described above, by using a laminated structure and a rectangular housing design, the present invention can reliably seal the resonator and the chip, ensuring that the conductive components on the chip are fully protected, thereby effectively reducing the probability of product defects and simultaneously achieving a thinner product.

[0038] Although the present invention has been described in detail with reference to the above embodiments, they are not intended to limit the present invention. Those skilled in the art will understand that changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the following claims. [Industrial Applicability]

[0039] The package structure can be applied to the field of crystal frequency devices. [Explanation of symbols]

[0040] 10 Rectangular storage section 20 Joint parts 100, 200 package structure 110 1st layer 110b, 120b, 130b bottom 110t, 120t, 130t upper 120, 220 2nd layer 121 Outer Frame 121t top surface 121b Bottom 122 Resonator 123, 223 chips 123C Conductive parts 130 3rd layer E1 1st electrode E2 2nd electrode C1, C2, C3, C4, C5, C6 bonding pads D direction V1, V2, V3, V4, V5, V6, V7, V8 Via

Claims

1. The first layer, a second layer including an outer frame, a resonator, and a chip, the resonator and the outer frame being an integral structure; a third layer having the second layer disposed between the first layer and the third layer; wherein the outer frame, the first layer, and the third layer form a rectangular housing, the resonator and the chip are located within the rectangular housing, the chip is located on one side of the resonator, and the chip is electrically connected to the third layer and the resonator via a plurality of conductive components on the chip.

2. 2. The package structure of claim 1, wherein the first layer, the outer frame, the resonator, and the third layer are made of quartz crystal.

3. The package structure of claim 1 , wherein the first layer, the second layer, and the third layer are electrically connected to each other through a plurality of vias.

4. The package structure of claim 1 , wherein the resonator and the chip are located on the same horizontal plane.

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