Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of reducing an on-resistance.SOLUTION: A semiconductor device according to an embodiment includes: a silicon carbide layer having a first face parallel to a first direction and a second direction perpendicular to the first direction, and a second face; a first trench, a second trench, and a third trench extending in the first direction; an n-type first region disposed in the silicon carbide layer; a p-type second region disposed between the n-type first region and the first face, and disposed between the first trench and the second trench; a p-type sixth region disposed on a bottom surface of the first trench; a p-type seventh region disposed on a bottom surface of the second trench; a p-type eighth region disposed on a bottom surface of the third trench; a p-type ninth region in contact with the sixth region and the second region; and a p-type tenth region in contact with the seventh region and the second region. At a cross section perpendicular to the first direction and including the ninth region and the tenth region, the first region is in contact with a side surface of the first trench on the third trench side and a side surface of the third trench on the first trench side.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these physical properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) using silicon carbide are required to have low on-resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-195081 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0006] The semiconductor device of the embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side surface, a second side surface, and a first bottom surface between the first side surface and the second side surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench extending in a first direction and having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a second gate insulating layer present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the second trench and the second trench; a fifth side surface; a sixth side surface facing the first side surface; and a third bottom surface between the fifth side surface and the sixth side surface. a third trench having a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; and a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench. a p-type third silicon carbide region located in the silicon carbide layer between the second silicon carbide region and the first surface; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface;an eighth p-type silicon carbide region located between the first silicon carbide region and the third bottom surface; a plurality of ninth p-type silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, and in contact with the second side surface, and repeatedly arranged in the first direction; and a plurality of tenth p-type silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, and in contact with the third side surface, and repeatedly arranged in the first direction. a plurality of p-type eleventh silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the third silicon carbide region, and in contact with the first side surface, and repeatedly arranged in the first direction; and a plurality of p-type twelfth silicon carbide regions located in the silicon carbide layer, in contact with the eighth silicon carbide region, in contact with the third silicon carbide region, and in contact with the sixth side surface, and repeatedly arranged in the first direction; In a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and includes one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface. In a second cross section that is parallel to the first cross section, is positioned in the first direction relative to the first cross section, and includes one of the eleventh silicon carbide regions and one of the twelfth silicon carbide regions, the first silicon carbide region is in contact with the second side surface and the third side surface. . [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 5] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 6] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 7] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 8] 10A and 10B are diagrams illustrating problems in a semiconductor device of a comparative example. [Figure 9] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 10] FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. [Figure 11] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second modified example of the first embodiment. [Figure 12] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 13]FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 15] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 10 is a schematic diagram of a drive device according to a sixth embodiment. [Figure 17] FIG. 13 is a schematic diagram of a vehicle according to a seventh embodiment. [Figure 18] FIG. 13 is a schematic diagram of a vehicle according to an eighth embodiment. [Figure 19] FIG. 13 is a schematic diagram of an elevator according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - and p + , p, p - When the notation is used, these notations represent the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] The trench width, trench spacing, trench depth, insulating layer thickness, etc. can be measured on an image obtained by, for example, SIMS or a Transmission Electron Microscope (TEM).

[0012] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, and having a first side surface, a second side surface, and a first bottom surface between the first side surface and the second side surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench having a third side surface facing the first side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench existing in the silicon carbide layer, extending in a first direction on the first surface, a first trench being located between the second trench and the third trench, the third trench having a fifth side surface, a sixth side surface facing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; and an n-type fourth silicon carbide region located in the silicon carbide layer, between the second silicon carbide region and the first surface. a fifth n-type silicon carbide region located in the silicon carbide layer and located between the third silicon carbide region and the first surface; a sixth p-type silicon carbide region located in the silicon carbide layer and located between the first silicon carbide region and the first bottom surface; a seventh p-type silicon carbide region located in the silicon carbide layer and located between the first silicon carbide region and the second bottom surface; an eighth p-type silicon carbide region located in the silicon carbide layer and located between the first silicon carbide region and the third bottom surface; and an eighth p-type silicon carbide region located in the silicon carbide layer in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, and in contact with the second side surface;The silicon carbide layer includes a plurality of p-type ninth silicon carbide regions repeatedly arranged in a first direction, and a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, contacting the seventh silicon carbide region, contacting the second silicon carbide region, and contacting the third side surface, and repeatedly arranged in the first direction. In a first cross section perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region contacts the first side surface and the sixth side surface.

[0013] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a trench-gate vertical MOSFET 100 made of silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0014] Fig. 2 is a schematic plan view of the semiconductor device of the first embodiment. Fig. 2 is a plan view of the first plane (F1 in Fig. 1) of Fig. 1. The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction.

[0015] Fig. 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Fig. 3 is a cross-section taken along Fx in Fig. 1. Fig. 3 is a cross-section parallel to the first direction and the second direction. Fig. 3 is a cross-section parallel to the first plane F1. Fig. 1 is an AA' cross-section in Fig. 3. The AA' cross-section is an example of a first cross-section.

[0016] Fig. 4 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line BB' in Fig. 3. The BB' cross-section is an example of the second cross-section.

[0017] 5 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line CC' in FIG.

[0018] The MOSFET 100 includes a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a third trench 31, a third gate electrode 32, a third gate insulating layer 33, a source electrode 41, a drain electrode 42, and an interlayer insulating layer 43.

[0019] Hereinafter, the first trench 11, the second trench 21, and the third trench 31 may be collectively referred to as trenches. Also, the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 may be collectively referred to as gate electrodes. Also, the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33 may be collectively referred to as gate insulating layers.

[0020] In the silicon carbide layer 10, n + n-type drain region 50 - a p-type drift region 51 (first silicon carbide region), a p-type first body region 52a (second silicon carbide region), a p-type second body region 52b (third silicon carbide region), a p-type third body region 52c, a p-type fourth body region 52d, an n-type + a first source region 53a (fourth silicon carbide region) of n type; + a second source region 53b (fifth silicon carbide region) of n type; + The third source region 53c, n + A fourth source region 53d of type p + The first electric field relaxation region 54a (sixth silicon carbide region) of p + the second electric field relaxation region 54b (seventh silicon carbide region) of p + a third electric field relaxation region 54c (eighth silicon carbide region) of p + a first connection region 55a (ninth silicon carbide region) of type p + a second connection region 55b (tenth silicon carbide region) of type p + a third connection region 55c (eleventh silicon carbide region) of type p + a fourth connection region 55d (twelfth silicon carbide region) of type p + The fifth connection region 55e, p+ The sixth connection region 55f of the type and + A mold contact area 56 is provided.

[0021] Hereinafter, the first body region 52a, the second body region 52b, the p-type third body region 52c, and the fourth body region 52d may be collectively referred to as body regions 52. The first source region 53a, the second source region 53b, the third source region 53c, and the fourth source region 53d may be collectively referred to as source regions 53. The first electric field relief region 54a, the second electric field relief region 54b, and the third electric field relief region 54c may be collectively referred to as electric field relief regions 54. The first connection region 55a, the second connection region 55b, the third connection region 55c, the fourth connection region 55d, the fifth connection region 55e, and the sixth connection region 55f may be collectively referred to as connection regions 55.

[0022] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0023] Silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). First surface F1 and second surface F2 face each other. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth in the direction toward second surface F2, with first surface F1 as the reference.

[0024] 1 to 5, the first direction and the second direction are parallel to the first plane F1 and the second plane F2, and the third direction is perpendicular to the first plane F1 and the second plane F2.

[0025] The first plane F1 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (0001) plane. That is, the normal is a plane inclined at an angle of 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off-angle with respect to the (0001) plane is 0 to 8 degrees. The second plane F2 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane.

[0026] The (0001) plane is called the silicon plane. The (000-1) plane is called the carbon plane. The tilt direction of the first plane F1 and the second plane F2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 1, for example, the second direction shown in the figure is the a-axis direction.

[0027] The first trench 11, the second trench 21, and the third trench 31 are present in the silicon carbide layer 10. The first trench 11, the second trench 21, and the third trench 31 extend in a first direction as shown in FIG.

[0028] The widths in the second direction of the first trench 11, the second trench 21, and the third trench 31 (w in FIG. 2) are, for example, smaller than the distance between the first trench 11 and the second trench 21 (d in FIG. 2) and the distance between the first trench 11 and the third trench 31 (d in FIG. 2).

[0029] The width in the second direction of the first trench 11, the second trench 21, and the third trench 31 (w in FIG. 2) is, for example, 0.3 μm or more and 1 μm or less. The distance between the first trench 11 and the second trench 21 (d in FIG. 2) and the distance between the first trench 11 and the third trench 31 (d in FIG. 2) are, for example, 0.5 μm or more and 2 μm or less. The depth of the first trench 11, the second trench 21, and the third trench 31 are, for example, 1 μm or more and 2 μm or less.

[0030] A plurality of trenches including the first trench 11, the second trench 21, and the third trench 31 are repeatedly arranged in the second direction. The repeat pitch of the trenches in the second direction is, for example, not less than 1 μm and not more than 5 μm.

[0031] The first trench 11 is located between the second trench 21 and the third trench 31 .

[0032] The first trench 11 has a first side surface 11a, a second side surface 11b, and a first bottom surface 11c. The first bottom surface 11c is provided between the first side surface 11a and the second side surface 11b.

[0033] The first gate electrode 12 is provided in the first trench 11. The first gate electrode 12 is provided between the source electrode 41 and the drain electrode 42. The first gate electrode 12 extends in a first direction.

[0034] The first gate insulating layer 13 is provided between the first gate electrode 12 and the silicon carbide layer 10. The first gate insulating layer 13 is provided between the first gate electrode 12 and each of the first source region 53 a, the second source region 53 b, the first body region 52 a, the second body region 52 b, the first electric field relief region 54 a, the first connection region 55 a, and the third connection region 55 c.

[0035] The second trench 21 has a third side surface 21a, a fourth side surface 21b, and a second bottom surface 21c. The second bottom surface 21c is provided between the third side surface 21a and the fourth side surface 21b. The third side surface 21a faces the second side surface 11b.

[0036] The second gate electrode 22 is provided in the second trench 21. The second gate electrode 22 is provided between the source electrode 41 and the drain electrode 42. The second gate electrode 22 extends in the first direction.

[0037] The second gate insulating layer 23 is provided between the second gate electrode 22 and the silicon carbide layer 10. The second gate insulating layer 23 is provided between the second gate electrode 22 and each of the first source region 53 a, the third source region 53 c, ​​the first body region 52 a, the third body region 52 c, the second electric field relief region 54 b, the second connection region 55 b, and the fifth connection region 55 e.

[0038] The third trench 31 has a fifth side surface 31a, a sixth side surface 31b, and a third bottom surface 31c. The third bottom surface 31c is provided between the fifth side surface 31a and the sixth side surface 31b. The sixth side surface 31b faces the first side surface 11a.

[0039] The third gate electrode 32 is provided in the third trench 31. The third gate electrode 32 is provided between the source electrode 41 and the drain electrode 42. The third gate electrode 32 extends in the first direction.

[0040] The third gate insulating layer 33 is provided between the third gate electrode 32 and the silicon carbide layer 10. The third gate insulating layer 33 is provided between the third gate electrode 32 and each of the second source region 53b, the fourth source region 53d, the second body region 52b, the fourth body region 52d, the third electric field reduction region 54c, the fourth connection region 55d, and the sixth connection region 55f.

[0041] The first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 are conductive layers, and are, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0042] The first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33 are, for example, silicon oxide films. For example, a high-k insulating film (a high-dielectric-constant insulating film such as HfSiON, ZrSiON, or AlON) can be used for the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33. Furthermore, for example, a stacked film of a silicon oxide film (SiO2) and a high-k insulating film can also be used for the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33.

[0043] The interlayer insulating layer 43 is provided on the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32. The interlayer insulating layer 43 is, for example, a silicon oxide film.

[0044] The source electrode 41 is provided on the surface side of the silicon carbide layer 10. The source electrode 41 is provided on the surface of the silicon carbide layer 10. The source electrode 41 is electrically connected to the body region 52, the source region 53, and the contact region 56. The source electrode 41 is in contact with the source region 53 and the contact region 56.

[0045] The source electrode 41 includes a metal. The metal forming the source electrode 41 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 41 may include a metal silicide or a metal carbide in contact with the silicon carbide layer 10.

[0046] The drain electrode 42 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 42 is provided on the back surface of the silicon carbide layer 10. The drain electrode 42 is in contact with the drain region 50.

[0047] The drain electrode 42 is, for example, a metal or a metal-semiconductor compound, and includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0048] n + The n-type drain region 50 is provided on the back surface side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 50 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0049] n - A type drift region 51 is provided on the drain region 50. The drift region 51 is provided between the drain region 50 and the surface of the silicon carbide layer 10.

[0050] The drift region 51 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 51 is, for example, 4×10 14 cm-3 More than 1×10 18 cm -3 The thickness of the drift region 51 in the third direction is, for example, not less than 4 μm and not more than 150 μm.

[0051] The p-type first body region 52a is provided between the drift region 51 and the surface of the silicon carbide layer 10. The first body region 52a is provided between the first trench 11 and the second trench 21. The first body region 52a is in contact with the second side surface 11b and the third side surface 21a.

[0052] The p-type second body region 52b is provided between the drift region 51 and the surface of the silicon carbide layer 10. The second body region 52b is provided between the first trench 11 and the third trench 31. The second body region 52b is in contact with the first side surface 11a and the sixth side surface 31b.

[0053] The body region 52 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in the region of the body region 52 that is in contact with the gate insulating layer.

[0054] The body region 52 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 52 is, for example, 5×10 16 cm -3 5x10 or more 17 cm -3 The depth of the body region 52 is, for example, not less than 0.2 μm and not more than 1.0 μm.

[0055] n + The first source region 53a is provided between the first body region 52a and the surface of the silicon carbide layer 10. The first source region 53a is in contact with the source electrode 41. The first source region 53a is in contact with the first gate insulating layer 13 and the second gate insulating layer 23. The first source region 53a is in contact with the second side surface 11b and the third side surface 21a.

[0056] n +The second source region 53b is provided between the second body region 52b and the surface of the silicon carbide layer 10. The second source region 53b is in contact with the source electrode 41. The second source region 53b is in contact with the first gate insulating layer 13 and the third gate insulating layer 33. The second source region 53b is in contact with the first side surface 11a and the sixth side surface 31b.

[0057] The n-type impurity concentration of the source region 53 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The depth of the source region 53 is shallower than the depth of the body region 52, and is, for example, not less than 0.1 μm and not more than 0.3 μm. The distance between the drift region 51 and the source region 53 is, for example, not less than 0.1 μm and not more than 0.9 μm.

[0058] p + The contact region 56 is provided between the body region 52 and the surface of the silicon carbide layer 10. The contact region 56 is in contact with the source electrode 41. The contact regions 56 are repeatedly arranged in the first direction.

[0059] The contact region 56 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 56 is higher than the p-type impurity concentration of the body region 52.

[0060] The p-type impurity concentration of the contact region 56 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The contact area of ​​the contact region 56 with the source electrode 41 preferably has a high concentration, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0061] p +The first electric field relaxation region 54a is provided between the drift region 51 and the first trench 11. The first electric field relaxation region 54a is provided between the drift region 51 and the first bottom surface 11c. The first electric field relaxation region 54a is in contact with the first bottom surface 11c.

[0062] p + The second electric field relaxation region 54b is provided between the drift region 51 and the second trench 21. The second electric field relaxation region 54b is provided between the drift region 51 and the second bottom surface 21c. The second electric field relaxation region 54b contacts the second bottom surface 21c.

[0063] p + The third electric field relaxation region 54c is provided between the drift region 51 and the third trench 31. The third electric field relaxation region 54c is provided between the drift region 51 and the third bottom surface 31c. The third electric field relaxation region 54c is in contact with the third bottom surface 31c.

[0064] The electric field buffer region 54 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field buffer region 54 is higher than the p-type impurity concentration of the body region 52. The p-type impurity concentration of the electric field buffer region 54 is, for example, 1×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0065] The electric field relaxation region 54 can be formed, for example, by forming a trench in the silicon carbide layer 10 and then ion-implanting aluminum (Al) into the silicon carbide layer 10 from the bottom surface of the trench.

[0066] The potential of the electric field relaxation region 54 is fixed to the potential of the source electrode 41. The potential of the electric field relaxation region 54 is fixed to the source potential. The electric field relaxation region 54 has the function of relaxing the electric field applied to the gate insulating layer at the bottom of the trench.

[0067] p +The first connection region 55a of the first trench 11 contacts the first electric field relief region 54a, the first body region 52a, and the second side surface 11b of the first trench 11.

[0068] The plurality of first connection regions 55a are repeatedly arranged in a first direction. The first connection regions 55a are repeatedly arranged in the first direction at a first pitch (P1 in FIG. 3).

[0069] The length of the first connection region 55a in the first direction (L1 in FIG. 3) is, for example, not less than 0.5 μm and not more than 3 μm.

[0070] p + The second connection region 55b of the second trench 21 is in contact with the second electric field relief region 54b, the first body region 52a, and the third side surface 21a of the second trench 21.

[0071] The second connection regions 55b are repeatedly arranged in the first direction. The second connection regions 55b are arranged in the first direction at a first repeat pitch (P1 in FIG. 3).

[0072] The second connection region 55b faces the first connection region 55a in the second direction.

[0073] In a first cross section (FIG. 1) that is perpendicular to the first face F1, perpendicular to the first direction, and that includes one of the first connection regions 55a and one of the second connection regions 55b, the drift region 51 contacts the first side surface 11a of the first trench 11 and the sixth side surface 31b of the third trench 31. In the first cross section (FIG. 1), there is a p + No mold connection area is provided.

[0074] The length of the second connection region 55b in the first direction (L1 in FIG. 3) is, for example, not less than 0.5 μm and not more than 3 μm.

[0075] p+ The third connection region 55c is in contact with the first electric field relief region 54a, the second body region 52b, and the first side surface 11a of the first trench 11.

[0076] The third connection regions 55c are repeatedly arranged in the first direction. The third connection regions 55c are repeatedly arranged in the first direction at a second repeat pitch (P2 in FIG. 3).

[0077] The length of the third connection region 55c in the first direction (L2 in FIG. 3) is, for example, not less than 0.5 μm and not more than 3 μm.

[0078] p + The fourth connection region 55d of the third trench 31 is in contact with the third electric field reduction region 54c, the second body region 52b, and the sixth side surface 31b of the third trench 31.

[0079] The plurality of fourth connection regions 55d are repeatedly arranged in the first direction The fourth connection regions 55d are arranged in the first direction at a second repeat pitch (P2 in FIG. 3).

[0080] The fourth connection region 55d faces the third connection region 55c in the second direction.

[0081] In a second cross section (FIG. 4) that is parallel to the first cross section (FIG. 1), is located in a first direction of the first cross section (FIG. 1), and includes one of the third electric field relaxation regions 54c and one of the fourth connection regions 55d, the drift region 51 contacts the second side surface 11b of the first trench 11 and the third side surface 21a of the second trench 21. In the second cross section (FIG. 4), there is a p + No mold connection area is provided.

[0082] The length of the fourth connection region 55d in the first direction (L2 in FIG. 3) is, for example, not less than 0.5 μm and not more than 3 μm.

[0083] The first connection regions 55a and the third connection regions 55c are alternately arranged in the first direction. The first repeat pitch P1 is, for example, equal to the second repeat pitch P2.

[0084] The first connection regions 55a and the third connection regions 55c are alternately arranged at the same repeat pitch in the first direction, for example. The repeat pitch in the first direction of the first connection regions 55a and the third connection regions 55c is, for example, half the first repeat pitch P1. The repeat pitch in the first direction of the first connection regions 55a and the third connection regions 55c is, for example, half the second repeat pitch P2.

[0085] Half the first repeat pitch P1 is, for example, 5 μm or more and 100 μm or less, and half the second repeat pitch P2 is, for example, 5 μm or more and 100 μm or less.

[0086] Half the first repeat pitch P1 of the first connection region 55a is, for example, 50 times or less the length in the first direction of the first connection region 55a (L1 in FIG. 3). Half the second repeat pitch P2 of the third connection region 55c is, for example, 50 times or less the length in the first direction of the third connection region 55c (L2 in FIG. 3).

[0087] The connection region 55 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the connection region 55 is higher than the p-type impurity concentration of the body region 52. The p-type impurity concentration of the connection region 55 is, for example, 1×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0088] The connection region 55 can be formed, for example, by forming a trench in the silicon carbide layer 10 and then ion-implanting aluminum (Al) into the silicon carbide layer 10 from the side surface of the trench using oblique ion implantation.

[0089] The connection region 55 serves to electrically connect the electric field relaxation region 54 and the body region 52. The connection region 55 fixes the electric field relaxation region 54 to the potential of the source electrode 41. The connection region 55 fixes the electric field relaxation region 54 to the source potential.

[0090] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0091] The MOSFET 100 of the first embodiment can simultaneously achieve a reduced on-resistance, improved reliability of the gate insulating layer, and reduced switching loss, as will be described in detail below.

[0092] The MOSFET 100 employs a trench gate structure in which a gate electrode is provided in a trench. The trench gate structure increases the channel area per unit area, thereby reducing the on-resistance of the MOSFET 100. For example, if the MOSFET 100 is miniaturized by reducing the trench width or the trench repetition pitch, the on-resistance of the MOSFET 100 can be further reduced.

[0093] MOSFET 100 also has an electric field relaxation region 54 at the bottom of the trench. By providing electric field relaxation region 54, the electric field applied to the gate insulating layer at the bottom of the trench is relaxed when MOSFET 100 is in an off state, thereby improving the reliability of the gate insulating layer.

[0094] For example, if the potential of the electric field relaxation region 54 is in a floating state, the switching loss of the MOSFET increases. For example, if the potential of the electric field relaxation region 54 is in a floating state, it takes time to discharge holes from the electric field relaxation region 54 during the turn-off operation of the MOSFET, which increases the switching loss.

[0095] MOSFET 100 has connection region 55 that electrically connects electric field relaxation region 54 and body region 52. By having connection region 55, MOSFET 100 fixes the potential of electric field relaxation region 54 to the potential of source electrode 41. Therefore, for example, when the MOSFET is turned off, the discharge of holes from electric field relaxation region 54 is promoted. As a result, the switching loss of MOSFET 100 can be reduced.

[0096] 6 is a schematic cross-sectional view of a semiconductor device of a comparative example. The semiconductor device of the comparative example is a trench-gate vertical MOSFET 900 using silicon carbide. MOSFET 900 is an n-channel MOSFET that uses electrons as carriers.

[0097] Fig. 7 is a schematic cross-sectional view of a semiconductor device of a comparative example. Fig. 7 is a cross-section taken along Fy in Fig. 6. Fig. 7 is a cross-section parallel to the first direction and the second direction. Fig. 7 is a cross-section parallel to the first plane F1. Fig. 6 is a cross-section taken along DD' in Fig. 7.

[0098] The MOSFET 900 of the comparative example differs from the MOSFET 100 of the first embodiment in that the first connection regions 55a and the second connection regions 55b are alternately arranged in the first direction between the first trench 11 and the second trench 21. The first connection regions 55a and the second connection regions 55b do not face each other in the second direction.

[0099] Also, the MOSFET 100 of the first embodiment differs from the MOSFET 100 of the first embodiment in that the third connection region 55c and the fourth connection region 55d are alternately arranged in the first direction between the first trench 11 and the third trench 31. The third connection region 55c and the fourth connection region 55d do not face each other in the second direction.

[0100] In the MOSFET 100 of the first embodiment, in the AA' cross section, two connection regions 55 are arranged between the first trench 11 and the second trench 21, and no connection region 55 is arranged between the first trench 11 and the third trench 31. On the other hand, in the MOSFET 900 of the comparative example, in the DD' cross section, one connection region 55 is arranged between the first trench 11 and the second trench 21, and one connection region 55 is also arranged between the first trench 11 and the third trench 31.

[0101] 3 and 7, the area occupied by connection region 55 is the same in MOSFET 100 and MOSFET 900. Therefore, the electrical resistance from source electrode 41 to electric field relaxation region 54 is the same in MOSFET 100 and MOSFET 900.

[0102] Fig. 8 is an explanatory diagram of the problem in the semiconductor device of the comparative example, and is a cross-sectional view corresponding to Fig. 6. Fig. 8 shows the current path during the ON operation of a MOSFET 900 of the comparative example.

[0103] In the MOSFET 900 of the comparative example, two current paths exist between the second trench 21 and the third trench 31. The two current paths are a first current path X and a second current path Y.

[0104] The first current path X exists between the first trench 11 and the third trench 31. In the first current path X, a current flows through a channel formed in a region where the sixth side surface 31b of the third trench 31 and the body region 52 contact each other.

[0105] The second current path Y exists between the first trench 11 and the second trench 21. In the second current path Y, a current flows through a channel formed in a region where the second side surface 11b of the first trench 11 and the body region 52 contact each other.

[0106] On the other hand, no current flows in the region along the first side surface 11a of the first trench 11 because the connection region 55 exists below the body region 52. Similarly, no current flows in the region along the third side surface 21a of the second trench 21 because the connection region 55 exists below the body region 52.

[0107] In the first current path X, the current path is narrowed between the third trench 31 and the connection region 55. Furthermore, in the first current path X, the current path is narrowed between the electric field relaxation region 54 and the connection region 55.

[0108] In the second current path Y, the current path is narrowed between the first trench 11 and the connection region 55. Furthermore, in the second current path Y, the current path is narrowed between the electric field relaxation region 54 and the connection region 55.

[0109] The narrowing of the first current path X and the second current path Y increases the on-resistance of the MOSFET 900. In particular, as the MOSFET 900 is miniaturized, the narrowing of the current paths becomes stronger as the distance between the trenches in the second direction becomes shorter. Therefore, the increase in the on-resistance of the MOSFET 900 associated with miniaturization becomes more pronounced.

[0110] Fig. 9 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. Fig. 9 is a cross-sectional view corresponding to Fig. 1. Fig. 9 shows a current path during an on-operation of the MOSFET 100 of the first embodiment.

[0111] In the MOSFET 100 of the first embodiment, two current paths exist between the second trench 21 and the third trench 31. The two current paths are a first current path X and a second current path Y.

[0112] The first current path X exists between the first trench 11 and the third trench 31. In the first current path X, a current flows through a channel formed in a region where the sixth side surface 31b of the third trench 31 and the body region 52 contact each other.

[0113] The second current path Y exists between the first trench 11 and the third trench 31. In the second current path Y, a current flows through a channel formed in a region where the first side surface 11a of the first trench 11 and the body region 52 are in contact with each other.

[0114] On the other hand, no current flows through the region along the second side surface 11b of the first trench 11 because the connection region 55 is present below the body region 52. Similarly, no current flows through the region along the third side surface 21a of the second trench 21 because the connection region 55 is present below the body region 52.

[0115] There is no connection region 55 between the first trench 11 and the third trench 31. Therefore, in the first current path X and the second current path Y, the current path is not narrowed between the trench and the connection region 55 or between the electric field relaxation region 54 and the connection region 55.

[0116] The first current path X and the second current path Y are not narrowed by the connection region 55, which suppresses an increase in the on-resistance of the MOSFET 100. In particular, even when the MOSFET 100 is miniaturized and the distance between the trenches in the second direction is shortened, an increase in the on-resistance is suppressed.

[0117] In the MOSFET 100, as shown in FIG. 3, the first connection regions 55a and the third connection regions 55c are alternately arranged in the first direction. This results in current paths being alternately formed in the first direction. This results in heat generation being distributed evenly within the MOSFET 100. This reduces the risk of failure of the MOSFET 100 due to heat generation, improving the reliability of the MOSFET 100.

[0118] From the viewpoint of miniaturizing the MOSFET 100 and reducing the on-resistance, the distance between the first trench 11 and the second trench 21 (d in FIG. 2) and the distance between the first trench 11 and the third trench 31 (d in FIG. 2) are preferably 2 μm or less, more preferably 1.5 μm or less, and even more preferably 1 μm or less.

[0119] From the viewpoint of miniaturizing the MOSFET 100 and reducing the on-resistance, the width in the second direction (w in FIG. 2) of the first trench 11, the second trench 21, and the third trench 31 is preferably 1 μm or less, and more preferably 0.7 μm or less.

[0120] From the viewpoint of reducing the electrical resistance between the source electrode 41 and the electric field relaxation region 54, the length in the first direction of the first connection region 55a and the second connection region 55b (L1 in FIG. 3) is preferably 0.5 μm or more, more preferably 1 μm or more, and even more preferably 2 μm or more.

[0121] From the viewpoint of reducing the on-resistance of MOSFET 100, the length in the first direction of first connection region 55a (L1 in FIG. 3) is preferably 3 μm or less, more preferably 2 μm or less, and even more preferably 1 μm or less.

[0122] From the viewpoint of reducing the electrical resistance between the source electrode 41 and the electric field relaxation region 54, the length in the first direction of the third connection region 55c and the fourth connection region 55d (L2 in FIG. 3) is preferably 0.5 μm or more, more preferably 1 μm or more, and even more preferably 2 μm or more.

[0123] From the viewpoint of reducing the on-resistance of MOSFET 100, the length in the first direction of third connection region 55c and fourth connection region 55d (L2 in FIG. 3) is preferably 3 μm or less, more preferably 2 μm or less, and even more preferably 1 μm or less.

[0124] From the viewpoint of reducing the electrical resistance between the source electrode 41 and the electric field relaxation region 54, half of the first repeat pitch P1 in the first direction of the first connection region 55a and the second connection region 55b is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 10 μm or less.

[0125] From the viewpoint of reducing the on-resistance of MOSFET 100, half of the first repeat pitch P1 in the first direction of first connection region 55a and second connection region 55b is preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 50 μm or more.

[0126] From the viewpoint of reducing the electrical resistance between the source electrode 41 and the electric field relaxation region 54, half of the second repeat pitch P2 in the first direction of the third connection region 55c and the fourth connection region 55d is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 10 μm or less.

[0127] From the viewpoint of reducing the on-resistance of MOSFET 100, half of the second repeat pitch P2 in the first direction of the third connection region 55c and the fourth connection region 55d is preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 50 μm or more.

[0128] From the viewpoint of reducing the electrical resistance between the source electrode 41 and the electric field relaxation region 54, half the first repeat pitch P1 of the first connection region 55a is preferably 50 times or less, more preferably 10 times or less, and even more preferably 5 times or less, the length of the first connection region 55a in the first direction (L1 in FIG. 3). Half the second repeat pitch P2 of the third connection region 55c is preferably 50 times or less, more preferably 10 times or less, and even more preferably 5 times or less, the length of the third connection region 55c in the first direction (L2 in FIG. 3).

[0129] (First Modification) Fig. 10 is a schematic cross-sectional view of a semiconductor device according to a first modification of the first embodiment, which corresponds to Fig. 3 of the first embodiment.

[0130] The MOSFET 101 of the first modification differs from the MOSFET 100 of the first embodiment in that the third connection region 55c and the fourth connection region 55d are not provided between the first trench 11 and the third trench 31. The MOSFET 101 of the first modification does not have the connection region 55 between the first trench 11 and the third trench 31.

[0131] The first repetition pitch P1 in the first direction of the first connection region 55a and the second connection region 55b is preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 50 μm or more.

[0132] Half the first repeat pitch P1 of the first connection region 55a is preferably 50 times or less, more preferably 10 times or less, and even more preferably 5 times or less, the length of the first connection region 55a in the first direction.

[0133] (Second Modification) Fig. 11 is a schematic cross-sectional view of a semiconductor device according to a second modification of the first embodiment, which corresponds to Fig. 2 of the first embodiment.

[0134] The MOSFET 102 of the second modification has p + The MOSFET 100 differs from the MOSFET 100 of the first embodiment in that the contact regions 56 are stripes extending in the first direction.

[0135] According to the MOSFET 102 of the second modification, the electrical resistance between the source electrode 41 and the electric field relaxation region 54 can be further reduced.

[0136] As described above, the MOSFETs of the first embodiment and the modifications thereof can simultaneously achieve a reduced on-resistance, improved reliability of the gate insulating layer, and reduced switching loss.

[0137] (Second embodiment) The semiconductor device of the second embodiment differs from the first embodiment in that the ninth silicon carbide region and the tenth silicon carbide region are in contact with each other in the first cross section. Hereinafter, some of the description overlapping with the first embodiment will be omitted.

[0138] Fig. 12 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment is a trench-gate vertical MOSFET 200 using silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers. Fig. 12 corresponds to Fig. 1 of the first embodiment.

[0139] In the MOSFET 200 of the second embodiment, the first connection region 55a (ninth silicon carbide region) and the second connection region 55b (tenth silicon carbide region) are adjacent to each other in the second direction. In the MOSFET 200 of the second embodiment, the third connection region 55c (eleventh silicon carbide region) and the fourth connection region 55d (twelfth silicon carbide region) are adjacent to each other in the second direction.

[0140] In the MOSFET 200 of the second embodiment, the electrical resistance between the source electrode 41 and the electric field relaxation region 54 is further reduced compared to the MOSFET 100 of the first embodiment. Therefore, the switching loss of the MOSFET 200 is further reduced.

[0141] As described above, the MOSFET of the second embodiment can simultaneously achieve a reduced on-resistance, improved reliability of the gate insulating layer, and reduced switching loss.

[0142] (Third embodiment) The semiconductor device of the third embodiment differs from the first embodiment in that, in a first cross section, the sixth silicon carbide region is in contact with the first side surface and the seventh silicon carbide region is in contact with the fourth side surface. Hereinafter, some description of the content that overlaps with the first embodiment will be omitted.

[0143] Fig. 13 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. The semiconductor device according to the third embodiment is a trench-gate vertical MOSFET 300 using silicon carbide. The MOSFET 300 is an n-channel MOSFET that uses electrons as carriers. Fig. 13 corresponds to Fig. 1 of the first embodiment.

[0144] In the MOSFET 300 of the third embodiment, the first electric field relaxation region 54a (sixth silicon carbide region) is in contact with the first side surface 11a of the first trench 11. The second electric field relaxation region 54b (seventh silicon carbide region) is in contact with the fourth side surface 21b of the second trench 21.

[0145] The end of the first electric field reduction region 54 a on the third trench 31 side is located closer to the third trench 31 than the first side surface 11 a of the first trench 11 .

[0146] In the MOSFET 300 of the third embodiment, the bottom of the trench is covered with the electric field relief region 54 and the connection region 55. Therefore, compared to the MOSFET 100 of the first embodiment, the reliability of the gate insulating layer is further improved.

[0147] As described above, the MOSFET of the third embodiment can simultaneously achieve a reduced on-resistance, improved reliability of the gate insulating layer, and reduced switching loss.

[0148] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the first embodiment in that the first silicon carbide region includes a first region and a second region provided between the first region and the second silicon carbide region and having a higher n-type impurity concentration than the first region. Hereinafter, some of the description overlapping with the first embodiment will be omitted.

[0149] Fig. 14 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. The semiconductor device according to the fourth embodiment is a trench-gate vertical MOSFET 400 using silicon carbide. The MOSFET 400 is an n-channel MOSFET that uses electrons as carriers. Fig. 14 corresponds to Fig. 1 of the first embodiment.

[0150] The MOSFET 400 of the fourth embodiment has n - The drift region 51 includes a first region 51a and a second region 51b. The second region 51b is provided between the first region 51a and the body region 52. The second region 51b is provided, for example, between the first region 51a and the first body region 52a.

[0151] The n-type impurity concentration of the second region 51b is higher than the n-type impurity concentration of the first region 51a, and is, for example, at least twice the n-type impurity concentration of the first region 51a.

[0152] The MOSFET 400 of the fourth embodiment has a reduced electrical resistance in the drift region 51 compared to the MOSFET 100 of the first embodiment. Therefore, the on-resistance of the MOSFET 400 is reduced.

[0153] As described above, the MOSFET of the fourth embodiment can simultaneously achieve a reduced on-resistance, improved reliability of the gate insulating layer, and reduced switching loss.

[0154] (Fifth embodiment) The semiconductor device of the fifth embodiment differs from the first embodiment in that the upper surface of the interlayer insulating layer 43 is provided in a trench. Hereinafter, some of the description overlapping with the first embodiment will be omitted.

[0155] Fig. 15 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. The semiconductor device according to the fifth embodiment is a trench-gate vertical MOSFET 500 using silicon carbide. The MOSFET 500 is an n-channel MOSFET that uses electrons as carriers. Fig. 15 corresponds to Fig. 1 of the first embodiment.

[0156] In the MOSFET 500 of the fifth embodiment, the upper surface of the interlayer insulating layer 43 is provided in the trench. In the MOSFET 500 of the fifth embodiment, patterning of the interlayer insulating layer 43 on the surface of the silicon carbide layer 10 is not required. Therefore, miniaturization is easier than in the MOSFET 100 of the first embodiment. Therefore, in the MOSFET 500 of the fifth embodiment, it is easier to further reduce the on-resistance.

[0157] As described above, the MOSFET of the fifth embodiment can simultaneously achieve a reduced on-resistance, improved reliability of the gate insulating layer, and reduced switching loss.

[0158] (Sixth embodiment) The inverter circuit and the drive device of the sixth embodiment are drive devices that include the semiconductor device of the first embodiment.

[0159] 16 is a schematic diagram of a driving device according to the sixth embodiment. The driving device 1000 includes a motor 140 and an inverter circuit 150.

[0160] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0161] According to the sixth embodiment, the inverter circuit 150 and the driving device 1000 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 1000.

[0162] (Seventh embodiment) The vehicle of the seventh embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0163] 17 is a schematic diagram of a vehicle according to the seventh embodiment. The vehicle 1100 according to the seventh embodiment is a railway vehicle. The vehicle 1100 includes a motor 140 and an inverter circuit 150.

[0164] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 1100 are rotated by the motor 140.

[0165] According to the seventh embodiment, the vehicle 1100 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1100.

[0166] (Eighth embodiment) The vehicle of the eighth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0167] 18 is a schematic diagram of a vehicle according to an eighth embodiment. The vehicle 1200 according to the eighth embodiment is an automobile. The vehicle 1200 includes a motor 140 and an inverter circuit 150.

[0168] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0169] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 1200.

[0170] According to the eighth embodiment, the vehicle 1200 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1200.

[0171] (Ninth embodiment) The elevator of the ninth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0172] 19 is a schematic diagram of an elevator according to the ninth embodiment. The elevator 1300 according to the ninth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0173] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0174] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0175] According to the ninth embodiment, the elevator 1300 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1300.

[0176] In the above, the first to fifth embodiments have been described using an example in which the silicon carbide crystal structure is 4H—SiC, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0177] Although the first to fifth embodiments have been described using a MOSFET as an example of a semiconductor device, the present invention can also be applied to an Insulated Gate Bipolar Transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 50 of the MOSFET 100 from n-type to p-type.

[0178] Furthermore, in the sixth to ninth embodiments, the semiconductor device of the first embodiment has been described as an example, but the semiconductor devices of the second to fifth embodiments can also be applied.

[0179] Furthermore, in the sixth to ninth embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0180] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0181] 10 Silicon carbide layer 11 First Trench 11a First Aspect 11b The second aspect 11c First bottom 12 First gate electrode 13 First gate insulating layer 21 Second Trench 21a The Third Aspect 21b The Fourth Aspect 21c Second bottom 22 second gate electrode 23 Second gate insulating layer 31 Third Trench 31a The fifth aspect 31b The Sixth Aspect 31c Third bottom 32 Third gate electrode 33 Third gate insulating layer 51 drift region (first silicon carbide region) 52a: First body region (second silicon carbide region) 52b: second body region (third silicon carbide region) 53a first source region (fourth silicon carbide region) 53b second source region (fifth silicon carbide region) 54a First electric field relaxation region (sixth silicon carbide region) 54b Second electric field relaxation region (seventh silicon carbide region) 54c Third electric field relaxation region (eighth silicon carbide region) 55a: first connection region (ninth silicon carbide region) 55b second connection region (tenth silicon carbide region) 55c third connection region (eleventh silicon carbide region) 55d Fourth connection region (12th silicon carbide region) 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 500 MOSFET (semiconductor device) 1000 Drive Unit 1100 vehicles 1200 vehicles 1300 elevator AA' section First section BB' section Second section F1 First Side F2 Second side P1 First repeat pitch P2 Second repeat pitch

Claims

1. a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; a plurality of p-type eleventh silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the third silicon carbide region, in contact with the first side surface, and repeatedly arranged in the first direction; a plurality of p-type twelfth silicon carbide regions located in the silicon carbide layer, in contact with the eighth silicon carbide region, in contact with the third silicon carbide region, in contact with the sixth side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; In a second cross section that is parallel to the first cross section, is positioned in the first direction relative to the first cross section, and includes one of the eleventh silicon carbide regions and one of the twelfth silicon carbide regions, the first silicon carbide region contacts the second side surface and the third side surface.

2. The semiconductor device according to claim 1 , wherein the ninth silicon carbide regions and the eleventh silicon carbide regions are alternately arranged in the first direction.

3. 3 . The semiconductor device according to claim 2 , wherein a repeat pitch of the ninth silicon carbide regions in the first direction is equal to a repeat pitch of the eleventh silicon carbide regions in the first direction.

4. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; the ninth silicon carbide region and the tenth silicon carbide region are in contact with each other in the first cross section.

5. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; In the first cross section, the sixth silicon carbide region contacts the first side surface, and the seventh silicon carbide region contacts the fourth side surface.

6. 6. The semiconductor device according to claim 1, wherein the width of the first trench in the second direction is smaller than the distance between the first trench and the second trench.

7. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; The semiconductor device, wherein the distance between the first trench and the second trench is 2 μm or less.

8. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; The semiconductor device, wherein the width of the first trench in the second direction is 1 μm or less.

9. 2 . The semiconductor device according to claim 1 , wherein a repeat pitch of said ninth silicon carbide regions in said first direction is 50 times or less the length of said ninth silicon carbide regions in said first direction.

10. 4. The semiconductor device according to claim 3, wherein half the repeat pitch of said ninth silicon carbide region in said first direction is 50 times or less the length of said ninth silicon carbide region in said first direction.

11. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; the length of the ninth silicon carbide region in the first direction is not less than 0.5 μm and not more than 3 μm.

12. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, extending in the first direction in the first surface, the first trench having a first side, a second side, and a first bottom surface between the first side and the second side; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction in the first surface, the second trench having a third side surface facing the second side surface, a fourth side surface, and a second bottom surface between the third side surface and the fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, the first trench being located between the third trench and the second trench, the third trench having a fifth side surface, a sixth side surface opposing the first side surface, and a third bottom surface between the fifth side surface and the sixth side surface; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first bottom surface; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second bottom surface; a p-type eighth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the third bottom surface; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, in contact with the second silicon carbide region, in contact with the second side surface, and repeatedly arranged in the first direction; a plurality of p-type tenth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, in contact with the second silicon carbide region, in contact with the third side surface, and repeatedly arranged in the first direction; Equipped with in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and including one of the ninth silicon carbide regions and one of the tenth silicon carbide regions, the first silicon carbide region is in contact with the first side surface and the sixth side surface; a repeating pitch of the ninth silicon carbide regions in the first direction is not less than 5 μm and not more than 100 μm.

13. 4. The semiconductor device according to claim 3, wherein half the repeat pitch of said ninth silicon carbide regions in said first direction is not less than 5 [mu]m and not more than 100 [mu]m.

14. An inverter circuit comprising the semiconductor device according to claim 1 .

15. A driving device comprising the semiconductor device according to any one of claims 1 to 13.

16. A vehicle comprising the semiconductor device according to any one of claims 1 to 13.

17. An elevator comprising the semiconductor device according to any one of claims 1 to 13.

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