Nonvolatile memory device and nonvolatile memory system including the same

Abstract

To provide a nonvolatile memory device capable of maintaining connection reliability between an uppermost end of a cell region and an uppermost end of a peripheral circuit region and lowering a unit price of process by reducing a size of the cell region and / or the peripheral circuit region, and a nonvolatile memory system.SOLUTION: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer sequentially laminated in a first direction, a lower metal layer included in the first lower interlayer insulation layer, and a plurality of lower bonding metals included in the first lower interlayer insulation layer and the second lower interlayer insulation layer and separated from each other in a second direction perpendicular to the first direction. An uppermost end in the first direction of the lower metal layer is lower than an uppermost end in the first direction of the plurality of lower bonding metals, and the lower metal layer is arranged between the plurality of lower bonding metals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile memory device and a nonvolatile memory system including the same. [Background technology]

[0002] In electronic systems requiring data storage, there is a demand for nonvolatile memory devices capable of storing large amounts of data. Accordingly, methods for increasing the data storage capacity of nonvolatile memory devices have been studied. For example, as one method for increasing the data storage capacity of nonvolatile memory devices, a nonvolatile memory device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed.

[0003] For example, a nonvolatile memory device has been proposed in which the top end of a cell region including memory cells arranged three-dimensionally is bonded to the top end of a peripheral circuit region including peripheral circuit elements that drive the memory cells.

[0004] In this case, when connecting the top end of the cell region and the top end of the peripheral circuit region, it is necessary to eliminate the influence of factors that deteriorate the reliability of the connection, such as dishing. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-33244 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a nonvolatile memory device and a nonvolatile memory system that maintains connection reliability between the top of the cell region and the top of the peripheral circuit region while reducing the size of the cell region and / or the peripheral circuit region. [Means for solving the problem]

[0007] In order to achieve the above object, a nonvolatile memory device according to one aspect of the present invention comprises a first lower interlayer insulating layer and a second lower interlayer insulating layer stacked in sequence in a first direction, a lower metal layer included in the first lower interlayer insulating layer, and a plurality of lower bonding metals included in the first lower interlayer insulating layer and the second lower interlayer insulating layer and spaced apart from each other in a second direction perpendicular to the first direction, wherein the uppermost end of the lower metal layer in the first direction is lower than the uppermost ends of the plurality of lower bonding metals in the first direction, and the lower metal layer is disposed between the plurality of lower bonding metals.

[0008] In order to achieve the above object, a nonvolatile memory device according to another aspect of the present invention includes a first substrate, a plurality of metal lines stacked in a first direction on the first substrate, a channel structure penetrating the plurality of metal lines, a plurality of upper metal layers electrically connected to the plurality of metal lines and the channel structure, a plurality of upper bonding metals electrically connected to one or more of the plurality of upper metal layers, a first lower interlayer insulating layer and a second lower interlayer insulating layer stacked in sequence on the upper bonding metals, a plurality of lower bonding metals electrically connected to the upper bonding metals and included in the first lower interlayer insulating layer and the second lower interlayer insulating layer, and a lower metal layer disposed between the plurality of lower bonding metals and electrically connected to peripheral circuit elements and included in the second lower interlayer insulating layer, wherein the uppermost end of the lower metal layer in the first direction is lower than the height at which the plurality of lower bonding metals contact the plurality of upper bonding metals.

[0009] In order to achieve the above object, one aspect of the present invention provides a nonvolatile memory system comprising: a main substrate; a nonvolatile memory device on the main substrate; and a controller electrically connected to the nonvolatile memory device on the main substrate, wherein the nonvolatile memory device comprises a first substrate; a lower metal layer disposed on the first substrate and spaced apart from the first substrate in a first direction; and a plurality of lower bonding metals spaced apart from each other in a second direction perpendicular to the first direction, wherein the uppermost end of the lower metal layer in the first direction is lower than the uppermost ends of the plurality of lower bonding metals in the first direction, and the lower metal layer is disposed between the plurality of lower bonding metals.

[0010] According to one embodiment, a method for manufacturing a nonvolatile memory device includes the steps of forming peripheral circuit elements on a substrate, forming a first insulating layer in a first direction from the peripheral circuit elements, etching the first insulating layer to form a first trench, filling the first trench with a first metal material to form a metal layer, forming a second insulating layer on the metal layer and the first insulating layer, etching the first insulating layer and the second insulating layer to form a second trench and a third trench, and filling the second trench and the third trench with a second metal material to form a plurality of bonding metals, the plurality of bonding metals being spaced apart from each other around the metal layer, and the top ends of the metal layer in the first direction being lower than the top ends of the plurality of bonding metals in the first direction. [Effects of the Invention]

[0011] According to the nonvolatile memory device of the present invention, since the merged wiring is not exposed on the surface where the first structure and the second structure are connected, it is possible to eliminate the dishing phenomenon that occurs when performing a planarization process on the metal disposed on the surface where the cell region and the peripheral circuit region meet, thereby maintaining the connection reliability between the top of the cell region and the peripheral circuit region and reducing the size of the peripheral circuit region, thereby reducing the process cost. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is an exemplary diagram illustrating a nonvolatile memory device according to an embodiment; [Figure 2] FIG. 2 is an exemplary enlarged view of the R1 region of FIG. 1. [Figure 3] FIG. 3 is a top view taken along the line AA' in FIG. 2. [Figure 4] FIG. 3 is a top view taken along the line BB' in FIG. 2. [Figure 5] 1A to 1C are exemplary diagrams illustrating intermediate steps of a method for manufacturing a nonvolatile memory device according to an embodiment; [Figure 6] 1A to 1C are exemplary diagrams illustrating intermediate steps of a method for manufacturing a nonvolatile memory device according to an embodiment; [Figure 7] 1A to 1C are exemplary diagrams illustrating intermediate steps of a method for manufacturing a nonvolatile memory device according to an embodiment; [Figure 8] 1A to 1C are exemplary diagrams illustrating intermediate steps of a method for manufacturing a nonvolatile memory device according to an embodiment; [Figure 9] 1A to 1C are exemplary diagrams illustrating intermediate steps of a method for manufacturing a nonvolatile memory device according to an embodiment; [Figure 10] 2A-2C are various exemplary enlarged views illustrating the CSLR region of FIG. 1. [Figure 11] 2A-2C are various exemplary enlarged views illustrating the CSLR region of FIG. 1. [Figure 12] FIG. 2 is an exemplary enlarged view of the R2 region of FIG. 1. [Figure 13] FIG. 2 is an exemplary enlarged view of the R3 region of FIG. 1. [Figure 14] 10 is an exemplary diagram illustrating another nonvolatile memory device according to an embodiment; [Figure 15] FIG. 15 is an exemplary enlarged view of the R4 region of FIG. 14. [Figure 16] 10 is an exemplary diagram illustrating another nonvolatile memory device according to an embodiment; [Figure 17]1 is an exemplary block diagram illustrating a nonvolatile memory system including a nonvolatile memory device according to an embodiment; [Figure 18] 1 is an exemplary perspective view illustrating a nonvolatile memory system including a nonvolatile memory device according to an embodiment; [Figure 19] 19 is an exemplary cross-sectional view illustrating a region cut along II' of the nonvolatile memory package of FIG. 18 including a nonvolatile memory device according to an embodiment. [Figure 20] 19 is an exemplary cross-sectional view illustrating a region cut along II' of the nonvolatile memory package of FIG. 18 including a nonvolatile memory device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0014] FIG. 1 is an exemplary diagram illustrating a nonvolatile memory device according to an embodiment.

[0015] Referring to FIG. 1, the nonvolatile memory device 300a according to this embodiment has a chip-to-chip (C2C) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other by a bonding method. For example, the bonding method refers to electrically connecting an upper bonding metal (e.g., 372a, 372b, 372c, or 392) formed on the top metal layer of the upper chip to a lower bonding metal (e.g., 272a, 272b, 272c, 273a, or 252) formed on the top metal layer of the lower chip to each other. For example, if the upper and lower bonding metals are made of copper (Cu), the bonding method is Cu-Cu bonding. The upper and lower bonding metals may be made of aluminum or tungsten.

[0016] Each of the peripheral circuit region PERI and the cell region CELL of the nonvolatile memory device 300a according to this embodiment includes an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0017] The peripheral circuit region PERI includes a first substrate 210, an interlayer insulating layer 215, a plurality of peripheral circuit elements (220a, 220b, 220c) formed on the first substrate 210, first metal layers (230a, 230b, 230c) connected to each of the plurality of peripheral circuit elements (220a, 220b, 220c), and second metal layers (240a, 240b, 240c) formed on the first metal layers (230a, 230b, 230c). In one embodiment, the first metal layers (230a, 230b, 230c) are formed of tungsten, which has a relatively high resistance, and the second metal layers (240a, 240b, 240c) are formed of copper, which has a relatively low resistance.

[0018] Although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are illustrated and described herein, the present invention is not limited thereto, and at least one more metal layer may be formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c is formed of aluminum or the like, which has a lower resistance than copper, which forms the second metal layers 240a, 240b, and 240c.

[0019] The lower interlayer insulating layer 215 is disposed on the first substrate 210 to cover the peripheral circuit elements (220a, 220b, 220c), the first metal layers (230a, 230b, 230c), and the second metal layers (240a, 240b, 240c), and includes an insulating material such as silicon oxide, silicon nitride, etc. The lower interlayer insulating layer 215 is composed of multiple layers.

[0020] Lower bonding metals (271b, 272b) are formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals (271b, 272b) in the peripheral circuit region PERI are electrically connected to the upper bonding metals (371b, 372b) in the cell region CELL by bonding, and the lower bonding metals (271b, 272b) and the upper bonding metals (371b, 372b) are formed of aluminum, copper, tungsten, or the like. The lower bonding metals (271b, 272b) and the upper bonding metals (371b, 372b) are spaced apart from each other in the first direction x.

[0021] In this case, the peripheral circuit region PERI can reduce its size and process costs by merging metal layers to form a single wiring. For example, assuming that a third metal layer (not shown) is formed on top of the second metal layers (240a, 240b, 240c) in the peripheral circuit region PERI, if the third metal layer is formed on top of the second metal layers (240a, 240b, 240c), the thickness of the peripheral circuit region PERI in the third direction z will be thicker than the thickness shown in this drawing. However, by merging the third metal layer through the lower metal layers (250a, 250b, 250c), the third metal layer can be eliminated.

[0022] Here, each of the lower metal layers (250a, 250b, 250c) is disposed between a plurality of lower bonding metals. For example, the lower metal layer 250b is disposed between a plurality of lower bonding metals 272b. As another example, the lower metal layer 250a is disposed between the lower metal pattern 273a and the lower bonding metal 272b. As yet another example, the lower metal layer 250c is disposed between the lower bonding metal 272c and the lower metal pattern 252. In other words, by merging one metal layer into a metal layer (e.g., the lower metal layer 250b), the size of the peripheral circuit region PERI can be reduced, thereby reducing the process cost.

[0023] However, if the top end in the third direction z of a metal layer that combines one or more metal layers (e.g., the lower metal layer 250b of the word line bonding area WLBA, the lower metal layer 250a of the external pad bonding area PA, or the lower metal layer 250c of the bit line bonding area BLBA) is located at the same height as the height at which the cell area CELL and the peripheral circuit area PERI meet, a dishing phenomenon occurs, reducing the connection reliability between the top end of the cell area CELL and the peripheral circuit area PERI.

[0024] Therefore, in the nonvolatile memory device 300a according to this embodiment, the uppermost end in the third direction z of a metal layer (e.g., the lower metal layer 250b of the word line bonding area WLBA, the lower metal layer 250a of the external pad bonding area PA, or the lower metal layer 250c of the bit line bonding area BLBA) formed by combining one or more metal layers is formed lower than the height at which the cell region CELL and the peripheral circuit region PERI meet. This prevents dishing that occurs when a planarization process is performed on metal (e.g., the lower bonding metals 272b, the lower metal pattern 273a, and the lower metal pattern 252) disposed at the interface between the cell region CELL and the peripheral circuit region PERI. This maintains the reliability of the connection between the uppermost end of the cell region CELL and the peripheral circuit region PERI, and reduces the size of the peripheral circuit region PERI, thereby reducing the process cost.

[0025] The structure and manufacturing method of the word line bonding area WLBA of the nonvolatile memory device according to an embodiment will be described in detail below with reference to FIGS.

[0026] Fig. 2 is an exemplary enlarged view of the R1 region in Fig. 1. For reference, the description of the R1 region of the word line bonding region WLBA is of course applicable to other parts of the word line bonding region WLBA.

[0027] 2, the uppermost end P2 of the lower metal layer 250b in the third direction z is formed lower than the uppermost end C_F of the lower bonding metals 271b and 272b in the third direction z. The uppermost end C_F of the lower bonding metals 271b and 272b in the third direction z is a contact surface where the lower bonding metal 272b and the upper bonding metal 372b come into contact. That is, the contact surface C_F is a bonding surface where the cell region CELL and the peripheral circuit region PERI are bonded.

[0028] The lower interlayer insulating layer 215 includes a plurality of lower interlayer insulating layers. A first lower interlayer insulating layer 215a is formed on the first substrate 210. A first metal layer 230b and a second metal layer 240b are formed in the first lower interlayer insulating layer 215a. The first lower interlayer insulating layer 215a may include a plurality of first lower interlayer insulating layers.

[0029] A second lower interlayer insulating layer 215b is formed on the first lower interlayer insulating layer 215a. A lower bonding metal 271b is formed in the second lower interlayer insulating layer 215b. A via portion of the lower metal layer 250b is also formed in the second lower interlayer insulating layer 215b. More specifically, a via portion of the lower bonding metal 271b and the lower metal layer 250b is formed between the bottom end P0 and the top end P1 of the second lower interlayer insulating layer 215b.

[0030] A third lower interlayer insulating layer 215c is formed on the second lower interlayer insulating layer 215b. A pad region of the lower metal layer 250b is formed in the third lower interlayer insulating layer 215c. Also, at least a portion of each of the lower bonding metals 272b is formed in the third lower interlayer insulating layer 215c. More specifically, at least a portion of the lower bonding metal 272b and a pad portion of the lower metal layer 250b are formed between the bottom end P1 and the top end P2 of the third lower interlayer insulating layer 215c.

[0031] A fourth lower interlayer insulating layer 215d is formed on the third lower interlayer insulating layer 215c. Remaining portions of the lower bonding metals 272b are formed in the fourth lower interlayer insulating layer 215d. More specifically, the remaining portions of the lower bonding metals 272b are formed between the bottom end P2 and the top end C_F of the fourth lower interlayer insulating layer 215d.

[0032] That is, the lower metal layer 250b is formed inside the second lower interlayer insulating layer 215b and the third lower interlayer insulating layer 215c, and the lower bonding metals (271b, 272b) are formed inside the second lower interlayer insulating layer 215b, the third lower interlayer insulating layer 215c, and the fourth lower interlayer insulating layer 215d.

[0033] As a result, the lower metal layer 250b is disposed between the lower bonding metals (271b, 272b) and is not exposed to the bonding surface C_F. This will be explained in more detail with reference to the top views of FIGS.

[0034] FIG. 3 is a top view taken along line AA' in FIG.

[0035] Referring to Figures 2 and 3, when the lower portion of the bonding surface C_F is viewed from the third direction z, a plurality of lower bonding metals 272b and lower metal layers 250b formed in the third lower interlayer insulating layer 215c can be seen.

[0036] FIG. 4 is a top view taken along line BB' in FIG.

[0037] 2 and 4, when the bonding surface C_F is viewed from the third direction z, only the lower bonding metals 272b formed in the fourth lower interlayer insulating layer 215d can be seen, unlike in FIG. 3. That is, it can be seen that the lower metal layer 250b is not exposed on the bonding surface C_F.

[0038] A method for manufacturing a nonvolatile memory device according to an embodiment will be described from an intermediate stage with reference to FIGS.

[0039] 5 to 9 are exemplary diagrams illustrating intermediate steps of a method for manufacturing a nonvolatile memory device according to an embodiment. For reference, the manufacturing method described with reference to FIGS. 5 to 9 may also be applied to other regions of a nonvolatile memory device according to some embodiments.

[0040] 5, peripheral circuit elements 220b and a first lower interlayer insulating layer 215a are formed on a first substrate 210. The first substrate 210 includes, but is not limited to, a base substrate and an epitaxial layer grown on the base substrate. For example, the first substrate 210 may include only the base substrate without the epitaxial layer. The first substrate 210 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate, or an SOI (Semiconductor On Insulator) substrate. Hereinafter, the first substrate 210 will be described as a silicon substrate.

[0041] Next, a first metal layer 230b and a second metal layer 240b electrically connected to the peripheral circuit elements 220b are sequentially formed in the first lower interlayer insulating layer 215a in the third direction z. The first metal layer 230b and the second metal layer 240b each include a via extending in the third direction z and a pad extending in the first direction x. However, the structures of the first metal layer 230b and the second metal layer 240b according to this embodiment are not limited thereto.

[0042] Next, referring to FIG. 6, a second lower interlayer insulating layer 215b is formed on the first lower interlayer insulating layer 215a and the second metal layer 240b.

[0043] More specifically, the second lower interlayer insulating layer 215b is formed from the first position P0 to the second position P1, but the thickness of the second lower interlayer insulating layer 215b is not limited thereto.

[0044] A lower bonding metal 271b is formed inside the second lower interlayer insulating layer 215b, and a part of the lower metal layer 250b is formed inside the second lower interlayer insulating layer 215b.

[0045] The lower bonding metal 271b is electrically connected to the second metal layer 240b, and a portion of the lower metal layer 250b is also electrically connected to the second metal layer 240b.

[0046] Next, referring to FIG. 7, a third lower interlayer insulating layer 215c is formed on the second lower interlayer insulating layer 215b, the lower bonding metal 271b, and a portion of the lower metal layer 250b.

[0047] A lower metal layer 250b is formed within the third lower interlayer insulating layer 215c. The lower metal layer 250b is included in the second lower interlayer insulating layer 215b and the third lower interlayer insulating layer 215c. The lower metal layer 250b is electrically connected to the second metal layer 240b.

[0048] Next, referring to FIG. 8, a fourth lower interlayer insulating layer 215d is stacked on the third lower interlayer insulating layer 215c and the lower metal layer 250b.

[0049] 9, the third and fourth lower interlayer insulating layers 215c and 215d are etched to form a lower bonding metal 272b. The lower bonding metal 272b is included in the second, third, and fourth lower interlayer insulating layers 215b, 215c, and 215d.

[0050] The fourth lower interlayer insulating layer 215d is formed from the third position P2 to the fourth position C_F, but the thickness of the fourth lower interlayer insulating layer 215d is not limited thereto.

[0051] The first to fourth lower interlayer insulating layers 215a to 215d include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. Examples of low dielectric constant materials include, but are not limited to, at least one of FOX (Flowable Oxide), TOSZ (Torene Silazene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof.

[0052] Furthermore, the material constituting the first metal layer 230b, the material constituting the second metal layer 240b, the first metal material, and the second metal material include metals such as aluminum (Al), copper (Cu), tungsten (W), etc., but are not limited to these.

[0053] 1, the cell region CELL provides at least one memory block. The cell region CELL includes a second substrate 310 and a common source line 320. A plurality of metal lines or word lines (331-338; 330) are stacked on the second substrate 310 along a direction (z-axis direction) perpendicular to the top surface of the second substrate 310. A string selection line and a ground selection line are respectively arranged above and below the metal lines or word lines 330, and a plurality of word lines 330 are arranged between the string selection line and the ground selection line.

[0054] In the bit line bonding area BLBA, the channel structure CH extends in a direction perpendicular to the top surface of the second substrate 310 and penetrates the word lines 330, the string select lines, and the ground select lines.

[0055] The second substrate 310, the common source line 320, and the channel structure CH of the nonvolatile memory device 300a according to this embodiment may be formed in various shapes. Various structures of the second substrate 310, the common source line 320, and the channel structure CH of the nonvolatile memory device 300a according to an embodiment will be exemplarily described with reference to FIGS. 10 and 11, with the CSLR region enlarged.

[0056] 10 and 11 are various exemplary enlarged views for explaining the CSLR region of FIG.

[0057] 1, 10, and 11, the channel structure CH includes a data storage layer 397, a channel layer 390, a buried insulating layer 391, etc., and the channel layer 390 is electrically connected to a first metal layer 350c and a second metal layer 360c. For example, the first metal layer 350c is a bit line contact, and the second metal layer 360c is a bit line. In this embodiment, the bit line 360c extends along a second direction y parallel to the top surface of the second substrate 310.

[0058] The channel structure CH extends in the vertical direction Z and penetrates the word lines 330, the string select lines, and the ground select lines. As shown in Figures 10 and 11, the channel structure CH includes a channel layer 390 and a data storage layer 397.

[0059] The channel layer 390 extends in a third direction Z. Although the channel layer 390 is shown to have a stacked cup shape, this is merely an example, and the channel layer 390 may have various shapes such as a cylindrical shape, a rectangular tubular shape, a solid filler shape, a single cup shape, etc. The channel layer 390 may be made of a semiconductor material such as, but not limited to, single crystal silicon, polycrystalline silicon, an organic semiconductor, or a carbon nanostructure.

[0060] The data storage layer 397 is interposed between the channel layer 390 and the word line 330. For example, the data storage layer 397 extends along the side of the channel layer 390.

[0061] In this embodiment, the data storage layer 397 is formed of multiple layers. For example, the data storage layer 397 includes a tunnel insulating layer 397a, a charge storage layer 397b, and a blocking insulating layer 397c, which are sequentially stacked on the channel layer 390. The tunnel insulating layer 397a includes, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage layer 397b includes, for example, silicon nitride. The blocking insulating layer 397c includes, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide. In this embodiment, the data storage layer 397 further includes a gate insulating layer 397d extending along the surface of each word line 330.

[0062] In this embodiment, the channel structure CH further includes a buried insulating layer 391. The buried insulating layer 391 is formed to fill the inside of the cup-shaped channel layer 390. The buried insulating layer 391 may include an insulating material, such as, but not limited to, silicon oxide.

[0063] The common source line 320 is formed to be connected to the channel layer 390 of the channel structure CH.

[0064] 10, in one example of this embodiment, the channel structure CH is embedded in the second substrate 310 through a common source line 320. The common source line 320 is connected to a side of the channel layer 390 through a portion of the data storage layer 397.

[0065] 11 , in another example of this embodiment, at least a portion of the common source line 320 is embedded in the second substrate 310. The common source line 320 is formed from the second substrate 310 by, for example, a selective epitaxial growth (SEG) process. The channel layer 390 penetrates a portion of the data storage layer 397 and is connected to an upper surface of the common source line 320.

[0066] 1, a common source line contact plug 380 is disposed in the external pad bonding area PA. The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon, and is electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a are sequentially stacked on the common source line contact plug 380. For example, the area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed is defined as the external pad bonding area PA.

[0067] Meanwhile, input / output pads 205, 305 are disposed in the external pad bonding area PA. Referring to FIG. 1, a lower insulating film 201 is formed under a first substrate 210 to cover the lower surface of the first substrate 210, and a first input / output pad 205 is formed on the lower insulating film 201. The first input / output pad 205 is connected to at least one of a plurality of circuit elements 220a, 220b, 220c disposed in the peripheral circuit area PERI via a first input / output contact plug 203 and is separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film is disposed between the first input / output contact plug 203 and the first substrate 210 to electrically separate the first input / output contact plug 203 from the first substrate 210.

[0068] Hereinafter, a structure of an external pad bonding area PA of a nonvolatile memory device according to an embodiment will be described in detail with reference to FIG.

[0069] Fig. 12 is an exemplary enlarged view of the R2 region in Fig. 1. For reference, the description of the R2 region of the external pad bonding area PA is of course applicable to other portions of the external pad bonding area PA.

[0070] 12, the uppermost end P2 of the lower metal layer 250a in the third direction z is formed lower than the uppermost end C_F of the lower metal pattern 273a and the lower bonding metal 272b in the third direction z. The uppermost end C_F of the lower metal pattern 273a and the lower bonding metal 272b in the third direction z is the contact surface where the lower metal pattern 273a contacts the upper metal pattern 372a. Also, the uppermost end C_F is the contact surface where the lower bonding metal 272b contacts the upper bonding metal 372b. That is, the contact surface C_F is the bonding surface where the cell region CELL and the peripheral circuit region PERI are bonded.

[0071] The lower interlayer insulating layer 215 includes a plurality of lower interlayer insulating layers. A first lower interlayer insulating layer 215a is formed on the first substrate 210. First metal layers (230a, 230b) and second metal layers (240a, 240b) are formed in the first lower interlayer insulating layer 215a. Also, a portion of the I / O contact plug 203 is formed in the first lower interlayer insulating layer 215a. The first lower interlayer insulating layer 215a may include a plurality of first lower interlayer insulating layers.

[0072] A second lower interlayer insulating layer 215b is formed on the first lower interlayer insulating layer 215a. A lower bonding metal 271b is formed in the second lower interlayer insulating layer 215b. A via portion of the lower metal layer 250a is also formed in the second lower interlayer insulating layer 215b. More specifically, the lower bonding metal 271b and the via portion of the lower metal layer 250a are formed between the bottom end P0 and the top end P1 of the second lower interlayer insulating layer 215b. The remainder of the I / O contact plug 203 is also formed in the second lower interlayer insulating layer 215b.

[0073] A third lower interlayer insulating layer 215c is formed on the second lower interlayer insulating layer 215b. A pad region of the lower metal layer 250a is formed in the third lower interlayer insulating layer 215c. At least a portion of the lower bonding metal 272b is formed in the third lower interlayer insulating layer 215c. At least a portion of the lower metal pattern 273a is formed in the third lower interlayer insulating layer 215c. More specifically, at least a portion of the lower bonding metal 272b, the pad portion of the lower metal layer 250a, and a portion of the lower metal pattern 273a are formed between the bottom end P1 and the top end P2 of the third lower interlayer insulating layer 215c.

[0074] A fourth lower interlayer insulating layer 215d is formed on the third lower interlayer insulating layer 215c. The remaining portion of the lower bonding metal 272b is formed in the fourth lower interlayer insulating layer 215d. Also, the remaining portion of the lower metal pattern 273a is formed in the fourth lower interlayer insulating layer 215d. More specifically, the remaining portion of the lower bonding metal 272b and the remaining portion of the lower metal pattern 273a are formed between the bottom end P2 and the top end C_F of the fourth lower interlayer insulating layer 215d.

[0075] That is, the lower metal layer 250a is formed within the second and third lower interlayer insulating layers 215b and 215c, the lower bonding metal 272b is formed within the second, third and fourth lower interlayer insulating layers 215b, 215c and 215d, and the lower metal pattern 273a is formed within the third and fourth lower interlayer insulating layers 215c and 215d.

[0076] The manufacturing method for the R2 region of the nonvolatile memory device according to this embodiment is the same as that described above with reference to FIGS. 5 to 9, and therefore the description thereof will be omitted.

[0077] 1, an upper insulating film 301 is formed on the second substrate 310 to cover the upper surface of the second substrate 310, and a second I / O pad 305 is disposed on the upper insulating film 301. The second I / O pad 305 is connected to at least one of the plurality of circuit elements (220a, 220b, 220c) disposed in the peripheral circuit region PERI via a second I / O contact plug 303.

[0078] According to the embodiment, the second substrate 310, the common source line 320, etc. are not arranged in the region where the second I / O contact plug 303 is arranged. Also, the second I / O pad 305 does not overlap the word line 330 in the third direction (Z-axis direction). Referring to FIG. 1, the second I / O contact plug 303 is separated from the second substrate 310 in a direction parallel to the top surface of the second substrate 310 and is connected to the second I / O pad 305 through the upper interlayer insulating layer 315 of the cell region CELL.

[0079] Depending on the embodiment, the first I / O pad 205 and the second I / O pad 305 may be selectively formed. For example, the nonvolatile memory device 300a may include only the first I / O pad 205 disposed on the first substrate 210, or only the second I / O pad 305 disposed on the second substrate 310. Alternatively, the nonvolatile memory device 300a may include both the first I / O pad 205 and the second I / O pad 305.

[0080] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty.

[0081] 1, the region where the channel structure CH and the bit line 360c are disposed is defined as a bit line bonding region BLBA. The bit line 360c is electrically connected to a circuit element 220c that provides a page buffer 393 in the peripheral circuit region PERI in the bit line bonding region BLBA. For example, the bit line 360c is connected to upper bonding metals 371c and 372c in the peripheral circuit region PERI, and the upper bonding metals 371c and 372c are connected to lower bonding metals 271c and 272c that are connected to the circuit element 220c of the page buffer 393.

[0082] Hereinafter, the structure of the bit line bonding area BLBA of the nonvolatile memory device according to an embodiment will be described in detail with reference to FIG.

[0083] Fig. 13 is an exemplary enlarged view of the R3 region in Fig. 1. For reference, the description of the R3 region of the bit line bonding region BLBA is of course applicable to other parts of the bit line bonding region BLBA.

[0084] 13, the uppermost end P2 of the lower metal layer 250c in the third direction z is formed lower than the uppermost end C_F of the lower metal pattern 252 and the lower bonding metal 272c in the third direction z. The uppermost end C_F of the lower metal pattern 252 and the lower bonding metal 272c in the third direction z is a contact surface where the lower metal pattern 252 contacts the upper metal pattern 392. In addition, the uppermost end C_F is a contact surface where the lower bonding metal 272c contacts the upper bonding metal 372c. In other words, the contact surface C_F is a bonding surface where the cell region CELL and the peripheral circuit region PERI are bonded.

[0085] The lower interlayer insulating layer 215 includes a plurality of lower interlayer insulating layers. A first lower interlayer insulating layer 215a is formed on the first substrate 210. A first metal layer 230c and a second metal layer 240c are formed in the first lower interlayer insulating layer 215a. The first lower interlayer insulating layer 215a may include a plurality of first lower interlayer insulating layers.

[0086] A second lower interlayer insulating layer 215b is formed on the first lower interlayer insulating layer 215a. A lower bonding metal 271c and a via portion 251 of the lower metal pattern are formed in the second lower interlayer insulating layer 215b. Also, a via portion of a lower metal layer 250c is formed in the second lower interlayer insulating layer 215b. More specifically, the lower bonding metal 271c, the via portion 251 of the lower metal pattern, and the via portion of the lower metal layer 250c are formed between the bottom end P0 and the top end P1 of the second lower interlayer insulating layer 215b.

[0087] A third lower interlayer insulating layer 215c is formed on the second lower interlayer insulating layer 215b. A pad region of the lower metal layer 250c is formed in the third lower interlayer insulating layer 215c. At least a portion of a lower bonding metal 272c is formed in the third lower interlayer insulating layer 215c. A portion of the lower metal pattern 252 is formed in the third lower interlayer insulating layer 215c. More specifically, at least a portion of the lower bonding metal 272c, the pad portion of the lower metal layer 250c, and a portion of the lower metal pattern 252 are formed between the bottom end P1 and the top end P2 of the third lower interlayer insulating layer 215c.

[0088] A fourth lower interlayer insulating layer 215d is formed on the third lower interlayer insulating layer 215c. The remaining portion of the lower bonding metal 272c is formed in the fourth lower interlayer insulating layer 215d. Also, the remaining portion of the lower metal pattern 252 is formed in the fourth lower interlayer insulating layer 215d. More specifically, the remaining portion of the lower bonding metal 272c and the remaining portion of the lower metal pattern 252 are formed between the bottom end P2 and the top end C_F of the fourth lower interlayer insulating layer 215d.

[0089] That is, the lower metal layer 250c is formed inside the second lower interlayer insulating layer 215b and the third lower interlayer insulating layer 215c, the lower bonding metal 272c is formed inside the second lower interlayer insulating layer 215b, the third lower interlayer insulating layer 215c, and the fourth lower interlayer insulating layer 215d, and the lower metal pattern 252 is formed inside the third lower interlayer insulating layer 215c and the fourth lower interlayer insulating layer 215d.

[0090] The manufacturing method for the R3 region of the nonvolatile memory device according to the embodiment is the same as that described above with reference to FIGS. 5 to 9, and therefore the description thereof will be omitted.

[0091] Referring again to FIG. 1, in the word line bonding region WLBA, the word lines 330 extend in a first direction x parallel to the top surface of the second substrate 310 and are connected to a plurality of cell contact plugs (341-347; 340). The word lines 330 and the cell contact plugs 340 are connected to each other through pads formed by extending at least some of the word lines 330 at different lengths along the first direction x. A first metal layer 350b and a second metal layer 360b are sequentially connected to the top of the cell contact plugs 340 connected to the word lines 330. The cell contact plugs 340 are connected to the peripheral circuit region PERI in the word line bonding region WLBA via upper bonding metals (371b, 372b) of the cell region CELL and lower bonding metals (271b, 272b) of the peripheral circuit region PERI.

[0092] The cell contact plug 340 is electrically connected to a circuit element 220b that provides a row decoder 394 in the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 220b that provides the row decoder 394 is different from the operating voltage of the circuit element 220c that provides the page buffer 393. For example, the operating voltage of the circuit element 220c that provides the page buffer 393 is higher than the operating voltage of the circuit element 220b that provides the row decoder 394.

[0093] In the nonvolatile memory device 300a according to this embodiment, a lower metal pattern 273a having the same shape as the upper metal pattern 372a of the cell region CELL is formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a separate contact in the peripheral circuit region PERI. Similarly, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the upper metal layer of the cell region CELL in the external pad bonding region PA, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0094] Lower bonding metals 271b and 272b are formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b in the peripheral circuit region PERI are electrically connected to the upper bonding metals 371b and 372b in the cell region CELL by bonding.

[0095] In addition, in the bit line bonding region BLBA, an upper metal pattern 392 having the same shape as the lower metal pattern 252 in the peripheral circuit region PERI is formed in the uppermost metal layer of the cell region CELL in correspondence with the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI. No contact is formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.

[0096] FIG. 14 is an exemplary diagram illustrating another nonvolatile memory device according to an embodiment.

[0097] 14, the nonvolatile memory device 300b according to this embodiment further includes an upper metal layer 370 in the cell region CELL, unlike the nonvolatile memory device 300a according to the embodiment of FIG. 1. The number and shape of the upper metal layer 370 are not limited thereto.

[0098] In the cell region CELL according to this embodiment, the size of the cell region CELL can be reduced by merging metal layers to form a single wiring, thereby reducing process costs. For example, assuming that a third metal layer (not shown) is formed on top of the second metal layers (360a, 360b, 360c) of the cell region CELL, if the third metal layer is formed on top of the second metal layers (360a, 360b, 360c), the thickness of the cell region CELL in the third direction z will be thicker than the thickness shown in this drawing. However, by merging the third metal layer through the upper metal layer 370, the third metal layer can be eliminated.

[0099] Here, each upper metal layer 370 is disposed between a plurality of upper bonding metals. For example, upper metal layer 370 is disposed between a plurality of upper bonding metals (372b, 372c). That is, by merging one metal layer into a metal layer (e.g., upper metal layer 370), the size of the cell region CELL can be reduced, and the process cost can also be reduced.

[0100] However, if the top end in the third direction z of a metal layer (e.g., upper metal layer 370) that combines one or more metal layers is located at the same height as the height at which the cell region CELL and the peripheral circuit region PERI meet, a dishing phenomenon occurs, reducing the connection reliability between the top end of the cell region CELL and the peripheral circuit region PERI.

[0101] Therefore, in the nonvolatile memory device 300b according to this embodiment, the top end in the third direction z of a metal layer (e.g., upper metal layer 370) formed by combining one or more metal layers is formed lower than the height at which the cell region CELL and the peripheral circuit region PERI meet. This prevents dishing that occurs when a planarization process is performed on metal (e.g., a plurality of upper bonding metals 372b, 372c) disposed at the interface between the cell region CELL and the peripheral circuit region PERI. This maintains the reliability of the connection between the top end of the cell region CELL and the peripheral circuit region PERI, and reduces the size of the cell region CELL, thereby reducing process costs.

[0102] Hereinafter, a structure of a cell region CELL of a nonvolatile memory device according to an embodiment will be described in detail with reference to FIG.

[0103] Fig. 15 is an exemplary enlarged view of the R4 region in Fig. 14. For reference, the description of the R4 region of the cell region CELL can of course also be applied to other parts of the cell region CELL.

[0104] 15, the top end P2' of the upper metal layer 370 in the third direction z is formed lower than the top end C_F of the upper bonding metals 372b and 372c in the third direction z. For reference, the height criteria will be described assuming that the contact surface C_F between the cell region and the peripheral circuit region is the highest in the third direction z. The top end C_F of the upper bonding metals 372b and 372c in the third direction z is the contact surface between the upper bonding metals 372b and 372c and the lower bonding metals 272b and 272c. In other words, the contact surface C_F is the bonding surface where the cell region CELL and the peripheral circuit region PERI are bonded.

[0105] The upper interlayer insulating layer 315 includes a plurality of upper interlayer insulating layers. A first upper interlayer insulating layer 315a is formed on the second substrate 310 of FIG. 14. First metal layers (350b, 350c) and second metal layers (360b, 360c) are formed in the first upper interlayer insulating layer 315a. The first upper interlayer insulating layer 315a may include a plurality of first upper interlayer insulating layers.

[0106] A second upper interlayer insulating layer 315b is formed on the first upper interlayer insulating layer 315a. Upper bonding metals (371b, 371c) are formed in the second upper interlayer insulating layer 315b. Also, a via portion of the upper metal layer 370 is formed in the second upper interlayer insulating layer 315b. More specifically, the upper bonding metals (371b, 371c) and the via portion of the upper metal layer 370 are formed between the bottom end P0' and the top end P1' of the second upper interlayer insulating layer 315b.

[0107] A third upper interlayer insulating layer 315c is formed on the second upper interlayer insulating layer 315b. A pad region of the upper metal layer 370 is formed in the third upper interlayer insulating layer 315c. Also, at least a portion of each of the upper bonding metals (372b, 372c) is formed in the third upper interlayer insulating layer 315c. More specifically, at least a portion of the upper bonding metals (372b, 372c) and a pad portion of the upper metal layer 370 are formed between the lowest end P1' and the highest end P2' of the third upper interlayer insulating layer 315c.

[0108] A fourth upper interlayer insulating layer 315d is formed on the third upper interlayer insulating layer 315c. Remaining portions of the upper bonding metals (372b, 372c) are formed in the fourth upper interlayer insulating layer 315d. More specifically, the remaining portions of the upper bonding metals (372b, 372c) are formed between the bottom end P2' and the top end C_F of the fourth upper interlayer insulating layers (372b, 372c).

[0109] That is, the upper metal layer 370 is formed inside the second upper interlayer insulating layer 315b and the third upper interlayer insulating layer 315c, and the upper bonding metals (372b, 372c) are formed inside the third upper interlayer insulating layer 315c and the fourth upper interlayer insulating layer 315d.

[0110] As a result, the upper metal layer 370 is disposed between the plurality of upper bonding metals 372b, 372c and is not exposed to the bonding surface C_F. The method for manufacturing the cell region CELL of the nonvolatile memory device 300b according to this embodiment is the same as that described above with reference to FIGS. 5 to 9, and therefore, a description thereof will be omitted.

[0111] FIG. 16 is an exemplary diagram illustrating another nonvolatile memory device according to an embodiment.

[0112] 16, unlike the nonvolatile memory device 300a according to the embodiment of FIG. 1, another nonvolatile memory device 300c according to this embodiment of FIG. 16 does not include the first I / O contact plug 203 and the first I / O pad 205. The rest of the description is the same as that of FIG. 1, so a description thereof will be omitted.

[0113] FIG. 17 is an exemplary block diagram illustrating a nonvolatile memory system including a nonvolatile memory device according to an embodiment.

[0114] 17, a nonvolatile memory system 1000 according to this embodiment includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The nonvolatile memory system 1000 is a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the nonvolatile memory system 1000 is a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more nonvolatile memory devices 1100.

[0115] The semiconductor device 1100 is a nonvolatile memory device, such as the nonvolatile memory device according to the embodiments described above with reference to FIGS. 1 to 16. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F is disposed adjacent to the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0116] In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to a common source line CSL, upper transistors (UT1, UT2) adjacent to a bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiment.

[0117] In one embodiment, the upper transistors (UT1, UT2) comprise string select transistors, and the lower transistors (LT1, LT2) comprise ground select transistors. The lower gate lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the upper gate lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0118] In one embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 is used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0119] The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via first connecting lines 1115 that extend from the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via second connecting lines 1125 that extend from the first structure 110F to the second structure 1100S.

[0120] The first structure 1100F and the second structure 1100S of the semiconductor device 1100 according to this embodiment include a layer including bonding metal that connects them to each other. By merging other wirings into the layer including bonding metal and wiring them, the size of each of the first structure 1100F and the second structure 1100S can be reduced, thereby reducing the process cost. In this case, unlike the nonvolatile memory devices according to the embodiments described above with reference to FIGS. 1 to 16, the merged wirings are not exposed on the surfaces where the first structure 1100F and the second structure 1100S are connected, so the connection reliability between the first structure 1100F and the second structure 1100S is not reduced.

[0121] In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform control operations on at least one selected memory cell transistor of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending to the second structure 1100S within the first structure 1100F.

[0122] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. According to one embodiment, the non-volatile memory system 1000 includes multiple semiconductor devices 1100, where the controller 1200 controls the multiple semiconductor devices 1100.

[0123] The processor 1210 controls the overall operation of the nonvolatile memory system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. are transferred via the NAND interface 1221. The host interface 1230 provides a communication function between the nonvolatile memory system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0124] FIG. 18 is an exemplary perspective view illustrating a nonvolatile memory system including a nonvolatile memory device according to an embodiment.

[0125] 18, a nonvolatile memory system 2000 according to this embodiment includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0126] The main board 2001 includes a connector 2006 having a plurality of pins for coupling with an external host. The number and arrangement of the pins of the connector 2006 vary depending on the communication interface between the nonvolatile memory system 2000 and the external host. In one embodiment, the nonvolatile memory system 2000 communicates with the external host via one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In one embodiment, the nonvolatile memory system 2000 operates using power supplied from the external host via the connector 2006. The nonvolatile memory system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0127] The controller 2002 writes data to or reads data from the semiconductor package 2003 to improve the operating speed of the non-volatile memory system 2000 .

[0128] The DRAM 2004 is a buffer memory for reducing the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the nonvolatile memory system 2000 also operates as a kind of cache memory, providing space for temporarily storing data during control operations for the semiconductor package 2003. When the nonvolatile memory system 2000 includes the DRAM 2004, the controller 2002 further includes a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0129] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) spaced apart from each other. Each of the first and second semiconductor packages (2003a, 2003b) includes a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0130] The package substrate 2100 is a printed circuit board including upper package pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. The input / output pads 2210 correspond to the input / output pads 1101 in FIG. 17. Each semiconductor chip 2200 includes a plurality of metal lines 3210 and a channel structure 3220. Each semiconductor chip 2200 includes a nonvolatile memory device as described above with reference to FIGS. 1 to 16.

[0131] In this embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the connecting structure 2400 using a bonding wire method.

[0132] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. In another embodiment, the controller 2002 and the semiconductor chip 2200 are mounted on the main substrate 2001 and a separate interposer substrate, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0133] FIG. 19 is an exemplary cross-sectional view illustrating a region cut along II' of the nonvolatile memory package of FIG. 18 including a nonvolatile memory device according to an embodiment.

[0134] Referring to FIG. 19, in the semiconductor package 2003a, each of the semiconductor chips 2200a includes a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 by a wafer bonding method.

[0135] The first structure 4100 includes a peripheral circuit region including peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 includes a common source line 4205, a plurality of metal lines 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and an isolation structure 4230 that penetrate the plurality of metal lines 4210, and an upper bonding metal 4250 that is electrically connected to the channel structure 4220 and the word lines (WL in FIG. 17 ) of the plurality of metal lines 4210. For example, the upper bonding metal 4250 is electrically connected to the channel structure 4220 and the word lines (WL in FIG. 17 ) via a bit line 4240 that is electrically connected to the channel structure 4220 and a first connecting wiring 1115 of FIG. 17 that is electrically connected to the word line (WL in FIG. 1 ). The lower bonding metal 4150 of the first structure 4100 and the upper bonding metal 4250 of the second structure 4200 are in contact with each other and bonded to each other. The bonded portions of the first bonding structure 4150 and the second bonding structure 4250 are made of, for example, copper (Cu).

[0136] In this case, as illustrated in the enlarged view of the portion where the first structure 4100 and the second structure 4200 are coupled, the merged wiring (e.g., the lower metal layer 250b of FIG. 2, the lower metal layer 250a of FIG. 12, the lower metal layer 250c of FIG. 13, or the upper metal layer 370 of FIG. 15) according to this embodiment is not exposed on the surface where the first structure 4100 and the second structure 4200 are coupled. This prevents a decrease in the coupling reliability between the first structure 4100 and the second structure 4200, and reduces the size of the first structure 4100 and / or the second structure 4200, thereby reducing the process cost. Each of the semiconductor chips 2200a further includes an input / output pad 2210 and an input / output connecting wiring 4265 below the input / output pad 2210. The input / output connecting wiring 4265 is electrically connected to some of the metal lines 4210.

[0137] The semiconductor chips 2200a are electrically connected to each other by bonding wire-type connection structures 2400. However, in one embodiment, semiconductor chips within a single semiconductor package, such as the semiconductor chip 2200a, may be electrically connected to each other by connection structures including through-silicon vias (TSVs).

[0138] FIG. 20 is an exemplary cross-sectional view illustrating a region cut along II' of the nonvolatile memory package of FIG. 18 including a nonvolatile memory device according to an embodiment.

[0139] 20, in a semiconductor package 2003b, semiconductor chips 2200b are aligned vertically to one another. Each of the semiconductor chips 2200b includes a semiconductor substrate 5010, a first structure 5100 formed below the semiconductor substrate 5010, and a second structure 5200 bonded to the first structure 5100 by wafer bonding below the first structure 5100.

[0140] The first structure 5100 includes a peripheral circuit region including peripheral wiring 5110 and a first junction structure 5150. The second structure 5200 includes a common source line 5205, a plurality of metal lines 5210 between the common source line 5205 and the first structure 5100, a channel structure 5220 and an isolation structure 5230 penetrating the plurality of metal lines 5210, and an upper bonding metal 5250 electrically coupled to the channel structure 5220 and the word lines (WL in FIG. 17 ) of the plurality of metal lines 5210. For example, the upper bonding metal 5250 is electrically coupled to the channel structure 5220 and the word lines (WL in FIG. 17 ) via a bit line 5240 electrically coupled to the channel structure 5220 and a first connecting wiring 1115 (see FIG. 17 ) electrically coupled to the word lines (WL in FIG. 17 ). The lower bonding metal 5150 of the first structure 5100 and the upper bonding metal 5250 of the second structure 5200 are in contact with each other and bonded to each other. The bonded portions of the first and second bonding structures 5150 and 5250 are made of, for example, copper (Cu).

[0141] In this case, as illustrated in the enlarged view of the portion where the first structure 5100 and the second structure 5200 are coupled, the merged wiring (e.g., the lower metal layer 250b of FIG. 2, the lower metal layer 250a of FIG. 12, the lower metal layer 250c of FIG. 13, or the upper metal layer 370 of FIG. 15) according to this embodiment is not exposed on the surface where the first structure 5100 and the second structure 5200 are coupled, so that the reliability of the connection between the first structure 5100 and the second structure 5200 is not reduced, and the size of the first structure 5100 and / or the second structure 5200 can be reduced, thereby reducing the process cost. Each of the semiconductor chips 2200b further includes an input / output pad 2210 and an input / output connecting wiring 5265 below the input / output pad 2210. The input / output connecting wiring 5265 is electrically connected to some of the metal lines 5210.

[0142] The remaining semiconductor chips 2200b, excluding the topmost semiconductor chip, further include a rear insulating layer 5300 on the semiconductor substrate 5010, rear input / output pads 5320 on the rear insulating layer 5300, and through-electrode structures 5310 that penetrate the semiconductor substrate 5010 and the rear insulating layer 5300 to electrically connect the peripheral wiring 5110 of the first structure 5100 to the rear input / output pads 5320. Each through-electrode structure 5310 includes a through-electrode 5310a and an insulating spacer 5310b surrounding a side of the through-electrode 5310a. The semiconductor device 2003b further includes connecting structures 5400, such as conductive bumps, disposed below each of the semiconductor chips 2200b. The connecting structures 5400 electrically connect the semiconductor chips 2200b and electrically connect the semiconductor chips 2200b to the package substrate 2100. A layer of underfill material 5510 surrounds the sides of conductive bump 5400 .

[0143] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0144] 201, 301 Lower and upper insulating films 203, 303 First and second input / output contact plugs 205, 305 1st and 2nd input / output pads 210, 310 First and second substrates 215, 315 Upper and lower interlayer insulating layers 215a, 215b, 215c, 215d First to fourth lower interlayer insulating layers 220a, 220b, 220c Peripheral circuit elements 230a, 230b, 230c, 350a, 350b First metal layer 240a, 240b, 240c, 360a, 360b Second metal layer 250a, 250b, 250c Bottom metal layer 251 via part 252, 272a, 272b, 272c Lower bonding metal (lower metal pattern) 271a, 271b, 271c Lower bonding metal 273a Lower metal pattern 300a, 300b, 300c non-volatile memory devices 315a, 315b, 315c, 315d First to fourth upper interlayer insulating layers 320 common source line 330, 331-338 Word lines 340, 341~347 Cell contact plug 350c 1st metal layer (bit line contact) 360c 2nd metal layer (bit line) 370 Upper Metal Layer 371a, 371b, 371c Upper bonding metal 372a, 372b, 372c, 392 Upper bonding metal (upper metal pattern) 380 Common source line contact plug 390 Channel Layer 391 Buried insulating layer 393 page buffers 394 Low Decoder 397 Data Storage Layer 397a Tunnel insulating film 397b Charge storage film 397c Blocking insulating film 397d Gate insulating film 1000, 2000 Non-volatile memory system 1100 Semiconductor devices 1100F, 1100S 1st and 2nd structures 1101, 2210 Input / Output Pads 1110 decoder circuit 1115, 1125 1st and 2nd connection wiring 1120 page buffers 1130 Logic Circuit 1135, 4265 input / output connection wiring 1200, 2002 controller 1210 processor 1220 NAND controller 1221 NAND interface 1230 host interface 2001 Main board 2003 Semiconductor Package 2003a, 2003b First and second semiconductor packages 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 package substrate 2130 Package top pad 2200, 2200a, 2200b semiconductor chips 2300 Adhesive layer 2400 Connected structures 2500 molding layer 3210, 4210, 5210 metal wire 3220, 4220, 5220 channel structures 4010, 5010 semiconductor substrate 4100, 5100 1st structure 4200, 5200 2nd structure 4110, 5110 peripheral wiring 4150, 5150 Lower bonding metal (first bonding structure) 4250 Second joint structure 4205, 5205 common source line 4230, 5230 Separation structure 4240, 5240 bit lines 4250, 5250 Upper bonding metal (second bonding structure) 5265 Input / output connection wiring 5300 Rear insulation layer 5310 Through electrode structure 5310a Through electrode 5310b Insulating Spacer 5320 Rear I / O pad 5400 Connecting structure (conductive bump) 5510 Underfill material layer BL bit line BLBA Bit Line Bonding Area CELL Cell area CH Channel structure CSL Common Source Line CSTR Memory Cell String LL1, LL2 1st and 2nd gate lower lines LT1, LT2 lower transistors MCT memory cell transistor PA External Pad Bonding Area PERI Peripheral circuit area UL1, UL2 1st and 2nd gate upper lines UT1, UT2 upper transistors WL Word Line WLBA Word Line Bonding Area

Claims

1. a first lower interlayer insulating layer and a second lower interlayer insulating layer stacked in order in a first direction; a lower metal layer included in the first lower interlayer insulating layer; a plurality of lower bonding metals included in the first lower interlayer insulating layer and the second lower interlayer insulating layer, the lower bonding metals being spaced apart from each other in a second direction perpendicular to the first direction; a top end of the lower metal layer in the first direction is lower than top ends of the plurality of lower bonding metals in the first direction; the lower metal layer is disposed between the plurality of lower bonding metals, a bottom surface of the lower metal layer in the first direction and bottom surfaces of the plurality of lower bonding metals in the first direction are flush with each other; A nonvolatile memory device, characterized in that an upper surface of the lower metal layer in the first direction is disposed lower than upper surfaces of the plurality of lower bonding metals in the first direction.

2. 2. The nonvolatile memory device of claim 1, wherein the number of the lower metal layers disposed between the plurality of lower bonding metals is two or more.

3. 2. The nonvolatile memory device of claim 1, further comprising peripheral circuit elements electrically connected to the lower metal layer.

4. 4. The nonvolatile memory device of claim 3, wherein the peripheral circuit elements include a page buffer circuit.

5. an input / output contact plug electrically connected to the lower metal layer; an input / output pad electrically connected to the input / output contact plug; 4. The nonvolatile memory device of claim 3, wherein the input / output pads are electrically connected to the peripheral circuit elements.

6. 10. The nonvolatile memory device of claim 1, further comprising a plurality of circuit elements electrically connected to the lower metal layer.

7. a plurality of upper bonding metals disposed on the plurality of lower bonding metals and in contact with the uppermost ends of the plurality of lower bonding metals; an upper metal layer disposed between the plurality of upper bonding metals; a top of the upper metal layer is formed at the same height as tops of the plurality of upper bonding metals; The nonvolatile memory device of claim 1 , wherein the height of the bottom of the upper metal layer is higher than the bottom of the plurality of upper bonding metals.

8. a first upper interlayer insulating layer and a second upper interlayer insulating layer sequentially stacked on the plurality of lower bonding metals; the first upper interlayer insulating layer and the second upper interlayer insulating layer surround the upper bonding metal; The nonvolatile memory device of claim 7 , wherein the second upper interlayer insulating layer surrounds the upper metal layer.

9. a first substrate; a plurality of metal wires stacked in a first direction on the first substrate; a channel structure passing through the plurality of metal lines; a plurality of upper metal layers electrically connected to the plurality of metal lines and the channel structure; a plurality of upper bonding metals electrically connected to one or more of the upper metal layers; a first lower interlayer insulating layer and a second lower interlayer insulating layer stacked in sequence on the upper bonding metal; a plurality of lower bonding metals electrically connected to the upper bonding metals and included in the first lower interlayer insulating layer and the second lower interlayer insulating layer; a lower metal layer disposed between the plurality of lower bonding metals and electrically connected to a peripheral circuit element, the lower metal layer being included in the second lower interlayer insulating layer; an uppermost end of the lower metal layer in the first direction is lower than a height at which the lower bonding metals and the upper bonding metals contact each other; a bottom surface of the lower metal layer in the first direction and a bottom surface of the lower bonding metals in the first direction that are flush with each other;

10. 10. The nonvolatile memory device of claim 9, wherein the number of lower metal layers disposed between the plurality of lower bonding metals is two or more.

11. an input / output contact plug electrically connected to the lower metal layer; an input / output pad electrically connected to the input / output contact plug; 10. The nonvolatile memory device of claim 9, wherein the input / output pads are electrically connected to the peripheral circuit elements.

12. 10. The nonvolatile memory device of claim 9, further comprising a plurality of circuit elements electrically connected to the lower metal layer.

13. the lower metal layer is electrically connected to at least one of the lower bonding metals; 13. The nonvolatile memory device of claim 12, wherein the plurality of circuit elements switches at least one of the metal lines.

14. a lowermost portion of the upper metal layer is formed at the same height as a lowermost portion of the plurality of upper bonding metals; 10. The nonvolatile memory device of claim 9, wherein the height of the top of the upper metal layer is lower than the top of the plurality of upper bonding metals.

15. a first upper interlayer insulating layer and a second upper interlayer insulating layer that surround the plurality of upper bonding metals and are stacked in the first direction; The nonvolatile memory device of claim 14 , wherein the first upper interlayer insulating layer surrounds the upper metal layer.

16. The main board and a non-volatile memory device on the main board; a controller electrically connected to the nonvolatile memory device on the main board; The nonvolatile memory device is a first substrate; a lower metal layer disposed on the first substrate and spaced apart from the first substrate in a first direction; a plurality of lower bonding metals spaced apart from each other in a second direction perpendicular to the first direction, a top end of the lower metal layer in the first direction is lower than top ends of the plurality of lower bonding metals in the first direction; the lower metal layer is disposed between the plurality of lower bonding metals, a bottom surface of the lower metal layer in the first direction and bottom surfaces of the plurality of lower bonding metals in the first direction are flush with each other; A nonvolatile memory system, characterized in that an upper surface of the lower metal layer in the first direction is disposed lower than upper surfaces of the plurality of lower bonding metals in the first direction.

17. The nonvolatile memory device further includes a first lower interlayer insulating layer and a second lower interlayer insulating layer stacked in the first direction on the first substrate, the lower metal layer is disposed in the first lower interlayer insulating layer; 17. The nonvolatile memory system of claim 16, wherein the plurality of lower bonding metals are disposed within the first lower interlayer insulating layer and the second lower interlayer insulating layer.

18. The nonvolatile memory device is an upper bonding metal electrically connected to the plurality of lower bonding metals; a plurality of metal lines electrically connected to the upper bonding metal and stacked in the first direction; a channel structure electrically connected to the upper bonding metal and passing through the plurality of metal lines; 20. The nonvolatile memory system of claim 17, further comprising: a second substrate disposed on the plurality of metal lines and the channel structure and spaced apart from the first substrate in the first direction.

19. 18. The nonvolatile memory system of claim 17, wherein the number of the lower metal layers disposed between the plurality of lower bonding metals is two or more.

20. 20. The nonvolatile memory system of claim 17, further comprising peripheral circuit elements electrically connected to the lower metal layer.

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