Detection device

Abstract

Provided is a technology for detecting a neutron ray or an X-ray with low illuminance while reducing the pixel area of sensor pixels and maintaining a layout symmetry. This detection device has a plurality of photo sensors and signal read-out lines, and each of the plurality of photo sensors has a photodiode and an amplification circuit. The plurality of amplification circuits provided to the plurality of photo sensors are connected in series, the output of each of the plurality of photodiodes is connected to the input of each of the plurality of amplification circuits via a selective switch circuit, and the outputs of the plurality of amplification circuits are respectively connected to the signal read-out lines via read-out switch circuits.

Description

[Technical Field]

[0001] The present disclosure relates to a detection device, and is particularly applicable to a detection device that detects neutron rays, X-rays, and the like. [Background technology]

[0002] There is a radiographic imaging device that uses neutron beams to fluoroscopically image a subject. Such a radiographic imaging device includes a neutron source that emits neutron beams and a neutron detector that detects the neutron beams that have passed through the subject. JP 2011-133441 A proposes a neutron detector that detects neutron beams. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-133441 Summary of the Invention [Problem to be solved by the invention]

[0004] The following description is not publicly known, but has been considered by the present inventors.

[0005] According to the studies of the present inventors, a detection device for detecting neutron rays, X-rays, and the like may have a high-gain amplifier circuit amp built into each of multiple sensor pixels PX in a detection device 10r in order to sense low-intensity neutron rays or X-rays, as shown in Fig. 1. In Fig. 1, one sensor pixel PX includes one photodiode PD and three amplifier circuits amp connected in series. In this case, the circuit configuration of one sensor pixel PX becomes large, the pixel area of ​​one sensor pixel PX becomes large, and it is thought that the resolution will decrease.

[0006] Another method for reducing pixel size is to separate the four photodiodes (PD1-PD4) that make up multiple sensor pixels with transfer switches (TR1-TR4) and share one amplifier circuit amp with the four sensor pixels, as shown in pixel layout examples 2L1 and 2L2 in Figure 2. However, this method may result in a loss of layout symmetry between the multiple sensor pixels.

[0007] Furthermore, as shown in Figure 3, the load capacitances (ΔC1, ΔC2, ΔC3, ΔC4) of the sensor pixels (PD1-PD4) are not the same but different, so the high-gain amplifier circuit amp amplifies and outputs the difference in detection signal due to this load difference (ΔV = Q / ΔC). In other words, ΔV is amplified by the amplifier circuit amp, and is then amplified by the amplification factor A (A × ΔV), which can potentially result in fixed pattern noise.

[0008] An object of the present disclosure is to provide a technology for detecting low-intensity neutron rays and X-rays while reducing the pixel area of ​​the sensor pixels and maintaining layout symmetry.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A brief summary of representative aspects of this disclosure is as follows.

[0011] That is, the detection device according to one embodiment includes: a plurality of optical sensors; a signal readout line; Each of the plurality of optical sensors includes a photodiode and an amplifier circuit; the amplifier circuits provided in the optical sensors are connected in series; an output of each of the plurality of photodiodes is connected to an input of each of the plurality of amplifier circuits via a selection switch circuit; The outputs of the plurality of amplifier circuits are connected to the signal read lines via respective read switch circuits. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 10 is a diagram illustrating a detection device according to a comparative example. [Figure 2] FIG. 2 is a diagram illustrating an example of the layout of a sensor pixel. [Figure 3] FIG. 3 is a diagram illustrating a problem with the layout example of FIG. 2. [Figure 4] FIG. 2 is a conceptual diagram illustrating a pixel region of the detection device according to the embodiment. [Figure 5] FIG. 5 is a conceptual cross-sectional view of the detection device of FIG. 4. [Figure 6] 1 is a circuit diagram showing the overall configuration of a detection device according to an embodiment. [Figure 7] FIG. 4 is a diagram illustrating a first example of a readout operation of the detection device according to the embodiment. [Figure 8] FIG. 10 is a diagram illustrating a second example of the readout operation of the detection device according to the embodiment. [Figure 9] FIG. 10 is a circuit diagram showing the overall configuration of a detection device according to a first modified example. [Figure 10] FIG. 10 is a circuit diagram showing the overall configuration of a detection device according to a second modification. [Figure 11] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel of the detection device according to the embodiment. [Figure 12] FIG. 10 is a diagram illustrating the timing of a readout operation of the detection device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Each embodiment of the present disclosure will be described below with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings will be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate. [Example]

[0014] Fig. 4 is a conceptual diagram illustrating a pixel region of a detection device according to an embodiment, and Fig. 5 is a conceptual cross-sectional view of the detection device of Fig. 4.

[0015] As shown in FIG. 4, the pixel region 10G of the detection device 10 has a plurality of pixels PX (PXnm: n=1, 2, 3, 4, . . . , m=1, 2, 3, 4, . . . ) arranged in a matrix. The pixels PX are arranged in a matrix at equal intervals in the vertical and horizontal directions. A scintillator 20 is provided on the pixel region 10G so as to overlap the pixel region 10G. That is, as shown in FIG. 5, a scintillator layer 20S is provided on the substrate 10S on which the detection device 10 is formed so as to overlap the pixel region 10G. In this example, the plurality of pixels PX (PX11-PX43) are depicted in a 4-row x 3-column matrix configuration, but this is not limiting and may be an N-row x M-column matrix configuration. The pixels PX can be referred to as photosensors. The pixel region 10G can be referred to as a detection region.

[0016] Each of the plurality of pixels PX includes a photodiode PD as an optical sensor element (photodetection element) that detects neutron rays, X-rays, etc., an amplifier circuit amp, a first switch element SW1 as a selection switch circuit provided between the output of the photodiode PD and the input of the amplifier circuit amp, and a second switch element SW2 as a readout switch circuit provided between the output of the amplifier circuit amp and a column signal line cn (n=1, 2, 3, 4, . . .) that serves as a signal readout line.

[0017] Furthermore, in each column of pixels PX (e.g., PX11, PX21, PX31, and PX41), the multiple amplifier circuits arranged in the column direction are connected in series. That is, the output of the amplifier circuit amp11 of pixel PX11 is electrically connected to the input of the amplifier circuit amp21 of pixel PX21, the output of the amplifier circuit amp21 of pixel PX21 is electrically connected to the input of the amplifier circuit amp31 of pixel PX31, and the output of the amplifier circuit amp31 of pixel PX31 is electrically connected to the input of the amplifier circuit amp41 of pixel PX41. As illustrated in FIG. 11 , in the multiple amplifier circuits connected in series, the output of the amplifier circuit and the input of the amplifier circuit are connected in an AC manner via a capacitance element (CE). For example, the output of the amplifier circuit amp11 of pixel PX11 and the input of the amplifier circuit amp21 of pixel PX21 are electrically connected in an AC manner via the capacitance element CE. The capacitance element CE blocks (cuts) the DC component.

[0018] Therefore, the outputs of the photodiodes PD are connected to the inputs of the amplifier circuits amp via the selection switch circuits (SW1), and the outputs of the amplifier circuits amp are connected to the signal readout lines cn via the readout switch circuits (SW2).

[0019] The column signal lines cn (n=1, 2, 3, 4, . . . ) are selectively configured to be connected to the input of an output buffer circuit OB. A signal from the selected column signal line cn (n=1, 2, 3, 4, . . . ) is output as an output signal Dout by the output buffer circuit OB.

[0020] When neutrons are incident on the scintillator layer 20S, fluorescence is generated in the scintillator layer 20S and detected by the photodiode. For example, when the detection signal detected by the photodiode PD21 of pixel PX21 is amplified and output, the first switch element SW1 of pixel PX21 is turned on, and the detection signal detected by the photodiode PD21 is input to the input of the amplifier circuit amp21 and amplified. When the detection signal detected by the photodiode PD21 is amplified using three amplifier circuits, the second switch elements SW2 of pixels PX11, PX21, and PX31 are turned off, and only the second switch element SW2 of pixel PX41 is turned on. As a result, the detection signal detected by the photodiode PD21 is amplified using the three amplifier circuits, amp21, amp31, and amp41, and input to the output buffer circuit OB via the column signal line c1. The selection switch circuit (first switch element SW1) to be selected and the readout switch circuit (second switch element SW2) to be readout are configured to be positioned differently in the column direction.

[0021] That is, when reading out the output of a predetermined photodiode (PD21) in a predetermined photosensor (pixel PX21), the selection switch circuit (SW1) connected to the output of the predetermined photodiode (PD21) is turned on, and the readout switch circuit (SW2) connected to the output of the amplifier circuit (amp21) in the predetermined photosensor (pixel PX21) is turned off. Then, the readout switch circuit (SW2 of photosensor PX41) between the output of the amplifier circuit (amp41 of photosensor PX41) several stages downstream of the amplifier circuit (amp21) in the predetermined photosensor (pixel PX21) and the signal readout line (c1) is turned on.

[0022] According to the detection device 10 shown in FIG. 4, one or more of the following effects can be obtained.

[0023] 1) The number of elements required for one pixel is reduced, and the pixel area of ​​one pixel is reduced. This allows for improved resolution. Furthermore, the reduced load on one pixel allows for improved sensitivity. In other words, the pixel area of ​​one pixel PX can be reduced compared to the pixel configuration of Figure 1, so resolution can be maintained or improved without being reduced.

[0024] 2) Since pixels with similar configurations are arranged in a matrix, the pixel layout is highly symmetrical and fixed pattern noise does not occur. In other words, because layout symmetry is maintained between multiple pixels, the load capacitance of each pixel (PX11-PX44) can be made the same. Therefore, even if the detection signal is amplified by the high-gain amplifier circuit amp, the occurrence of fixed pattern noise can be prevented.

[0025] 3) By changing the drive, the number of stages of the amplifier circuit amp used for amplification can be switched between 1 stage, 2 stages, and 3 stages, thereby enabling the amplification rate to be switched.

[0026] FIG. 6 is a circuit diagram showing the overall configuration of the detection device according to the embodiment.

[0027] In the detection device 10 shown in Fig. 6, a plurality of pixels PX are arranged in a matrix configuration of 4 rows x 4 columns, for example. Each pixel PX has a configuration similar to that of Fig. 4, but the first switch element SW1 serving as a selection switch circuit and the second switch element SW2 serving as a readout switch circuit are depicted as N-channel MOSFETs. The source-drain path of the MOSFET of the first switch element SW1 is connected between the output of the photodiode PD and the input of the amplifier circuit amp. The source-drain path of the MOSFET of the second switch element SW2 is connected between the output of the amplifier circuit amp and a column signal line cn (n = 1, 2, 3, 4) serving as a signal readout line.

[0028] The gate of each first switch element SW1 of each pixel PX in the first row is connected to gate line g1, the gate of each first switch element SW1 of each pixel PX in the second row is connected to gate line g2, the gate of each first switch element SW1 of each pixel PX in the third row is connected to gate line g3, and the gate of each first switch element SW1 of each pixel PX in the fourth row is connected to gate line g4.

[0029] The gate of each second switch element SW2 of each pixel PX in the first row is connected to a row selection line r1, the gate of each second switch element SW2 of each pixel PX in the second row is connected to a row selection line r2, the gate of each second switch element SW2 of each pixel PX in the third row is connected to a row selection line r3, and the gate of each second switch element SW2 of each pixel PX in the fourth row is connected to a row selection line r4.

[0030] The source-drain paths of the N-channel MOSFETs of the column switch circuits CSW1-CSW4 are connected between the plurality of column signal lines c1-c4 and the input of the output buffer circuit OB.

[0031] The gate lines g1-g4 are connected to a transfer decoder TRDEC serving as a first driving circuit. Therefore, the transfer decoder TRDEC is connected to the gates of a plurality of selection switch circuits (first switch elements SW1) arranged in the row direction. The transfer decoder TRDEC has transfer selection drivers TRSEL1, TRSEL2, TRSEL3, and TRSEL4 connected to the gate lines g1, g2, g3, and g4, respectively. The transfer decoder TRDEC selects one of the gate lines g1-g4 (high level) based on an input transfer selection signal.

[0032] The row select lines r1-r4 are connected to a row decoder RDEC serving as a second drive circuit. Therefore, the row decoder RDEC is connected to the gates of the read switch circuits (second switch elements SW2) arranged in the row direction. The row decoder RDEC has row select drivers RSEL1, RSEL2, RSEL3, and RSEL4 connected to the row select lines r1, r2, r3, and r4, respectively. The row decoder RDEC selects one of the row select lines r1-r4 (high level) based on an input row select signal.

[0033] The gates of the N-channel MOSFETs of the column switch circuits CSW1-CSW4 are connected to a column decoder CDEC, which is a selection switch circuit. The column decoder CDEC has column selection drivers CSEL1, CSEL2, CSEL3, and CSEL4 connected to the gates of the N-channel MOSFETs (CSW1-CSW4), respectively. The column decoder CDEC selects (turns on) one of the column switch circuits CSW1-CSW4 based on an input column selection signal.

[0034] The detection area 10G, in which multiple pixels PX are arranged in a matrix, has a rectangular shape when viewed from above, and has a first side 1S, a second side 2S opposite the first side 1S, a third side between the first side 1S and the second side 2S, and a fourth side 4S opposite the third side 3S.

[0035] The first drive circuit (transfer decoder TRDEC) is arranged in a peripheral area SAR1 outside the detection area 10G along a first side 1S of the detection area 10G.

[0036] The second drive circuit (row decoder RDEC) is arranged in the peripheral area SAR2 outside the detection area 10G along a second side 2S of the detection area 10 opposite to the first side 1S.

[0037] A selection switch circuit (column decoder CDEC) that selects a specific signal readout line from among the multiple signal readout lines (column signal lines cn) is arranged in the peripheral area SAR3 outside the detection area 10G along the arrangement direction of the multiple signal readout lines (column signal lines cn).

[0038] FIG. 7 is a diagram illustrating a first example of a readout operation of a detection device according to an embodiment. FIG. 7 illustrates an example of a readout operation in which the output of a photodiode PD is amplified by three amplifier circuits amp and input to an output buffer circuit OB. In this example, the transfer selection driver TRSEL1 selects the gate line g1 (high level), the row selection driver RSEL3 selects the row selection line r3 (high level), and the column selection driver CSEL2 selects the column switch circuit CSW2 (on state). As a result, the first switch element SW1, the second switch element SW2, and the column switch circuit CSW2, indicated by circles, are selected (on state), and the output of the photodiode PD12 is amplified by the three amplifier circuits amp and supplied to the input of the output buffer circuit OB. Therefore, the column positions of the selected selection switch circuit (the first switch element SW1 turned on) and the readout switch circuit (the second switch element SW2 turned on) are different.

[0039] 8 is a diagram illustrating a second example of a readout operation of the detection device according to the embodiment. FIG. 8 illustrates an example of a readout operation in which the output of the photodiode PD is amplified by two amplifier circuits amp and input to the output buffer circuit OB. In this example, the transfer selection driver TRSEL1 selects the gate line g1 (high level), the row selection driver RSEL2 selects the row selection line r2 (high level), and the column selection driver CSEL2 selects the column switch circuit CSW2 (on state). As a result, the first switch element SW1, the second switch element SW2, and the column switch circuit CSW2, indicated by circles, are selected (on state), and the output of the photodiode PD12 is amplified by the two amplifier circuits amp and supplied to the input of the output buffer circuit OB.

[0040] Similarly, in the case of a read operation in which the output of the photodiode PD is amplified by a single amplifier circuit amp and input to the output buffer circuit OB, in Fig. 8, instead of the row selection driver RSEL2, the row selection driver RSEL1 selects the row selection line r1 (high level), the transfer selection driver TRSEL1 selects the gate line g1 (high level), and the column selection driver CSEL2 selects the column switch circuit CSW2 (on state).

[0041] FIG. 9 is a circuit diagram showing the overall configuration of a detection device according to Modification 1. In the configuration of the detection device 10 shown in FIG. 6, when the output of the photodiodes PD is amplified by three amplifier circuits amp, the output of the photodiodes PD of the pixels PX connected to the lower two rows cannot be read out. In such a case, as shown in FIG. 9, in Modification 1, the lower two rows are designated as non-sense operation regions NonS, which function as amplification stages for the output signals of the photodiodes PD in the upper rows. In the non-sense operation regions NonS, dummy elements (dummy photodiodes) DPD are placed to maintain the symmetry of the layout of the pixels PX and to apply a uniform load to each amplifier circuit. Therefore, the transfer selection drivers TRSEL3 and TRSEL4 are configured to output a fixed low level to the gate lines g3 and g4 in order to deselect the gate lines g3 and g4.

[0042] In this example, the transfer select driver TRSEL2 selects the gate line g2 (high level), the row select driver RSEL4 selects the row select line r4 (high level), and the column select driver CSEL1 selects the column switch circuit CSW1 (on state). As a result, the first switch element SW1, the second switch element SW2, and the column switch circuit CSW2, indicated by circles, are selected (on state), and the output of the photodiode PD21 is amplified by the three amplifier circuits amp and supplied to the input of the output buffer circuit OB. Of the three amplifier circuits amp, the bottom two amplifier circuits amp are amplifier circuits in the non-sense operation region NonS.

[0043] In this example, the photodiodes of multiple pixels in two rows (the bottom two rows) closest to the selection switch circuit (column decoder CDEC) are dummy elements DPD, but the photodiodes of multiple pixels in at least one row (the bottom row) closest to the selection switch circuit (column decoder CDEC) may also be dummy elements DPD. When the photodiodes of multiple pixels in the bottom row are dummy elements DPD, the photodiodes PD in the second row counting from the bottom are used, and therefore are amplified by two amplifier circuits.

[0044] Fig. 10 is a circuit diagram showing the overall configuration of a detection device according to Modification 2. In Fig. 9, the bottom two rows are designated as non-sense operation regions NonS, resulting in wasted area on the substrate of the detection device 10. In Modification 2, wiring LA is added so that the output of the lowest amplifier circuit amp is connected to, for example, the input of the highest amplifier circuit amp. Therefore, the outputs of the photodiodes PD of the pixels PX connected to the bottom two rows can also be amplified and read out by the three amplifier circuits amp.

[0045] In this example, the transfer selection driver TRSEL4 selects the gate line g4 (high level), the row selection driver RSEL2 selects the row selection line r2 (high level), and the column selection driver CSEL3 selects the column switch circuit CSW3 (on state). As a result, the first switch element SW1, the second switch element SW2, and the column switch circuit CSW2, indicated by circles, are selected (on state), and the output of the photodiode PD43 is amplified by the three amplifier circuits amp and supplied to the input of the output buffer circuit OB. Of the three amplifier circuits amp, the upper (upstream) two amplifier circuits amp are used.

[0046] That is, in the column direction, the output of the amplifier circuit amp in the bottom row is connected to the input of the amplifier circuit amp in the top row. When detection is performed by the photodiode PD in the pixel PX in the bottom row, the output of the photodiode PD in the pixel PX in the bottom row is amplified using the amplifier circuit amp in the top row as well.

[0047] FIG. 11 is a circuit diagram showing a detailed configuration example of a pixel of a detection device according to an embodiment. FIG. 12 is a diagram illustrating the timing of a readout operation of a detection device according to an embodiment. FIG. 11 illustrates detailed circuit configurations of three pixels PX11, PX21, and PX31 as an example. Since the three pixels PX11, PX21, and PX31 have the same circuit configuration, the circuit configuration of pixel PX11 will be described as a representative. PVSS is the ground potential of photodiode PD11.

[0048] In pixel PX11, amplifier circuit amp11 is formed by an inverter circuit configured with PMOS transistor PM1 and NMOS transistor NM1. The source-drain path of PMOS transistor PM1 and the source-drain path of NMOS transistor NM1 are directly connected between the power supply potential VDD and the ground potential VSS. The input of amplifier circuit amp11 is the shared gate electrode of PMOS transistor PM1 and NMOS transistor NM1, and the output of amplifier circuit amp11 is the shared drain electrode of PMOS transistor PM1 and NMOS transistor NM1.

[0049] The first switch element SW1 is composed of two NMOS transistors NM3 and NM4. The gate electrodes of the NMOS transistors NM3 and NM4 are connected to the gate line g1. The source-drain path of the NMOS transistor NM3 and the source-drain path of the NMOS transistor NM4 are connected directly between the output of the photodiode PD11 and the input of the amplifier circuit amp11.

[0050] The second switch element SW2 is composed of two NMOS transistors NM5 and NM6. The gate electrodes of the NMOS transistors NM5 and NM6 are connected to the row selection line r1. The source-drain path of the NMOS transistor NM5 and the source-drain path of the NMOS transistor NM6 are connected directly between the output of the amplifier circuit amp11 and the column signal line c1.

[0051] The third switch element SW3, which is a reset circuit, is composed of two NMOS transistors NM7 and NM8. The gate electrodes of the NMOS transistors NM7 and NM8 are connected to a reset signal line rs1. The source-drain path of the NMOS transistor NM7 and the source-drain path of the NMOS transistor NM8 are directly connected between the input and output of the amplifier circuit amp11. When the third switch element SW3 is turned on, the input and output of the amplifier circuit amp11 are electrically connected and the potential thereof is reset. In the pixels PX21 and PX31, the gate electrodes of the NMOS transistors NM7 and NM8 are similarly connected to reset signal lines rs2 and rs3, respectively.

[0052] The capacitance element CE is connected between the output of the amplifier circuit amp11 and the input of the amplifier circuit amp21 of the pixel PX21. Similarly, the capacitance element CE is connected between the output of the amplifier circuit amp21 and the input of the amplifier circuit amp31 of the pixel PX31.

[0053] Next, the readout operation of the photodiode PD of the pixel PX will be described with reference to FIG.

[0054] 12, the period from time t1 to time t2 is one frame, and a readout operation of photodiode PD11 is performed during one frame from time t1 to time t2. A readout operation of photodiode PD21 is performed during one frame from time t2 to time t3, a readout operation of photodiode PD31 is performed during one frame from time t3 to time t4, and a readout operation of photodiode PD41 is performed during one frame from time t4 to time t5.

[0055] As a representative example, the readout operation of photodiode PD11 during one frame period from time t1 to time t2 will be described. One frame period includes an Amp reset period in which consecutive amplifier circuits amp11, amp21, amp31, amp41, etc. in the column direction are simultaneously reset, a PD reset period, exposure period, and readout period for photodiode PD11, and a reset and signal readout period for column signal line c1.

[0056] During the Amp reset period, the reset signals rst1, rst2, and rst3 on the reset signal lines rs1, rs2, and rs3 are changed from low to high, turning on the third switch elements SW3 of the pixels PX11, PX21, and PX31. The reset signal rst4 on the reset signal line rs4 is kept high for one frame (the amplifier circuit amp41 maintains the reset state). This electrically connects the inputs and outputs of the amplifier circuits (amp11, amp21, amp31, amp41, ...) arranged consecutively in the column direction, resetting their potentials. The reset signal rst1 transitions from high to low, and the reset signal rst2 transitions to low after the reset signal rst1 transitions to low. The reset signal rst3 transitions to low after the reset signal rst2 transitions to low. In other words, the reset period of the amplifier circuits located lower in the column direction is longer than the reset period of the amplifier circuits located upper in the column direction. This ensures that the three amplifier circuits are reset. In this example, when three amplifier circuits (amp21, amp31, amp41) are used for amplification, the three amplifier circuits (amp21, amp31, amp41) are reset by reset signals rst2, rst3, rst4 during the reset period. Furthermore, the amplifier circuit (amp11) located above the three amplifier circuits (amp21, amp31, amp41) and the amplifier circuit (amp51) located below the three amplifier circuits (amp21, amp31, amp41) are also continuously reset by reset signals rst1 and rst5 during one frame period. This reduces the influence of the amplifier circuits (amp11, amp51) located above and below the three amplifier circuits (amp21, amp31, amp41) used for amplification when the three amplifier circuits (amp21, amp31, amp41) are performing amplification, thereby enabling accurate amplification of the output signal from the photodiode (PD21).

[0057] Meanwhile, in synchronization with the transition of the reset signal rst1 from low to high, the gate signal gate1 of the gate line g1 and the readout signal read3 of the row selection line r3 transition from low to high. This initiates a PD reset period for the photodiode PD11. During the PD reset period, the first switch element SW1 of pixel PX11 is turned on. Furthermore, the second switch element SW2 in pixel PX3 is turned on, resetting the potential of the column signal line c1.

[0058] When the PD reset period ends, the gate signal gate1 transitions from high to low, starting the exposure period for photodiode PD11. When the exposure period ends, the gate signal gate1 transitions from low to high, starting the readout period for photodiode PD11. At this time, the reset signals rst1, rst2, and rst3 are low, so the third switch elements SW3 of pixels PX11, PX21, and PX31 are off. The first switch element SW1 of pixel PX11 is on, and the second switch element SW2 in pixel PX3 is on. Therefore, the output of photodiode PD11 is amplified by amplifier circuits amp11, amp21, and amp31 and read out to column signal line c1. When readout to column signal line c1 ends, the gate signal gate1 of gate line g1 and the readout signal read3 of row selection line r3 transition from high to low, ending one frame period.

[0059] Thereafter, similar operations are performed to read out the photodiode PD21 from time t2 to time t3, the photodiode PD31 from time t3 to time t4, and the photodiode PD41 from time t4 to time t5.

[0060] All detection devices that can be implemented by a person skilled in the art by appropriately modifying the design of the detection device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0061] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention. For example, to the above-described embodiments, a person skilled in the art may appropriately add, delete, or modify components, or add, omit, or change conditions of steps, and these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0062] Furthermore, other effects and advantages brought about by the aspects described in this embodiment that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention.

[0063] Various inventions can be formed by appropriately combining multiple components disclosed in the above embodiments. For example, some components may be omitted from all components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of symbols]

[0064] 10:Detection device 20: Scintillator PX: Pixel (light sensor) PD: Photodiode amp: amplifier circuit SW1: First switch element (selection switch circuit) SW2: Second switch element (read switch circuit) SW3: Third switch element (reset circuit) cn: Column signal line (signal readout line) OB: Output buffer circuit

Claims

1. a plurality of optical sensors; a signal readout line; Each of the plurality of optical sensors includes a photodiode and an amplifier circuit; the plurality of amplifier circuits provided in the plurality of optical sensors are connected in series, an output of each of the plurality of photodiodes is connected to an input of each of the plurality of amplifier circuits via a selection switch circuit; outputs of the plurality of amplifier circuits are connected to the signal readout lines via respective readout switch circuits; When reading out the output of a given photodiode in a given photosensor, the selection switch circuit connected to the output of the predetermined photodiode is turned on; the readout switch circuit connected to the output of the amplifier circuit in the predetermined optical sensor is turned off; The detection device, wherein the read switch circuit between the output of the amplifier circuit several stages ahead of the amplifier circuit in the predetermined optical sensor and the signal read line is turned on.

2. In claim 1, The detection device, wherein the plurality of optical sensors are arranged in a matrix at equal intervals in the vertical and horizontal directions.

3. In claim 1, The amplifier circuit an inverter circuit composed of a PMOS transistor and an NMOS transistor; a reset circuit electrically connecting the output and input of the inverter circuit.

4. A plurality of optical sensors; a signal readout line; Each of the plurality of optical sensors includes a photodiode and an amplifier circuit; the plurality of amplifier circuits provided in the plurality of optical sensors are connected in series, an output of each of the plurality of photodiodes is connected to an input of each of the plurality of amplifier circuits via a selection switch circuit; outputs of the plurality of amplifier circuits are connected to the signal readout lines via respective readout switch circuits; a first drive circuit; a second drive circuit; the plurality of optical sensors are arranged in a matrix; A plurality of the signal readout lines are provided, the first drive circuit is connected to gates of the plurality of selection switch circuits arranged in a row direction; the second drive circuit is connected to gates of the plurality of read switch circuits arranged in the row direction; A detection device, wherein the selection switch circuit to be selected and the readout switch circuit to be readout are located at different positions in the column direction.

5. In claim 4, a column switch circuit for selecting a predetermined signal readout line from among the plurality of signal readout lines; the plurality of optical sensors are disposed in a detection area; the first driving circuit is disposed in a peripheral region along a first side of the detection region; the second drive circuit is disposed in a peripheral region along a second side of the detection region opposite to the first side, the column switch circuit is arranged in a peripheral region of the detection region along an arrangement direction of the plurality of signal readout lines.

6. In claim 4, a column switch circuit for selecting a predetermined signal readout line from among the plurality of signal readout lines; The detection device, wherein the photodiodes of at least one row of photosensors closest to the column switch circuit are dummy elements.

7. In claim 4, The amplifier circuit an inverter circuit composed of a PMOS transistor and an NMOS transistor; a reset circuit electrically connecting the output and input of the inverter circuit.

8. In claim 7, The detection device, wherein the plurality of amplifier circuits consecutive in a column direction are reset simultaneously.

9. In claim 4, In the column direction, the output of the amplifier circuit in the bottom row is connected to the input of the amplifier circuit in the top row; A detection device in which, when detection is performed by the photodiodes in the photosensors in the bottom row, the outputs of the photodiodes are amplified using the amplifier circuits in the top row as well.

10. In claim 5, A detection device in which a scintillator overlaps the detection area.

11. In claim 4, The detection device, wherein the plurality of optical sensors are arranged in a matrix at equal intervals in the vertical and horizontal directions.

Images