Data storage device and method for generating a read threshold voltage

Abstract

To provide a data storage device, and a date storage system and method, capable of using a BER result to identify a memory page having the lowest reliability, and updating a Vth tracking parameter to reduce a BER of the page.SOLUTION: A data storage device 100 includes a nonvolatile memory controller 102 coupled with a nonvolatile memory that may be configured of one or more nonvolatile memory dies 104. The nonvolatile memory controller 102 interfaces with a host system and transmits a command sequence for a read-out operation, a program operation and an erasure operation to the nonvolatile memory dies 104.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] Bit error rate (BER) estimation scan (BES) and valley search (VS) are operations that can be used to optimize read threshold voltages for specific word lines in the memory of a data storage device. One approach is to track read thresholds for groups of blocks. For example, blocks that are written at approximately the same time and temperature can be grouped into time and temperature (TT) groups. Read thresholds can be tracked for each time and temperature group, typically obtained on a representative word line from the blocks in the group. When the host performs a read operation, the read threshold associated with the time and temperature group corresponding to the read block can be used, with or without additional adaptation. [Brief explanation of the drawings]

[0002] [Figure 1A] FIG. 2 is a block diagram of a data storage device according to an embodiment. [Figure 1B] FIG. 2 is a block diagram illustrating a storage module of one embodiment. [Figure 1C] FIG. 1 is a block diagram illustrating a hierarchical storage system of one embodiment. [Figure 2A] 1B is a block diagram illustrating components of a controller of the data storage device illustrated in FIG. 1A according to one embodiment. [Figure 2B] 1B is a block diagram illustrating components of the data storage device illustrated in FIG. 1A, according to one embodiment. [Figure 3] FIG. 2 is a block diagram of a host and a data storage device of one embodiment. [Figure 4] 1 is a flowchart of a deep read exception handling (REH) method of one embodiment. [Figure 5]1 is a flowchart illustrating the use of a bit error rate (BER) estimation scan (BES) of one embodiment during a time tag (TT) update. [Figure 6] 1 is a graph of a BES with on-chip threshold voltage (Vt) tracking convergence from left to right after a particular program-erase count (PEC) cycle due to data retention (DR). [Figure 7] 10 is a graph of BES with right-to-left on-chip Vt tracking convergence after a certain number of program erase count (PEC) cycles due to DR. [Figure 8] 1 is a flowchart illustrating the use of a bit error rate (BER) estimation scan (BES) of one embodiment during a time tag (TT) update. DETAILED DESCRIPTION OF THE INVENTION

[0003] The following embodiments generally relate to data storage devices and methods for generating read threshold voltages (e.g., to improve memory reliability using BES and selective on-chip Vth tracking). In one embodiment, a data storage device is provided that includes a memory and one or more processors. The one or more processors are configured, individually or in combination, to obtain bit error rate (BER) estimation scan (BES) results from a page in the memory, update threshold voltage (Vth) tracking parameters using the BES results from the page in the memory, and use the updated Vth tracking parameters to read the page in the memory, where using the updated Vth tracking parameters to read the page in the memory reduces the BER of the page.

[0004] In another embodiment, a method is provided that is performed in a data storage device having a memory, the method including: performing a default read on a plurality of pages of the memory, performing a bit error rate (BER) estimation scan (BES) on each of the plurality of pages of the memory, updating threshold voltage (Vth) tracking parameters using the BER results for failed pages of the memory, adjusting read levels for the failed pages according to the updated Vth tracking parameters, and reading the failed pages using the adjusted read levels.

[0005] In yet another embodiment, a data storage device is provided comprising: a memory; and means for using a bit error rate (BER) to identify unreliable pages in the memory and updating an on-chip threshold voltage (Vth) tracking parameter to reduce the BER of the unreliable pages.

[0006] Other embodiments are possible, each of which can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the accompanying drawings.

[0007] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, hybrid drives, etc. Details of exemplary DSDs are provided below.

[0008] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in FIGS. 1A-1C. Note that these are merely examples and other implementations may be used. FIG. 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to FIG. 1A, the data storage device 100 in this example includes a controller 102 coupled to nonvolatile memory, which may be comprised of one or more nonvolatile memory dies 104. As used herein, the term die refers to a collection of nonvolatile memory cells and associated circuitry for managing the physical operation of these nonvolatile memory cells formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the nonvolatile memory dies 104. Also, as used herein, the phrases "in communication with" or "coupled to" can mean in direct communication with / coupled to one or more components, or indirect communication with / coupled through one or more components, which may or may not be shown or described herein. The communication / coupling can be wired or wireless.

[0009] The controller 102 (which may be a non-volatile memory controller (e.g., flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include one or more components, individually or in combination, configured to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, as shown in FIG. 2A , the controller 102 may include one or more processors 138, individually or in combination, configured to perform functions, including but not limited to those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-transitory memories 139 within the controller 102 and / or external to the controller 102 (e.g., in random access memory (RAM) 116 or read-only memory (ROM) 118). As another example, one or more components may include circuits such as, but not limited to, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0010] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device, using any suitable operating system. The non-volatile memory controller 102 can have a variety of functionality in addition to the specific functionality described herein. For example, the non-volatile memory controller can format the non-volatile memory to ensure that the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to replace future failed cells. Some of the spare cells can be used to hold firmware (and / or other metadata used for housekeeping and tracking) to operate the non-volatile memory controller and implement other features. In operation, when the host needs to read data from or write data to the non-volatile memory, the host can communicate with the non-volatile memory controller. If the host provides a logical address to which data is to be read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address within the non-volatile memory. The non-volatile memory controller may also perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing out particular blocks of memory that would otherwise be written to repeatedly) and garbage collection (moving only valid pages of data to a new block after the block becomes full so that the full block can be erased and reused).

[0011] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be single-time programmable, multiple-time programmable, or multi-time programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or may use other memory cell level technologies now known or later developed. The memory cells may also be fabricated in two or three dimensions.

[0012] The interface between the controller 102 and the non-volatile memory die 104 may be any suitable flash interface, such as toggle mode 200, 400, or 800. In one embodiment, data storage device 100 may be a card-based system, such as a secure digital (SD) or micro secure digital (micro-SD) card. In an alternative embodiment, data storage device 100 may be part of an embedded data storage device.

[0013] 1A, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104, although the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in FIGS. 1B and 1C), two, four, eight, or more memory channels may exist between the controller and the memory device, depending on the capabilities of the controller. In any of the embodiments described herein, even if a single channel is shown in the figures, more than a single channel may exist between the controller and the memory die.

[0014] 1B illustrates a storage module 200 including multiple non-volatile data storage devices 100. Accordingly, the storage module 200 may include a storage controller 202, which interfaces with a host and a data storage system 204, which includes multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a serial advanced technology attachment (SATA), a peripheral component interconnect express (PCIe) interface, a double-data-rate (DDR) interface, or a serial attached small scale compute interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), such as those found in server PCs or portable computing devices, such as laptop computers and tablet computers.

[0015] FIG. 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes multiple storage controllers 202, each controlling a respective data storage device 204. A host system 252 may access memory in the storage system 250 through a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in FIG. 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as might be found in a data center or other location where mass storage is needed.

[0016] Referring again to FIG. 2A , the controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls internal bus arbitration for the controller 102. The modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. While illustrated in FIG. 2A as being located separately from the controller 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the controller 102. In still other embodiments, portions of the RAM 116 and the ROM 118 may be located both within and outside the controller 102.

[0017] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with a host or next-level storage controller. The choice of host interface 120 type may depend on the type of memory being used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serially Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0018] The back-end module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, sent to the non-volatile memory die 104. A redundant array of independent drives (RAID) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data being written to the memory device 104. In some cases, the RAID module 128 may be part of the ECC engine 124. A memory interface 130 provides command sequences to and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110 .

[0019] Data storage device 100 also includes other separate components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that may interface with controller 102. In alternative embodiments, one or more of physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components not required in controller 102.

[0020] FIG. 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in two-dimensional and / or three-dimensional configurations. The non-volatile memory die 104 also includes a data cache 156 for caching data and address decoders 148 and 150. The peripheral circuitry 141, in this example, includes a state machine 152 that provides state information to the controller 102. The peripheral circuitry 141 may also include one or more components, individually or in combination, configured to perform certain functions, including, but not limited to, the functions described and illustrated in the flowcharts herein. 2B, memory die 104 may include one or more processors 168, individually or in combination, configured to execute computer-readable program code stored in one or more non-transitory memories 169, in memory array 142, or stored external to memory die 104. As another example, one or more components may include circuits such as, but not limited to, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0021] In addition to or instead of one or more processors 138 (or, more generally, components) in the controller 102 and one or more processors 168 (or, more generally, components) in the memory die 104, the data storage device 100 may include another set of one or more processors (or, more generally, components). Generally, one or more processors (or, more generally, components) in the data storage device 100, regardless of where they are located and how many are present, individually or in combination, may be configured to perform various functions, including, but not limited to, the functions described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be located in the controller 102, the memory device 104, and / or elsewhere in the data storage device 100. Also, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Furthermore, a means for performing a function may be implemented using a controller that includes one or more components (e.g., a processor or other component as described above).

[0022] Referring again to FIG. 2A , flash control layer 132 (referred to herein as flash translation layer (FTL)) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, is responsible for the internals of memory management, translating writes from the host into writes into memory 104. The FTL may be needed because memory 104 may have limited endurance, may only be written in multiples of pages, and / or may not be written to unless erased as a block. The FTL understands these potential limitations of memory 104, which may not be visible to the host. Thus, the FTL attempts to translate writes from the host into writes into memory 104.

[0023] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this manner, the FTL translates logical block addresses (LBAs) from the host into physical addresses within memory 104. The FTL may include other features, including, but not limited to, power-off recovery (so that the FTL's data structures can be recovered in the event of a sudden power loss) and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear in any particular block that may result in a greater chance of failure).

[0024] Referring again to the drawings, FIG. 3 is a block diagram of a host 300 and a data storage device 100 in one embodiment. The host 300 can take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host 300 (here, a computing device) in this embodiment comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in the one or more memories 340 configures the one or more processors 330 to perform the operations described herein as being performed by the host 300. Accordingly, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) executing on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the data storage device's memory 104.

[0025] As described above, bit error rate (BER) estimation scan (BES) and valley search (VS) are operations that can be used to optimize read voltage thresholds for specific word lines in the memory of a data storage device. One approach is to track read thresholds for groups of blocks. For example, blocks that are written at approximately the same time and temperature can be grouped into time and temperature (TT) groups. Read thresholds can be tracked for each time and temperature group, typically obtained on a representative word line from the blocks in the group. When the host performs a read operation, the read threshold associated with the time and temperature group corresponding to the read block is used, with or without additional adaptation.

[0026] The following paragraphs highlight the limitations of performing BES operations. For example, BES typically uses static read thresholds during the scan process. These fixed thresholds may not adapt to variations in memory cell characteristics, leading to suboptimal bit error rate (BER) estimation and error correction. BES has limitations in adapting to changing memory block behavior. Conventional BER estimation techniques, such as interpolation estimators, require multiple read senses to identify regions with low BER (using BES-7, 21 sense operations). However, these methods can be time-consuming and resource-intensive. Furthermore, they may not fully utilize the potential benefits of on-chip Vth tracking, which enables adaptive read thresholds based on the changing characteristics of memory cells. (As used herein, "on-chip" refers to performing operations within an integrated circuit (e.g., within a controller) within a data storage device.) Furthermore, without knowing the specific regions with high / low BER, low-density parity check (LDPC) error correction mechanisms may treat the entire memory device as having the same level of reliability. As a result, error correction algorithms may not be effectively utilized to increase the reliability of data storage. This increases the effort required by data storage device manufacturers to provide characterization results.

[0027] More specifically, some data storage devices define threshold regions for considering high and low BER. Based on these considerations, BES coarse, BES extended, and BES fine operations are performed. During each BES operation, the controller of the data storage device estimates the BER and determines which region of the BER the estimate corresponds to using a deep-learning accelerator (DLA) read to avoid read disturb (RD). These are static thresholds that do not change through degradation of the BiCS device.

[0028] 4 is a flowchart of a deep read exception handling (REH) method of one embodiment. As shown in FIG. 4, at the start of the method, the controller 102 of the data storage device 100 performs a first iteration of BES (410), which includes a metablock refresh (412), a coarse BES (414), and a BER estimation (416). If the BER estimation exceeds a certain threshold, the controller 102 performs an extended BES operation and performs another BER estimation (420, 422, 424). Depending on the result of that estimation, the controller performs either operation 432 or 470, as described below.

[0029] Returning to operation 416, if the BER estimate in operation 416 is below a certain threshold, the controller 102 performs a second iteration of BES (430), which includes a fine BES (432) and a BER estimate (434). If the BER estimate is greater than the threshold, the controller 102 enters SB1 mode (450, 452) and then SB2 mode (460, 462), after which an uncorrectable error correction code (UECC) error is reported (465). However, if the BER estimate is above a certain threshold, or if the BER estimate in operation 416 is below another threshold, the controller 102 obtains SB mode 470, sets the decoding mode to SB1 or SB2 depending on different criteria (operations 475, 485), and retries the read (operation 480).

[0030] Therefore, in an exemplary scenario for the extreme cases of DR or RD, the worst-case paths in the flowchart would be interpreted as follows: (1) BES course (7 read senses with delta 12) using BER estimation for default read parameter values. The result of the estimation is greater than the high BER threshold region. (2) Extended BES (7 read senses with delta 16) using BER estimation for default read parameter values. The result of the estimation is greater than the low BER threshold region. (3) BES fine (7 read senses with delta 8) using BER estimation for optimal read parameters from the previous BES operation. The result of the estimation is greater than the low BER threshold region. (4) If decoding using SB1 and SB2 both fails, an uncorrectable error correcting code (UECC) error is reported and XOR recovery is performed.

[0031] 5 is a flowchart 500 of a cell voltage distribution (CVD) tracking method similar to flowchart 400, but with some modifications. As shown in FIG. 5, the method includes controller 102 of data storage device 100 reacquiring read parameters (operation 505), performing a course BES on a representative word line in memory 104 (operation 510), performing a BER estimation (operation 515), and determining whether the BER area exceeds a threshold (operation 520). If the BER area does not exceed the threshold, controller 102 generates a running average of the parameters (operation 525), performs another BER estimation (operation 530), determines whether the BER is below a BER deviation threshold (operation 535), sets "status ok" or "status error" accordingly (operations 540, 545), and then ends the process of reacquiring read parameters (operation 550).

[0032] Returning to operation 520, if the BER region is above a threshold, the controller 102 determines whether the BER region is above another threshold (operation 555). If not, the controller 102 performs a fine BES operation (operation 560), and the method proceeds to operation 525, as described above. However, the controller 102 performs an extended BES operation (operation 565) and determines whether the BER region is above a threshold (operation 580). If yes, the controller 102 performs a fine BES operation (operation 560), as described above. If not, the controller 102 generates a moving average of the parameters (operation 525), as described above.

[0033] As mentioned above, there may be limitations to the implementation of BES operations. To address these limitations, the following embodiments provide a hybrid variation of BES and on-chip (e.g., in the controller ASIC) Vth tracking, which can prove beneficial before applying soft bit decoding. In one exemplary embodiment, the feedback loop in the algorithm used by the controller 102 is a process that uses BER results from BES-failed pages to update on-chip Vth tracking parameters relative to scan voltage, scan number, and voltage size between scans. The BER results are used to identify the most unreliable pages, and the Vth tracking parameters are updated to reduce the BER for those pages. This process is repeated until the Vth tracking parameters converge to a local minimum. The underlying assumption here is that the BES course returns parameters closer to a low BER value before failure, from which on-chip Vth tracking begins.

[0034] FIG. 6 is a graph of a BES with on-chip Vt tracking convergence from left to right after a certain program-erase count (PEC) cycle due to data retention (DR). This graph illustrates a general case of a CVD state after “X” PEC cycles. Here, the CVD state on the right shifts to the left due to a possible case of data retention (DR). Therefore, in this scenario, the failed-bit count (FBC) is approximately 800, which is greater than the correction capability, and the default read fails (any page decoding during the default read fails). Therefore, in this example, the controller 102 can apply a Vth offset shift associated with the “X” PEC cycle. FIG. 6 assumes that the BES course fails the BER check and returns the direction of the delta to be applied. FIG. 7 is a graph of a BES with on-chip Vt tracking convergence from right to left after a certain program-erase count (PEC) cycle due to DR. This graph illustrates a similar case for RD.

[0035] FIG. 8 is a flowchart 800 illustrating the use of a bit error rate (BER) estimation scan (BES) of one embodiment during a time tag (TT) update. As shown in FIG. 8, at the start of the method, the controller 102 performs a default read (operation 810) and determines whether all page reads pass after BER estimation (operation 820). If all page reads pass, the read values ​​are optimal read values ​​(operation 830), and the method ends. However, if all page reads do not pass, the controller 102 performs a BES course for all pages for which the default read failed (operation 840) and determines whether the failed page reads pass after BER estimation (operation 850). If the failed page reads pass after BER estimation, the method loops back to 830. However, if the failed page reads do not pass after BER estimation, the controller 102 obtains the BER results of the failed pages and the last read value for which the read failed (operation 860). The controller 102 then updates the Vth parameter (operation 870) and reads the failed pages using that parameter. The method then loops back to 850.

[0036] Therefore, this flowchart 800 illustrates the flow of the feedback mechanism. Generally speaking, the controller 102 performs a default read for all pages. Based on which page reads fail, the controller 102 performs a BES course for each logical page. The BES course can be performed by reading data from each logical page at different voltage levels and comparing the results with expected data. The BER (equivalent syndrome weight (SW)) can then be calculated. Based on which page reads fail, the controller 102 can use the BER results to update the Vth tracking parameters. The read levels for each page can be adjusted according to the updated Vth tracking parameters. The read levels for the least reliable pages can be adjusted to obtain a lower BER on such pages. This reduces the BER for those pages and improves their reliability. This process is repeated until the Vth tracking parameters converge to a local minimum in the direction of the last updated read threshold.

[0037] There are several advantages associated with these embodiments. For example, these embodiments can be used to improve reliability. By ensuring that all logical pages are read at the correct voltage level, these embodiments can reduce the number of errors that occur. This can improve the reliability of read operations. If data retention affects a specific page, UECC marking after a BES7 failure can be further considered using the new Vth parameter. As another advantage, these embodiments can be used to reduce overhead. By only applying Vth tracking to logical pages that fail the BES7 course, these embodiments can reduce the overhead of read operations. This can improve the performance of read operations. As yet another advantage, these embodiments can provide increased flexibility. By having different read thresholds, these embodiments can be more flexible in how data is read from the memory. This can be useful in situations where some logical pages are more important than others. Furthermore, BiCS10 devices propose to implement on-chip Vth tracking that is faster than traditional Vth tracking. These embodiments can be used to simplify the design flow and reduce the number of read senses. Additionally, on-chip Vth tracking can be faster than other approaches to Vth tracking. Having this solution together with the existing BES could prove a good combination to improve read performance.

[0038] In summary, these embodiments provide a hybrid variation of BES and on-chip Vth tracking, which enables adaptive read thresholds based on the changing characteristics of memory cells. BER results from BES-failed pages can be used to update on-chip Vth tracking parameters for scan voltage, scan number, and / or voltage size between scans. BER results can be used to identify the most unreliable pages, and Vth tracking parameters can be updated to reduce the BER for those pages. On-chip Vth tracking is faster than BES because separate on-chip and off-chip (as with BES) calculations are not required. Therefore, on-chip Vth tracking results can provide a good margin for comparison with BES (the trade-off here is accuracy vs. speed). Conventional systems may use BES or Vth tracking but do not exploit the benefits of using both. While the process in such conventional systems may be BES (coarse, extended, fine) fail → SB decode, in one exemplary embodiment, the process is BES (coarse) fail → Vth fail → SB decode. That is, BES is used first, followed by Vth. Therefore, in this exemplary embodiment, there is no need to track Vth to determine the BES window. Therefore, from the course window, the controller already knows the read voltage at which the BES course failed and uses that as the reference for Vth start and stop in the next read sense. Between these start and end points there is a valley point. For DR, the valley point shifts to the left, and for RD, it shifts to the right. Also, in these embodiments, instead of the BES valley search, a Vth valley search can be used to find the optimal read voltage, which can be faster than BES given the smaller start-stop window criteria. The window at which the BES failed can be scanned.

[0039] Finally, as noted above, any suitable type of memory may be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") and static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which may be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), magnetoresistive random access memory ("MRAM"), and other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0040] Memory devices may be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element such as an anti-fuse, a phase change material, and optionally a steering element such as a diode. By way of further non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0041] The memory elements may be configured such that the memory elements are connected in series or such that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically include memory elements connected in series. A NAND memory array may be configured such that the array is made up of multiple strings of memory, each consisting of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be configured alternatively.

[0042] The semiconductor memory elements located within and / or above the substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure, a three-dimensional memory structure, or the like.

[0043] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., an xz-direction plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer on or within which layers of memory elements are formed, or may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0044] The memory elements may be arranged in an ordered array, such as multiple rows and / or columns, in a single memory device level. However, the memory elements may be arranged in a non-regular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0045] A three-dimensional memory array is one in which memory elements are arranged to occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional (i.e., x, y, and z directions, where the y direction is substantially perpendicular to the major surface of the substrate and the x and z directions are substantially parallel to the major surface of the substrate) structure.

[0046] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements in each column. The columns may be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also make up a three-dimensional memory array.

[0047] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations are possible, in which some NAND strings contain memory elements at a single memory level and other strings contain memory elements across multiple memory levels. Three-dimensional memory arrays may also be designed in NOR and ReRAM configurations.

[0048] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers making up each memory device level of the array are typically formed on layers of the memory device level below the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intervening layers between the memory device levels.

[0049] Similarly, two-dimensional arrays may then be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but the resulting memory array is not a monolithic three-dimensional memory array because the memory device levels are first formed across separate substrates. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0050] Associated circuitry is typically required for operation of and communication with the memory elements. As a non-limiting example, a memory device may have circuitry used to control and drive the memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read and write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0051] Those skilled in the art will appreciate that the present invention is not limited to the two-dimensional and three-dimensional structures described, but rather encompasses all relevant memory structures within the spirit and scope of the present invention as described herein and as understood by those skilled in the art.

[0052] The above detailed description is intended to be understood as an illustration of selected forms that the invention may take, and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the embodiments described herein may be used alone or in combination with each other.

Claims

1. 1. A data storage device comprising: Memory and and one or more processors, wherein the one or more processors individually or in combination: obtaining a bit error rate (BER) estimation scan (BES) result from a page in the memory; updating a threshold voltage (Vth) tracking parameter using the BES results from the page in the memory; and 1. A data storage device configured to use the updated Vth tracking parameter to read the page in the memory, wherein using the updated Vth tracking parameter to read the page in the memory reduces the BER of the page.

2. The data storage device of claim 1 , wherein the one or more processors comprise an integrated circuit, and the Vth tracking parameters are updated on-chip in the integrated circuit.

3. The one or more processors, individually or in combination: The data storage device of claim 1 , further configured to further update the Vth tracking parameter until the Vth tracking parameter converges to a local minimum.

4. The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to perform soft bit decoding operations.

5. The data storage device of claim 1 , wherein the Vth tracking parameter comprises a scan voltage.

6. The data storage device of claim 1 , wherein the Vth tracking parameter comprises a scan number.

7. The data storage device of claim 1 , wherein the Vth tracking parameter comprises a voltage magnitude between scans.

8. The data storage device of claim 1 , wherein the BES is performed during a time tag update.

9. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

10. A data storage device comprising a memory, performing a default read on a plurality of pages of the memory; performing a bit error rate (BER) estimation scan (BES) for each of the plurality of pages of the memory; updating a threshold voltage (Vth) tracking parameter using the BER results for the failed pages of the memory; and adjusting a read level for the failed page according to the updated Vth tracking parameter; reading the failed page using the adjusted read level.

11. The method of claim 10 , wherein the Vth tracking parameter is updated on-chip in an integrated circuit within the data storage device.

12. The method of claim 10 , further comprising further updating the Vth tracking parameter until the Vth tracking parameter converges to a local minimum.

13. The method of claim 10 further comprising performing a soft bit decoding operation.

14. Implementing the BES course reading data from each of the plurality of pages at a different voltage level; and comparing the retrieved data with expected data.

15. The method of claim 10 , wherein the BES is performed during a time tag update.

16. The method of claim 10 , wherein the Vth tracking parameter comprises a scan voltage.

17. The method of claim 10 , wherein the Vth tracking parameters include a scan number.

18. The method of claim 10 , wherein the Vth tracking parameters include a voltage magnitude between scans.

19. The method of claim 10 , wherein the memory comprises a three-dimensional memory.

20. 1. A data storage device comprising: Memory and means for identifying unreliable pages in the memory using a bit error rate (BER) and updating on-chip threshold voltage (Vth) tracking parameters to reduce the BER for the unreliable pages.

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