Self-aligned top via

Abstract

Embodiments of the present invention include a method and resulting structure for fabricating a semiconductor device. Mandrels are patterned on a liner, and the liner is positioned on a semiconductor substrate. Spacers are formed on sidewalls of the mandrels. Dielectric material lines are formed on the exposed surface of the liner in multiple gaps between the spacers. The mandrels are removed. At least one of the dielectric material lines is removed from within at least one of the multiple gaps between the spacers. A conductive metal is formed in each gap. The conductive metal is patterned to form metal interconnect lines and vias. The multiple spacers and remaining dielectric material lines are removed.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor structures and fabrication, and more specifically to the fabrication of top vias and metal interconnect wiring structures. [Background technology]

[0002] Back end of line (BEOL) is the portion of integrated circuit fabrication where individual devices (transistors, capacitors, resistors, etc.) are interconnected with the wiring, or metallization, layers on the wafer. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

[0003] A via is an electrical connection between layers in a physical electronic circuit, passing through the plane of one or more adjacent layers. In integrated circuit design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

[0004] Damascene processing is an additive process in which a dielectric is deposited, the dielectric is etched according to a defined pattern, the pattern is filled with metal, and the excess metal is removed by a chemical-mechanical polishing / planarization (CMP) process. Summary of the Invention

[0005] Embodiments of the present invention include methods and resulting structures for fabricating semiconductor devices. Applicable The method can include patterning mandrels on the liner; Applicable A liner is positioned over the semiconductor substrate. Applicable The method is: Applicable On the sidewall of the mandrel Multiple Forming spacers can also be included. ApplicableThe method is: Applicable On the exposed surface of the liner The plurality of It may also include forming lines of dielectric material in the gaps between the spacers. Applicable The method is: Applicable Removing the mandrel may also be included. Applicable The method is: The plurality of Between spacers Applicable It may also include removing at least one of the lines of dielectric material within at least one of the plurality of gaps. Applicable The method may also include forming a conductive metal in each gap. Applicable Method for patterning conductive metal to form metal interconnect lines and vias. It can also include. Applicable The method is: Applicable Multiple spacers and remaining Applicable Removing the lines of dielectric material may also be included.

[0006] Embodiments of the present invention may additionally include alternative methods and resulting structures for fabricating semiconductor devices. Applicable The method can include providing a dielectric layer overlying a surface of the liner, the dielectric layer comprising: Applicable A liner is located on the surface of the semiconductor substrate. Applicable The method is: Applicable It may also include forming a plurality of trenches of a depth that exposes the surface of the liner and creates lines of dielectric material from the remaining dielectric layer. Applicable The method includes depositing a dielectric material on the sidewalls of the line. Multiple Forming spacers can also be included. Applicable There are two ways Applicable It can also include removing at least one of the lines of dielectric material between the spacers. Applicable The method may also include forming a conductive metal in each existing gap. Applicable Method for patterning conductive metal to form metal interconnect lines and vias. It can also include. Applicable The method is: Applicable Removing the spacers and remaining lines of dielectric material may also be included. [Brief explanation of the drawings]

[0007] [Figure 1] 1 illustrates a semiconductor substrate and a stack comprising a liner, a dielectric layer and a hard mask according to an embodiment of the present invention. [Figure 2] 1 illustrates a process for forming mandrels from dielectric layers of a stack according to an embodiment of the present invention. [Figure 3] 10 illustrates a process for forming spacers on the sidewalls of a mandrel according to an embodiment of the present invention. [Figure 4] 1 illustrates a process for forming a dielectric layer in the exposed gaps between the spacers according to an embodiment of the present invention. [Figure 5] 10 illustrates a process for removing the mandrel according to an embodiment of the present invention. [Figure 6] 1 illustrates a process for removing dielectric material lines according to an embodiment of the present invention. [Figure 7] 1 illustrates a process for forming a conductive metal in an existing gap according to an embodiment of the present invention. [Figure 8] 1 illustrates a process for forming top vias and metal interconnect lines according to one embodiment of the present invention. [Figure 9] 10 illustrates a process for removing remaining portions of the dielectric layer and spacers according to an embodiment of the present invention. [Figure 10] 1 illustrates a process for creating a trench according to an embodiment of the present invention. [Figure 11] 10 illustrates a process of forming spacers on sidewalls of exposed sides of a dielectric layer according to an embodiment of the present invention. [Figure 12] 1 illustrates a process for removing dielectric material lines according to an embodiment of the present invention. [Figure 13] 1 illustrates a process for forming a conductive metal in an existing gap according to an embodiment of the present invention. [Figure 14]1 illustrates a process for forming top vias and metal interconnect lines according to one embodiment of the present invention. [Figure 15] 10 illustrates a process for removing remaining portions of the dielectric layer and spacers according to an embodiment of the present invention. [Figure 16] 10 illustrates a process for removing exposed portions of the liner according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Embodiments of the present invention describe methods and resulting structures for forming self-aligned back-end-of-line (BEOL) metal line and top via structures. Embodiments of the present invention recognize that conductive metals are optically opaque and can pose alignment and overlay challenges. Thick conductive metals can cause high stresses that lead to wafer bow. Furthermore, embodiments of the present invention recognize that subtractive etching of thick metals can cause line-edge roughness defects, mouse-biting, or other issues. Compared to subtractive patterning, damascene techniques can improve line-edge roughness but can cause line-wiggling issues. Accordingly, embodiments of the present invention describe an approach that forms metal interconnect lines through damascene and vias through a subtractive etching process, resulting in a structure in which both the metal interconnect lines and vias are self-aligned. Furthermore, embodiments of the present invention recognize that such an approach does not require a scaffold, as the spacers utilized serve as scaffolds and are removed after top via formation.

[0009] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. In addition, each example given in connection with the various embodiments is intended to be illustrative and not limiting. Furthermore, the figures are not necessarily to scale, and some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to employ the disclosed methods and structures in various ways. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0010] In the following description, numerous specific details are presented, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, those skilled in the art will recognize that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0011] References herein to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is stated that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0012] For purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the drawings. The terms "overlaying," "atop," "positioned on," or "positioned atop" mean that a first element, e.g., a first structure, is present on a second element, e.g., a second structure, and that an intervening element, e.g., an interfacial structure, may be present between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected without an intervening conductive, insulating, or semiconducting layer at the interface of the two elements.

[0013] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will also be understood that the element can be directly below or under the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0014] The present invention will now be described in detail with reference to the figures.

[0015] Figure 1 shows an isometric view of a device at an early stage in a method of forming the device. The semiconductor structure of Figure 1 includes a semiconductor material stack comprising a liner 110 on a surface of a semiconductor substrate 100, a dielectric layer 120 on that surface, and a hard mask 130 on that surface.

[0016] The semiconductor substrate 100 may be composed of a silicon-containing material, including, but not limited to, silicon, monocrystalline silicon, polycrystalline silicon, SiGe, monocrystalline SiGe, polycrystalline SiGe, or carbon-doped silicon (Si:C), amorphous silicon, and combinations and multilayers thereof. The semiconductor substrate 100 may also be composed of other semiconductor materials, such as germanium (Ge), and compound semiconductor substrates, such as III / V semiconductor substrates, e.g., gallium arsenide (GaAs). In some embodiments, the semiconductor substrate 100 may be a wafer with front-end-of-line (FEOL), middle-of-the-line (MOL), and / or BEOL metallization. Generally, the semiconductor substrate 100 is a substrate with a smooth surface.

[0017] The liner 110 is formed by sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD) and is a conductor such as titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the liner 110 may be made of other conductive materials, such as aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), or combinations thereof.

[0018] A dielectric layer 120 is deposited over the liner 110. The dielectric layer 120 is generally a layer of insulating material. The dielectric layer 120 may be composed of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), (SiOCN), (SiBCN), or other insulating materials known in the art. The dielectric layer 120 is deposited such that the dielectric layer 120 has a thickness that corresponds to the desired combined height of the vias and metal lines of the resulting device.

[0019] A hard mask 130 is deposited over the dielectric layer 120. A hard mask is a material used in semiconductor processing as an etch mask. The hard mask 130 may be composed of a metal or dielectric material, such as SiN, silicon oxide, or a combination of silicon nitride and silicon oxide, which may be deposited using a process such as low-pressure chemical vapor deposition (LPCVD). In various embodiments, standard photolithography processes are used to define the pattern of the hard mask 130 in a layer of photoresist (not shown) deposited over the hard mask 130. The desired hard mask pattern may then be formed in the hard mask 130 by removing the hard mask 130 from areas not protected by the pattern in the photoresist layer. The hard mask 130 may be removed using, for example, reactive ion etching (RIE). RIE uses a chemically reactive plasma generated by an electromagnetic field to remove various materials. Those skilled in the art will recognize that the type of plasma used will depend on the material comprising the hard mask 130, or other etch processes, such as wet chemical etching or laser ablation, may be used. Although not shown, the hard mask 130 may be patterned such that the hard mask 130 covers areas of the dielectric layer 120 that will become the mandrels 210 (see FIG. 2).

[0020] FIG. 2 shows an isometric view of fabrication steps according to one embodiment of the present invention. FIG. 2 illustrates the formation of mandrels 210 from dielectric layer 120 and the removal of hard mask 130. The mandrels are used for spacer patterning. Spacer patterning is a technique employed to pattern features with smaller linewidths than can be achieved by conventional lithography. Typically, spacers (e.g., spacers 310, see FIG. 3) are deposited over the mandrels (e.g., mandrels 210), which are pre-patterned features. The spacers are then etched back so that the spacer portions covering the mandrels are etched away, while the spacer portions on the sidewalls remain. The mandrels may then be removed, leaving two spacers per mandrel (one per edge).

[0021] The mandrels 210 may be formed by an etching process, such as RIE, laser ablation, or any etch process that can be used to selectively remove portions of a material, such as the dielectric layer 120. As described above with reference to FIG. 1, a hard mask 130 may be patterned to cover the mandrels 210 during creation of the mandrels 210 and utilized during the etching process. The etching process removes only the portions of the dielectric layer 120 that are not protected by the hard mask 130, and the etching process stops at the liner 110. Each mandrel has a height equal to the combined height of the desired metal lines and vias.

[0022] In some embodiments, the hard mask 130 is removed after the formation of the mandrels 210. Generally, the process of removing the hard mask 130 involves the use of an etching process such as RIE, laser ablation, or any etch process that can be used to selectively remove portions of material, such as the hard mask 130. In alternative embodiments, the hard mask 130 may not be removed at this time, but rather remains on the device until a subsequent metal chemical mechanical polishing / planarization (CMP) step (see FIG. 7) is performed.

[0023] FIG. 3 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 3 illustrates the formation of spacers 310 on the exposed sides of mandrels 210. Spacers 310 are comprised of a metal (e.g., TiN, TaN) or any dielectric spacer material, including, for example, a dielectric oxide, a dielectric nitride, and / or a dielectric oxynitride. In some embodiments, spacers 310 are comprised of a non-conductive, low-capacitance dielectric material, such as silicon dioxide (SiO). Generally, spacers 310 are comprised of a material different from liner 110. The process of forming spacers 310 may include depositing a conformal layer of insulating material (not shown), such as silicon nitride, over the exposed surfaces of liner 110 and mandrels 210. Spacers 310 can be deposited using, for example, CVD, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other deposition processes. An anisotropic etch process, in which the etch rate in the forward direction is greater than the etch rate in the lateral direction, may be used to partially remove the insulating layer, thereby forming spacers 310 located on the sidewalls of the mandrels 210, as shown in FIG. 3.

[0024] FIG. 4 shows an isometric view of fabrication steps according to one embodiment of the present invention. FIG. 4 illustrates the formation of a dielectric layer 410 on the liner 110 within the exposed gaps between the spacers 310. The portions of the dielectric layer 410 within each exposed gap may produce multiple lines of dielectric material. As described above with reference to the dielectric layer 120, the dielectric layer 410 is generally a layer of insulating material and may be composed of, for example, SiN, SiCN, SiOCN, SiBCN, or other insulating materials known in the art. In some embodiments, the dielectric layer 410 is a layer of a low-κ dielectric material. Low-κ is a material with a low relative dielectric constant (κ) compared to SiO. Low-κ materials include, for example, fluorine-doped SiO, organosilicate glass (OSG), porous SiO, porous organosilicate glass, spin-on organic polymer dielectrics, and spin-on silicon-based polymer dielectrics. In some embodiments, the dielectric layer 410 is spin-on glass. Spin-on-glass is an interlayer dielectric material that is applied in liquid form to fill narrow gaps in sub-dielectric surfaces. In some embodiments, the dielectric layer 410 is deposited using flowable chemical vapor deposition (fCVD) or spin-on dielectric methods. The dielectric layer 410 may be created by depositing the dielectric layer 410 above a desired height and then utilizing a planarization process, such as CMP, to reduce the height of the dielectric layer 410 so that the top surfaces of the mandrels 210 are exposed.

[0025] Figure 5 shows an isometric view of a fabrication step according to one embodiment of the present invention. Figure 5 illustrates the removal of mandrel 210 to create a first trench in the gap shown in Figure 5. Mandrel 210 may be removed using an etching process that is selective to spacer 310 and dielectric layer 410 in removing the physically exposed portion of mandrel 210 to create the gap comprising the first trench. The etching process utilized may be a dry etching or a wet etching process.

[0026] FIG. 6 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 6 illustrates the partial removal of dielectric layer 410 to create a second trench. One or more lines of dielectric material may be removed. In the embodiment shown, the central and edge portions of dielectric layer 410 are not removed. The portions of dielectric layer 410 to be removed may be removed by using standard photolithography processes to define the desired shape of the second trench in a layer of photoresist (not shown) deposited on the top surfaces of spacer 310, dielectric layer 410, and / or liner 110. In various embodiments, standard photolithography processes are used to remove portions of the photoresist layer corresponding to the areas of the dielectric layer to be removed during formation of the second trench. The portions of dielectric layer 410 may be removed using, for example, a dry etch process such as RIE to remove the desired portion(s) of dielectric layer 410. As a result of etching those portions of dielectric layer 410, liner 110 is exposed in the area defined as the second trench.

[0027] FIG. 7 shows an isometric view of a fabrication step according to an embodiment of the present invention. FIG. 7 illustrates the formation of conductive metal 710 in a gap comprising first and second trenches. The conductive metal 710 may be any type of conductive metal. For example, the conductive metal 710 may be composed of Ru, Co, molybdenum (Mo), tungsten (W), Al, or rhodium (Rh). The conductive metal 710 may be deposited using, for example, CVD, PECVD, PVD, or other deposition processes. The conductive metal 710 may be produced by depositing the conductive metal 710 above a desired height and then utilizing a planarization process, such as CMP, to reduce the height of the conductive metal 710 so that the top surfaces of the spacers 310 and the dielectric layer 410 are exposed.

[0028] In some embodiments, spacers 310 comprise TiN, which may reduce line wiggling compared to other materials. Embodiments of the present invention recognize that a template with a higher modulus can reduce line wiggling after metal filling. A TiN template with spacers 310 comprised of TiN has a modulus of approximately 500 gigapascals (GPa), which is higher than many other materials.

[0029] FIG. 8 shows an isometric view of fabrication steps according to one embodiment of the present invention. FIG. 8 illustrates the formation of top vias and metal interconnect lines by a subtractive patterning process, during which non-via portions of conductive metal 710 are recessed to a target depth for the desired via structure. The formation of the top vias may be performed using a photolithographic subtractive patterning process. A masking step is utilized to form the vias in conductive metal 710. Such masking may involve depositing a photoresist layer and patterning the layer using ultraviolet light, allowing removal of only selected portions of the photoresist, followed by etching of conductive metal 710 according to the photoresist pattern. It should be noted that the via placement shown in FIG. 8 (and subsequent similar figures) may vary based on the implementation details of the final desired via structure. In some embodiments, a selective etching process may be utilized. In some embodiments, such as the embodiment shown in FIG. 8, dielectric layer 410 may be damaged as a result of the etching process, which is represented in FIG. 8 by the reduced height of dielectric layer 410.

[0030] 9 shows an isometric view of a fabrication step according to one embodiment of the present invention. Figure 9 illustrates the selective removal of spacers 310 and dielectric layer 410, as well as the resulting via structure including one or more vias formed in conductive metal 710 and liner 110 on semiconductor substrate 100. Spacers 310 and dielectric layer 410 may be removed using an etching process that is selective to conductive metal 710 in removing physically exposed portions of spacers 310 and / or dielectric layer 410 to remove all of spacers 310 and dielectric layer 410 and partially expose liner 110. The etching process utilized may be a dry etching or a wet etching process.

[0031] In some embodiments, the exposed portions of liner 110 remain on semiconductor substrate 100. In other embodiments, the exposed portions of liner 110 are etched away so that liner 110 is only present below conductive metal 710 (see FIG. 16, where conductive metal 1310 is similar to conductive metal 710).

[0032] The resulting structure is a BEOL metal line and top via structure, which may be, for example, a metal-insulator-metal capacitor including metal lines formed by damascene and top vias formed by subtractive processes, with the spacers 310 acting as scaffolds during the top via etching process.

[0033] Figures 10-16 show embodiments of the present invention formed by different fabrication processes beginning with a trench etch.

[0034] The fabrication process illustrated by FIG. 10 is performed on the same device first shown in FIG. 1, which shows an isometric view of a device including a semiconductor material stack comprising a liner 110 on a semiconductor substrate 100, a dielectric layer 120 thereon, and a hard mask 130 thereon, as previously described.

[0035] FIG. 10 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 10 illustrates the partial removal of the hard mask 130 and the dielectric layer 120 to create a trench. The trench may be formed by an etching process, such as RIE, laser ablation, or any etch process that can be used to selectively remove portions of material, such as the dielectric layer 120. The hard mask 130 may be patterned, as shown in FIG. 10, before performing the etching process to aid in the creation of the trench by preventing the remaining portions of the dielectric layer 120 from being removed during the etching process. The etching process stops on the liner 110, removing only the portions of the dielectric layer 120 that are not protected by the hard mask 130. The trench width is selected based on the sum of the final desired metal line width and the spacer thickness. In some embodiments, the trench width is equal to three times the final desired metal line width. The remaining portions of the dielectric layer 120 may form the dielectric material lines.

[0036] FIG. 11 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 11 illustrates the formation of spacers 1110 on the exposed side of the dielectric layer 120. The spacers 1110 are composed of a metal (e.g., TiN, TaN) or any dielectric spacer material, including, for example, a dielectric oxide, a dielectric nitride, and / or a dielectric oxynitride. In some embodiments, the spacers 1110 are composed of a non-conductive, low-capacitance dielectric material, such as silicon dioxide (SiO). Generally, the spacers 1110 are composed of a different material than the liner 110. The process of forming the spacers 1110 may include depositing a conformal layer of insulating material (not shown), such as silicon nitride, over the exposed surfaces of the liner 110 and the mandrel dielectric layer 120. The spacers 1110 can be deposited using, for example, CVD, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other deposition processes. An anisotropic etch process, in which the etch rate in the forward direction is greater than the etch rate in the lateral direction, may be used to partially remove the insulating layer, thereby forming spacers 1110 located on the sidewalls of the dielectric layer 120, as shown in FIG. 11.

[0037] 11 also illustrates the removal of the hard mask 130. Generally, the process of removing the hard mask 130 involves the use of an etching process such as RIE, laser ablation, or any etch process that can be used to selectively remove portions of material, such as the hard mask 130.

[0038] FIG. 12 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 12 illustrates the partial removal of dielectric layer 120 to create a second trench. In the embodiment shown, the central and edge portions of dielectric layer 120 are not removed. The portions of dielectric layer 120 to be removed may be removed by using standard photolithography processes to define the desired shape of the second trench in a layer of photoresist (not shown) deposited on the top surfaces of spacer 1110, dielectric layer 120, and / or liner 110. In various embodiments, standard photolithography processes are used to remove portions of the photoresist layer corresponding to the areas of the dielectric layer to be removed during formation of the second trench. The portions of dielectric layer 120 may be removed using, for example, a dry etch process such as RIE to remove the desired portion(s) of dielectric layer 120. As a result of etching those portions of dielectric layer 120, liner 110 is exposed in the areas defined as the second trench.

[0039] FIG. 13 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 13 illustrates the formation of conductive metal 1310 in a gap comprising a trench. The conductive metal 1310 may be any type of conductive metal. For example, the conductive metal 1310 may be composed of Ru, Co, Mo, W, Al, or Rh. The conductive metal 1310 may be deposited using, for example, CVD, PECVD, PVD, or other deposition processes. The conductive metal 1310 may be produced by depositing the conductive metal 1310 above a desired height and then utilizing a planarization process, such as CMP, to reduce the height of the conductive metal 1310 so that the top surfaces of the spacers 1110 and the dielectric layer 120 are exposed.

[0040] In some embodiments, where the spacers 1110 are made of TiN, line wiggling may be reduced compared to using other materials. Embodiments of the present invention recognize that a template with a higher modulus can reduce line wiggling after metal filling. A TiN template with spacers 1110 made of TiN has a modulus of approximately 500 GPa, which is higher than many other materials.

[0041] FIG. 14 shows an isometric view of fabrication steps according to one embodiment of the present invention. FIG. 14 illustrates the formation of top vias and metal interconnect lines by a subtractive patterning process, during which non-via portions of conductive metal 1310 are recessed to a target depth for the desired via structure. The formation of the top vias may be performed using a photolithographic subtractive patterning process. A masking step is utilized to form the vias in conductive metal 1310. Such masking may involve depositing a photoresist layer and patterning the layer using ultraviolet light, allowing removal of only selected portions of the photoresist, followed by etching of conductive metal 1310 according to the photoresist pattern. It should be noted that the via placement illustrated in FIG. 14 (and subsequent similar figures) may vary based on the implementation details of the final desired via structure. In some embodiments, a selective etching process may be utilized. In some embodiments, such as the embodiment shown in FIG. 14, the dielectric layer 120 may be damaged as a result of the etching process, which is represented in FIG. 14 by a reduced height of the dielectric layer 120.

[0042] 15 shows an isometric view of a fabrication step according to one embodiment of the present invention. Figure 15 illustrates the selective removal of spacers 1110 and dielectric layer 120, and the resulting via structure including one or more vias formed in conductive metal 1310 and liner 110 on semiconductor substrate 100. Spacers 1110 and dielectric layer 120 may be removed using an etching process that is selective to conductive metal 1310 in removing physically exposed portions of spacers 1110 and / or dielectric layer 120 to remove all of spacers 1110 and dielectric layer 120 and partially expose liner 110. The etching process utilized may be a dry etching or a wet etching process.

[0043] In some embodiments, the exposed portions of liner 110 remain on semiconductor substrate 100. In other embodiments, the exposed portions of liner 110 are etched away so that liner 110 resides only below conductive metal 1310 (see FIG. 16).

[0044] FIG. 16 shows an isometric view of a fabrication step according to one embodiment of the present invention. FIG. 16 illustrates selective removal of exposed portions of the liner 110. The liner 110 is removed using an etching technique, such as RIE. RIE uses a chemically reactive plasma generated by an electromagnetic field to remove various materials. Those skilled in the art will recognize that the type of plasma used will depend on the material from which the liner 110 is composed, or that other etch processes, such as wet chemical etching or laser ablation, may be used. In one embodiment, chemical etching is used to remove the exposed portions of the liner 110 to expose the surface of the semiconductor substrate 100. In some embodiments, TiN and TaN wet removal processes may be utilized to remove the exposed portions of the liner 110, such as when the liner 110 is composed of TiN or TaN.

[0045] The resulting structure is a BEOL metal line and top via structure, which may be, for example, a metal-insulator-metal capacitor including metal lines formed by damascene and top vias formed by subtractive processes, with the spacers 1110 acting as scaffolds during the top via etching process.

[0046] The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects, or embedded interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] While the present application has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and shown, but fall within the scope of the appended claims.

[0049] In a preferred embodiment of the present invention, a method is provided that includes providing a dielectric layer overlying a liner, the liner overlying a surface of a semiconductor substrate; forming a plurality of trenches to a depth that exposes the surface of the liner and creates dielectric material lines from the remaining dielectric layer; forming spacers on sidewalls of the dielectric material lines; removing at least one of the dielectric material lines between two spacers; forming conductive metal in each existing gap; patterning the conductive metal to form metal interconnect lines and vias; and removing the plurality of spacers and the remaining dielectric material lines. The width of the trenches may be equal to the sum of the desired metal interconnect line width and the expected spacer thickness. The width of the trenches may be three times greater than the desired metal interconnect line width. The spacers may be composed of titanium nitride (TiN). The conductive metal may be selected from the group consisting of ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), tungsten (W), and rhodium (Rh). The method may further include removing the exposed portion of the liner after removing the plurality of spacers and the remaining dielectric material lines. Patterning the conductive metal to form the metal interconnect lines and vias may utilize a subtractive patterning process.

[0050] In another preferred embodiment of the present invention, a semiconductor structure is provided, comprising: a semiconductor substrate; a liner on a surface of the semiconductor substrate; a plurality of interconnect lines and vias on the surface of the liner, the plurality of interconnect lines and vias being composed of a conductive metal; and a plurality of spacers between each of the plurality of interconnect lines and vias. The plurality of spacers may be composed of titanium nitride (TiN). The conductive metal may be selected from the group consisting of ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), tungsten (W), and rhodium (Rh). The liner may be composed of titanium nitride (TiN) or a metal selected from the group consisting of tantalum nitride (TaN), titanium (Ti), and tantalum (Ta). Each of the plurality of interconnect lines and vias may include at least one via protruding from the surface of the interconnect line. The surface of the interconnect line may be a top surface.

Claims

1. patterning mandrels on a liner, the liner resting on a semiconductor substrate; forming a plurality of spacers on a sidewall of the mandrel; forming lines of dielectric material on the exposed surface of the liner within the gaps between the spacers; removing the mandrel; removing at least one of the lines of dielectric material within at least one of the gaps between the spacers; forming a conductive metal in each gap; patterning the conductive metal to form metal interconnect lines and vias; removing the plurality of spacers and the remaining lines of dielectric material; A method comprising:

2. forming the dielectric material line depositing a dielectric material to a height above the mandrels via a process selected from the group consisting of spin-on-glass and flowable chemical vapor deposition; utilizing a planarization process to reduce the height of the dielectric material to form the dielectric material lines and expose top surfaces of the mandrels; The method of claim 1 , comprising:

3. The method of claim 1 , wherein the spacers are comprised of titanium nitride (TiN).

4. 10. The method of claim 1, wherein the conductive metal is selected from the group consisting of ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), tungsten (W), and rhodium (Rh).

5. removing the exposed portion of the liner after removing the plurality of spacers and the remaining lines of dielectric material. The method of claim 1 further comprising:

6. The method of claim 1 , wherein patterning the conductive metal utilizes a subtractive patterning process.

7. providing a dielectric layer overlying a liner, the liner overlying a semiconductor substrate; forming a plurality of trenches of a depth exposing a surface of the liner to create lines of dielectric material from the remaining dielectric layer; forming a plurality of spacers on sidewalls of the dielectric material line; removing at least one of the lines of dielectric material between two of the spacers; forming a conductive metal in each gap; patterning the conductive metal to form metal interconnect lines and vias; removing the plurality of spacers and the remaining lines of dielectric material; A method comprising:

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