Indication device

Abstract

To solve the problem of a display device whose rear part can be seen through, in which the whole display device is not integrated enough due to a difference in transparency between a display region where pixels are arranged and a peripheral region where wires are led.SOLUTION: A display device includes an array substrate including a display region where pixels are arranged and a peripheral region outside the display region, a counter substrate that faces the array substrate, and a liquid crystal layer between the array substrate and the counter substrate. The display region includes a scan signal line extending in a first direction and arranged in a second direction intersecting with the first direction and a data signal line extending in the second direction and arranged in the first direction. The peripheral region includes a first wiring pattern where dummy wires and first wires connecting a scan signal line driving circuit and a scan signal line form a first lattice pattern, and a second wiring pattern where second wires to which a certain potential is applied form a second lattice pattern.SELECTED DRAWING: Figure 6A

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a wiring structure of a display device. [Background technology]

[0002] Known liquid crystal display devices include transmissive displays that display images by transmitting light from a backlight placed behind the liquid crystal panel, reflective displays that display images by reflecting external light from pixel electrodes, and semi-transmissive displays that combine the features of both transmissive and reflective types. These liquid crystal display devices are used as displays for electronic devices such as personal computers and smartphones, and are configured so that the background cannot be seen through the screen.

[0003] In response to this, display devices have been developed that allow the user to see through to what is behind while displaying an image. For example, a display device has been disclosed in which the display area is formed by a polymer dispersed liquid crystal disposed between a pair of light-transmitting substrates, allowing the user to see through to what is behind (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-092748 [Patent Document 2] Patent Publication No. 2021-092702 Summary of the Invention [Problem to be solved by the invention]

[0005] Display devices that allow the viewer to see behind them can enhance their design by making not only the display area but also the peripheral area (also called the frame area) outside the display area transparent. However, there is a problem in that the display area where the pixels are arranged and the peripheral area where the wiring is routed have different levels of transparency, which causes a lack of unity in the display device as a whole. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention has an array substrate including a display area in which pixels are arranged and a peripheral area outside the display area, an opposing substrate facing the array substrate, and a liquid crystal layer between the array substrate and the opposing substrate, wherein the display area has a plurality of scanning signal lines extending in a first direction and arranged in a second direction intersecting the first direction, and a plurality of data signal lines extending in the second direction and arranged in the first direction, and the peripheral area has a first wiring pattern in which a first grid pattern is formed by a plurality of first wires and a plurality of dummy wires that connect a scanning signal line driving circuit to the plurality of scanning signal lines, and a second wiring pattern in which a second grid pattern is formed by second wires to which a constant potential is applied. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram showing a configuration of a display device according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view schematically illustrating a structure corresponding to the area between V1 and V2 of the display device shown in FIG. [Figure 3] 1 is a diagram showing a configuration of an array substrate side of a display device according to an embodiment of the present invention; [Figure 4] 1 is a plan view showing a configuration of a light-shielding layer in a display device according to an embodiment of the present invention. [Figure 5] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Figure 6A] 1 is a plan view showing a configuration of wiring provided in a peripheral region of a display device according to an embodiment of the present invention. [Figure 6B] 1 is a cross-sectional view showing the configuration of a light-shielding layer provided in a peripheral region of a display device according to one embodiment of the present invention. [Figure 6C] 1 is a cross-sectional view showing the configuration of wiring and a light-shielding layer provided in a peripheral region of a display device according to one embodiment of the present invention. [Figure 7A] 1 is a plan view showing the configuration of wiring and a planarization layer provided in a peripheral region of a display device according to an embodiment of the present invention. [Figure 7B] 1 is a cross-sectional view showing the configuration of wiring, a planarizing layer, and a light-shielding layer provided in a peripheral region of a display device according to one embodiment of the present invention. [Figure 8] 1 is a plan view showing the configuration of wiring, a planarizing layer, and a light-shielding layer provided in a peripheral region of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals (or reference numerals with A, B, a, b, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0009] In this specification, when a component or region is described as being "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0010] [First embodiment] A display device 100 according to one embodiment of the present invention will be described with reference to the drawings.

[0011] 1-1. Display device overview 1 is a perspective view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a display panel 102, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B sandwiching the display panel 102. The display panel 102 includes an array substrate 150, a counter substrate 152, and a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152. The display panel 102 has a display area 112 and a peripheral area 114. The display area 112 is provided with a plurality of pixels 116, and the peripheral area 114 is provided with drive circuits such as a scanning signal line drive circuit 106 and a data signal line drive circuit 108, a first wiring pattern 118, a second wiring pattern 120, etc.

[0012] In the following description, one direction when the display panel 102 is viewed in a plan view is referred to as a D1 direction, a direction perpendicular to the D1 direction is referred to as a D2 direction, and a direction perpendicular to the D1-D2 plane is referred to as a D3 direction.

[0013] The array substrate 150 and the counter substrate 152 are translucent. The array substrate 150 and the counter substrate 152 are preferably transparent to visible light. The counter substrate 152 is disposed in the direction D3 so as to face the array substrate 150. The array substrate 150 and the counter substrate 152 are fixed together by a sealant 154 while facing each other with a gap therebetween. There is a gap between the array substrate 150 and the counter substrate 152, and a liquid crystal layer (not shown) is provided in the gap.

[0014] In the display area 112, a plurality of pixels 116 are arranged in a D1 direction (row direction) and a D2 direction (column direction). For example, in the display area 112, m pixels are arranged along the D1 direction, and n pixels are arranged along the D2 direction. The number of the plurality of pixels 116 (the values ​​of m and n) is set appropriately according to the display resolution in the vertical direction and the display resolution in the horizontal direction. In addition, in the display area 112, scanning signal lines extending in the D1 direction are arranged along the D2 direction, and data signal lines extending in the D2 direction are arranged along the D1 direction.

[0015] The scanning signal line driving circuit 106 and the data signal line driving circuit 108 are provided in a peripheral region 114 of the array substrate 150. Fig. 1 shows an embodiment in which the scanning signal line driving circuit 106 and the data signal line driving circuit 108 are provided as integrated circuits (ICs) and mounted on the array substrate 150 by a chip-on-glass (COG) method. The scanning signal line driving circuit 106 and the data signal line driving circuit 108 are not limited to the embodiment shown in the figure, and may be mounted by a chip-on-film (COF) method or formed by thin film transistors (TFTs) on the array substrate 150.

[0016] The peripheral region 114 includes a first wiring pattern 118, a second wiring pattern 120, and a third wiring pattern 122. The first wiring pattern 118 is formed by first wiring that connects the scanning signal line driving circuit 106 and the scanning signal lines 107 (see FIG. 3) arranged in the display region 112. The second wiring pattern 120 is formed by second wiring that surrounds the outside of the display region 112. A constant voltage (common voltage) is applied to the second wiring, so it can also be called a common wiring. The second wiring is also used as wiring that applies the common voltage to a counter electrode 162 (see FIG. 5) provided on the counter substrate 152. The third wiring pattern 122 is formed by third wiring that connects the data signal line driving circuit 108 and the data signal lines 109 (see FIG. 3) arranged in the display region 112.

[0017] The light source 104 has a structure along the D1 direction. The light source 104 is composed of, for example, light-emitting diodes (LEDs) arranged along the D1 direction. The detailed structure of the light source 104 is not limited, and in addition to the light-emitting diodes arranged in the D1 direction, optical components such as a reflector, a diffuser, and a lens may be included. The light source 104 and the light-emission control circuit 110 that controls the light source 104 may be provided as separate components independent of the display panel 102. Furthermore, the light-emission timing of the light source 104 may be controlled by the light-emission control circuit 110 that is synchronized with the scanning signal line drive circuit 106 and the data signal line drive circuit 108. The light-emission control circuit 110 that controls the light source 104 may be provided as a separate component separate from the display panel 102, like the light source 104, or may be mounted on the array substrate 150 as a separate component, or may be incorporated into the scanning signal line drive circuit 106 or the data signal line drive circuit 108.

[0018] The first transparent substrate 151A and the second transparent substrate 151B are disposed to sandwich the display region 112 and the peripheral region 114. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. As will be described with reference to FIG. 2, the first transparent substrate 151A and the second transparent substrate 151B also function as light guide plates that introduce light emitted from the light source 104 into the display panel 102.

[0019] FIG. 2 shows a cross-sectional structure of the display device 100 corresponding to the V1-V2 area shown in FIG. 1. As shown in FIG. 2, a first transparent substrate 151A and a second transparent substrate 151B are disposed to sandwich the display panel 102. The first transparent substrate 151A is disposed on the array substrate 150 side, and the second transparent substrate 151B is disposed on the counter substrate 152 side. Glass substrates or plastic substrates are used as the first transparent substrate 151A and the second transparent substrate 151B. It is preferable that the first transparent substrate 151A and the second transparent substrate 151B are transparent and have the same refractive index as the array substrate 150 and the counter substrate 152. The array substrate 150 and the first transparent substrate 151A, and the counter substrate 152 and the second transparent substrate 151B are bonded together with a transparent adhesive (not shown).

[0020] In a plan view, the array substrate 150 is larger than the counter substrate 152, and a portion of the peripheral region 114 is exposed from the counter substrate 152. A driving circuit is provided in this exposed region. Fig. 2 shows an aspect in which the data signal line driving circuit 108, among the driving circuits, is provided. Furthermore, terminals (not shown) are provided in the peripheral region 114, and a flexible wiring substrate 124 is attached to the terminals.

[0021] The light source 104 is disposed adjacent to one side surface of the first transparent substrate 151A or the second transparent substrate 151B. FIG. 2 shows a configuration in which the light source 104 is disposed adjacent to the first side surface 15C of the second transparent substrate 151B. The light source 104 is sometimes called a side light source because it emits light L toward the first side surface 15C. While FIG. 2 shows a configuration in which the light source 104 is attached to the array substrate 150, there are no limitations on the configuration in which the light source 104 is disposed, and there are no limitations on the attachment structure as long as the attachment position can be fixed. The light source 104 may be supported by a housing that surrounds the display panel 102, for example.

[0022] 2, light emitted from light source 104 enters second transparent substrate 151B from first side surface 15C. First side surface 15C of second transparent substrate 151B facing light source 104 serves as a light incident surface.

[0023] 2, light L incident on the first side surface 15C of the second transparent substrate 151B enters the display panel 102 and propagates in a direction away from the first side surface 15C (direction D2) while being reflected by the first flat surface 15A of the first transparent substrate 151A and the second flat surface 15B of the second transparent substrate 151B. When light L travels from the first flat surface 15A of the first transparent substrate 151A and the second flat surface 15B of the second transparent substrate 151B to the outside, it travels from a medium with a larger refractive index to a medium with a smaller refractive index. If the angle of incidence of light L on the first flat surface 15A and the second flat surface 15B is greater than the critical angle, the light is totally reflected and is guided in the direction D2 while being reflected by the first flat surface 15A and the second flat surface 15B.

[0024] The liquid crystal layer 126 is made of polymer-dispersed liquid crystal. The scattering state and non-scattering state of the liquid crystal layer 126, which is made of polymer-dispersed liquid crystal, are controlled for each pixel 116 (see FIG. 1). As shown in FIG. 2, light L propagating while being reflected by the first plane 15A and the second plane 15B is at least partially scattered when there is a pixel where the liquid crystal layer 126 is in the scattering state. The incident angle of the scattered light becomes smaller than the critical angle, and scattered light LA ​​and LB are emitted to the outside from the first plane 15A and the second plane 15B, respectively. The emitted scattered light LA ​​and LB are observed by the viewer. In the display panel 102, areas other than those through which the scattered light LA ​​and LB are emitted are substantially transparent because the array substrate 150, the counter substrate 152, the first transparent substrate 151A, and the second transparent substrate 151B are translucent (transparent to visible light) and the liquid crystal layer 126 is in the non-scattering state. This allows the viewer to view the rear side through the display panel 102.

[0025] 1-2. Array board configuration 3 is a plan view illustrating the configuration of the array substrate 150. The array substrate 150 includes a display region 112 and a peripheral region 114. A plurality of pixels 116 are arranged in a matrix in the display region 112. Although not shown, each of the plurality of pixels 116 includes a pixel electrode, a transistor connected to the pixel electrode, a counter electrode, and a liquid crystal layer. In the display region 112, a plurality of scanning signal lines 107 extending in the D1 direction are arranged in the D2 direction, and a plurality of data signal lines 109 extending in the D2 direction are arranged in the D1 direction.

[0026] The peripheral region 114 is provided with a scanning signal line driving circuit 106 and a data signal line driving circuit 108. Also provided in the peripheral region 114 are a first wiring pattern 118 formed by a plurality of first wirings extending from the scanning signal line driving circuit 106 to the display region 112, a second wiring pattern 120 formed by second wirings to which a constant voltage (common voltage) is applied, and a plurality of third wiring patterns 122 formed by third wirings extending from the data signal line driving circuit 108 to the display region 112.

[0027] Furthermore, second wiring patterns 120 (120-1, 120-2), a common pad 125, a scanning signal line inspection circuit 130, a data signal line inspection circuit 132, and multiple terminals 128 for inputting signals from external circuits are provided in the peripheral region 114. The multiple terminals 128 are arranged along the direction D1 on the periphery of the array substrate 150. A flexible wiring substrate 124 is attached to the multiple terminals 128. The scanning signal line driving circuit 106, the second wiring patterns 120 (120-1, 120-2), the ESD protection circuit 137, and the QD pads 136 are electrically connected to the flexible wiring substrate 124.

[0028] The scanning signal line driving circuit 106 is connected to the plurality of scanning signal lines 107 via a plurality of first wirings that form a first wiring pattern 118. Each of the plurality of scanning signal lines 107 is electrically connected to a respective one of the plurality of pixels 116 in the display region 112. The number of the plurality of first wirings that form the first wiring pattern 118 corresponds to the number of scanning signal lines 107 connected to the scanning signal line driving circuit 106. Note that although the first wiring pattern 118 is shown in FIG. 3 as being spaced apart from the display region 112, in reality it is continuous with the scanning signal lines 107.

[0029] The data signal line driving circuit 108 is connected to a plurality of data signal lines 109. Each of the plurality of data signal lines 109 is electrically connected to a respective one of a plurality of pixels 116 in the display area 112. In FIG. 3, the third wiring pattern 122 connecting the data signal line driving circuit 108 and the plurality of data signal lines 109 is shown to be provided apart from the display area 112, but in reality it is continuous with the data signal lines 109.

[0030] 3, the plurality of first wirings forming the first wiring pattern 118 extend from the scanning signal line driving circuit 106 in the direction D2, bend midway in the direction D1, and connect to the scanning signal lines 107. In addition, in the region where the first wirings are arranged, dummy wirings are provided between the wirings.

[0031] Between the first wiring pattern 118 and the display region 112, there are provided a second wiring pattern 120-2, an ESD protection circuit 131, a scanning signal line inspection circuit 130, and an inspection line 134. Between the third wiring pattern 122 and the display region 112, there are provided a second wiring pattern 120-2, an ESD protection circuit 133, a data signal line inspection circuit 132, and an inspection line 134. The inspection line 134 is connected to an ESD protection circuit 135 and a QD pad 136. The second wiring pattern 120-2 is connected to an ESD protection circuit 137. The second wiring pattern 120-1 is provided so as to surround the peripheral region 114 of the array substrate 150, and a signal is supplied from the flexible wiring substrate 124.

[0032] 1-3. Configuration of the opposing substrate 4 is a plan view showing the configuration of the counter substrate 152. As shown in FIG. 4, the counter substrate 152 is provided with a light-shielding layer 160 and a counter electrode 162. The light-shielding layer 160 is provided in the display region 112 and the peripheral region 114. The counter electrode 162 is provided in the display region 112. The counter electrode 162 may be provided not only in the display region 112 but also in the peripheral region 114.

[0033] The light-shielding layer 160 has a grid-like pattern that overlaps with the scanning signal lines 107 and the data signal lines 109 in the display region 112. That is, the light-shielding layer 160 has a pattern that opens the transparent regions of the pixels 116 and hides regions that overlap with wiring that blocks transmitted light. In the display region 112, the pixels 116 are periodically arranged in a matrix. The light-shielding layer 160 has a grid-like periodic pattern that overlaps with the scanning signal lines and the data signal lines.

[0034] As will be described later (see FIG. 6A ), the first wiring pattern 118 and the second wiring pattern 120 have a grid pattern. Therefore, the light-shielding layer 160 also has a grid pattern in the peripheral region 114. Note that the wiring density of the first wiring pattern 118 is higher than the wiring density of the scanning signal lines 107 and the data signal lines 109 in the display region 112, so the grid pattern of the light-shielding layer 160 in the region overlapping with the first wiring pattern 118 is denser than the grid pattern of the region overlapping with the display region 112. In other words, the spacing between the wires of the first wiring pattern is narrower than the spacing between the wires of the scanning signal lines 107 and the data signal lines 109 in the display region 112, so the grid pattern of the light-shielding layer 160 in the region overlapping with the first wiring pattern 118 has a smaller grid size than the grid pattern of the region overlapping with the display region 112.

[0035] By having the light-shielding layer 160 have a grid pattern that is continuous from the display region 112 to the peripheral region 114, the entire display panel 102 has the same transmittance, and it is possible to make the boundary between the display region 112 and the peripheral region 114 invisible. As a result, even when the display panel 102 is used as a display device that allows a viewer to see through the back (transparent display), it is possible to make the boundary between the display region 112 and the peripheral region 114 invisible, and to avoid giving an uncomfortable feeling to the overall transparency.

[0036] The light-shielding layer 160 is made of a black resin material or a metal material. The light-shielding layer 160 is formed in contact with the counter electrode 162 (see FIG. 5). By forming the light-shielding layer 160 from a metal material, the counter electrode 162 is formed of a transparent conductive film, and the light-shielding layer 160 can function as an auxiliary electrode to reduce resistance loss. As the metal material for the light-shielding layer 160, chromium, molybdenum, titanium, or the like, which have a relatively low reflectance compared to aluminum, are preferably used.

[0037] A common pad 163 is provided on the counter substrate 152. The common pad 163 is formed in the same layer as the light-shielding layer 160 and is provided so as to be electrically connected to the light-shielding layer 160. The common pad 163 is provided at a position overlapping the common pad 125 of the array substrate 150. The display panel 102 is configured so that the common pad 125 on the array substrate 150 side and the common pad 163 on the counter substrate 152 side are electrically connected to each other. This allows a common voltage to be applied from the array substrate 150 to the counter electrode 162. The common pads 125 and 163 are provided on the periphery of the panel. The light-shielding layer 160 functions as wiring that connects the common pad 163 and the counter electrode 162. The light-shielding layer 160 has a second grid pattern, which can reduce wiring resistance.

[0038] 1-4. Cross-sectional structure of pixel FIG. 5 shows the cross-sectional structure of a pixel 116. As shown in FIG. 5, a transistor 170 is provided on an array substrate 150. The transistor 170 includes a first conductive layer 171 serving as a gate electrode, a first insulating layer 172, a semiconductor layer 173, and a second conductive layer 174 forming a source electrode 174A and a drain electrode 174B. The first insulating layer 172 is interposed between the first conductive layer 171 and the semiconductor layer 173 and functions as a gate insulating layer. The semiconductor layer 173 is formed of, for example, an oxide semiconductor. The source electrode 174A is connected to the data signal line 109, and the drain electrode 174B is connected to a second transparent conductive layer 184 serving as a pixel electrode. The first conductive layer 171 is formed of the same layer as the conductive layer forming the scanning signal line 107, and the source electrode 174A and the drain electrode 174B are formed of the conductive layer forming the data signal line 109. The first insulating layer 172 may have a single-layer structure or a structure in which multiple insulating layers are stacked. For example, the first insulating layer 172 may have a structure in which a silicon nitride layer 172A and a silicon oxide layer 172B are stacked.

[0039] 5 shows an example of a transistor 170 having a bottom-gate (also called inverted staggered) structure in which a first conductive layer 171 as a gate electrode, a first insulating layer 172 as a gate insulating layer, and a semiconductor layer 173 are stacked from the array substrate 150 side, with a source electrode 174A and a drain electrode 174B sandwiching the semiconductor layer 173. The transistor 170 that can be used in the pixel 116 is not limited to the structure shown in FIG. 5, and a top-gate structure can also be applied.

[0040] A second insulating layer 176 is provided on the transistor 170. The second insulating layer 176 is provided as a passivation layer. The second insulating layer 176 may have a single-layer structure or a structure in which multiple insulating layers are stacked. For example, the second insulating layer 176 may have a structure in which a silicon oxide layer 176A and a silicon nitride layer 176B are stacked. Furthermore, a third conductive layer 177 may be provided on the second insulating layer 176 in a region overlapping with the semiconductor layer 173. The third conductive layer 177 is used as a light-shielding layer for the semiconductor layer 173, and is used as a back gate electrode when a certain potential is applied to it.

[0041] A planarization layer 178 is provided on the second insulating layer 176 and the third conductive layer 177. The planarization layer 178 is a transparent organic insulating layer made of an organic material such as acrylic, and is provided to reduce unevenness caused by various members that constitute the transistor 170, such as the first conductive layer 171, the semiconductor layer 173, the source electrode 174A, and the drain electrode 174B.

[0042] As shown in FIG. 5 , a first transparent conductive layer 180 is provided from the upper surface of the planarization layer 178 to the side surface (the stepped portion where the planarization layer 178 has been removed). A fourth conductive layer 181 is provided in a portion of the first transparent conductive layer 180. The first transparent conductive layer 180 is used as a capacitor electrode, and the fourth conductive layer 181 is used as a capacitor wiring. A third insulating layer 182, which is an inorganic insulating layer made of an inorganic material such as silicon nitride, is provided to cover the first transparent conductive layer 180 and the fourth conductive layer 181 and to cover the planarization layer 178 and the second insulating layer 176 exposed from the planarization layer 178. A second transparent conductive layer 184 is provided on the third insulating layer 182. The second transparent conductive layer 184 extends over the region where the planarization layer 178 has been removed, and is provided so that a portion of the second transparent conductive layer 184 overlaps with the first transparent conductive layer 180 via the third insulating layer 182. The second transparent conductive layer 184 forms a pixel electrode. The second transparent conductive layer 184 serving as a pixel electrode is connected to the drain electrode 174B through a contact hole formed in the second insulating layer 176. A storage capacitor is formed in the region where the second transparent conductive layer 184 and the first transparent conductive layer 180 overlap with the third insulating layer 182 interposed therebetween. The array substrate 150 is also provided with a first alignment film (not shown) formed to cover the pixel electrode (second transparent conductive layer 184) and the third insulating layer 182.

[0043] In a display device 100 that allows viewing behind, the planarization layer 178 may be removed in the region where the second transparent conductive layer 184 is provided in order to increase transparency. This reduces light absorption by the planarization layer 178, thereby increasing transparency. Figure 5 shows a structure in which the planarization layer 178 is provided in the region overlapping the transistor 170, and the planarization layer 178 is removed in the region outside the transistor 170 where the second transparent conductive layer that forms the pixel electrode is provided. In the region outside the transistor 170, the second insulating layer 176 is exposed from the planarization layer 178.

[0044] A counter substrate 152 is provided opposite the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 160 and a counter electrode 162. In the structure shown in FIG. 5, the light-shielding layer 160 is provided, for example, in a region overlapping with the source electrode 174A (data signal line 109). The counter electrode 162 has a size that extends over the entire surface of the display region 112. The light-shielding layer 160 may be formed of a metal film as described above, and functions as an auxiliary electrode by being provided in contact with the counter electrode 162 formed of a transparent conductive film. In addition, the counter substrate 152 is provided with a second alignment film (not shown) formed so as to cover the counter electrode 162.

[0045] A liquid crystal layer 126 is provided between the array substrate 150 and the counter substrate 152. The liquid crystal layer 126 is made of polymer dispersed liquid crystal. The polymer dispersed liquid crystal can be in either a normal mode, in which the liquid crystal changes from a scattering state to a non-scattering state (transparent) depending on whether a voltage is applied to the second transparent conductive layer 184 serving as a pixel electrode or not, or a reverse mode, in which the liquid crystal changes from a non-scattering state (transparent) to a scattering state. Because the polymer dispersed liquid crystal does not require a polarizing plate, in the non-scattering state (transparent), the display panel 102 can be seen through, and the rear side can be seen.

[0046] 1-5. Wiring pattern Next, the first wiring pattern 118 and the second wiring pattern 120 will be described in detail with reference to FIGS. 6A, 6B, and 6C.

[0047] 6A shows a first wiring pattern 118 and a second wiring pattern 120 provided on an array substrate 150. The first wiring pattern 118 and the second wiring pattern 120 are provided in the peripheral region 114. The first wiring pattern 118 includes first wiring 119 that connects the scanning signal line driving circuit 106 and the scanning signal lines 107. The second wiring pattern 120 includes second wiring 121 having a common potential.

[0048] The first wirings 119 are arranged appropriately according to the number of scanning signal lines 107. FIG. 6A shows, as an example, a plurality of first wirings 119-1, 119-2, 119-3, 119-4, and 119-5. Focusing on the first wiring 119-1, the first wiring 119-1 includes a first straight portion 119-11 extending in the D2 direction, and a second straight portion 119-12 extending in the D1 direction from one end of the first straight portion 119-11 and connected to the scanning signal line 107. Since the D1 direction and the D2 direction are perpendicular to each other, the first wiring 119-1 has a shape in which a single wiring is bent 90 degrees midway. The other multiple first wirings 119-2, 119-3, 119-4, and 119-5 also have a similar shape, but since the scanning signal lines 107 are arranged at intervals in the D2 direction, the position of the bent portion of the first wiring 119 changes from the upper right to the lower left of the drawing.

[0049] The second wiring pattern 120 has a grid pattern in an area adjacent to the display area 112. In other words, the second wiring 121 is formed in a grid pattern. As will be described with reference to FIG. 3, the second wiring pattern 120 is provided so as to extend from one end to the other end of the array substrate 150. A common potential is applied to the second wiring 121 that forms the second wiring pattern 120, and having the grid pattern reduces wiring resistance.

[0050] Dummy wirings 123 are provided in the first wiring pattern 118 so as to form a grid pattern similar to the second wiring pattern 120. The dummy wirings 123 are provided between the first wirings 119 and between the first wirings 119 and the second wirings 121. The dummy wirings 123 include a plurality of first dummy wirings 123-1 extending in the D2 direction and arranged in the D1 direction, and a plurality of second dummy wirings 123-2 extending in the D1 direction and arranged in the D2 direction.

[0051] The plurality of first dummy wirings 123-1 and the plurality of second dummy wirings 123-2 are arranged at a distance from each other so as not to be connected to the first wirings 119. The plurality of first dummy wirings 123-1 are arranged at a distance in the D1 direction so as to have the same spacing as the grid of the second wiring pattern 120. The plurality of second dummy wirings 123-2 are arranged at a distance in the D2 direction so as to form a grid together with the second straight line portions 190-12 of the first wiring 119. In this way, the first wiring pattern 118 forms a grid pattern with the first wirings 119 and the dummy wirings 123. The first wirings 119 and dummy wirings 123 that form the first wiring pattern 118 and the second wirings 121 that form the second wiring pattern 120 are not connected to each other, but can be seen to have a grid pattern from a bird's eye view.

[0052] FIG. 6B shows the pattern of the light-shielding layer 160 provided on the counter substrate 152. As described with reference to FIG. 4, the light-shielding layer 160 has a first grid pattern and a second grid pattern in the display region 112 and the peripheral region 114. The grid pattern of the light-shielding layer 160 is provided so as to overlap with the first wirings 119 and dummy wirings 123 that form the first wiring pattern 118, and the second wirings 121 that form the second wiring pattern 120. By providing the light-shielding layer 160, it is possible to shield the first wiring pattern 118 and the second wiring pattern 120, which are formed of a metal film, in the peripheral region 114. Furthermore, since the light-shielding layer 160 has a grid pattern that is continuous from the display region 112 to the peripheral region 114, it is possible to achieve the same or similar aperture ratio (the ratio of the light-blocking area to the light-transmitting area per unit area) as the light-shielding layer 160 in the display region 112. This makes it possible to make the transparency of the display area 112 and the peripheral area 114 the same, and to make these two areas indistinguishable from one another.

[0053] 6C is a cross-sectional view of the peripheral region 114, showing the cross-sectional structure of the first wiring pattern 118. As shown in FIG. 6C, the first wiring 119 on the array substrate 150 side is formed by a first conductive layer 171 and a second conductive layer 174. A first insulating layer 172 is provided between the first conductive layer 171 and the second conductive layer 174, but the first conductive layer 171 and the second conductive layer 174 may be connected to each other by a contact hole at any position not shown. The dummy wiring 123 is also formed by the same first conductive layer 171 and second conductive layer 174 as the first wiring 119.

[0054] The first conductive layer 171 and the second conductive layer 174 are formed of a metal film. The metal film is formed of a metal material such as aluminum, titanium, or molybdenum, or a conductive metal compound such as titanium nitride. Although not shown in detail in FIG. 6C , the first conductive layer 171 and the second conductive layer 174 may be formed by stacking multiple metal films. For example, the first conductive layer 171 may be formed by stacking an aluminum layer and a titanium layer. The second conductive layer 174 may have a structure in which titanium layers sandwich an aluminum layer above and below, and a titanium nitride layer may be further provided on the outside thereof.

[0055] The first wiring 119 is buried in a planarization layer 178, and a first transparent conductive layer 180 is provided thereon as a shielding layer. The first transparent conductive layer 180 is provided so as to extend over the entire area in which the first wiring pattern 118 and the second wiring pattern 120 are provided. A fourth conductive layer 181 is provided in contact with the first transparent conductive layer 180. Although not shown in FIG. 6C , the fourth conductive layer 181 has a grid pattern that overlaps with the first wiring 119. The fourth conductive layer 181 may also have a grid pattern that overlaps with the second grid pattern of the light-shielding layer 160. The fourth conductive layer 181 is provided in contact with the first transparent conductive layer 180, which is provided as a shielding layer, and thus functions as an auxiliary wiring that reduces resistance loss in the shielding layer.

[0056] The light-shielding layer 160 on the counter substrate 152 side is provided so as to overlap the first wiring 119. In addition, a counter electrode 162 is provided so as to cover the light-shielding layer 160. Since the peripheral region 114 is not an image display region, the counter electrode 162 is not essential, but by providing the counter electrode 162 in the same manner as the display region 112, it is possible to prevent a difference in transparency (or transmittance) between the display region 112 and the peripheral region 114. The liquid crystal layer 126 in the peripheral region 114 is sandwiched between the first transparent conductive layer 180 as a shield layer and the counter electrode 162, and both are fixed at a constant potential, so that the orientation state of the liquid crystal layer 126 is not affected and the non-scattering state (transparency) can be maintained.

[0057] In this way, in the transparent display, in the peripheral region 114, the first wiring 119 (wiring connecting the scanning signal line driving circuit 106 and the scanning signal lines 107) that forms the first wiring pattern 118 is formed of a wiring portion that extends in the first direction (D1 direction) and a wiring portion that extends in the second direction (D2 direction), and the second wiring 121 (common wiring) that forms the second wiring pattern 120 is also formed of a wiring portion that extends in the first direction (D1 direction) and a wiring portion that extends in the second direction (D2 direction).This makes it possible to form a wiring pattern similar to the wiring group (scanning signal lines 107) that extends in the first direction and the wiring group (data signal lines 109) that extends in the second direction, as in the display region 112, and prevents any difference in appearance (transparency) between the display region 112 and the peripheral region 114 in terms of external light reflection.

[0058] By forming the first wiring pattern 118 and the second wiring pattern 120 in the same pattern, it is possible to make the boundary between the routing wiring and the common wiring of the scanning signal line 107 less noticeable. In addition, by arranging the light-shielding layer 160 having a grid pattern in both the display area 112 and the peripheral area 114, it is possible to make the difference in visibility (transparency) between the display area 112 and the peripheral area 114 uniform.

[0059] [Second embodiment] This embodiment shows an aspect in which the structure of the peripheral region 114 is different from that of the display device 100 shown in the first embodiment.

[0060] FIG. 7A shows a plan view of the first wiring pattern 118 and the second wiring pattern 120 provided on the array substrate 150, and FIG. 7B is a cross-sectional view of the peripheral region 114, showing the cross-sectional structure of the first wiring pattern 118. The first wiring pattern 118 has the same structure as in the first embodiment. The dummy wirings 123 also have the same configuration as in the first embodiment. The first wirings 119, the dummy wirings 123, and the second wirings 121 are provided on a planarization layer 178, but the planarization layer around them has been removed. As shown in FIG. 7A, in the peripheral region 114, the planarization layer 178 has been removed from the region surrounded by the first wirings 119 (119-1 to 119-5), the dummy wirings 123 (123-1, 123-2), and the second wirings 121. As shown in FIG. 7B, the first transparent conductive layer 180 covers the upper and side surfaces of the planarization layer 178 and is provided along the upper surface of the second insulating layer 176 in the area where the planarization layer has been removed.

[0061] As described with reference to FIGS. 1 and 2, light emitted from the light source 104 is incident from the side surface of the counter substrate 152. Here, as shown in FIG. 8, when light is emitted from the light source 104 in the direction D2, if the planarization layer 178 between the wirings is removed, there is a concern that the light will be scattered at the edge portions, resulting in light leakage. FIG. 8 shows a structure in which the first linear portion 119-11 of the first wiring 119 is disposed in the direction D2, and the second linear portion 119-12 is disposed in the direction D1. Corresponding to this wiring pattern, the planarization layer 178 also has a pattern in which portions are removed along the directions D1 and D2. In this case, the portions of the pattern of the planarization layer 178 that extend in a direction parallel to the direction D2 are parallel to the traveling direction of the light emitted from the light source 104, so there is no effect of scattering at the edge portions. On the other hand, in the pattern of the planarization layer 178, the portion extending in a direction intersecting with the D2 direction (D1 direction) intersects with the traveling direction of the light emitted from the light source 104, so there is concern about the influence of scattering at the edge portion.

[0062] To solve this problem, as shown in FIG. 8 , the pattern of the light-shielding layer 160 is made different between the portion extending in the D1 direction and the portion extending in the D2 direction. That is, the width of the portion of the light-shielding layer 160 extending in the D1 direction is wider than the portion extending in the D2 direction. Specifically, the portion extending in the D1 direction is made wider than the width of the planarization layer 178. In this way, by setting the width of the light-shielding layer 160 extending in the D1 direction so as to cover the edge portions of the planarization layer 178, the effect of light leakage can be reduced. On the other hand, in the D2 direction, the effect of scattering at the edge portions of the planarization layer 178 does not need to be considered. Therefore, it is sufficient that the light-shielding layer 160 has a width sufficient to cover the first wiring 119, and the edge portions of the planarization layer 178 extending in the D2 direction may be exposed from the light-shielding layer 160.

[0063] 8 is a schematic partial enlarged view, and as shown in FIG. 7A, the length of the first wiring 119 in the D1 direction is shorter than the length in the D2 direction. Therefore, even if the width of the pattern extending in the D1 direction of the light-shielding layer 160 is increased, the decrease in the aperture ratio is slight. In fact, an improvement in the aperture ratio is expected by narrowing the width of the pattern extending in the D2 direction. In this way, even if the planarization layer 178 between the wirings in the first wiring pattern 118 and the second wiring pattern 120 is removed, by making the pattern width of the light-shielding layer 160 different in the D1 direction and the D2 direction, it is possible to increase the aperture ratio of the light-shielding layer 160 while preventing light leakage.

[0064] According to this embodiment, the peripheral region 114 has an area where the planarization layer 178 is partially removed, similar to the display region 112. With this configuration, the influence of light absorption by the planarization layer 178 can be reduced in the peripheral region 114 as well. Specifically, light absorption on the short wavelength side by the planarization layer 178 is reduced. This makes it possible to make the difference in color tone between the display region 112 and the peripheral region 114 invisible, and to eliminate the difference in transparency. The display device 100 in this embodiment has the same configuration as that in the first embodiment, except that the planarization layer 178 is partially removed, and can achieve the same effects.

[0065] The first to third embodiments described above as embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, liquid crystal display devices of the respective embodiments, to which a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions, are also included within the scope of the present invention as long as they include the gist of the present invention.

[0066] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0067] 100: display device, 102: display panel, 104: light source, 106: scanning signal line drive circuit, 107: scanning signal line, 108: data signal line drive circuit, 109: data signal line, 110: light emission control circuit, 112: display area, 114: peripheral area, 116: pixel, 118: first wiring pattern, 119: first wiring, 119-11: first straight line portion, 119-12: second straight line portion, 120 , 120-1, 120-2: second wiring pattern, 121: second wiring, 122: third wiring pattern, 123: dummy wiring, 123-1: first dummy wiring, 123-2: second dummy wiring, 124: flexible wiring board, 125: common pad, 126: liquid crystal layer, 128: terminal, 130: scanning signal line inspection circuit, 131: ESD protection circuit, 132: data signal line inspection circuit, 13 3: ESD protection circuit, 134: inspection line, 135: ESD protection circuit, 136: QD pad, 137: ESD protection circuit, 150: array substrate, 151A: first transparent substrate, 151B: second transparent substrate, 152: opposing substrate, 154: sealing material, 160: light-shielding layer, 162: opposing electrode, 163: common pad, 170: transistor, 171: first conductive layer, 172: first insulating layer, 172A: silicon nitride layer, 172B: silicon oxide layer, 173: semiconductor layer, 174: second conductive layer, 174A: source electrode, 174B: drain electrode, 176: second insulating layer, 176A: silicon oxide layer, 176B: silicon nitride layer, 177: third conductive layer, 178: planarizing layer, 180: first transparent conductive layer, 181: fourth conductive layer, 182: third insulating layer, 184: second transparent conductive layer

Claims

1. an array substrate including a display area in which pixels are arranged and a peripheral area outside the display area; an opposing substrate facing the array substrate; a liquid crystal layer between the array substrate and the counter substrate, the display area includes a plurality of scanning signal lines extending in a first direction and arranged in a second direction intersecting the first direction, and a plurality of data signal lines extending in the second direction and arranged in the first direction; The peripheral region has a first wiring pattern in which a first grid pattern is formed by a plurality of first wirings connecting a scanning signal line driving circuit and the plurality of scanning signal lines and a plurality of dummy wirings, and a second wiring pattern in which a second grid pattern is formed by second wirings to which a constant potential is applied. A display device characterized by:

2. the opposing substrate has a light-shielding layer, 2. The display device according to claim 1, wherein the light-shielding layer has a third grid pattern that overlaps with the plurality of data signal lines and the plurality of scanning signal lines in the display region, and a fourth grid pattern that overlaps with the first wiring pattern and the second wiring pattern in the peripheral region.

3. The display device according to claim 2 , wherein the light-shielding layer is provided so that the third grid pattern and the fourth grid pattern are continuous with each other.

4. each of the plurality of first wirings has a first linear portion extending in the second direction and a second linear portion extending in the first direction from an end of the first linear portion and connected to one of the plurality of scanning signal lines; 3. The display device of claim 2, wherein the plurality of dummy wirings include a plurality of first dummy wirings extending in the second direction and arranged at a distance in the first direction, and a plurality of second dummy wirings extending in the first direction and arranged in the second direction.

5. The pixel includes a pixel electrode and a transistor connected to the pixel electrode, the array substrate has a planarization layer extending over the display area and the peripheral area; the pixel is provided in a region where the planarization layer has been removed, The display device according to claim 4 , wherein the first wiring pattern and the second wiring pattern are embedded in the planarization layer.

6. The display device according to claim 5 , wherein the planarization layer around the plurality of first wirings, the plurality of dummy wirings, and the second wirings is removed.

7. a light source provided along the first direction and configured to emit light from a side surface of the opposing substrate in the second direction; The display device according to claim 6 , wherein the third grid pattern and the fourth grid pattern of the light-shielding layer have a pattern width along the first direction that is wider than a pattern width along the second direction.

8. The display device according to claim 4 , wherein the plurality of first wirings and the plurality of dummy wirings are provided in the same conductive layer.

9. The display device according to claim 1 , further comprising a light source provided along the first direction and configured to emit light in the second direction from a side surface of the opposing substrate.

10. 9. The display device according to claim 1, wherein the liquid crystal layer is a polymer dispersed liquid crystal.

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