Display panel and manufacturing method thereof

Abstract

In an embodiment of the present invention, a display panel and a manufacturing method thereof are disclosed. The display panel includes a substrate, a plurality of anodes located on the substrate, and a plurality of pixel definition portions that cover edges of the anodes and expose a part of the anodes. Here, one of the pixel definition portions is arranged to surround one of the anodes, and adjacent pixel definition portions are spaced apart. The pixel definition portion includes a first side surface far from the anode in a direction parallel to the substrate. The first side surface forms a first included angle with the substrate, with the side closer to the substrate, and the first included angle is 35° or more and 45° or less.

Description

[Technical Field]

[0001] The present application relates to the display field, and in particular to a display panel and a manufacturing method thereof. [Background technology]

[0002] With the development of display technology, OLED (Organic Light-Emitting Diode) display panels have been widely used due to their advantages such as high brightness, low power consumption, fast response, high resolution, and high luminous efficiency.

[0003] However, in an OLED display panel, light-emitting elements are formed in openings formed in a pixel definition layer formed over the entire surface, and therefore, there is a technical problem that the pixel definition layer is difficult to remove stress from, which affects the quality of the display panel.

[0004] Therefore, a display panel and a manufacturing method thereof are desired to solve the above technical problems. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a display panel and a manufacturing method thereof, which can solve the technical problem that a pixel definition layer is formed on all layers of a current display panel, making it difficult to relieve stress and affecting the quality of the display panel. [Means for solving the problem]

[0006] In order to solve the above problems, the technical solutions provided by this application are as follows:

[0007] The present invention provides a display panel including: a substrate; a plurality of anodes disposed on the substrate; and a plurality of pixel definition portions covering edges of the anodes and exposing portions of the anodes, wherein each pixel definition portion is disposed to surround one of the anodes and adjacent pixel definition portions are disposed at an interval, and each pixel definition portion includes a first side surface farther from the anodes in a direction parallel to the substrate, and a side of the first side surface closer to the substrate forms a first included angle with the substrate, the first included angle being equal to or greater than 35° and equal to or less than 45°.

[0008] Preferably, the display panel further includes a first metal layer, the first metal layer being sandwiched between the anode and the substrate; the display panel further includes a first insulating layer, the first insulating layer being sandwiched between the first metal layer and the anode; the first insulating layer including a first via hole; the anode including a first connection portion located in the first via hole; the first connection portion being connected to the first metal layer; and the pixel definition portion covering the first connection portion.

[0009] Preferably, the display panel further includes an active layer, the active layer being sandwiched between the first metal layer and the substrate, the active layer including a channel portion and a first conductor sub-portion and a second conductor sub-portion respectively located on opposite sides of the channel portion, the first metal layer including a source and a drain, the source being located in the first conductor sub-portion and the drain being located in the second conductor sub-portion, wherein at least a portion of the source is in contact with the first conductor sub-portion on the side closer to the active layer, and at least a portion of the drain is in contact with the second conductor sub-portion on the side closer to the active layer.

[0010] Preferably, the display panel further includes a gate, the gate being sandwiched between the source and the drain, and a positive projection of the gate in the active layer covering the channel portion, and the display panel further includes a gate insulating layer, the gate insulating layer being sandwiched at least between the gate and the channel portion.

[0011] Preferably, the gate is located in the first metal layer, and the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion arranged at a distance from each other, the first insulating portion being sandwiched between the channel portion and the gate, the second insulating portion being sandwiched between a portion of the source and the first conductor sub-portion, the third insulating portion being sandwiched between a portion of the drain and the second conductor sub-portion, and an end of the source close to the gate contacting the first conductor sub-portion and an end of the drain close to the gate contacting the second conductor sub-portion.

[0012] Preferably, the gate is located on the side of the first metal layer remote from the substrate, there is no insulating layer between the source and the first conductor sub-portion, and there is no insulating layer between the drain and the second conductor sub-portion.

[0013] Preferably, in a plane parallel to the substrate, an edge of the source farther from the gate extends beyond an edge of the first conductor sub-portion farther from the channel portion in a direction from the channel portion toward the first conductor sub-portion, and in a plane parallel to the substrate, an edge of the drain farther from the gate extends beyond an edge of the second conductor sub-portion farther from the channel portion in a direction from the channel portion toward the second conductor sub-portion.

[0014] Preferably, the display panel further includes a second metal layer sandwiched between the active layer and the substrate, the second metal layer including a first light-shielding portion, and an orthogonal projection of the active layer on the substrate located within an orthogonal projection of the first light-shielding portion on the substrate. The display panel further includes a buffer layer located on a side of the active layer closer to the substrate, the buffer layer covering the second metal layer.

[0015] Preferably, the first insulating layer includes a passivation layer on a side closer to the substrate, and the buffer layer is sandwiched between the second metal layer and the active layer, the side of the buffer layer farther from the substrate being in direct contact with the active layer and the passivation layer, and the side of the buffer layer closer to the substrate being in direct contact with the second metal layer and the substrate.

[0016] Preferably, when the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart, an end of the second insulating portion that is far from the first insulating portion contacts the buffer layer, and an end of the third insulating portion that is far from the first insulating portion contacts the buffer layer.

[0017] Preferably, the first insulating layer further includes a second via hole, the second via hole being located on one side of the active layer. The buffer layer includes a third via hole, the third via hole being in communication with the second via hole, and the anode is connected to the first light-shielding portion through the second and third via holes. The anode includes a second connection portion, and an orthogonal projection of the pixel definition portion on the substrate covers an orthogonal projection of the second connection portion on the substrate.

[0018] Preferably, the gate insulating layer includes a fourth via hole, the fourth via hole being located on a side of the second insulating part farther from the active layer, the buffer layer includes a fifth via hole, the fourth via hole is in communication with the fifth via hole, and the source is connected to the first light-shielding part through the fourth via hole and the fifth via hole.

[0019] Preferably, the gate insulating layer includes a sixth via hole, the sixth via hole being located on a side of the third insulating part farther from the active layer, the buffer layer includes a seventh via hole, the sixth via hole being connected to the seventh via hole, and the drain being connected to the first light-shielding part through the sixth via hole and the seventh via hole.

[0020] Preferably, the display panel includes a display area and a non-display area located on at least one side of the display area, and the display panel further includes terminals located in the non-display area, the terminals being located on the first metal layer, wherein the terminals include first type terminals, and the first type terminals are connected to the second metal layer.

[0021] Preferably, when the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart, the gate insulating layer further includes a fourth insulating portion sandwiched between the terminal and the buffer layer, the gate insulating layer further includes an eighth via hole, the eighth via hole penetrating the fourth insulating portion, the buffer layer including a ninth via hole, the ninth via hole penetrating the buffer layer sandwiched between the wiring of the second metal layer and the fourth insulating portion, and an orthogonal projection of the eighth via hole on the substrate covers an orthogonal projection of the ninth via hole on the substrate. The first class terminal includes a first class terminal connection portion, the first class terminal connection portion being located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole exposing the wiring of the second metal layer, and the first class terminal connection portion being in contact with the wiring of the second metal layer.

[0022] Preferably, the pixel definition portion has an overlapping portion with the anode, and the width of the overlapping portion as orthogonally projected on the substrate is 2 μm or more.

[0023] Preferably, the display panel further includes an organic layer located on a side of the anode farther from the substrate, the organic layer including an emissive layer, the pixel definition portion including a second side surface closer to the anode in a direction parallel to the substrate, and an orthogonal projection of the anode on the substrate and an orthogonal projection of the second side surface on the substrate both covering an orthogonal projection of the emissive layer on the substrate.

[0024] Preferably, the second side surface closer to the anode forms a second included angle of 35° or more with the anode, and the second included angle is 35° or more and 45° or less.

[0025] The present invention further provides a method for manufacturing a display panel, the method comprising: Providing a substrate; forming an anode material layer on the substrate; forming a pixel defining material layer on the anode material layer; forming the anode material layer and the pixel defining material layer into a plurality of anodes and a plurality of pixel defining portions, respectively, through a first patterning process; Here, the pixel definition portion covers the edge of the anode and exposes a part of the anode, one pixel definition portion is arranged surrounding one anode, and adjacent pixel definition portions are arranged with a gap between them.

[0026] Preferably, before forming an anode material layer on the substrate, forming a layer of semiconductor material on the substrate; forming a first metal layer on the semiconductor material layer such that the first metal layer is in direct contact with the semiconductor material layer; forming the semiconductor material layer and the first metal material layer into a semiconductor layer and a first metal layer, respectively, through a second patterning process; Here, the first metal layer includes a source and a drain, and the source and the drain are located on opposite sides of the semiconductor layer, respectively. [Effects of the Invention]

[0027] In the present invention, by arranging the pixel defining portions in one-to-one correspondence with the anodes, adjacent pixel defining portions are spaced apart, reducing the stress on the pixel defining portions and making the slope of the first side of the pixel defining portion more gentle, thereby increasing the contact area between the pixel defining portion and the adjacent film layer, strengthening the strength of the bond between the pixel defining portion and the adjacent film layer, and improving the product quality of the display panel. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a structural schematic diagram showing a first configuration of a display panel provided by an embodiment of the present invention; [Figure 2] FIG. 2 is a structural schematic diagram showing a second structure of a display panel provided by an embodiment of the present invention. [Figure 3] 1 is a step flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention. [Figure 4a] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4b] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4c] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4d] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4e] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4f] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4g] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4h] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4i] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4j] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4k] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4l] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; [Figure 4m] 1 is a flow diagram illustrating a method for manufacturing a display panel provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0029] The present application provides a display module, and in order to make the objectives, technical solutions and effects of the present application clearer, the present application will be described in more detail below by way of examples with reference to the accompanying drawings. It should be understood that the embodiments described herein are merely for the purpose of illustrating the present application and are not intended to limit the present application.

[0030] Conventionally, since the pixel definition layer is formed over the entire surface of a display panel, it is difficult to remove stress from the pixel definition layer, which has a technical problem of affecting the quality of the display panel.

[0031] Referring to FIGS. 1 and 2, an embodiment of the present invention provides a display panel 100, which comprises: a substrate 101; a plurality of anodes 102 located on the substrate 101; a plurality of pixel defining portions 103 that cover the edges of the anode 102 and expose portions of the anode 102; Here, one pixel definition section 103 is disposed surrounding one anode 102, and adjacent pixel definition sections 103 are disposed with an interval therebetween.

[0032] The pixel defining portion 103 includes a first side 103a that is farther from the anode 102 in a direction parallel to the substrate 101, and the side of the first side 103a that is closer to the substrate 101 forms a first included angle α with the substrate 101, and the first included angle α is greater than or equal to 35° and less than or equal to 45°.

[0033] In the embodiment of the present invention, the pixel defining portions 103 are arranged in one-to-one correspondence with the anodes 102, so that adjacent pixel defining portions 103 are spaced apart, which reduces the stress experienced by the pixel defining portions 103. At the same time, the slope of the first side 103 a of each pixel defining portion 103 is made gentler, which increases the contact area between the pixel defining portion 103 and the adjacent film layer, strengthens the bond between the pixel defining portion 103 and the adjacent film layer, and improves the product quality of the display panel 100.

[0034] The technical solution of the present invention will be described below with specific examples.

[0035] 1 and 2, in this embodiment, the display panel 100 further includes a first metal layer 104 , which is sandwiched between the anode 102 and the substrate 101 .

[0036] The display panel 100 further includes a first insulating layer sandwiched between the first metal layer 104 and the anode 102, the first insulating layer including a first via hole H1, the anode 102 including a first connection portion located in the first via hole H1, the first connection portion being connected to the first metal layer 104, and the pixel definition portion 103 covering the first connection portion.

[0037] In some embodiments, the first metal layer 104 may be a single layer or multiple layers of a low-resistivity material such as Al, Ti, Mo, Cu, Ni, or alloys containing these metals. For example, the first metal layer 104 may be a three-layer stack of MoTi / Cu / MoTi, which is made of MoTi and Cu.

[0038] When the first metal layer 104 has a three-layer structure of MoTi / Cu / MoTi consisting of a MoTi layer, a Cu layer, and a MoTi layer, the thickness of the MoTi layer closer to the substrate 101 is 250 Å to 350 Å, the thickness of the Cu layer is 4200 Å to 6500 Å, and the thickness of the MoTi layer farther from the substrate 101 is 400 Å to 500 Å.

[0039] In some embodiments, the anode 102 includes a material having a high work function. The anode 102 may include any one of transparent conductive materials having a relatively high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3). In addition to the conductive materials described above, the anode 102 may include a reflective material, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a combination thereof. The anode 102 may be composed of a single layer or multiple layers of transparent conductive material and / or reflective conductive material. For example, the anode 102 may have a triple-layer structure of IZO / Ag / IZO, composed of IZO and Ag. In this case, the thickness of the IZO layer closer to the substrate 101 is 100 Å to 200 Å, the thickness of the Ag layer is 1000 Å to 1500 Å, and the thickness of the IZO layer farther from the substrate 101 is 700 Å to 1000 Å.

[0040] 1 and 2, in this embodiment, the pixel defining portion 103 is disposed to surround the anode 102 and has a pixel defining opening that exposes the anode 102.

[0041] In some embodiments, the material of the pixel defining portion 103 is selected from organic materials such as a positive photoresist material or a negative photoresist material, and the material of the pixel defining portion 103 can be used as a photoresist. The pixel defining portion 103 and the anode 102 can be formed by the same patterning process, which reduces the number of manufacturing steps and reduces process costs. To form the pixel defining opening with a sufficient depth, the thickness of the pixel defining portion 103 may be 2.8 μm to 3.7 μm, for example, 3 μm, 3.2 μm, 3.4 μm, 3.5 μm, 3.6 μm, etc.

[0042] In some embodiments, the first insulating layer includes a passivation layer 112 on a side closer to the substrate 101 and a planarization layer 113 on a side farther from the substrate 101, where the passivation layer 112 covers at least the first metal layer 104, and the planarization layer 113 serves to provide a planar surface for forming the anode 102, which can be formed directly on the planarization layer 113, the side farther from the buffer layer 111. Furthermore, the first insulating layer may be composed of the passivation layer 112 and the planarization layer 113.

[0043] The material of the passivation layer 112 is selected from inorganic materials such as silicon nitride compounds or silicon oxide compounds, and the material of the planarization layer 113 may be selected from organic materials such as positive photoresist materials or negative photoresist materials, so that the passivation layer 112 and the planarization layer 113 can be formed by the same patterning process, reducing the number of manufacturing steps and reducing the process cost.

[0044] To completely cover the first metal layer 104, the passivation layer 112 may have a thickness of 3500 Å to 5000 Å, such as 3600 Å, 3800 Å, 4000 Å, 4200 Å, 4500 Å, 4800 Å, etc. To provide a flat surface, the planarization layer 113 may have a thickness of 3500 Å to 5000 Å, such as 3600 Å, 3800 Å, 4000 Å, 4200 Å, 4500 Å, 4800 Å, etc.

[0045] The first via hole H1 exposes the first metal layer 104, and the anode 102 includes a first connection portion located in the first via hole H1, which contacts the first metal layer 104 within the first via hole H1, thereby realizing connection between the anode 102 and the first metal layer 104. Since the first connection portion is filled in the first via hole H1 to be connected to the first metal layer 104, the pixel definition portion 103 covers the first via hole H1 to prevent an organic layer (e.g., an emitting layer) formed on the anode 102 from sinking into the first via hole H1.

[0046] When the first insulating layer is composed of the passivation layer 112 and the planar layer 113, the first via hole H1 includes a first sub-via hole located in the passivation layer 112 and a second sub-via hole located in the planar layer 113.

[0047] In some embodiments, the substrate 101 may be a rigid substrate or a flexible substrate, and if the substrate 101 is a rigid substrate, the substrate 101 may be a glass substrate. If the substrate 101 is a flexible substrate, the material of the substrate 101 may be polyimide.

[0048] Referring to Figures 1 and 2, in this embodiment, the first metal layer 104 includes a source 106 and a drain 107, the first via hole H1 exposes the source 106, and the first connection portion contacts the source 106, or the first metal layer 104 exposes the drain 107, and the first connection portion contacts the drain 107.

[0049] Referring to Figures 1 and 2, in this embodiment, the display panel 100 further includes an active layer 105, which is sandwiched between the first metal layer 104 and the substrate 101, and which includes a channel portion 105a and a first conductor sub-portion 105b and a second conductor sub-portion 105c located on opposite sides of the channel portion 105a.

[0050] The source 106 is located in the first conductor sub-portion 105b, and the drain 107 is located in the second conductor sub-portion 105c.

[0051] Here, at least a portion of the source 106 contacts the first conductor sub-portion 105b on the side closer to the active layer 105, and at least a portion of the drain 107 contacts the second conductor sub-portion 105c on the side closer to the active layer 105.

[0052] In some embodiments, the material of the active layer 105 may be selected from conductive oxide materials such as indium gallium zinc oxide (IGZO). During the formation of the active layer 105, the first conductive sub-portion 105b and the second conductive sub-portion 105c can be made conductive by ion implantation, ion bombardment, or other methods. When using ion implantation, specific doping elements or particles include, but are not limited to, H, He, B, Al, N, F, P, Ar, and S. When using plasma bombardment, high-energy particles bombard the material surface of the active layer 105 to form defects (oxygen defects). These oxygen defects generate carriers, increasing the conductive properties, thereby making the first conductive sub-portion 105b and the second conductive sub-portion 105c conductive.

[0053] In some embodiments, the material of the active layer 105 may be selected from polysilicon.

[0054] In this embodiment, the thickness of the active layer 105 may be 200 Å to 500 Å, for example, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, or the like.

[0055] 1 and 2, in this embodiment, the display panel 100 further includes a gate 108, which is located on the side of the active layer 105 farther from the buffer layer 111, and is sandwiched between the source 106 and the drain 107, and the orthogonal projection of the gate 108 on the active layer 105 covers the channel portion 105a.

[0056] In this embodiment, the display panel 100 further includes a gate insulating layer 109, which is located on a side of the gate 108 closer to the active layer 105, and is sandwiched between at least the gate 108 and the channel region 105a. The planarization layer 113 covers the gate insulating layer 109, the first metal layer 104, and / or the gate 108.

[0057] In some embodiments, the material of the gate 108 may be selected from low resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys containing these metals, and the gate 108 may have a single layer or multi-layer structure composed of the above metals or alloys.

[0058] Referring to FIG. 1, in some embodiments, the gate 108 is located on the first metal layer 104, and the source 106, the drain 107, and the gate 108 can be formed using the same material and the same process, allowing for manufacturing with fewer processes and reducing process costs.

[0059] In some embodiments, the material of the gate insulating film 109 may be selected from at least one of silicon nitride and silicon oxy compound. The gate insulating film 109 may be composed of a single layer or multiple layers of silicon nitride or silicon oxy compound, for example, the gate insulating film 109 may have a single layer structure composed of silicon oxide.

[0060] The thickness of the gate insulating film 109 is 1000 Å to 2000 Å, and may be, for example, 1200 Å, 1500 Å, or 1800 Å.

[0061] In some embodiments, the gate 109 includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart, the first insulating portion being sandwiched between the channel portion 105a and the gate 108, the second insulating portion being sandwiched between a portion of the source 106 and the first conductor sub-portion 105b, and the third insulating portion being sandwiched between a portion of the drain 107 and the second conductor sub-portion 105c.

[0062] The first insulating portion, the second insulating portion, and the third insulating portion are spaced apart, i.e., their orthogonal projections on the substrate 101 are spaced apart from one another. A cut is made between the first insulating portion and the second insulating portion, and a cut is made between the first insulating portion and the third insulating portion. The gate insulating layer 109 includes a first opening sandwiched between the first insulating portion and the second insulating portion, and the gate insulating layer 109 includes a second opening sandwiched between the first insulating portion and the third insulating portion.

[0063] The first insulating portion is sandwiched between the channel portion 105a and the gate 108, i.e., the channel portion 105a and the gate 108 are located on both sides of the first insulating portion in the direction from the substrate 101 toward the first metal layer 104. The side of the gate 108 closer to the first insulating portion is in direct contact with the first insulating portion, and the side of the first insulating portion closer to the active layer 105 is in direct contact with the channel portion 105a. The orthogonal projection of the gate 108 on the substrate 101 is located within the orthogonal projection of the first insulating portion on the buffer layer 111, and the orthogonal projection of the channel portion 105a on the substrate 101 is located within the orthogonal projection of the first insulating portion on the buffer layer 111.

[0064] The second insulating portion is sandwiched between a portion of the source 106 and the first conductor sub-portion 105b, the side of the second insulating portion closer to the buffer layer 111 directly contacts the end of the first conductor portion 105b far from the channel portion 105a, the second insulating portion covers at least a portion of the end of the first conductor sub-portion 105b far from the channel portion 105a, the end of the source 106 closer to the gate 108 contacts the first conductor sub-portion 105b through the first opening, and the end of the source 106 closer to the gate 108 covers the end of the second insulating portion closer to the first insulating portion.

[0065] The third insulating portion is sandwiched between a portion of the source 106 and the second conductor sub-portion 105c, the side of the third insulating portion closer to the buffer layer 111 directly contacts the end of the second conductor sub-portion 105c far from the channel portion 105a, the third insulating portion covers at least a portion of the end of the second conductor sub-portion 105c far from the channel portion 105a, the end of the drain 107 closer to the gate 108 contacts the second conductor sub-portion 105c through the second opening, and the end of the drain 107 closer to the gate 108 covers the end of the third insulating portion closer to the first insulating portion.

[0066] 2, in some embodiments, there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c. That is, the source 106 is located directly on the first conductor sub-portion 105b, and the drain 107 is located directly on the second conductor sub-portion 105c. This advantageously allows the first metal layer 104 and the active layer 105 to be formed in a single patterning process, which facilitates process simplification and reduces process costs.

[0067] When there is no insulating layer between the source 106 and the first conductor subportion 105b and no insulating layer between the drain 107 and the second conductor subportion 105c, the gate 108 is located on the side of the first metal layer 104 farther from the buffer layer 111, and the gate insulating layer 109 is sandwiched between the channel portion 105a and the gate 108. The orthogonal projection of the gate 108 on the buffer layer 111 is located within the orthogonal projection of the gate insulating layer 109 on the buffer layer 111, and the orthogonal projection of the channel portion 105a on the buffer layer 111 is located within the orthogonal projection of the gate insulating layer 109 on the buffer layer 111. In this case, the material of the gate 108 may be a two-layer structure consisting of a Cu layer and a MoTi alloy layer, where the Cu layer is located on the side of the gate 108 farther from the buffer layer 111. The thickness of the Cu layer is 1800 Å to 4200 Å, and may be, for example, 1900 Å, 2500 Å, 3000 Å, 3500 Å, 4000 Å, etc. The thickness of the MoTi alloy layer is 250 Å to 350 Å, and may be, for example, 280 Å, 300 Å, 320 Å, 340 Å, etc.

[0068] If there is no insulating layer between the source 106 and the first conductor sub-portion 105b and no insulating layer between the drain 107 and the second conductor sub-portion 105c, then in a plane parallel to the substrate 101, along the direction from the channel portion 105a to the first conductor sub-portion 105b, the edge of the source 106 remote from the gate 108 extends beyond the edge of the first conductor sub-portion 105b remote from the channel portion 105a, and in a plane parallel to the substrate 101, along the direction from the channel portion 105a to the second conductor sub-portion 105c, the edge of the drain 107 remote from the gate 108 extends beyond the edge of the second conductor sub-portion 105c remote from the channel portion 105a.

[0069] In this embodiment, the thin film transistor device of the display panel 100 is composed of the gate 108 , the source 106 , the drain 107 and the active layer 105 .

[0070] 1 and 2, in this embodiment, the display panel 100 further includes a second metal layer 110, which is sandwiched between the active layer 105 and the substrate 101. The second metal layer 110 includes a first light-shielding portion 110a, and the orthogonal projection of the active layer 105 on the buffer layer 111 is located within the orthogonal projection of the first light-shielding portion 110a on the buffer layer 111. The arrangement of the first light-shielding portion 110a is advantageous in preventing light from the substrate 101 from irradiating the active layer 105 and interfering with the operating performance of the active layer 105.

[0071] In some embodiments, the material of the second metal layer 110 may be selected from metal materials such as Al, Ti, Mo, Cu, Ni, or alloys thereof. The second metal layer 110 may be a single layer or multiple layers composed of these metal materials or alloys containing these metal materials. For example, the second metal layer 110 may have a MoTi / Cu double-layer structure composed of a Cu layer and a MoTi alloy layer, with the MoTi alloy layer located closer to the substrate 101 and the Cu layer located farther from the substrate 101. The MoTi / Cu structure of the second metal layer 110, combining the light-shielding properties of MoTi with the conductive properties of Cu, is advantageous for achieving light-shielding while maintaining the conductivity of the wiring in the second metal layer 110. Preferably, the thickness of the MoTi alloy layer is 250 Å to 350 Å, such as 280 Å, 300 Å, 320 Å, or 340 Å. The thickness of the Cu layer is 2800 Å to 8000 Å, and may be, for example, 2900 Å, 3000 Å, 3500 Å, 4000 Å, 4500 Å, 5000 Å, 5500 Å, 6000 Å, 6500 Å, 7000 Å, 7500 Å, or the like.

[0072] The display panel 100 further includes a buffer layer 111 , which is located closer to the active layer 105 and covers the second metal layer 110 .

[0073] The buffer layer 111 is sandwiched between the second metal layer 110 and the active layer 105, and the side of the buffer layer 111 farther from the substrate 101 is in direct contact with the active layer 105, and the side of the buffer layer 111 farther from the substrate 101 is in direct contact with the passivation layer 112.

[0074] In some embodiments, the side of the buffer layer 111 closest to the substrate 101 is in direct contact with the second metal layer 110 , and the side of the buffer layer 111 closest to the substrate 101 is in direct contact with the substrate 101 .

[0075] In some embodiments, the material of the buffer layer 111 is selected from at least one of a silicon nitride compound and a silicon oxy compound. The buffer layer 111 may be a single layer or a stack of layers made of a silicon nitride compound or a silicon oxy compound. For example, the buffer layer 111 includes a first buffer sublayer and a second buffer sublayer, the first buffer sublayer being made of a silicon nitride compound and the second buffer sublayer being made of a silicon oxy compound, the first buffer sublayer being located on a side of the buffer layer 111 closer to the substrate 101, and the second buffer sublayer being located on a side of the buffer layer 111 farther from the substrate 101. The thickness of the first buffer sublayer is between 500 Å and 2000 Å, and may be, for example, 800 Å, 1000 Å, 1200 Å, 1500 Å, 1800 Å, etc. The second buffer sub-layer may have a thickness of 2000 Å to 3000 Å, for example, 2200 Å, 2500 Å, 2600 Å, 2800 Å, etc.

[0076] When the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are spaced apart, the end of the second insulating portion far from the first insulating portion contacts the buffer layer 111, and the end of the third insulating portion far from the first insulating portion contacts the buffer layer 111.

[0077] In some embodiments, the first light-shielding portion 110a is connected to the source 106, or the first light-shielding portion 110a is connected to the drain 107. The connection between the first light-shielding portion 110a and the source 106 or the drain 107 prevents electrical drift of the thin film transistor device due to the first light-shielding portion 110a, thereby improving the operating performance of the thin film transistor device.

[0078] 2, when the gate 108 is located on the side of the first metal layer 104 farther from the buffer layer 111, and there is no insulating layer between the source 106 and the first conductor sub-portion 105b and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c, the source 106 and the first light-shielding portion 110a are connected through the anode 102, or the drain 107 and the first light-shielding portion 110a are connected through the anode 102. In this case, the first insulating layer further includes a second via hole located on one side of the active layer 105, the buffer layer 111 includes a third via hole therein, the third via hole communicates with the second via hole, and the anode 102 is connected to the first light-shielding portion 110a through the second and third via holes. The anode 102 includes the second connection portion, and the orthogonal projection of the pixel definition portion 103 on the substrate 101 covers the orthogonal projection of the second connection portion on the substrate 101. Specifically, the buffer layer 111 includes a buffer portion covering the first light-shielding portion 110a, the second via hole penetrates the first insulating layer, the third via hole penetrates the buffer portion of the buffer layer 111, and the orthogonal projection of the second via hole on the substrate 101 covers the orthogonal projection of the third via hole on the substrate 101. The second and third via holes expose the first light-shielding portion 110a, and the second connection portion contacts the first light-shielding portion 110a. When the anode 102 is connected to the source 106, the source 106 is connected to the first light-shielding portion 110a via the anode 102. When the anode 102 is connected to the drain 107, the drain 107 is connected to the first light-shielding portion 110a through the anode 102.

[0079] When the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are spaced apart, the gate insulating layer 109 includes a fourth via hole that is located on a side of the second insulating portion far from the active layer 105, the buffer layer 111 includes a fifth via hole that is located on the buffer layer 111 and communicates with the fifth via hole, and the source 106 is connected to the first light-shielding portion 110a through the fourth and fifth via holes. Specifically, the buffer layer 111 includes a buffer portion that covers the first light-shielding portion 110a, the fourth via hole penetrates the side of the second insulating portion far from the active layer 105, the fifth via hole penetrates the buffer portion, and the orthographic projection of the fourth via hole on the substrate 101 covers the orthographic projection of the fifth via hole on the substrate 101. The source 106 includes a source 106 connection portion, the source 106 connection portion is located in the fourth via hole and the fifth via hole, the fourth via hole and the fifth via hole expose the first light-shielding portion 110a, and the source 106 connection portion contacts the first light-shielding portion 110a, thereby realizing the connection between the source 106 and the first light-shielding portion 110a.

[0080] 1 , when the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are spaced apart, the gate insulating layer 109 preferably includes a sixth via hole penetrating a side of the third insulating portion farther from the active layer 105, the buffer layer 111 preferably includes a seventh via hole penetrating the buffer layer 111, the sixth via hole being in communication with the seventh via hole, and the drain 107 being connected to the first light-shielding portion 110a through the sixth and seventh via holes. Specifically, the sixth via hole penetrates a side of the third insulating layer farther from the active layer 105, the seventh via hole penetrates a buffer portion, and the orthographic projection of the sixth via hole on the substrate 101 covers the orthographic projection of the seventh via hole on the substrate 101. The drain 107 includes a drain 107 connection portion, which is located in the sixth via hole and the seventh via hole, which expose the first light-shielding portion 110a, and which contacts the first light-shielding portion 110a to realize the connection between the drain 107 and the first light-shielding portion 110a.

[0081] In this embodiment, the display panel 100 includes a display area and a non-display area located on at least one side of the display area, and the display panel 100 further includes a terminal located in the non-display area, the terminal being located on the first metal layer 104.

[0082] The non-display area has a plurality of terminals including a first type terminal connected to the second metal layer 110. The second metal layer 110 further includes wiring of the second metal layer, and the first type terminal is connected to the wiring of the second metal layer.

[0083] When the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are spaced apart, the gate insulating layer 109 further includes a fourth insulating portion sandwiched between the terminal and the buffer layer 111, the gate insulating layer 109 further includes an eighth via hole penetrating the fourth insulating portion, the buffer layer 111 includes a ninth via hole penetrating the buffer layer 111 between the wiring of the second metal layer and the fourth insulating portion, and an orthogonal projection of the eighth via hole on the substrate 101 covers an orthogonal projection of the ninth via hole on the substrate 101. The first type terminal includes a first type terminal connection portion, and the first type terminal connection portion is located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the wiring of the second metal layer, and the first type terminal connection portion contacts the wiring of the second metal layer.

[0084] When the gate 108 is located on the side of the first metal layer 104 farther from the buffer layer 111, there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c, the buffer layer 111 includes a tenth via hole, the tenth via hole penetrates the buffer layer 111 between the wiring of the second metal layer and the first type terminal, the first type terminal includes the first type terminal connection portion, the first type terminal connection portion is located in the tenth via hole, the tenth via hole exposes the wiring of the second metal layer, and the first type terminal connection portion contacts the wiring of the second metal layer.

[0085] In some embodiments, the pixel defining portion 103 has an overlapping portion with the anode 102, and the width of the overlapping portion as orthogonal projection on the substrate 101 is 2 μm or more, thereby preventing the edge of the anode 102 from being exposed due to process errors and facilitating the covering of the first connecting portion and / or the second connecting portion. The anode 102 has a central portion not covered by the pixel defining portion 103 and a peripheral portion covered by the pixel defining portion 103, and the orthogonal projection of the peripheral portion on the substrate 101 overlaps with the orthogonal projection of the overlapping portion on the substrate 101. The overlapping portion includes a first side closer to the central portion and a second side farther from the central portion, and the width of the overlapping portion as orthogonal projection on the substrate 101 is 2 μm or more, i.e., the minimum distance between the first side and the second side is 2 μm or more.

[0086] In some embodiments, the spacing between adjacent anodes 102 is 7 μm or more, which allows for a sufficient distance between the pixel defining portions 103 while still ensuring sufficient resolution, thereby reducing stress on the pixel defining portions 103 and improving the light emission rate of the display panel 100.

[0087] 1 and 2, in this embodiment, the planar layer 113 is parallel to the substrate 101, the pixel defining portion 103 is in direct contact with the planar layer 113, and the first included angle α is equal to the included angle between the first side surface 103a and the planar layer 113. The first included angle α is 35° or more and 45° or less, for example, the first included angle α may be 36°, 37°, 38°, 39°, 40°, 41°, 42°, 43°, 44°, etc. When the value of the first included angle α is within the above range, the slope of the first side surface 103a becomes gentler, and the total surface area of ​​the pixel defining portion 103 is increased without changing the height, which is advantageous for increasing the contact area between the pixel defining portion 103 and an adjacent film layer, strengthening the strength of the bond between the pixel defining portion 103 and the adjacent film layer, making it difficult for the film layer to separate when the display panel 100 is applied in a folding scenario, and improving the product quality of the display panel 100.

[0088] 1 and 2, in this embodiment, the display panel 100 further includes an organic layer 119 located on a side of the anode 102 farther from the buffer layer 111, and the organic layer 119 includes an emitting layer 120. The pixel defining portion 103 includes a second side 103b adjacent to the anode 102 in a direction parallel to the substrate 101, and the orthogonal projection of the anode 102 on the substrate 101 and the orthogonal projection of the second side 103b on the substrate 101 both cover the orthogonal projection of the emitting layer 120 on the substrate 101. That is, the emitting layer 120 is disposed within the pixel defining opening, and an edge of the emitting layer 120 does not extend beyond the second side 103b. The orthogonal projection of the anode 102 on the buffer layer 111 and the orthogonal projection of the second side surface 103b on the buffer layer 111 both cover the orthogonal projection of the light-emitting layer 120 on the buffer layer 111, which is advantageous in preventing light-emitting layers with different emission colors (e.g., red, green, and blue) from mixing outside the pixel definition region 103 and affecting the display quality of the display panel 100.

[0089] 1 and 2 , in some embodiments, the side of the second side surface 103b closest to the anode 102 forms a second included angle β with the anode 102 that is 35° or greater, and the second included angle β is 45° or less. For example, the second included angle β may be 36°, 37°, 38°, 39°, 40°, 41°, 42°, 43°, 44°, etc. When the second included angle β is within the above range, the second side surface 103b becomes more gentle, which is advantageous for forming the light-emitting layer 120 so that it does not extend beyond the second side surface 103b.

[0090] In this embodiment, the organic layer 119 includes a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer located within the pixel-defining opening. The hole injection layer is located on the side of the anode 102 farther from the buffer layer 111, and the hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer are sequentially stacked.

[0091] In this embodiment, the display panel 100 further includes a cathode, which covers at least the side of the organic layer 119 that is farther from the substrate 101 .

[0092] The anode 102, the cathode and the organic layer 119 constitute a light-emitting element.

[0093] In the embodiment of the present invention, the pixel defining portions 103 are arranged in one-to-one correspondence with the anodes 102, so that the distance between the adjacent pixel defining portions 103 is reduced, which reduces the stress applied to the pixel defining portions 103, and the slope of the first side 103 a of the pixel defining portion 103 is made gentler, which increases the contact area between the pixel defining portion 103 and the adjacent film layer, strengthens the strength of the bond between the pixel defining portion 103 and the adjacent film layer, and improves the product quality of the display panel 100.

[0094] 1 to 3 and 4a to 4m, an embodiment of the present invention further provides a method for manufacturing a display panel 100, the method including: S100, providing the substrate 101; S200, forming an anode material layer on the substrate 101; S300, forming a pixel defining material layer on the anode material layer; S400 includes forming the anode material layer and the pixel defining material layer into a plurality of anodes 102 and a plurality of pixel defining portions 103, respectively, through a first patterning process.

[0095] Here, the pixel definition portion 103 covers the edge of the anode 102 and exposes a part of the anode 102, and one pixel definition portion 103 is arranged surrounding one anode 102, and adjacent pixel definition portions 103 are arranged at an interval.

[0096] The pixel defining portion 103 includes a first side 103a that is farther from the anode 102 in a direction parallel to the substrate 101, and the side of the first side 103a that is closer to the substrate 101 forms a first included angle α with the substrate 101 that is greater than or equal to 35° and less than or equal to 45°. The pixel defining portion 103 includes a first side 103a that is farther from the anode 102 in a direction parallel to the substrate 101, and the side of the first side 103a that is closer to the substrate 101 forms a first included angle α with the substrate 101 that is greater than or equal to 35° and less than or equal to 45°.

[0097] In this embodiment, the material of the substrate 101 has been described in detail in the display panel 100, so it will not be described here.

[0098] In this embodiment, the anode material layer includes a material with a high work function. The anode material layer may include any one of transparent conductive materials with a relatively high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3). In addition to the conductive materials described above, the anode material layer may also include a reflective material, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a combination thereof. The anode material layer may be composed of a single layer or multiple layers of transparent conductive material and / or reflective conductive material. For example, the anode material layer may have a triple-layer stack structure of IZO / Ag / IZO composed of IZO and Ag. The anode material layer may be formed by physical vapor deposition or chemical vapor deposition. The anode material layer may be formed by physical vapor deposition or chemical vapor deposition.

[0099] In this embodiment, the material of the pixel defining material layer is selected from organic materials, such as positive photoresist materials or negative photoresist materials, and the pixel defining material layer can be used as a photoresist. The pixel defining portion 103 and the anode 102 are formed by the same patterning process, which allows for manufacturing with fewer processes and reduces process costs.

[0100] In some embodiments, step S400 includes:

[0101] S410, exposing the pixel defining material layer using a first mask.

[0102] The first mask may be a half-tone mask.

[0103] S420: After the pixel defining material layer is developed, a first photoresist region, a second photoresist region, and a first photoresist-free region are formed.

[0104] Here, the thickness of the pixel defining material layer in the first photoresist region is greater than the thickness of the pixel defining material layer in the second photoresist region.

[0105] S430: To form the anode 102, a first etching process is used to remove the anode material layer corresponding to the first photoresist-free area.

[0106] The first etching process is a wet etching process. When the anode material layer has a three-layer structure of IZO material layer / Ag material layer / IZO material layer formed of an IZO material layer and an Ag material layer, a first etching agent is used in the first etching process. The first etching agent includes phosphoric acid, nitric acid, etc. and is used to etch the Ag material layer and the IZO material layer.

[0107] S440: removing the pixel defining material layer in the second photoresist region, and retaining the pixel defining material layer in the first photoresist region to form the pixel defining portion 103;

[0108] The pixel defining material layer in the second photoresist region may be removed by an ashing process.

[0109] In some embodiments, step S400 further includes:

[0110] S450, the pixel definition portion 103 and the anode 102 are cleaned.

[0111] In step S460, the pixel definition unit 103 is subjected to a heat treatment.

[0112] The materials, thicknesses, structures, etc. of the anode 102 and the pixel definition portion 103 have been described in detail in the display panel 100, and will not be described here.

[0113] In this embodiment, before step S200, the following is included:

[0114] Referring to S500 of FIG. 4b, a second metal layer 110 is formed on the substrate 101.

[0115] In this embodiment, the material, thickness, structure, etc. of the second metal layer 110 have been described in detail in the display panel 100, so they will not be described here.

[0116] Referring to S600 of FIG. 4c, a buffer material layer 115 is formed on the second metal layer 110.

[0117] The buffer material layer 115 covers the second metal layer 110 and the substrate 101 .

[0118] S700, forming a thin film transistor layer on the buffer material layer 115;

[0119] S800, forming a passivation layer 112 and a planarization layer 113 on the thin film transistor layer.

[0120] In this embodiment, the materials, thicknesses, structures, etc. of the passivation layer 112 and the flattening layer 113 have been described in detail in the display panel 100, so they will not be described here.

[0121] The passivation material layer covers the thin film transistor layer, and the planarization material layer covers the passivation material layer, and the material of the planarization material layer is a positive photoresist material or a negative photoresist material.

[0122] Referring to FIGS. 4d to 4h, in some embodiments, step S700 includes:

[0123] S710, a semiconductor layer 114 and a first metal layer 104 are formed on the buffer layer 111;

[0124] Step S710 includes:

[0125] S711, forming a semiconductor material layer 116 on the substrate 101;

[0126] S712: forming a first metal material layer 117 on the semiconductor material layer 116, the first metal material layer 117 being in direct contact with the semiconductor material layer 116;

[0127] S713, the semiconductor material layer 116 and the first metal material layer 117 are formed on the semiconductor layer 114 and the first metal layer 104, respectively, through a second patterning process.

[0128] The first metal layer 104 includes a source 106 and a drain 107 , and the source 106 and the drain 107 are located on opposite sides of the semiconductor layer 114 , respectively.

[0129] There is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c.

[0130] Step S713 includes:

[0131] S713a: forming a first photoresist material layer 118 on the first metal material layer;

[0132] S713b, exposing the first photoresist material layer 118 using a second mask.

[0133] The second mask may be a half-tone mask.

[0134] S713c: After the first photoresist material layer 118 is developed, a third photoresist region, a fourth photoresist region, and a second photoresist-free region are formed.

[0135] Here, the thickness of the first photoresist material layer 118 in the third photoresist region is greater than the thickness of the first photoresist material layer 118 in the fourth photoresist region.

[0136] S713d: A second etching process is used to remove the semiconductor material layer 116 and the first metal material layer 117 corresponding to a second photoresist-free region to form the semiconductor layer 114.

[0137] The second etching step may be a wet etching step.

[0138] S713e, using an ashing process to remove the first photoresist material layer 118 in the fourth photoresist region.

[0139] Step S713f: to form the first metal layer 104, a third etching process is used to remove the first metal material layer 117 corresponding to the fourth photoresist region.

[0140] The third etching process may be a wet etching process. When the first metal material layer is a three-layer stacked structure of MoTi / Cu / MoTi consisting of a MoTi layer, a Cu layer, and a MoTi layer, a second etching agent is used in the third etching process. The second etching agent does not contain fluorine element to avoid damage to the semiconductor layer 114. The second etching agent is used for the first metal material layer and contains components such as hydrogen peroxide.

[0141] S713g, the first photoresist material layer 118 is removed.

[0142] S720, a gate insulating layer 109 and a gate 108 are formed between the source 106 and the drain 107.

[0143] Step S720 includes:

[0144] S721, forming a gate insulating material layer on the first metal layer 104;

[0145] S722, forming a gate material layer on the gate insulating material layer.

[0146] S723, the gate insulating material layer and the gate material layer are respectively formed into the gate insulating layer 109 and the gate 108 through a third patterning process.

[0147] Step S723 includes:

[0148] S723a, forming a second photoresist material layer on the gate material layer.

[0149] S723b exposes the second layer of photoresist material using a third mask.

[0150] S723c: After the second photoresist material layer is developed, a fifth photoresist region and a third photoresist-free region are formed.

[0151] S723d: removing the gate material layer corresponding to the third photoresist-free region using a fourth etching process to form the gate 108;

[0152] The fourth etching step may be a wet etching step.

[0153] S723e, to form the gate insulating film 109, a fifth etching process is used to remove the gate insulating material layer corresponding to the third photoresist-free region.

[0154] The fifth etching step may be a dry etching step.

[0155] S723f, removing the second photoresist material layer.

[0156] S730, the semiconductor layer 114 is subjected to a conductive treatment to form the active layer 105.

[0157] The conductive treatment may be performed by means of ion implantation, ion bombardment, or the like to form the active layer 105, which includes a channel portion 105a and a first conductor sub-portion 105b and a second conductor sub-portion 105c located on opposite sides of the channel portion 105a.

[0158] In this embodiment, the materials, thicknesses, and structures of the gate insulating film 109, the first metal layer 104, and the active layer 105 have been described in detail in the display panel 100 described above, so they will not be described here.

[0159] Referring to FIG. 4i, when the thin film transistor layer is formed in steps S710 to S730, step S800 includes:

[0160] S810, a passivation layer 112 and a buffer layer 111 are formed.

[0161] Step S810 includes:

[0162] S811, forming a third photoresist material layer on the passivation material layer.

[0163] S812, exposing the third photoresist material layer using a fourth mask.

[0164] S813: After the third photoresist material layer is developed, a sixth photoresist region and a fourth photoresist-free region are formed.

[0165] The fourth photoresist-free region includes a first photoresist-free sub-region and a second photoresist-free sub-region.

[0166] S814: To form the passivation layer 112 and the buffer layer 111, a sixth etching process is used to remove the passivation material layer corresponding to the first photoresist-free sub-region, and to remove the passivation material layer and the buffer material layer 115 corresponding to the second photoresist-free sub-region.

[0167] The sixth etching step may be a dry etching step.

[0168] S815, removing the third photoresist material layer.

[0169] S820, forming the planarization layer 113;

[0170] Step S820 includes:

[0171] S821, exposing the planar material layer using a fifth mask.

[0172] S822: After the planar material layer is developed, a via hole in the first planar layer 113 and a via hole in the second planar layer 113 are formed.

[0173] The planar layer 113 and the passivation layer 112 constitute a first insulating layer. The via hole in the first planar layer 113 and the portion formed by removing the passivation material layer corresponding to the first photoresist-free sub-region are formed as a first via hole H1 in the first insulating layer, and the anode 102 is connected to the source 106 or the drain 107 through the first via hole H1. The via hole in the second planar layer 113 and the portion formed by removing the passivation material layer corresponding to the second photoresist-free sub-region are formed as a second via hole in the first insulating layer. The portion formed by removing the buffer material layer 115 corresponding to the second photoresist-free sub-region is formed as a third via hole, which communicates with the second via hole. The anode 102 is connected to the first light-shielding portion 110a of the second metal layer 110 through the second via hole.

[0174] The source 106 or the drain 107 is exposed by removing the passivation material layer corresponding to the first photoresist-free sub-region, and the passivation material layer and the buffer material layer 115 corresponding to the second photoresist-free sub-region are removed while removing the passivation material layer corresponding to the first photoresist-free sub-region, which results in over-etching of the source 106 or the drain 107. Because dry etching can avoid damage to metal materials, it is preferable to form the passivation layer 112 and the buffer layer 111 using the same etching process, which can reduce process costs.

[0175] Referring to FIGS. 4j-4l, in some embodiments, step S700 includes:

[0176] S740: forming a semiconductor layer 114 on the buffer layer 111;

[0177] In some embodiments, step S740 includes:

[0178] S741, forming a semiconductor material layer on the buffer layer 111;

[0179] S742, forming the semiconductor material layer into a semiconductor layer 114 through a fourth patterning process.

[0180] Step S742 includes:

[0181] S742a, forming a fourth photoresist material layer on the semiconductor material layer.

[0182] S742b, exposing the fourth layer of photoresist material using a sixth mask;

[0183] S742c: After the fourth photoresist material layer is developed, a seventh photoresist region and a fifth photoresist-free region are formed.

[0184] S742d, using a seventh etching step to remove the semiconductor material layer corresponding to the fifth photoresist-free area to form the semiconductor layer 114;

[0185] The seventh etching step may be a wet etching step.

[0186] S742e, removing the fourth photoresist material layer.

[0187] In step S750, the gate insulating layer 109 and the buffer layer 111 are formed.

[0188] Step S750 includes:

[0189] S751, forming a gate insulating material layer on the semiconductor layer 114, the gate insulating material layer covering the semiconductor layer 114 and the buffer material layer 115;

[0190] S752, the gate insulating material layer is patterned to form the semiconductor layer 114 through a fifth patterning process.

[0191] Step S752 includes:

[0192] S752a, forming a fifth photoresist material layer on the gate insulating material layer.

[0193] S752b, exposing the fifth layer of photoresist material using a seventh mask.

[0194] S752c: After the fifth photoresist material is developed, an eighth photoresist region and a sixth photoresist-free region are formed.

[0195] The sixth photoresist-free region includes a third photoresist-free sub-region, a fourth photoresist-free sub-region and a fourth photoresist-free sub-region.

[0196] S752d: Using an eighth etching process, the gate insulating material layer corresponding to the third photoresist-free sub-region and the fourth photoresist-free sub-region, the gate insulating material layer corresponding to the fifth photoresist-free sub-region, and the buffer material layer 115 are removed to form the gate insulating layer 109 and the buffer layer 111.

[0197] The eighth etching step may be a dry etching step.

[0198] The gate insulating layer 109 includes a first insulating portion, a second insulating portion, and a third insulating portion. The gate insulating material layer and the buffer layer 111 corresponding to the third photoresist sub-region, the fourth photoresist sub-region, and the fifth photoresist sub-region are removed to respectively form a first opening, a second opening, and a fourth or sixth via hole in the gate insulating layer 109, and a fifth or seventh via hole in the buffer layer 111.

[0199] The fourth via hole is located on a side of the second insulating portion farther from the active layer 105, the buffer layer 111 includes a fifth via hole, the fourth via hole is in communication with the fifth via hole, and the source 106 and the first light-shielding portion 110a of the second metal layer 110 are connected through the fourth and fifth via holes. Alternatively, the sixth via hole is located on a side of the third insulating portion farther from the active layer 105, the buffer layer 111 includes a seventh via hole, the sixth via hole is in communication with the seventh via hole, and the drain 107 and the first light-shielding portion 110a are connected through the sixth and seventh via holes.

[0200] S760, forming an active layer 105 on the semiconductor layer 114;

[0201] The semiconductor layer 114 is subjected to a conductive treatment using the first opening and the second opening to form the active layer 105 .

[0202] The conductive treatment may be performed by ion implantation, ion bombardment, or the like.

[0203] In step S770, the first metal layer 104 is formed on the gate insulating film 109.

[0204] The first metal layer 104 includes a source 106, a drain 107, and a gate 108.

[0205] Step S770 includes:

[0206] S771, forming a first metal material layer on the gate insulating layer 109;

[0207] S772, forming a first metal material layer on the first metal layer 104 by a sixth patterning process.

[0208] Step S772 includes:

[0209] S772a, forming a sixth photoresist material layer on the first metal material layer.

[0210] S772b, exposing the sixth layer of photoresist material using an eighth mask.

[0211] S772c: After the sixth photoresist material layer is developed, a ninth photoresist region and a seventh photoresist-free region are formed.

[0212] The ninth photoresist region includes a first photoresist sub-region, a second photoresist sub-region, and a third photoresist sub-region.

[0213] Step S772d: remove the first metal material layer corresponding to the seventh photoresist-free region using a ninth etching process to form the first metal layer 104.

[0214] The first metal material layer corresponding to the first photoresist sub-region, the second photoresist sub-region and the third photoresist sub-region is formed on the source 106, the drain 107 and the gate 108, respectively.

[0215] The ninth etching step may be a wet etching step.

[0216] S772e, removing the sixth photoresist material layer.

[0217] In this embodiment, the materials, thicknesses, and structures of the gate insulating film 109, the first metal layer 104, and the active layer 105 have been described in detail in the display panel 100 described above, so they will not be described here.

[0218] Referring to FIG. 4m, when steps S740 to S770 form a thin film transistor layer, step S800 includes:

[0219] S830, forming a passivation layer 112 and a planarization layer 113 on the thin film transistor layer.

[0220] Step S830 includes:

[0221] S831, forming a passivation material layer on the thin film transistor layer.

[0222] S832, forming a planar material layer on the passivation material layer.

[0223] The material of the planar material layer is selected from a positive photoresist material or a negative photoresist material.

[0224] S834, the passivation material layer and the planarization material layer are respectively formed into the passivation layer 112 and the planarization layer 113 by a seventh patterning process.

[0225] Step S834 includes:

[0226] S834a, exposing the planar material layer using an eighth mask.

[0227] S834b: To form the planarization layer 113, the planarization material layer is developed, and then a tenth photoresist region and an eighth photoresist-free region are formed.

[0228] S834c: removing the passivation material layer corresponding to the eighth photoresist-free region using a tenth etching process to form the passivation layer 112;

[0229] The tenth etching step may be a dry etching step.

[0230] The via hole in the planar layer 113 and the passivation layer 112 constitute a first insulating layer, and the eighth photoresist-free region and the portion of the passivation material layer corresponding to the eighth photoresist-free region formed by removing the region are formed in a first via hole H1 in the first insulating layer, and the anode 102 is connected to the first metal material layer through the first via hole H1.

[0231] In this embodiment, step S500 further includes:

[0232] S510, forming a second metal material layer on the substrate 101;

[0233] S520, forming the second metal material layer on the second metal layer 110 by an eighth patterning process.

[0234] Step S520 includes:

[0235] S520a, forming a seventh photoresist material layer on the second metal material layer.

[0236] S520b, the seventh layer of photoresist material is exposed using a tenth mask.

[0237] S520c: After the seventh photoresist material is developed, an eleventh photoresist region and a ninth photoresist-free region are formed.

[0238] S520d: using an eleventh etching process to remove the second metal material layer corresponding to the ninth photoresist-free region to form the second metal layer 110;

[0239] The eleventh etching step may be a wet etching step.

[0240] S520e, removing the seventh photoresist material layer.

[0241] In the method for manufacturing a display panel provided by the embodiment of the present invention, the manufacturing of the film layers between the substrate 101 and the pixel defining portions 103 requires only six patterning processes, thereby reducing process costs and improving process efficiency. In addition, the pixel defining portions 103 are arranged in one-to-one correspondence with the anodes 102, and adjacent pixel defining portions 103 are arranged with a gap between them, thereby reducing stress on the pixel defining portions 103. The slope of the first side surface 103a of each pixel defining portion 103 is more gentle, which increases the contact area between the pixel defining portion 103 and an adjacent film layer, improving the strength of the bond between the pixel defining portion 103 and an adjacent film layer, and improving the product quality of the manufactured display panel.

[0242] An embodiment of the present invention discloses a display panel and a manufacturing method thereof. The display panel includes a substrate, a plurality of anodes disposed on the substrate, and a plurality of pixel definition portions covering the edges of the anodes and exposing portions of the anodes. Each pixel definition portion is disposed around one of the anodes, and adjacent pixel definition portions are spaced apart. The pixel definition portions have a first side surface farther from the anodes in a direction parallel to the substrate, and the first side surface near the substrate forms a first included angle with the substrate, the first included angle being greater than or equal to 35° and less than or equal to 45°. By arranging the pixel definition portions in a one-to-one correspondence with the anodes, adjacent pixel definition portions are spaced apart, reducing stress on the pixel definition portions and providing a gentler slope of the first side surface of the pixel definition portions. This increases the contact area between the pixel definition portions and adjacent film layers, strengthening the strength of the bond between the pixel definition portions and adjacent film layers, and improving the product quality of the display panel.

[0243] It should be understood that a person skilled in the art can make equivalent substitutions or modifications based on the technical ideas and technical concepts described in the claims, and such modifications or modifications fall within the technical scope of the claims.

Claims

1. A display panel, A substrate; a plurality of anodes located on the substrate; a plurality of pixel defining portions covering edges of the anode and exposing portions of the anode; wherein one pixel definition unit is disposed surrounding one anode, and adjacent pixel definition units are disposed at an interval, the pixel definition portion includes a first side surface farther from the anode in a direction parallel to the substrate, the first side surface having a side closer to the substrate forming a first included angle with the substrate, the first included angle being greater than or equal to 35° and less than or equal to 45°; the display panel further includes a first metal layer, the first metal layer being sandwiched between the anode and the substrate; the display panel further includes a first insulating layer, the first insulating layer being sandwiched between the first metal layer and the anode, the first insulating layer including a first via hole, the anode including a first connection portion located in the first via hole, the first connection portion being connected to the first metal layer, and the pixel definition portion covering the first connection portion; Display panel.

2. the display panel further includes an active layer, the active layer being sandwiched between the first metal layer and the substrate, the active layer including a channel portion and a first conductor sub-portion and a second conductor sub-portion located on opposite sides of the channel portion, respectively; the first metal layer includes a source and a drain, the source being located in the first conductor sub-portion and the drain being located in the second conductor sub-portion; wherein at least a portion of the source contacts the first conductor sub-portion on a side closer to the active layer, and at least a portion of the drain contacts the second conductor sub-portion on a side closer to the active layer. The display panel according to claim 1 .

3. the display panel further includes a gate, the gate being sandwiched between the source and the drain, and a positive projection of the gate in the active layer covering the channel portion; the display panel further includes a gate insulating layer, the gate insulating layer being sandwiched between at least the gate and the channel portion; The display panel according to claim 2 .

4. the gate is located in the first metal layer, the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion spaced apart, the first insulating portion being sandwiched between the channel portion and the gate, the second insulating portion being sandwiched between a portion of the source and the first conductor sub-portion, and the third insulating portion being sandwiched between a portion of the drain and the second conductor sub-portion; an end of the source close to the gate contacts the first conductor sub-portion, and an end of the drain close to the gate contacts the second conductor sub-portion; The display panel according to claim 3 .

5. the gate is located on a side of the first metal layer distal to the substrate, with no insulating layer between the source and the first conductor sub-portion and no insulating layer between the drain and the second conductor sub-portion; The display panel according to claim 3 .

6. in a plane parallel to the substrate, in a direction from the channel portion toward the first conductor sub-portion, an edge of the source remote from the gate extends beyond an edge of the first conductor sub-portion remote from the channel portion; In a plane parallel to the substrate, in a direction from the channel portion toward the second conductor sub-portion, an edge of the drain remote from the gate extends beyond an edge of the second conductor sub-portion remote from the channel portion. The display panel according to claim 5 .

7. the display panel further includes a second metal layer, the second metal layer being sandwiched between the active layer and the substrate, the second metal layer including a first light-shielding portion, and an orthogonal projection of the active layer on the substrate being located within an orthogonal projection of the first light-shielding portion on the substrate; the display panel further includes a buffer layer, the buffer layer being located on a side of the active layer closer to the substrate, and the buffer layer covering the second metal layer; The display panel according to claim 2 .

8. the first insulating layer includes a passivation layer on a side closer to the substrate, the buffer layer being sandwiched between the second metal layer and the active layer, and the side of the buffer layer farther from the substrate being in direct contact with the active layer and the passivation layer; a side of the buffer layer that is closest to the substrate is in direct contact with the second metal layer and the substrate; The display panel according to claim 7 .

9. When the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart from each other, an end of the second insulating portion farther from the first insulating portion contacts the buffer layer, and an end of the third insulating portion farther from the first insulating portion contacts the buffer layer. The display panel according to claim 8 .

10. the first insulating layer further includes a second via hole, the second via hole being located on one side of the active layer; the buffer layer includes a third via hole, the third via hole is in communication with the second via hole, and the anode is connected to the first light-shielding portion through the second via hole and the third via hole; the anode includes a second connection portion, the second connection portion is in contact with the first light-shielding portion, and an orthogonal projection of the pixel definition portion on the substrate covers an orthogonal projection of the second connection portion on the substrate. The display panel according to claim 7 .

11. the gate insulating layer includes a fourth via hole, the fourth via hole being located on a side of the second insulating part farther from the active layer; the buffer layer includes a fifth via hole, the fourth via hole being in communication with the fifth via hole; and the source is connected to the first light-shielding part through the fourth via hole and the fifth via hole; The display panel according to claim 7 .

12. the gate insulating layer includes a sixth via hole, the sixth via hole being located on a side of the third insulating part farther from the active layer; the buffer layer includes a seventh via hole, the sixth via hole being in communication with the seventh via hole; and the drain is connected to the first light-shielding part through the sixth via hole and the seventh via hole. The display panel according to claim 7 .

13. the display panel includes a display area and a non-display area located on at least one side of the display area, the display panel further includes a terminal located in the non-display area, the terminal being located on the first metal layer; wherein the terminals include a first type of terminal, and the first type of terminal is connected to a second metal layer; The display panel according to claim 1 .

14. when the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are arranged apart from each other, the gate insulating layer further includes a fourth insulating portion sandwiched between the terminal and a buffer layer, the gate insulating layer further includes an eighth via hole, the eighth via hole penetrating the fourth insulating portion, the buffer layer includes a ninth via hole, the ninth via hole penetrating the buffer layer sandwiched between the wiring of the second metal layer and the fourth insulating portion, and an orthogonal projection of the eighth via hole on the substrate covers an orthogonal projection of the ninth via hole on the substrate; the first-class terminals include first-class terminal connection portions, the first-class terminal connection portions are located in the eighth via holes and the ninth via holes, the eighth via holes and the ninth via holes expose the wiring of the second metal layer, and the first-class terminal connection portions contact the wiring of the second metal layer; The display panel according to claim 13.

15. the pixel definition portion has an overlapping portion with the anode, and a width of the overlapping portion as orthogonally projected on the substrate is 2 μm or more; The display device according to any one of claims 1 to 14.

16. the display panel further includes an organic layer located on a side of the anode farther from the substrate, the organic layer including a light-emitting layer; the pixel definition portion includes a second side surface closer to the anode in a direction parallel to the substrate, and an orthogonal projection of the anode on the substrate and an orthogonal projection of the second side surface on the substrate collectively cover an orthogonal projection of the light-emitting layer on the substrate; The display panel according to claim 15.

17. a second side surface of the second side surface closer to the anode and the second side surface forming a second included angle of 35° or more with the anode, the second included angle being 35° or more and 45° or less; The display panel according to claim 16.

18. Providing a substrate; forming an anode material layer on the substrate; forming a pixel defining material layer on the anode material layer; forming the anode material layer and the pixel defining material layer into a plurality of anodes and a plurality of pixel defining portions, respectively, through a first patterning process; wherein the pixel definition portion covers an edge of the anode and exposes a part of the anode, one pixel definition portion is disposed surrounding one anode, and adjacent pixel definition portions are disposed with an interval between them, the pixel definition portion includes a first side surface farther from the anode in a direction parallel to the substrate, the first side surface having a side closer to the substrate forming a first included angle with the substrate, the first included angle being greater than or equal to 35° and less than or equal to 45°; before forming an anode material layer on the substrate; forming a layer of semiconductor material on the substrate; forming a first metal layer on the semiconductor material layer such that the first metal layer is in direct contact with the semiconductor material layer; forming the semiconductor material layer and the first metal material layer into a semiconductor layer and a first metal layer, respectively, by a second patterning process; wherein the first metal layer includes a source and a drain, the source and the drain being located on opposite sides of the semiconductor layer, respectively. A method for manufacturing a display panel.

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