comparator

Abstract

To provide a comparator which has improved response characteristics without increasing a circuit current.SOLUTION: If a current flowing in a load resistor R2 is higher than a current flowing in a load resistor R1, then a shunt circuit 4 shunts a current flowing in a transistor M41 and flows a shunted portion of the current to the load resistor R1. Meanwhile, if the current flowing in the load resistor R1 is higher than the current flowing in the load resistor R2, then the shunt circuit shunts a current flowing in a transistor M42 and flows a shunted portion of the current to the load resistor R2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a comparator. [Background technology]

[0002] Global warming is believed to be caused by an intensification of the greenhouse effect in the atmosphere due to rising concentrations of greenhouse gases such as CO2, and with the rapid development of a communications and information society, reducing the power consumption of electronic devices has become a major issue. Many semiconductor integrated circuits are used in electronic devices, and the main performance characteristics of comparators, which are widely used in semiconductor integrated circuits, are response speed and current consumption. Since the response speed and current consumption of a comparator are inversely proportional, this technology aims to improve the response characteristics to input signals without increasing current consumption, thereby contributing to the prevention of global warming.

[0003] A circuit as shown in Fig. 6 is known as a comparator used in a semiconductor integrated circuit (see, for example, Patent Document 1). The comparator 100 shown in Fig. 6 is configured with a differential input section 102, a folded cascode section 103, and an output circuit 105 as main components.

[0004] The differential input section 102 is composed of differential transistors M1 and M2 whose sources are connected in common, load resistors R1 and R2 connected to the drains of the transistors M1 and M2, respectively, and a constant current source 21 connected between the common source of the transistors M1 and M2 and the positive power supply voltage VDD.

[0005] The folded cascode unit 103 includes transistors M3 and M4, the sources of which are connected to load resistors R1 and R2, constant current sources 311 and 312, each connected between the drains of the transistors M3 and M4 and a positive power supply voltage VDD, and a transistor M5, the gate and drain of which are connected to the drain of the transistor M4 and the source of which is connected to the gate of the transistor M4. In the folded cascode unit 103, the transistors M3 and M4 are connected as a current mirror, and an output is taken from the connection node between the drain of the transistor M4 and the constant current source 312.

[0006] Furthermore, the transistor M5 suppresses the rise in the gate potential of the transistor M6, thereby shortening the propagation delay time and improving the power supply voltage dependency of the propagation delay time (see, for example, Non-Patent Document 1).

[0007] The output circuit 105 comprises a transistor M6 whose gate is connected to the output of the folded cascode section 103 and whose source is connected to the negative power supply voltage VSS, and a constant current source 51 connected between the drain of the transistor M6 and the positive power supply voltage VDD, and is configured to extract an output signal VOUT from the connection node between the transistor M6 and the constant current source 51. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 4677284 [Non-patent literature]

[0009] [Non-Patent Document 1] Haruhiko Yoshida, Practical Design of CMOS Analog IC Circuits, CQ Publishing, 2010 (p. 144, Figure 4.10) Summary of the Invention [Problem to be solved by the invention]

[0010] A conventional comparator having the above-described configuration has a problem in that the circuit current must be increased in order to improve the response characteristics.

[0011] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a comparator with improved response characteristics without increasing the circuit current. [Means for solving the problem]

[0012] In order to achieve the above-mentioned object, the comparator according to the present invention is characterized by the following [1] to [8]. [1] a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential; a first load resistor connected in series with the first differential transistor; a differential input section having a second load resistor connected in series with the second differential transistor; a first folded cascode section including a third transistor connected in folded cascode to the first differential transistor and a fourth transistor connected in folded cascode to the second differential transistor, the fourth transistor constituting a first output stage; a second folded cascode section including a fifth transistor connected in folded cascode to the second differential transistor and a sixth transistor connected in folded cascode to the first differential transistor, the sixth transistor constituting a second output stage; an output circuit connected to the outputs of the first and second output stages to output an output signal, a shunt circuit that shunts a current flowing through the fourth transistor to flow through the first load resistor when the current flowing through the second load resistor is greater than the current flowing through the first load resistor, and that shunts a current flowing through the sixth transistor to flow through the second load resistor when the current flowing through the first load resistor is greater than the current flowing through the second load resistor;death, The shunt circuit includes: a seventh transistor having a source or emitter connected to the output of the first output stage, a drain or collector connected to the output of the second output stage, and a gate or base connected to the drain or collector of the third transistor; It is a comparator. [2] a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential; a first load resistor connected in series with the first differential transistor; a differential input section having a second load resistor connected in series with the second differential transistor; a first folded cascode section including a third transistor connected in folded cascode to the first differential transistor and a fourth transistor connected in folded cascode to the second differential transistor, the fourth transistor constituting a first output stage; a second folded cascode section including a fifth transistor connected in folded cascode to the second differential transistor and a sixth transistor connected in folded cascode to the first differential transistor, the sixth transistor constituting a second output stage; an output circuit connected to the outputs of the first and second output stages to output an output signal, a shunt circuit that shunts a current flowing through the fourth transistor to flow through the first load resistor when the current flowing through the second load resistor is greater than the current flowing through the first load resistor, and that shunts a current flowing through the sixth transistor to flow through the second load resistor when the current flowing through the first load resistor is greater than the current flowing through the second load resistor; death, The shunt circuit includes: a seventh transistor connected between the output of the first output stage and the output of the second output stage, the gate or the base of which is connected to the drain or the collector of the third transistor; an eighth transistor connected between the output of the first output stage and the output of the second output stage, the gate or the base of which is connected to the drain or the collector of the fifth transistor; the source or emitter of the seventh transistor and the drain or collector of the eighth transistor are connected to the output of the first output stage; the drain or collector of the seventh transistor and the source or emitter of the eighth transistor are connected to the output of the second output stage; It is a comparator. [3] a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential; a first load resistor connected in series with the first differential transistor; a differential input section having a second load resistor connected in series with the second differential transistor; a first folded cascode section including a third transistor connected in folded cascode to the first differential transistor and a fourth transistor connected in folded cascode to the second differential transistor, the fourth transistor constituting a first output stage; a second folded cascode section including a fifth transistor connected in folded cascode to the second differential transistor and a sixth transistor connected in folded cascode to the first differential transistor, the sixth transistor constituting a second output stage; an output circuit connected to the outputs of the first and second output stages to output an output signal, a shunt circuit that shunts a current flowing through the fourth transistor to flow through the first load resistor when the current flowing through the second load resistor is greater than the current flowing through the first load resistor, and that shunts a current flowing through the sixth transistor to flow through the second load resistor when the current flowing through the first load resistor is greater than the current flowing through the second load resistor; death, The shunt circuit includes: a ninth transistor connected between the output of the first output stage and a connection point of the first differential transistor and the first load resistor, the gate or base of the ninth transistor being connected to the drain or collector of the third transistor; a tenth transistor connected between the output of the second output stage and a connection point of the second differential transistor and the second load resistor, the gate or base of which is connected to the drain or collector of the fifth transistor; It is a comparator. [4] [1]~[ 3 The comparator according to any one of the above items, The output circuit an eleventh transistor having a gate or a base connected to the output of the first output stage; a twelfth transistor having a gate or a base connected to the output of the second output stage; a thirteenth transistor connected in series with the eleventh transistor, the gate or the base of which is connected to the drain or the collector of the twelfth transistor; The output signal is output from a connection point between the eleventh transistor and the thirteenth transistor. It is a comparator. [5] [ 4

[0023] The comparator according to

[0024] , The output circuit a fourteenth transistor connected in series with the twelfth transistor and having a gate connected to a connection point between the eleventh transistor and the thirteenth transistor; It is a comparator. [6] [ 4 ] or [ 5

[0023] The comparator according to

[0024] , The threshold voltages of the eleventh transistor and the twelfth transistor are lower than the threshold voltages of the third to sixth transistors. It is a comparator. [7] [1]~[ 6 The comparator according to any one of the above items, At least one of the transistors is a field effect transistor. It is a comparator. [8] [1]~[ 7 The comparator according to any one of the above items, At least one of the transistors is a bipolar transistor. It is a comparator. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide a comparator with improved response characteristics without increasing the circuit current.

[0014] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a circuit diagram showing a comparator according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing a comparator according to a second embodiment of the present invention. [Figure 3] FIG. 3 is a circuit diagram showing a comparator according to a third embodiment of the present invention. [Figure 4] FIG. 4 is a circuit diagram showing a comparator according to a fourth embodiment of the present invention. [Figure 5] FIG. 5 is a circuit diagram showing a comparator according to a fifth embodiment of the present invention. [Figure 6] FIG. 6 is a circuit diagram showing an example of a conventional comparator. DETAILED DESCRIPTION OF THE INVENTION

[0016] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0017] (First embodiment) First, a comparator 1 of the first embodiment will be described with reference to Fig. 1. As shown in the figure, the comparator 1 compares an inverting input potential INM (=first input potential) input to an inverting input terminal T11 with a non-inverting input potential INP (=second input potential) input to a non-inverting input terminal T12, and outputs the comparison result from an output terminal T3. The comparator 1 includes a differential input section 2, a folded cascode section 31 (=first folded cascode section), a folded cascode section 32 (=second folded cascode section), a shunt circuit 4, and an output circuit 5.

[0018] The differential input section 2 includes a differential transistor M1 (=first differential transistor) and a differential transistor M2 (=second differential transistor) whose sources are commonly connected, a load resistor R1 (=first load resistor) and a load resistor R2 (=second load resistor) connected to the drains of the transistors M1 and M2, respectively, and a constant current source 21.

[0019] The differential transistors M1 and M2 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. The sources of the differential transistors M1 and M2 are connected in common and to a constant current source 21.

[0020] The load resistor R1 is connected in series with the differential transistor M1. More specifically, the load resistor R1 is connected between the drain of the differential transistor M1 and the negative power supply terminal T22. The negative power supply terminal T22 is supplied with the negative power supply voltage VSS. The load resistor R2 is connected in series with the differential transistor M2. More specifically, the load resistor R2 is connected between the drain of the differential transistor M2 and the negative power supply terminal T22.

[0021] The constant current source 21 is connected between a positive power supply terminal T21 and the sources of the differential transistors M1 and M2, which are connected in common. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The differential input section 2 shunts a constant current I1 supplied by the constant current source 21 to the differential transistors M1 and M2. The current ratio (shunt ratio) of the currents flowing through the differential transistors M1 and M2 is a value that depends on the inverting input potential INM input to the inverting input terminal T11 and the non-inverting input potential INP input to the non-inverting input terminal T12.

[0022] The folded cascode unit 31 includes a transistor M31 (=third transistor) connected in folded cascode to the differential transistor M1, a transistor M41 (=fourth transistor) connected in folded cascode to the differential transistor M2, and constant current sources 311 and 312. The transistors M31 and M41 are configured by N-channel field effect transistors.

[0023] The gate and drain of the transistor M31 are connected together. The source of the transistor M31 is connected to the connection point between the load resistor R1 and the drain of the differential transistor M1, and the drain is connected to the constant current source 311. The gate of the transistor M41 is connected to the gate and drain of the transistor M31. The source of the transistor M41 is connected to the connection point between the load resistor R2 and the drain of the differential transistor M2, and the drain is connected to the constant current source 312.

[0024] The constant current source 311 is connected between the drain of the transistor M31 and the positive power supply terminal T21. The constant current source 312 is connected between the drain of the transistor M41 and the positive power supply terminal T21.

[0025] In the folded cascode section 31, the transistors M31 and M41 are connected in a current mirror configuration, and an output is taken out from a connection node A between the transistor M41 constituting the first output stage and the constant current source 312.

[0026] The folded cascode section 32 includes a transistor M32 (=fifth transistor) that is connected in a folded cascode manner to the differential transistor M2, a transistor M42 (=sixth transistor) that is connected in a folded cascode manner to the differential transistor M1, and constant current sources 321 and 322. The transistors M32 and M42 are configured by N-channel field effect transistors.

[0027] The gate and drain of the transistor M32 are connected together. The source of the transistor M32 is connected to the connection point between the load resistor R2 and the drain of the differential transistor M2, and the drain is connected to the constant current source 321. The gate of the transistor M42 is connected to the gate and drain of the transistor M32. The source of the transistor M42 is connected to the connection point between the load resistor R1 and the drain of the differential transistor M1, and the drain is connected to the constant current source 322.

[0028] The constant current source 321 is connected between the drain of the transistor M32 and the positive power supply terminal T21. The constant current source 322 is connected between the drain of the transistor M42 and the positive power supply terminal T21.

[0029] In the folded cascode section 32, the transistor M32 and the transistor M42 are connected in a current mirror configuration, and an output is taken out from a connection node B between the transistor M42 constituting the second output stage and the constant current source 322.

[0030] The shunt circuit 4 is a circuit that shunts the current flowing through the transistor M41 and directs it to the load resistor R1 when the current flowing through the load resistor R2 is greater than the current flowing through the load resistor R1. The shunt circuit 4 is also a circuit that shunts the current flowing through the transistor M42 and directs it to the load resistor R2 when the current flowing through the load resistor R1 is greater than the current flowing through the load resistor R2.

[0031] The shunt circuit 4 includes a transistor M101 (=seventh transistor) and a transistor M102 (=eighth transistor). The transistors M101 and M102 are configured by P-channel field effect transistors. The transistor M101 has a source connected to a connection node A, a drain connected to a connection node B, and a gate connected to a connection point between the constant current source 311 and the drain of the transistor M31.

[0032] The transistor M102 has a source connected to the connection node B, a drain connected to the connection node A, and a gate connected to the connection point between the constant current source 321 and the drain of the transistor M32.

[0033] The output circuit 5 includes transistors M6 to M8 and a constant current source 51. The transistors M6 and M7 are configured by N-channel field effect transistors. The transistor M6 (=the eleventh transistor) has a gate connected to the connection node A, a source connected to the negative power supply terminal T22, and a drain connected to the drain of the transistor M8 and the output terminal T3. The transistor M7 (the twelfth transistor) has a gate connected to the connection node B, a source connected to the negative power supply terminal T22, and a drain connected to the constant current source 51.

[0034] The transistor M8 (=the thirteenth transistor) is composed of a P-channel field-effect transistor. The transistor M8 is connected in series with the transistor M6. More specifically, the gate of the transistor M8 is connected to the connection point between the drain of the transistor M7 and the constant current source 51, the source is connected to the positive power supply terminal T21, and the drain is connected to the drain of the transistor M6 and the output terminal T3. The constant current source 51 is connected between the positive power supply terminal T21 and the drain of the transistor M7.

[0035] Next, we will explain the operation of the comparator 1 configured as described above. First, we will explain the operation when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT from the output terminal T3 is in the low state, that is, when the output signal VOUT is approximately equal to the negative power supply voltage VSS.

[0036] When the inverting input potential INM is higher than the non-inverting input potential INP, more current I1 from the constant current source 21 flows through the differential transistor M2 than through the differential transistor M1, which reduces the voltage drop across the load resistor R1 and increases the voltage drop across the load resistor R2.

[0037] Then, the gate-source potential difference of transistor M41 becomes smaller than the gate-source potential difference of transistor M31, and transistor M41 turns off. When transistor M41 turns off, the potential of connection node A rises. When the potential of connection node A rises and the gate-source potential difference of transistor M6 reaches the threshold voltage, transistor M6 turns on.

[0038] Furthermore, when the gate-source potential difference of transistor M42 becomes larger than the gate-source potential difference of transistor M32 and transistor M42 turns on, the potential at connection node B decreases. When the potential at connection node B decreases and the gate-source potential difference of transistor M7 falls below the threshold voltage, transistor M7 turns off.

[0039] When transistor M7 turns off, the drain potential of transistor M7 rises. As the drain potential of transistor M7 rises, the gate potential of transistor M8 rises accordingly, turning transistor M8 off. As a result, the output signal VOUT at output terminal T3 goes low.

[0040] Furthermore, as described above, when transistor M41 is turned off, the drain potential of transistor M41 rises, turning transistor M101 on. As a result, a portion of the current from constant current source 312 flows from the source to the drain of transistor M101, which is turned on, and then flows into transistor M42, increasing the current flowing through load resistor R1. Furthermore, a portion of the current from constant current source 312 flows from the drain to the source due to the reverse operation of transistor M102, and then flows into transistor M42, increasing the current flowing through load resistor R1. As a result, the potential of connection node B becomes higher than when transistors M101 and M102 are not connected, preventing the potential from decreasing to near the negative power supply voltage VSS.

[0041] Furthermore, when the output signal VOUT is in a low state, the transistor M101 clamps the potential of the connection node A to a voltage obtained by adding the drain potential of the transistor M31 to the gate-source potential difference of the transistor M101, preventing the potential of the connection node A from rising to near the positive power supply voltage VDD.

[0042] Next, the operation will be described when the non-inverting input potential INP is higher than the inverting input potential INM and the output signal VOUT of the output terminal T3 is in a High state, that is, when the output signal VOUT is approximately equal to the positive power supply voltage VDD.

[0043] When the non-inverting input potential INP is higher than the inverting input potential INM, more current I1 from the constant current source 21 flows through the differential transistor M1 than through the differential transistor M2, which reduces the voltage drop across the load resistor R2 and increases the voltage drop across the load resistor R1.

[0044] Then, the gate-source potential difference of transistor M41 becomes larger than the gate-source potential difference of transistor M31, and transistor M41 turns on. When transistor M41 turns on, the potential of connection node A drops. When the potential of connection node A drops and the gate-source potential difference of transistor M6 falls below the threshold voltage, transistor M6 turns off. As described above, when the output signal VOUT is low, the potential of connection node A is suppressed from rising by the clamp of transistor M101. Therefore, at this time, the time it takes for transistor M6 to turn off after turning on can be shortened.

[0045] Furthermore, when the gate-source potential difference of transistor M42 becomes smaller than the gate-source potential difference of transistor M32 and transistor M42 is turned off, the potential at connection node B rises. When the gate-source potential difference of transistor M7 rises and reaches the threshold voltage, transistor M7 turns on. As described above, when the output signal VOUT is in a low state, a decrease in the potential at connection node B is suppressed by a portion of the current from constant current source 312 flowing into load resistor R1. This shortens the time it takes for transistor M7 to turn on after it has been turned off.

[0046] When transistor M7 turns on, the drain potential of transistor M7 drops. When the drain potential of transistor M7 drops, the gate potential of transistor M8 drops accordingly, turning transistor M8 on. As a result, the output signal VOUT at output terminal T3 goes high. As described above, the time it takes for transistor M6 to go from on to off and for transistor M7 to go from off to on can be shortened, so the response speed of the output signal VOUT to change from low to high can be increased.

[0047] Furthermore, as described above, when transistor M42 is turned off, the drain potential of transistor M42 rises, turning transistor M102 on. As a result, a portion of the current from constant current source 322 flows from the source to the drain of transistor M102, which is in the on state, and flows into transistor M41, increasing the current flowing through load resistor R2. Furthermore, a portion of the current from constant current source 322 flows from the drain to the source due to the reverse operation of transistor M101, and flows into transistor M41, increasing the current flowing through load resistor R2. As a result, the potential of connection node A becomes higher than when transistors M101 and M102 are not connected, preventing the potential from decreasing to near the negative power supply voltage VSS.

[0048] Furthermore, when the output signal VOUT is in a high state, the transistor M102 clamps the potential of the connection node B to a voltage obtained by adding the drain potential of the transistor M32 to the gate-source potential difference of the transistor M102, preventing the potential of the connection node B from rising to near the positive power supply voltage VDD.

[0049] As described above, while the output signal VOUT is in a high state, it is possible to suppress an increase in the potential of the connection node B and a decrease in the potential of the connection node A. As a result, when the output signal inverts to a low state, it is possible to shorten the time it takes for the transistor M6 to change from off to on and for the transistor M7 to change from on to off, thereby increasing the response speed at which the output signal VOUT inverts from a high state to a low state.

[0050] By using transistors M6 and M7 whose threshold voltages are lower than those of the transistors M31, M32, M41, and M42, the time it takes for the transistors M6 and M7 to change from the off state to the on state can be further reduced, thereby further improving the response characteristics of the output circuit 5.

[0051] Thus, the comparator 1 in the first embodiment has the effect of improving response characteristics without increasing the circuit current.

[0052] (Second embodiment) Next, a comparator 1B according to a second embodiment will be described with reference to Fig. 2. In Fig. 2, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0053] The comparator 1B includes a differential input section 2, a folded cascode section 31, a folded cascode section 32, a shunt circuit 4, and an output circuit 5B. The differential input section 2, the folded cascode section 31, the folded cascode section 32, and the shunt circuit 4 have already been described in the first embodiment, so detailed description thereof will be omitted here.

[0054] The output circuit 5B has transistors M6 to M9. In the output circuit 5B of the second embodiment, the constant current source 51 of the first embodiment is replaced with a transistor M9 (=fourteenth transistor). The transistor M9 is configured by a P-channel field effect transistor. The transistor M9 has a gate connected to the output terminal T3, a source connected to the positive power supply terminal T21, and a drain connected to the drain of the transistor M7.

[0055] The comparator 1B of the second embodiment is basically the same as that of the first embodiment, except for the points described below.

[0056] That is, in the first embodiment, when transistor M7 is in the on state, the drain current of transistor M7 continues to flow as a steady current. In contrast, in the second embodiment, when transistor M7 is in the on state, transistor M8 is turned on, and the gate potential of transistor M9 rises. When the gate potential of transistor M9 rises, transistor M9 is turned off, and therefore the drain current does not flow as a steady current when transistor M7 is in the on state.

[0057] Therefore, the comparator 1B in the second embodiment has the effect of reducing current consumption and improving response characteristics.

[0058] (Third embodiment) Next, a comparator 1C according to a third embodiment will be described with reference to Fig. 3. In Fig. 3, the same components as those in the circuits shown in Fig. 1 and Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0059] The comparator 1C includes a differential input section 2, a folded cascode section 31, a folded cascode section 32, a shunt circuit 4C, and an output circuit 5B. The differential input section 2 and the folded cascode sections 31 and 32 have already been described in the first embodiment, so detailed descriptions thereof will be omitted here. The output circuit 5B has already been described in the second embodiment, so detailed descriptions thereof will be omitted here.

[0060] The difference between the shunt circuit 4 of the first embodiment and the shunt circuit 4C of the third embodiment is the connection of the drains of the transistor M101C (= ninth transistor) and the transistor M102C (= tenth transistor). The drain of the transistor M101C of the third embodiment is connected to the connection point between the source of the transistor M42 and the load resistor R1. The drain of the transistor M102C of the third embodiment is connected to the connection point between the source of the transistor M41 and the load resistor R2.

[0061] The comparator 1C of the third embodiment is basically the same as that of the second embodiment, except for the points described below.

[0062] In the third embodiment, when the output signal VOUT of the output terminal T3 is in a low state, a portion of the current from the constant current source 312 increases the current flowing through the transistor M101C into the load resistor R1 connected to the source of the transistor M42. As a result, the gate potential of the transistor M7 becomes higher than when the transistor M101C is not connected, shortening the time it takes for the transistor M7 to change from an off state to an on state. As a result, the propagation delay time for the output signal VOUT of the output terminal T3 to change from a low state to a high state is shortened.

[0063] Furthermore, when the output signal VOUT of the output terminal T3 is in a high state, a portion of the current from the constant current source 322 increases the current flowing into the load resistor R2 connected to the source of the transistor M41 via the transistor M102C. As a result, the gate potential of the transistor M6 becomes higher than when the transistor M102C is not connected, shortening the time it takes for the transistor M6 to change from an off state to an on state. As a result, the propagation delay time for the output signal VOUT of the output terminal T3 to change from a high state to a low state is shortened.

[0064] Therefore, the comparator 1C of the third embodiment has the effect of reducing current consumption and improving response characteristics.

[0065] (Fourth embodiment) Next, a comparator 1D according to a fourth embodiment will be described with reference to Fig. 4. In Fig. 4, the same components as those in the circuits shown in Fig. 1 and Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0066] The comparator 1D includes a differential input section 2, folded cascode sections 31 and 32, a shunt circuit 4D, and an output circuit 5B. The differential input section 2 and folded cascode sections 31 and 32 have already been described in the first embodiment, so detailed descriptions thereof will be omitted here. The output circuit 5B has already been described in the second embodiment, so detailed descriptions thereof will be omitted here.

[0067] The difference between the current dividing circuit 4 of the first embodiment and the current dividing circuit 4D of the fourth embodiment is that the current dividing circuit 4D is composed of only the transistor M101 and does not include the transistor M102.

[0068] The comparator 1D of the fourth embodiment is basically the same as that of the second embodiment, except for the points described below.

[0069] In the fourth embodiment, when the output signal VOUT of the output terminal T3 is in a low state, part of the current from the constant current source 312 flows from the source to the drain of the transistor M101 and then flows into the drain of the transistor M42, increasing the current flowing through the load resistor R1. Also, when the output signal VOUT of the output terminal T3 is in a high state, part of the current from the constant current source 322 flows from the drain to the source of the transistor M101 and then flows into the drain of the transistor M41, increasing the current flowing through the load resistor R2.

[0070] Furthermore, the transistor M101 clamps the potential of the junction node A to a voltage obtained by adding the drain potential of the transistor M31 to the gate-source potential difference of the transistor M101, and clamps the potential of the junction node B to a voltage obtained by adding the drain potential of the transistor M31 to the gate-drain potential difference of the transistor M101, thereby preventing the potentials from rising to near the positive power supply voltage VDD.

[0071] (Fifth embodiment) Next, a comparator 1E according to a fifth embodiment will be described with reference to Fig. 5. In Fig. 5, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0072] As shown in the figure, a comparator 1E includes a differential input section 2E, a folded cascode section 31E, a folded cascode section 32E, a current dividing circuit 4E, and an output circuit 5E, similar to the first embodiment.

[0073] The first embodiment differs from the fifth embodiment in that the conductivity types of transistors M1E, M2E, M31E, M41E, M32E, M42E, M6E to M8E, M101E, and M102E corresponding to transistors M1, M2, M31, M41, M32, M42, M6 to M8, M101, and M102 are reversed. Also, the first embodiment differs from the fifth embodiment in that the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed.

[0074] Similarly, in the second to fourth embodiments, the conductivity types of the transistors may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

[0075] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0076] In the first to fifth embodiments described above, the transistors are configured as field-effect transistors, but this is not limiting. At least one of the transistors may be replaced with a bipolar transistor. In this case, the gate of the transistor can be replaced with the base, the source with the emitter, and the drain with the collector. [Explanation of symbols]

[0077] 1, 1B, 1C, 1D, 1E Comparators 2, 2E Differential input section 4, 4C, 4D, 4E shunt circuit 5, 5B, 5E output circuit 31, 31E Folded cascode section (first folded cascode section) 32, 32E Folded cascode section (second folded cascode section) INM Inverting input potential (first input potential) INP Non-inverting input potential (second input potential) M1, M1E Differential transistor (first differential transistor) M2, M2E Differential transistor (second differential transistor) M31, M31E transistors (third transistors) M41, M41E transistors (fourth transistor) M32, M32E transistors (fifth transistor) M42, M42E transistors (sixth transistor) M101, M101E transistors (seventh transistor) M102, M102E transistors (8th transistor) M101C Transistor (9th Transistor) M102C transistor (10th transistor) M6, M6E transistors (11th transistor) M7, M7E transistors (12th transistor) M8, M8E transistors (13th transistor) M9 transistor (14th transistor) R1, R1E Load resistor (first load resistor) R2, R2E Load resistor (second load resistor)

Claims

1. a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential; a first load resistor connected in series with the first differential transistor; a differential input section having a second load resistor connected in series with the second differential transistor; a first folded cascode section including a third transistor connected in folded cascode to the first differential transistor and a fourth transistor connected in folded cascode to the second differential transistor, the fourth transistor constituting a first output stage; a second folded cascode section including a fifth transistor connected in folded cascode to the second differential transistor and a sixth transistor connected in folded cascode to the first differential transistor, the sixth transistor constituting a second output stage; an output circuit connected to the outputs of the first and second output stages to output an output signal, a shunt circuit that shunts a current flowing through the fourth transistor to flow through the first load resistor when the current flowing through the second load resistor is greater than the current flowing through the first load resistor, and that shunts a current flowing through the sixth transistor to flow through the second load resistor when the current flowing through the first load resistor is greater than the current flowing through the second load resistor; The shunt circuit includes: a seventh transistor having a source or emitter connected to the output of the first output stage, a drain or collector connected to the output of the second output stage, and a gate or base connected to the drain or collector of the third transistor; comparator.

2. a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential; a first load resistor connected in series with the first differential transistor; a differential input section having a second load resistor connected in series with the second differential transistor; a first folded cascode section including a third transistor connected in folded cascode to the first differential transistor and a fourth transistor connected in folded cascode to the second differential transistor, the fourth transistor constituting a first output stage; a second folded cascode section including a fifth transistor connected in folded cascode to the second differential transistor and a sixth transistor connected in folded cascode to the first differential transistor, the sixth transistor constituting a second output stage; an output circuit connected to the outputs of the first and second output stages to output an output signal, a shunt circuit that shunts a current flowing through the fourth transistor to flow through the first load resistor when the current flowing through the second load resistor is greater than the current flowing through the first load resistor, and that shunts a current flowing through the sixth transistor to flow through the second load resistor when the current flowing through the first load resistor is greater than the current flowing through the second load resistor; The shunt circuit includes: a seventh transistor connected between the output of the first output stage and the output of the second output stage, the gate or the base of which is connected to the drain or the collector of the third transistor; an eighth transistor connected between the output of the first output stage and the output of the second output stage, the gate or the base of which is connected to the drain or the collector of the fifth transistor; the source or emitter of the seventh transistor and the drain or collector of the eighth transistor are connected to the output of the first output stage; the drain or collector of the seventh transistor and the source or emitter of the eighth transistor are connected to an output of the second output stage; comparator.

3. a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential; a first load resistor connected in series with the first differential transistor; a differential input section having a second load resistor connected in series with the second differential transistor; a first folded cascode section including a third transistor connected in folded cascode to the first differential transistor and a fourth transistor connected in folded cascode to the second differential transistor, the fourth transistor constituting a first output stage; a second folded cascode section including a fifth transistor connected in folded cascode to the second differential transistor and a sixth transistor connected in folded cascode to the first differential transistor, the sixth transistor constituting a second output stage; an output circuit connected to the outputs of the first and second output stages to output an output signal, a shunt circuit that shunts a current flowing through the fourth transistor to flow through the first load resistor when the current flowing through the second load resistor is greater than the current flowing through the first load resistor, and that shunts a current flowing through the sixth transistor to flow through the second load resistor when the current flowing through the first load resistor is greater than the current flowing through the second load resistor; The shunt circuit includes: a ninth transistor connected between the output of the first output stage and the connection point of the first differential transistor and the first load resistor, the gate or base of which is connected to the drain or collector of the third transistor; a tenth transistor connected between the output of the second output stage and the connection point of the second differential transistor and the second load resistor, the gate or base of which is connected to the drain or collector of the fifth transistor; comparator.

4. The comparator according to any one of claims 1 to 3, The output circuit an eleventh transistor having a gate or a base connected to the output of the first output stage; a twelfth transistor having a gate or a base connected to the output of the second output stage; a thirteenth transistor connected in series with the eleventh transistor, the gate or the base of which is connected to the drain or the collector of the twelfth transistor; The output signal is output from a connection point between the eleventh transistor and the thirteenth transistor. comparator.

5. 5. A comparator according to claim 4, The output circuit a fourteenth transistor connected in series with the twelfth transistor and having a gate connected to a connection point between the eleventh transistor and the thirteenth transistor; comparator.

6. 6. A comparator according to claim 4 or 5, the threshold voltages of the eleventh transistor and the twelfth transistor are lower than the threshold voltages of the third to sixth transistors; comparator.

7. The comparator according to any one of claims 1 to 6, At least one of the transistors is a field effect transistor. comparator.

8. The comparator according to any one of claims 1 to 7, At least one of the transistors is a bipolar transistor. comparator.

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